مصطفي محمود كمال الدين ec6428f92d Refactoring the RISCV architecture to Auto-Sync on LLVM (#2756)
- Updated to LLVM-18
- Operands have now read/write access information
- Previously only the basic extensions and the compressed ISA was supported, now every extension supported by LLVM-18 also available (e.g. vector, crypto, ...)
- Changed register names
  * FP Regs: Instead of `RISCV_REG_F<n>_32` and `RISCV_REG_F<n>_64`, they're named `RISCV_REG_F<n>_F`
  and `RISCV_REG_F<n>_D` for n in `0..31`
- Added register names
  * Vector registes and combinations thereof `RISCV_REG_V<n>[_V<n_i>]*`, examples
    * `RISCV_REG_V21`
    * `RISCV_REG_V9_V10`
    * `RISCV_REG_V3_V4_V5`
    * etc... up to 8-register combinations
  * Half-percision (16-bit) FP registers `RISCV_REG_F<n>_H` for n in `0..31`
- Changed instruction names
  * Instructions ending in `_AQ_RL` now end in `_AQRL`
- Added instruction names: massive amount, see `include/capstone/riscv.h`
- Added `dimm` and `csr` fields inside the union data of `cs_riscv_op`, with corresponding `riscv_op_type`
  * `dimm` is used for instructions with FP immediates
  * `csr` is used for instructions with CSR systrem registes
- Added ISA flags to turn ISA extensions on and off
2026-02-01 11:53:24 +00:00
2024-04-22 11:55:44 +08:00
2024-09-23 11:26:56 +08:00
2024-05-12 21:17:20 +08:00
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2025-09-02 15:17:57 +00:00
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2023-05-19 19:50:46 +01:00
2025-01-28 22:34:24 +08:00
2026-01-13 14:12:23 +00:00
2025-01-28 22:34:24 +08:00

Capstone Engine

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Welcome to join our community group!  

Capstone is a disassembly framework with the target of becoming the ultimate disasm engine for binary analysis and reversing in the security community.

Created by Nguyen Anh Quynh, then developed and maintained by a small community, Capstone offers some unparalleled features:

  • Support multiple hardware architectures: ARM, AArch64, Alpha, ARC, BPF, Ethereum VM, LoongArch, HP PA-RISC (HPPA), M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86 (16, 32, 64), Xtensa.

  • Having clean/simple/lightweight/intuitive architecture-neutral API.

  • Provide details on disassembled instruction (called “decomposer” by others).

  • Provide semantics of the disassembled instruction, such as list of implicit registers read & written.

  • Implemented in pure C language, with lightweight bindings for Swift, D, Clojure, F#, Common Lisp, Visual Basic, PHP, PowerShell, Emacs, Haskell, Perl, Python, Ruby, C#, NodeJS, Java, GO, C++, OCaml, Lua, Rust, Delphi, Free Pascal & Vala ready either in main code, or provided externally by the community).

  • Native support for all popular platforms: Windows, Mac OSX, iOS, Android, Linux, *BSD, Solaris, etc.

  • Thread-safe by design.

  • Special support for embedding into firmware or OS kernel.

  • High performance & suitable for malware analysis (capable of handling various X86 malware tricks).

  • Distributed under the open source BSD license.

Further information is available at https://www.capstone-engine.org

Compile

See BUILDING.md file for how to compile and install Capstone.

Documentation

Contributing

See CONTRIBUTING.md for an intro.

Fuzz

See suite/fuzz/README.md for more information.

License

This project is released under the BSD license. If you redistribute the binary or source code of Capstone, please attach file LICENSE.TXT with your products.

S
Description
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
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