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Author SHA1 Message Date
raaller 04fd70b545 x86: decode reserved x87 register aliases (#3141) 2026-11-04 14:55:58 +00:00
raaller e4e3cfb966 x86: add missing FPU group for FCMOVNB (#3149) 2026-11-02 19:51:35 +00:00
dependabot[bot] ae90272c40 build(deps): bump pypa/cibuildwheel from 4.3.1 to 4.3.4 (#3144) 
Bumps [pypa/cibuildwheel](https://github.com/pypa/cibuildwheel) from 4.3.1 to 4.3.4.
- [Release notes](https://github.com/pypa/cibuildwheel/releases)
- [Changelog](https://github.com/pypa/cibuildwheel/blob/main/docs/changelog.md)
- [Commits](https://github.com/pypa/cibuildwheel/compare/v4.3.1...v4.3.4)

---
updated-dependencies:
- dependency-name: pypa/cibuildwheel
  dependency-version: 4.3.4
  dependency-type: direct:production
  update-type: version-update:semver-patch
...

Signed-off-by: dependabot[bot] <[email protected]>
Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
 2026-11-02 18:25:13 +00:00
raallerandRot127 8b95af3e94 x86: add SSSE3 groups for PABS instructions (#3137) 
Co-authored-by: Rot127 <[email protected]>
 2026-10-24 14:35:43 +00:00
Naren Sirigere d7fd1980d6 Update treesitter to 0.26.0 (#3138) 
Update query API
The argument tree in check_patching_result() is now of type Tree
Corrected the predicates in BitCastStdArray
Sorted imports and fixed some linter warnings
 2026-10-24 13:27:18 +00:00
raaller 901a4834d5 x86: decode reserved PREFETCH encodings (#3136) 2026-10-24 13:12:02 +00:00
Rot127 8e7cb27bbb Add timeout (#3135) 2026-10-22 15:32:14 +00:00
Samina 465bdbf567 Xtensa: fix SLLI shift amount of 32 not being printed (#3130) 
SLLI encodes its shift as 32 - shift in a 5-bit field, so field 0
means a shift of 32. decodeShimm1_31Operand already decodes this
correctly, but printShimm0_31_AsmOperand only accepted 0-31, so the
shift was dropped from the text (and assertion builds aborted).

Accept 0-32 in the printer. This operand range is only used by SLLI.

Example (esp32): 00 e8 01
  before: slli a14, a8,
  after:  slli a14, a8, 0x20
 2026-10-21 15:44:03 +00:00
Samina 6e7c5c19cc riscv: reject out-of-range immediates in decodeUImmOperand (#3133) 2026-10-21 15:33:40 +00:00
raaller 2b4a9407e6 x86: fix VADDPD metadata for embedded rounding (#3134) 2026-10-21 15:29:52 +00:00
raaller 4333798627 x86: fix x87 arithmetic register access (#3132) 2026-10-20 13:54:59 +00:00
raaller d01f16f4f6 x86: fix UD0 and UD1 instruction lengths (#3129) 2026-10-18 16:22:49 +00:00
phix33 cbdb30b52a x86: allow setting AT&T / Intel order for operand detail (#3127) 2026-10-18 15:38:49 +00:00
Samina a8adaf6096 sh: sign-extend 20-bit movi20 immediate (#3125) 
* sh: sign-extend 20-bit movi20 immediate

The SH2A movi20 path in decode_long() tested bit 27 for sign extension,
copied from the movi20s branch where the immediate is shifted left by 8.
movi20 is not shifted, so bit 27 is never set and negative immediates
decoded as large positive values. Test bit 19 instead.
 2026-10-18 15:32:28 +00:00
Julien Stephan 433cfc57b5 ci: build and test riscv64 wheels (#3120) 
Now that cibuildwheel and PyPI support riscv64, we can start building
riscv64 wheels.

Integrated in the same way as the other emulated architecture (i686),
running on the x86_64 runner via QEMU emulation.

Signed-off-by: Julien Stephan <[email protected]>
 2026-10-17 14:08:56 +00:00
dependabot[bot] 96d648e029 build(deps): bump pypa/cibuildwheel from 4.2.1 to 4.3.1 (#3122) 
Bumps [pypa/cibuildwheel](https://github.com/pypa/cibuildwheel) from 4.2.1 to 4.3.1.
- [Release notes](https://github.com/pypa/cibuildwheel/releases)
- [Changelog](https://github.com/pypa/cibuildwheel/blob/main/docs/changelog.md)
- [Commits](https://github.com/pypa/cibuildwheel/compare/v4.2.1...v4.3.1)

---
updated-dependencies:
- dependency-name: pypa/cibuildwheel
  dependency-version: 4.3.1
  dependency-type: direct:production
  update-type: version-update:semver-minor
...

Signed-off-by: dependabot[bot] <[email protected]>
Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
 2026-10-17 14:06:41 +00:00
raaller 484aaa30a1 x86: reject invalid mov to CS (#3124) 2026-10-17 13:40:06 +00:00
Samina 225a34a80f alpha: add missing Ra register operand to br/bsr detail mapping (#3121) 
The br/bsr printer path decodes Ra as operand[0] and disp21 as
operand[1], but the operand map only listed the disp, so the detail
operand types were wrong and set_detail_op_imm asserted on the disp.
Add the Ra register operand to both rows and keep it as an inc_patch.

Signed-off-by: bibi samina <[email protected]>
 2026-10-17 13:37:11 +00:00
Samina c3fbb86aa1 x86: mark cmpxchg destination operand as read-write (#3119) 2026-10-13 14:35:43 +00:00
Igor Savin 511056dd09 x86: Fix incorrect opcode 0x99 disassembly (#3115) 2026-10-12 13:34:10 +00:00
raaller cadc1428c6 x86: fix vmovsd store operand access (#3114) 2026-10-12 12:27:16 +00:00
Sree24-uiandSree24-ui bfb3a50661 X86: Correct memory access for FPU and MXCSR stores (#3112) 
Co-authored-by: Sree24-ui <[email protected]>
 2026-10-11 14:53:15 +00:00
raaller 7e5253aada x86: support repne bsf, bsr (#3113) 2026-10-11 13:35:43 +00:00
Abhinav 81497779ad AArch64: Fixes missing memory operand access value for SWP (#3111) 
* AArch64: Fixes missing memory operand access value for SWP

changes CS_AC_INVALID to CS_AC_READ | CS_AC_WRITE for all 16 swp versions in arch/AArch64/AArch64GenCSMappingInsnOp.inc and CS_AC_INVALID to CS_AC_READ_WRITE in arch/AArch64/AArch64GenCSMappingInsn.inc, added new patch file and tests for the same
 2026-10-09 17:14:06 +00:00
SaminaandRot127 e330ce90c9 mips: zero-extend microMIPS LWM16/SWM16 reglist offset (#2991) 
The ISA defines the offset as zero_extend(offset||0^2), but the non-MMR6
path in DecodeMemMMReglistImm4Lsl2 sign-extended the 4-bit field before
the << 2. When the field's top bit is set that makes Offset negative, so
Offset << 2 is a left shift of a negative value (UB), and the decoded
offset came out negative instead of the zero-extended value the ISA
requires.

Use fieldFromInstruction_4(Insn, 0, 4) to extract the field unsigned,
matching the MMR6 branch and the ISA. The shift is now always applied to
a non-negative value.

Verified under -fsanitize=undefined: before, cstool micromips 4508 and
test_poc abort at MipsDisassembler.c:2432 with 'left shift of negative
value -8'; after, test_poc exits clean and cstool prints
'lwm16 $s0, $ra, 0x20($sp)' (8 << 2 == 0x20).

Signed-off-by: bibi samina <[email protected]>
Co-authored-by: Rot127 <[email protected]>
 2026-10-09 15:08:20 +00:00
Samina 889185ee6f alpha: sign-extend memory-format displacement (#3036) 
* alpha: sign-extend memory-format displacement

* alpha: add inc patch for memory-format displacement sign extension
 2026-10-09 11:52:33 +00:00
pancakepancakeRot127
 		d868963b40 M68K: Fix operand size and write reports for the BTST/BCHG/BCLR/BSET instructions (#3099) 
---------

Co-authored-by: pancake <[email protected]>
Co-authored-by: Rot127 <[email protected]>
 2026-10-09 11:50:22 +00:00
phix33 b8c68d4865 x86: Fix BOUND operand access (both operands are read) (#3109) 2026-10-08 11:15:19 +00:00
pancakeandpancake 940af62c53 Fix oobread in x86 displacement decoding (coverity CID 656295) (#3083) 
Co-authored-by: pancake <[email protected]>
 2026-10-08 10:46:27 +00:00
raaller 454d9ae76a X86: Fix displacement size with 0x66 prefixes (#3105) 
* X86: Set displacement size for disp8 and disp16
 2026-10-08 10:40:24 +00:00
phix33 992e6d7fea x86: fix SETcc memory operand access (#3106) 2026-10-04 12:27:20 +00:00
Samina 84b5f9706d riscv: propagate decode failure in decodeCSSPushPopchk (#3104) 2026-10-04 12:16:24 +00:00
phix33 c4dd285170 x86: mark rotate memory destinations as written (#3103) 2026-10-04 12:11:23 +00:00
Samina 6f9738da4e utils: fix off-by-one out-of-bounds write in append_to_str_lower (#3102) 2026-10-04 11:44:43 +00:00
pancakeandpancake 17e40b3f66 ARM: Fix shift alias for MOVsi and MOVsr (#3098) 
---------

Co-authored-by: pancake <[email protected]>
 2026-09-30 15:37:31 +00:00
raaller e1a71eb2e8 x86: fix operand access for SHLD and SHRD (#3093) 2026-09-30 12:39:23 +00:00
dependabot[bot] 2827085524 Bump softprops/action-gh-release from 2 to 3 (#3095) 
Bumps [softprops/action-gh-release](https://github.com/softprops/action-gh-release) from 2 to 3.
- [Release notes](https://github.com/softprops/action-gh-release/releases)
- [Changelog](https://github.com/softprops/action-gh-release/blob/master/CHANGELOG.md)
- [Commits](https://github.com/softprops/action-gh-release/compare/v2...v3)

---
updated-dependencies:
- dependency-name: softprops/action-gh-release
  dependency-version: '3'
  dependency-type: direct:production
  update-type: version-update:semver-major
...

Signed-off-by: dependabot[bot] <[email protected]>
Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
 2026-09-30 12:31:09 +00:00
dependabot[bot] a7ae66e86e Bump actions/upload-artifact from 4 to 7 (#3096) 
Bumps [actions/upload-artifact](https://github.com/actions/upload-artifact) from 4 to 7.
- [Release notes](https://github.com/actions/upload-artifact/releases)
- [Commits](https://github.com/actions/upload-artifact/compare/v4...v7)

---
updated-dependencies:
- dependency-name: actions/upload-artifact
  dependency-version: '7'
  dependency-type: direct:production
  update-type: version-update:semver-major
...

Signed-off-by: dependabot[bot] <[email protected]>
Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
 2026-09-30 12:29:35 +00:00
jmestwa-coder a4ea4a9ea6 Alpha: Fix branch target truncation due to incorrect disp sign extension (#3092) 2026-09-28 12:04:48 +00:00
Rot127 9791930a89 Build and upload cross compiled tar.gz packages (#2862) 2026-09-24 21:02:12 +00:00
Rot127 ed8100114a Remove unused .gitmodules (#3087) 2026-09-24 16:34:38 +00:00
raaller 0083ee78a9 x86: fix TEST memory operand access and flags metadata (#3085) 2026-09-24 14:36:58 +00:00
pancakeandpancake 476a89c10d x86: Fix wrong displacements in mixed modes (#3084) 
Co-authored-by: pancake <[email protected]>
 2026-09-24 14:09:01 +00:00
Rot127 2b25a5bf77 Bump CS_VERSION_PRE_RELEASE after release (#3082) 2026-09-21 19:03:22 +00:00
Rot127 b2bf6327b5 Release 6.0.0-Alpha11 (#3079) 
* Update changelog to 6.0.0-Alpha11

* Increment version to 6.0.0-Alpha11

* Update bindings
6.0.0-Alpha11 		2026-09-21 16:06:22 +00:00
raallerRot127Copilot Autofix powered by AI
 		fab0851532 Add AI guidance (#3081) 
---------

Co-authored-by: Rot127 <[email protected]>
Co-authored-by: Copilot Autofix powered by AI <[email protected]>
 2026-09-21 15:09:53 +00:00
raaller 8f917b9afc x86: Fix access of X86_CMPSL memory operands - #3080 (#3080) 2026-09-19 15:19:49 +00:00
jmestwa-coder 31ec70e6f3 riscv: propagate register-class decode failure in decoders (#3071) 
Signed-off-by: Syed Mohammed Nayyar <[email protected]>
 2026-09-18 13:31:26 +00:00
raallerandRot127 b871849b6c x86: fix JO/JNO operand size in 64-bit mode by adding Intel/AMD mode flags (#3067) 
* x86: fix JO/JNO operand size in 64-bit mode
* x86: add explicit Intel/AMD near-Jcc decoding modes

---------

Co-authored-by: Rot127 <[email protected]>
 2026-09-18 12:29:39 +00:00
Rot127 59eec7ec25 Add Codecov workflow (#3076) 
* Setting leniency to 0% (for now).
 2026-09-15 16:26:30 +00:00