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darling-gdb/sim
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Andrew Cagney bc6df23d14 For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: Stepping 
through an exception may not work correctly.
For GDB reads/writes to the control registers, ensure the cpu state is
updated correctly.
1997-12-08 03:22:58 +00:00
..
arm
Regenerate configure files.
1997-12-04 17:26:06 +00:00
common
* Make-common.in (sim-core.o): Depend on $(sim_main_headers).
1997-12-05 00:04:46 +00:00
d10v
For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: Stepping
1997-12-08 03:22:58 +00:00
erc32
Remove need to update <targ>/Makefile.in when adding optional options
1997-09-23 01:25:26 +00:00
h8300
Correct name of file given in ChangeLog for change: Pass lma_p and
1997-10-25 05:04:25 +00:00
igen
* gen-idecode.c (print_jump_until_stop_body): Use `#if 0' instead of
1997-11-04 17:36:37 +00:00
m32r
* m32r-sim.h (MSPR_ADDR): New macro.
1997-12-05 00:48:05 +00:00
mips
Regenerate configure files.
1997-12-04 17:26:06 +00:00
mn10300
* simops.c (call:16 call:32): Stack adjustment is determined solely
1997-11-11 17:37:04 +00:00
ppc
Fix typo, WITH_TARGET_WORD_BITSIZE not WITH_TARGET_BITSIZE.
1997-10-02 23:37:30 +00:00
sh
Add LMA_P and DO_WRITE arguments to sim/common/sim-load.c:sim_load_file().
1997-10-22 05:26:27 +00:00
testsuite
For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: Stepping
1997-12-08 03:22:58 +00:00
tic80
Regenerate configure files.
1997-12-04 17:26:06 +00:00
v850
Reverrt breakpoint back to its old value.
1997-12-05 17:30:44 +00:00
w65
Add ABFD argument to sim_create_inferior. Document.
1997-08-27 04:44:41 +00:00
.Sanitize
r5900 sanitization fixes.
1997-09-24 07:27:43 +00:00
ChangeLog
v850eq wasn't building igen directory.
1997-09-12 03:13:27 +00:00
configure
v850eq wasn't building igen directory.
1997-09-12 03:13:27 +00:00
configure.in
Add support for Thumb target.
1997-12-02 18:17:13 +00:00
Makefile.in
TIc80 simulator checkpoint - runs 3 instructions - trap, addu, br.a.
1997-04-22 17:46:07 +00:00
README-HACKING
Doc C language guidelines.
1997-09-03 07:34:59 +00:00