DrZ80(snd) and Cyclone+DrZ80(snd) only replaced the Z80s flagged
CPU_AUDIO_CPU, and many sound Z80s are not flagged (CPS2, Taito,
Toaplan, the Mega Drive based boards...): those games kept the C Z80
with no sign in the log.
Now, on a board with no flagged CPU whose first CPU is not a Z80, its
first Z80 is taken as the sound CPU too, except where DrZ80 can't run
it: a Z80 with a daisy chain (DrZ80 has none), the CPS1 QSound Z80
(Kabuki-encrypted opcodes) and the Tatsumi sound Z80 (Round Up 5
hangs). The log says which Z80s are replaced and which are kept.
frontend_list.h: removed the entries that could do nothing, with the
same result for every game: 82 names not in the core, 531 games with
neither a 68000 nor a Z80, and a second zzyzzyx2 entry never reached.
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
Co-authored-by: Claude Opus 5.5 <[email protected]>
Bootleg clone set of cottonbm in English: the stage result lines, the
character select panels, the full names of the characters in the
attract mode, and the translation credit under the title logo. The game always
runs in its Japanese (translated) mode, so the whole translation shows
with every BIOS region. The four changed chips are built from cottonbm
with github.com/zanac/cottonbm, which writes a complete cottonbme.zip.
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
Co-authored-by: Claude Opus 5.5 <[email protected]>
goldnaxb (317-0110), goldnaxc (317-0122) and goldnaxj (317-0121) are the
Golden Axe sets with the FD1094 encrypted 68000 (MAME goldnaxe1,
goldnaxeu, goldnaxej). They were marked not working.
- The decryption keys are added to the sets and the code is decrypted
with the FD1094 module already used by Cotton (C 68000 core).
- They get their own memory maps: the ones of goldnaxa (171-5797 board)
and goldnaxe (171-5704 board) without the handlers that stand in for
the 8751 in the work RAM; these sets have no 8751, they read the I/O
and send the sound commands themselves.
- The 315-5195 memory mapper, as far as these games use it: register 3 is
the sound command, and every frame the program moves the sprite RAM to
one of 8 bases (0x200000-0x900000), so the sprite RAM follows the base
in register 0x19. The mapper registers are in the save states.
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
Co-authored-by: Claude Opus 5.5 <[email protected]>
Save states on ST-V were broken on master: a loaded state, a run-ahead
rewind or a netplay resync did not continue the emulation the same way.
Model 2 was almost right (hpyagu98 differed after a rewind).
Core:
- SH-2: each CPU registers its own state (both used to register the
boot buffer), and the rest of the CPU is saved: delay slot, divider,
interrupt queue and lines, on-chip registers, FRT, DMA timers.
- Memory banks are registered after the driver init, where the drivers
point them (ST-V work RAM was saved from the wrong buffer).
- cpu_spinuntil_time / cpu_yielduntil_time trigger counters are saved.
- The crosshair idle timer is saved (the crosshair hid at another frame
after a load or a rewind).
ST-V:
- SMPC, SCU registers and interrupts, SCU DSP, I/O, sound CPU control,
CD block scalars, VDP1 clipping, CRTC line counter are saved.
- The RTC starts from the host date and time at boot and then follows the
emulated time (it read the host clock at every query, so two runs from
the same state could read different times).
SH-2 recompiler: the polling loop skip counted a whole chain of blocks
that came back to the loop start as one loop iteration, skipping the
writes and calls in between. It now only skips when the block ran one
turn of the loop. Results with a warm or a cold block cache are now the
same.
Model 2: the polygon count of the last display list is saved.
SCSP (issue #2194, regression of #2198): a key off on a slot that had
already stopped (a one-shot sample past its end) left its envelope at the
level it stopped at, because a stopped slot no longer updates it. The
monitor register (0x408) then showed the slot as still sounding, the
sound drivers took it for busy and, after a while, put every new note on
the one slot left. Cotton Boomerang lost all but the drums at the first
boss, Winter Heat's voices cut each other from the first attract demo on.
Such a slot now ends its release at once.
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
Co-authored-by: Claude Opus 5.5 <[email protected]>
Renderer:
- texture sheets also kept one byte per texel, the texel fetch reads them
straight (inlined, an opaque and a translucent span)
- the pixel of each texel worked out once for the colours of a polygon
- translucent texel pairs packed from a table; a translucent pixel sure to
be discarded skips the next mipmap level
- 3D pixels kept as the 15-bit colour of the bitmap
- the tile layers drawn straight into the bitmap: the polygons are only
drawn over the tile pixels behind them, no copy passes
System 24 tiles (rgb version, Model 1 and 2): eight pixels at a time, a
group all of the layer's priority without a test each, the last pixels of
the line as groups too.
SCSP DSP: the steps that only multiply and accumulate on a short path,
decoded when MPRO changes; the delay RAM float packing from a table.
i960: opcodes read straight from the memory block of the last fetch
(memory_get_read_range), execute_op inlined.
SHARC: no DMA call while channels 6 and 7 are idle.
AArch64 (QEMU, instructions per frame): fvipers -26%, doa -28%, daytona
-31%, vf2 -25%. Frames and audio are the same on the Model 2 sets, the
ST-V sets and in save states.
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
Co-authored-by: Claude Opus 5.5 <[email protected]>
VDP2 tiles:
- vdp2_drawgfx_alpha drew every pixel through vdp2_window_process; with a
window it now draws the runs of each line the windows show, from the line
cache of vdp2_drawgfx_transpen (same pixels), and with no window it
copies without checks. Both work out the window key once per tile and
check the cached line inline.
- Each decoded element keeps two masks of its rows (a pixel other than
pen 0; no pen 0). With transparency vdp2_drawgfx_transpen skips tiles
and rows of pen 0 only and copies whole the rows without it.
VDP1 sprites: without color calculation draw_sprites walks the window runs
of the line instead of calling vdp2_window_process for every pixel.
SH-2:
- Only a read that includes FRC resyncs it (MAME frc_r); TIER and FTCSR
reads (MAME ftcsr_r) do not.
- The recompiler skips the iterations of polling loops that only read, as
it already did for the SGL idle loop: a block that starts with a short
loop back to itself which leaves every register as it found it and read
only RAM or TIER/FTCSR repeats the same iteration until the end of the
timeslice, so those iterations are counted at once.
Makefile (unix): -fvisibility=hidden, only retro_* leaves the library.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
SCSP (also used by Model 2):
- The slot engine from current MAME: key off goes to the release, the
envelope tables and the dB curve of the decay, pitch, interpolation,
the four loop modes, FM from the ring buffer, noise (SSCTL), SBCTL,
LPSLNK, STWINH/SDIR; 8-bit samples read in big-endian byte order.
- The monitor register 0x408 returns CA, SGC and EG of the slot set in
MSLC: the sound drivers look there for a free slot, and Winter Heat
played every voice on slot 0, each one cutting the previous.
- Real timers for timers A, B and C, as in MAME: counting them with the
generated samples delayed every interrupt until the next stream update.
- Interrupts as in MAME: each source raises its own level until it is
acknowledged in SCIRE, and an acknowledged expired timer is pending
again with no new interrupt. Reading MIBUF drops the MIDI interrupt:
left raised, the sound CPU took it again on an empty FIFO and read
stale bytes as MIDI data, which broke music commands in Model 2
(Fighting Vipers, Dead or Alive, Manx TT).
- The DMA used the common registers 0x412 words past them, inside the
slots: now as in MAME.
- The common registers are 0x400-0x42f only (0x500 is not a mirror),
the ring buffer at 0x600 can be read and written, the LFO saw wave and
rate as in MAME.
- ST-V: a 16-bit access of the SH-2 touches only its half of the SCSP
registers.
Batman Forever: the Acclaim RAX sound board (ADSP-2181), moved from zn.c
to sndhrdw/acclaim_rax.c and shared by NBA Jam Extreme and Batman
Forever, which writes its commands to 0x04800000 as in MAME.
docs/sega-model2.md: the MIDI interrupt of the sound link.
Fixes#2194.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
critcrsh / tatacot: the hammer was read from input ports 10 and 11,
which don't exist (the lightgun ports are 7 and 8), so the game always
saw it in the top left corner. The lightgun ports default to the
centre, since in this core the lightgun moves from the default value,
and the crosshair is drawn as in MAME. Fixes#2195.
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
Co-authored-by: Claude Opus 5.5 <[email protected]>
- techbowl, patocar, skychal, supgoal: trackball on the 315-5649 port G
counters, as in MAME (mode register bit 7, counter select and byte in
port G, auto-increment on read, reset when bit 7 is clear). New input
stvtrack with trackball X/Y. Fixes#2189.
- libretro video: the max geometry and the conversion buffer use the
larger of the default visible area and the screen size for raster
games, so ST-V frames up to 704x480 fit. Fixes#2190.
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
Co-authored-by: Claude Opus 5.5 <[email protected]>
Video, same results:
- vdp1_clear_framebuffer: rows filled as one or two runs, eight bytes at
a time, instead of a masked index per pixel.
- VDP2 windows: the coordinates of each line cached for the whole screen
update (one entry per line), and the runs of pixels each line shows for
the current layer cached too; the tiles of a window layer are drawn in
those runs instead of testing the windows on each pixel.
- Transparent tiles: four pixels tested at once, a transparent group is
skipped.
- Sprites: in a run of zero frame buffer pixels, four skipped at once.
- vdp2_copy_roz_bitmap: the layer settings read once per line.
Reset (#2188): the machine's timers are freed at each reset, but
machine_init only allocated the SCU DMA, hopper and SMPC INTBACK timers
when its pointers were NULL, so after a reset it adjusted freed timers
and the timer list looped forever. They are allocated at each
machine_init, as the other drivers do.
Fixes#2188
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
Co-authored-by: Claude Opus 5.5 <[email protected]>
jit_cmp() asked the flags of the compare with SLJIT_SET(cond & ~1). For
SLJIT_EQUAL that is SLJIT_SET(0), no flag at all: the x86 back ends
compare anyway, the AArch64 one does not, so CMP/EQ Rm,Rn and CMP/EQ
#imm,R0 set T from stale flags. The ST-V BIOS then took wrong branches
and games stayed on a black screen or ran with broken graphics with the
SH-2 Dynarec option on. The zero flag is now asked with SLJIT_SET_Z, as
the SH-3 recompiler already does.
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
Co-authored-by: Claude Opus 5.5 <[email protected]>
The cache and bus timing of every SH-3 data access (and of the
instruction fetch sampled with it) was most of the time spent on ARM.
Same output, cycle for cycle:
- fast RAM regions found through a 64 KB page table
- the time of the last bus access kept in 32 bits, relative to the
start of the timeslice (exact up to 2^30 cycles, "far" beyond, where
the timing only compares with small counts); the 64-bit value is
still the one saved in the states
- the tag of the most recently used way of each cache block kept next
to it, rebuilt eagerly instead of checked on every access
- the cycle count kept in locals across the fetch and data penalties
- the timing fields at the start of the CPU state
- the screen copy in at most two runs per line, with SSE2/NEON
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
Co-authored-by: Claude <[email protected]>
- cotton2e: Cotton 2 with the story scenes, ending and staff roll,
continue screen hints, prologue and character profiles in English,
from the English fan translation of the Saturn port. All eight ROMs
differ from cotton2; https://github.com/zanac/Cotton2 builds them.
- puyosune: Puyo Puyo Sun with the win quotes, story scenes, endings,
menus and in-game lettering in English, from the Puyo Nexus English
translation of the Windows version. Three ROMs differ from puyosun;
https://github.com/zanac/sega_st-v_puyosune builds them.
znpwfve (All Japan Pro-Wrestling, English) is already in master.
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
Co-authored-by: Claude Opus 5.5 <[email protected]>
- Driver, SCU (DMA, interrupts, timers, DSP), SMPC, MINIT/SINIT, EEPROM
and the protection chips as current MAME; the current MAME sets.
- VDP1/VDP2 video as current MAME's (one stvvid.c), with exact speedups:
partial redraw of the rotation plane cache, rotation copy, sprite
passes, window evaluation once per line.
- SH-2 recompiler on the bundled sljit (x86, x86-64, ARM32, ARM64; the
"SH-2 Dynarec" core option, off by default): blocks with chaining,
page tables for direct memory access, memory handlers called from the
blocks; the SGL idle loop is skipped exactly; context switch by
pointer. Same output as the interpreter on all the sets.
- "ST-V Threaded Video" core option (off by default): the screen drawn
in strips by 2-4 threads (libretro-common rthreads, where thread-local
storage is native), same output.
Two more sets of Zen Nippon Pro-Wrestling Featuring Virtua, both on the
Taiwan BIOS (the core selects it):
- znpwfvt: All Japan Pro-Wrestling Featuring Virtua (Taiwan), as in
current MAME.
- znpwfve: English translation (bootleg) on the Taiwan program, with the
graphics the English mode left in Japanese redrawn; the ROMs are built
from the original ones by https://github.com/zanac/znpwfvt
Claude-Session: https://claude.ai/code/session_013Vje3pEtpLHubqCGwCgoQX
Co-authored-by: Claude Opus 5.5 <[email protected]>
System E (segasyse.c, segasyse_vidhrdw.c, mc8123.c, sn76496.c):
- MC-8123 key based decryption from current MAME: Opa Opa (317-0042)
and Fantasy Zone II (317-0057) now run (MAME set names and keys)
- 315-5124 VDP as in MAME: per VDP status, line counter and frame
interrupts (only VDP #1 drives /INT), output levels, per-line CRAM and
scroll latching, front layer backdrop, mode 4 sprites
- Sega PSG clock (10.738635 MHz / 3) and noise
- trackball state saved (Riddle of Pythagoras, Megumi Rescue)
Super Hang-On (outrun.c): backport of MAME segaorun for shangon,
shangon1, shangon2, shangon3, shangon3d, shangonle (FD1089B, memory
mapper, interrupt timing, ADC, YM2151 + SegaPCM).
Enduro Racer (sharrier.c): backport of MAME segahang: FD1089B, both
8255 PPIs (mode 2 sound handshake), ADC0804, sub CPU mirrors, YM2151 and
YM2203 sound boards, Space Harrier sprites and road. Sets enduror,
endurora, endurorb, enduror1, endurobl, endurob2, endurord, enduror1d.
The Hang-On conversions shangonrb and shangonrb2 (old shangonb) use the
same code with the Hang-On main board map.
Sound:
- SegaPCM: register layout as in MAME (current address at 0x84,
loop at 0x04), 7-bit volumes, 8-voice discrete mode, save states;
Super Hang-On PCM pitch fixed
- Seibu sound: latches, IRQ vectors and bank saved (Zero Team save
states, run ahead and netplay now work)
Claude-Session: https://claude.ai/code/session_014P4GcczkZTrzVfrRW8odFY
Co-authored-by: zanac <[email protected]>
Co-authored-by: Claude Opus 5.5 <[email protected]>
- machine/megadriv.c / includes/megadriv.h: the Mega Drive part shared by
the Mega-Tech, Mega Play, bootleg, Y-BOX and Sun Mixing boards (the VDP
interrupts, also used by System C/C2, the sound Z80 and its bus, the I/O,
the machine drivers), moved out of segac2.c; the Mega-Tech / Mega Play
BIOS VDP ports go to megatech.c, its interrupt to megaplay.c; dead code
removed (the unused cart maps, inputs and I/O init)
- segac2.c: only System C/C2, with the sets, ROMs, titles, inputs and DIP
switches of current MAME (57 sets instead of 32; puyopuyo/puyopuya/puyopuyb are now
puyoj/puyoja/puyobl, columns2 and stkclmns (Japan) are now column2j and
stkclmnsj, with the World sets as parents)
- the protection chip as the EPM5032 logic of each game of current MAME
(identical to the old tables where they were real; Ribbit!, Poto Poto and
Puyo Puyo 2 had fake tables and workarounds)
- the alternate palette mode of Ribbit! and Twin Squash (control bit 2),
through palette lookups in the VDP, instead of watching Ribbit! ROM reads
- the 68000 at XL2/6 (8.95 MHz) and the refresh at 59.92 Hz as in current
MAME (it was XL2/7 and 60 Hz); V-INT and H-INT held until the 68000
acknowledges them, as on the board
- YM2612/YM3438 (shared): the busy flag for 192 clocks after a data write,
and a timer started long after its last overflow runs a whole period, as
in current MAME
- Mega Play: the BIOS VDP V-INT about 12 lines after the Mega Drive VBLANK,
as in current MAME (Tecmo World Cup could stay on a black screen)
- Mega Play / System E: the BIOS VDP tile lines read byte by byte (wrong
colours on big-endian hosts)
- the address mirrors, the battery-backed work RAM (0xff filled), the coin
meters on the I/O chip, the Waku Waku Marine / Anpanman wheel
- save states: the alternate palette mode and the Bloxeed YM3438 kludge
- metadata/mame2003-plus.xml, CHANGELOG.md
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
Co-authored-by: Claude <[email protected]>
- mspacman: the mapped ROM (decoded set or boot ROM)
- snk.c: the sound command/busy register, the sprite blink parity, the
tile cache marked dirty after a load
- fmopl.c: the whole YM3812/YM3526/Y8950 state (channels, operators,
envelopes, LFO, noise, timers, status, Delta-T ADPCM); replaces the
register replay of #2045 (3812intf.c back to its earlier version)
- scsp.c: chip registers, slots, LFOs, DSP, timers, MIDI FIFOs, DMA
- model2: which CPU waits on the i960/copro FIFOs, the SCSP IRQ line
- bublbobl: ROM bank, display enable, sound NMI, MCU port latches
- m6800.c: the 6801/6803/63701 internal registers (ports, timer, TCSR,
RAM control, WAI state)
- mb86233.c: the stall flag
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
Co-authored-by: Claude <[email protected]>
The TIME_LOOP_HACKS shortcut skips the iterations of a
DEC rr / LD A,r / OR r / JR NZ (or JP NZ) delay loop by burning their
cycles in one go. Each skipped iteration runs four opcodes (R is
advanced by 4), but only LD, OR and the jump were counted: the DEC was
left out, so every iteration took 6 cycles too few (20 instead of 26
with JR) and such delays ran about 23% short.
Count the DEC as well, for the BC, DE and HL loops with JR and JP.
Co-Authored-By: Claude Opus 5.5 <[email protected]>
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
register_banks() registers the RAM behind every bank that appears in a
memory map. Banks that only ever show up in read maps are ROM (the ST-V
cartridge bank, 48 MB, or the CAGE sound-board ROM banks, 2 + 16 MB),
but they were still copied into every save state, so states were
20-53 MB for those boards, and netplay, rewind and run-ahead keep many
states at once.
Remember whether each bank appears in a write map and skip a bank of
0x100000 bytes or more that never does. RAM banks and smaller banks are
unchanged, so the state layout of other drivers stays the same. An INFO
log line reports each skipped bank.
Co-authored-by: Squirbie <[email protected]>
Co-authored-by: Claude Opus 5.5 <[email protected]>
The H6280 core registered nothing with the save-state system, and the
HuC6270 video chip of the battlera board (VRAM, registers, palette,
scanline/IRQ bookkeeping) and the driver's port select / ADPCM toggle
were not registered either. After a state load the CPU kept running
from its own PC, registers, MMR bank map and timer, and the screen was
drawn from the old VRAM, so netplay guests saw a blank or diverging
screen and rewind / run-ahead diverged.
- h6280.c: register PPC/PC/SP/ZP/EA, A/X/Y/P, the 8 MMR registers, the
IRQ mask, timer status/ack/value/load, extra cycles and the IRQ lines
(plus NZ with LAZY_FLAGS) per CPU in h6280_init(), as m6809_init() does.
- battlera_vidhrdw.c: register VRAM, the 20 VDC registers, the VDC
pointers and flags, last_line (was a function-local static) and the
palette RAM; a postload handler marks everything dirty and rebuilds
the palette.
- battlera.c: register control_port_select, msm5205next and the ADPCM
toggle (was a function-local static) from a new DRIVER_INIT.
Co-authored-by: Squirbie <[email protected]>
Co-authored-by: Claude Opus 5.5 <[email protected]>
Phase 2.4/5 of the Sega VDP / segac2.c clean-up: Puckman Pockimon and the
other Y-BOX games, and Super Bubble Bobble (Sun Mixing), move from
drivers/segac2.c to drivers/megadriv_ybox.c and drivers/megadriv_sunmix.c,
as in current MAME.
- Sets as in current MAME: puckpkmn is the Genie 2000 set of MAME, the old
puckpkmn set is now its clone puckpkmnb; new jingling and topshoot.
xmvsfmb (not working in MAME) is not added: no ROMs.
- The Y-BOX games run on the Mega Drive machine, as MAME's md_ntsc (they
ran on the System C board): 68000, Z80, the YM3438 on the Z80 bus, I/O
(no pads), the RAM mirrors, and the VDP interrupts and HBLANK status as
on the real hardware (genesis_enable_iack). Songjiangyanyi Final waits
on HBLANK to write the scroll of each line: it hung on a grey screen,
it now works (imperfect graphics, as in MAME).
- Songjiangyanyi / Shuihu Feng Yun Zhuan protection as in MAME: two read
back latches selected by A2 (it was a list of fixed addresses), the
0x70001c value per game, the ROM address remapping at 0x600000 of
Shuihu Feng Yun Zhuan (an address XOR while a value is latched: the
data reads through a handler, the opcodes through an opbase handler).
- Jingling Jiazu / Puckman Pockimon: the ID at 0x4b2476 and 0x70001c.
- Top Shooter: the shared RAM inputs of the MCU (not emulated, as in MAME).
- Save states: the protection and remapping state.
- Metadata: mame2003-plus.xml, CHANGELOG.md.
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
Co-authored-by: Claude <[email protected]>
Loading a state, and so every RunAhead or netplay rollback, put back an
incomplete sound chip or CPU, and the game went on differently from the
run that never loaded: the audio of the Mega Drive based boards, Neo Geo
and the YM2203 games diverged, and on the 6809 games the game itself.
OPN chips (sound/fm.c):
- The reset sets the L/R pan of all the channels (0xb4-0xb6) and clears
0x30-0xb2 without storing them in REGS; the postload rewrites REGS, so
a channel the game never panned itself was muted after a load (the DAC
of the Bare Knuckle games). The reset values are now in REGS (YM2203,
YM2608, YM2610, YM2612), and the YM2612 DAC select too.
- The postloads of the YM2608 and YM2610 skipped 0xb6 (pan, AMS, PMS of
the 3rd channel of each bank), as the YM2612 one did before.
- The chip recomputes its phase steps and envelope rates only when a
register asks for it, so they can lag behind the registers (e.g. after
a 3 slot mode change). They are now saved as they are, with the key
codes and the LFO step, instead of being remade from the registers. The
YM2612 and YM2610 extra state is one shared block (OPN_EXT), now also
used by the YM2203, which had none.
- The YM2612 DAC value is saved as it is: before the first write it is 0,
which is not what the register gives (aladmdb).
- YM2610: the extra FM and SSG state was opt-in (only zn.c asked for it);
it is now always saved (Neo Geo). The opt-in FM timers stay as they were.
SSG (sound/ay8910.c): the periods of the SSG of a YM chip are saved as they
were made; the register rewrite of the postload remade them with the
current clock. The YM2203 now saves the SSG extra state too.
MultiPCM (sound/multipcm.c): the sample pointer of a voice was remade from
the registers at load, without the bank and with the sample number of now,
not of the key on; it is saved as its offset in the ROM. The release
counter is saved too (Star Wars Arcade).
6809 family: the M6809 did not save the accumulators (D), the HD6309 D and
W; the M6809, HD6309 and Konami did not save the cycles of an interrupt
taken outside the execute loop.
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
Co-authored-by: Claude <[email protected]>
Phase 2.3/5 of the Sega VDP / segac2.c clean-up: the coin-op bootlegs of
Mega Drive games move from drivers/segac2.c to drivers/megadriv_acbl.c,
with the board variants of current MAME, and the nine new sets we have
the ROMs for are added. The Mega Drive part stays shared with the other
Mega Drive based boards (includes/segac2.h).
- Moved: aladmdb, barek2ch, barek3mb, jparkmb, sonic2mb, sonic3mb,
twinktmb (titles as in current MAME). Same code paths as before: frames
and audio identical to the previous build.
- New: barekch, barek2mb, barek3mba, biohzdmb, bk3ssrmb, mk3mdb, srmdb,
srssf2mb, ssf2mdb.
- The board variants of MAME: the version register, 6 button pads (MAME's
TH counter with the 1.5ms timeout), the 3rd I/O port coins, the DIP
switches at 0x770070 of the scrambled boards (and the coins at 0x770078
of biohzdmb), the 6MB linear map of ssf2mdb, the PIC16C57 of barek2mb (emulated, with its latches; the
68000 byte writes reach both halves of the bus as on the real CPU; T0
is not connected), the simulated PIC of barek3mba.
- The new sets take V-INT / H-INT through the VDP interrupt enables, as on
the real hardware (mk3mdb took a V-INT before its RAM vector was set
and crashed); the moved sets keep the old mode.
- Big-endian hosts: the descrambling of the bootlegs uses BYTE_XOR_LE,
and the PIC program of barek2mb is put in the host order the PIC core
fetches its opcodes in.
- Mega Drive VDP: in H32 mode the sprite table base uses bit 0 of
register 5 (AT9), as on the real VDP and in MAME; it was always masked
as in H40 (ssf2mdb sets 0x6d in H32: the fighters were missing; the sprites
of mt_bbros were garbled).
- PIC16C5x core: the PC wraps at the end of the program memory (the 2K
parts start at 0x7ff and ran past the ROM), and the save states no
longer register the ports and STATUS through R.picRAM before it is set
(a NULL pointer: saving a game with a PIC crashed). They are in the data
RAM, saved with the CPU memory.
- Save states: the pad, frame counter and PIC latch state.
- Metadata: mame2003-plus.xml (the bootleg entries regenerated),
CHANGELOG.md.
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
Co-authored-by: Claude <[email protected]>
Phase 2.2/5 of the Sega VDP / segac2.c clean-up: the Mega-Tech BIOS,
memory maps, inputs, machine drivers, ROMs and game drivers move from
drivers/segac2.c to drivers/megatech.c. The Mega Drive part stays shared
with the other Mega Drive based boards (includes/segac2.h); genesis_base
now starts from the plain cartridge map, each board sets its own.
- Sets, ROM names and dumps as in current MAME (good dumps of mt_bbros,
mt_ggolf, mt_gng and mt_tetri), the instruction ROMs in the cart at
0x300000, titles and years as in current MAME.
- The Master System carts run on the Mega Drive in Mark III mode, as in
current MAME: the 68000 is off, the sound Z80 runs the cart with the
Sega mapper, 8KB of RAM, the PSG and the VDP in mode 4 (the 315-5313
variant of the 315-5124 core of MAME). Astro Warrior, Great Golf,
Shinobi, After Burner and Parlour Games work; Great Soccer is a bad
dump (as in MAME).
- The BIOS cart slots as in current MAME (the CXD1095 port E slot select,
the banked RAM per slot, the 0x6000 bank latch and the 0x8000 window
into the cart): the menu lists the cart in slot 1 only, not in all 8.
- The BIOS display: the 315-5246 224 line mode the menu uses (the MENU
title was cut), drawn line by line, its own palette levels.
- The Mega Drive VDP line timing and partial updates count its own lines
below the BIOS screen (segavdp line_scale; 1 for the other boards).
- The H32 games are centred in the 320 pixel screen.
- Mega Play: the BIOS overlay is transparent on colour 0 of both its
palettes and covers its borders, as in current MAME (the boot logo
screen was behind a green background).
- Crash fix: the 68000 writes to 0xa02000-0xa03fff went to the Mega Play
BIOS RAM pointer, NULL on the other boards (Great Golf crashed). The
Mega Play handler moves to drivers/megaplay.c.
- Save states: the Mega-Tech BIOS, the slots and the Mark III mode state.
- Metadata: mame2003-plus.xml (Mega-Tech entries regenerated), CHANGELOG.md.
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
Co-authored-by: Claude <[email protected]>
Phase 2.1/5 of the Sega VDP / segac2.c clean-up: the Mega Play BIOS, memory
maps, inputs, machine driver, NVRAM, ROMs and game drivers move from
drivers/segac2.c to drivers/megaplay.c. The Mega Drive part (68000, sound
Z80, I/O chip, interrupts, sound interfaces, pads) stays shared with the
other Mega Drive based boards and is declared in includes/segac2.h; the
Mega Play interrupt acknowledge is enabled through genesis_enable_iack().
- Set names as in current MAME: mp_twc is now mp_twcup, the BIOS version 2
ROM is epr-a15294.ic2; new clone mp_gaxe2a (Golden Axe II, original
revision), as in MAME.
- The Mega Play save state registrations move with the BIOS; the unused
BIOS variables (bios_game, bios_6204, bios_6402) are removed.
- Metadata: driver.c, mame2003-plus.xml (Mega Play entries regenerated),
catver.ini, history.dat, CHANGELOG.md.
Claude-Session: https://claude.ai/code/session_01N3fzdsnzkQVtgYtYzqepjX
Co-authored-by: Claude <[email protected]>
