libretro/ppsspp
1
0
Fork 0
mirror of https://github.com/libretro/ppsspp.git synced 2024-12-15 04:58:35 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
6,030 Commits 19 Branches 54 Tags 247 MiB
654490566f
Commit Graph

66 Commits

Author SHA1 Message Date
Unknown W. Brackets
e27ab6fa11 Add swl/swr to the x86 jit. 2013-07-04 17:34:56 -07:00
Unknown W. Brackets
203daf955b Implement lwl/lwr in the x86 jit. 2013-07-04 17:30:36 -07:00
Unknown W. Brackets
2d25d1eb05 Add a way to force alignment in JitSafeMem(). 2013-07-04 15:59:12 -07:00
Unknown W. Brackets
609f8d6340 Allow hitting Go on a breakpoint to continue. 
Doesn't work for branches though, because of delay slots.
 2013-06-29 11:23:24 -07:00
Henrik Rydgard
ce2c18d2fe Remove redundant vmov instructions (seen in wipeout) 2013-06-15 00:19:48 +02:00
Sacha
a26b48fc0b Stub wsbh/wsbw for x86. 2013-06-05 14:55:01 +10:00
Henrik Rydgard
1a1c161a0d Implement vmin/vmax in x86 jit, slots right into VecDo3 2013-04-27 20:52:42 +02:00
Henrik Rydgard
6f4ad05582 Remove some unused code, add some stubs to vfpu jit, some cleanup 2013-04-27 19:35:42 +02:00
Henrik Rydgard
9eace8a80e Combine the two JitCache implementations (x86, ARM) into one. 2013-04-27 01:32:03 +02:00
Unknown W. Brackets
3bb5651ca7 Initial x86 jit for vtfm/vhtfm. 2013-04-20 01:52:06 -07:00
Unknown W. Brackets
9245490b53 Initial / simple vmscl for x86 jit. 2013-04-20 01:34:16 -07:00
Unknown W. Brackets
29109d25af Non-optimal vmmul for x86 jit. 
It's faster than interpreter anyway, but it could be much better.
 2013-04-20 01:15:15 -07:00
Unknown W. Brackets
cfac7324d6 Implement vscl in the x86 jit. 2013-04-20 01:15:14 -07:00
Unknown W. Brackets
d051ea3106 Flush when checking for memcheck coreStates. 
Trouble is this has to be done outside the lock.  So, moved out.
 2013-03-09 02:41:50 -08:00
Unknown W. Brackets
d10bdd6938 Basic working imm mem breakpoints in x86 jit. 
Seems to work okay.  Doen't cover HLE of course.
 2013-03-09 02:41:48 -08:00
Unknown W. Brackets
6290b67984 Validate the full memory access is valid. 
Probably barely matters, but since we have the size now anyway...
 2013-03-09 02:41:47 -08:00
Unknown W. Brackets
2d6a730cac Add some basics for memory checks to x86 jit. 
Specifically, we will need to be able to bail in delayslots,
and we will need to know the size of the access (useful anyway.)
 2013-03-09 02:41:46 -08:00
Unknown W. Brackets
c4ab0855b4 Make sure interpreter and jit savestates match. 2013-03-08 08:49:21 -08:00
Unknown W. Brackets
313ffdb495 Add a stub for clz/clo in x86 jit. 2013-02-21 01:25:02 -08:00
Unknown W. Brackets
2db368c29a Add more imm handling for shifts in x86 jit. 
This is actually hit, and propagates more imms through.
 2013-02-21 01:25:00 -08:00
Unknown W. Brackets
a438791e7c Initial (very inefficient) vmmov for x86 jit. 
This makes #464 work (at least LittleBigPlanet), but only in x86 jit.
 2013-02-18 23:21:18 -08:00
Unknown W. Brackets
b8e2177591 Jit vzero/vone, which are easy and common (x86.) 2013-02-18 22:15:47 -08:00
Unknown W. Brackets
2dfdf3ffeb Implement Comp_VV2Op vfpu ops in the x86 jit. 
Also, some cleanup.  No need for this extra boilerplate, simplify...

This makes the Bink video issue slightly better, in jit only.
 2013-02-18 20:43:28 -08:00
Unknown W. Brackets
afb7c0b83c Assume prefixes start default until proven wrong. 
Currently this means nothing since the MIPSTables flags are wrong.
It will blow the cache once, after the first vfpu op.
 2013-02-18 01:14:57 -08:00
Unknown W. Brackets
8ea59990ab Make applying prefixes mostly automatic. 
And implement (hopefully) D prefixes.
 2013-02-18 00:11:57 -08:00
Unknown W. Brackets
27942606ad Use prefixD directly in jit, just like interp now. 2013-02-17 22:46:34 -08:00
Unknown W. Brackets
08a42a1aaf Preserve orig regs when applying vfpu prefixes. 2013-02-17 22:37:56 -08:00
Unknown W. Brackets
f532951331 Automatically eat prefixes in x86 jit. 
Simplifies the code and makes it easier to know they're eaten
even for ops not yet jitted.
 2013-02-17 17:53:53 -08:00
Unknown W. Brackets
2b441f1638 Initial implementation of jit vadd/vsub/vdiv/vmul. 2013-02-15 08:35:34 -08:00
Unknown W. Brackets
b9506c9568 Minor cleanup for vdot in x86 jit. 2013-02-15 08:35:34 -08:00
Unknown W. Brackets
ccad259ae5 Keep track of VFPU prefixes and flush them in jit. 2013-02-15 08:35:33 -08:00
Unknown W. Brackets
4eca76e0cc Check for s/t/d prefix reg changes in jit. 2013-02-14 00:27:09 -08:00
Unknown W. Brackets
19cc652a37 Correct NaN handling in fpu comparisons. 2013-02-13 01:54:07 -08:00
Henrik Rydgard
78923f5538 Jit a little more (vfpu single load/store, transfer instructions) 2013-02-10 12:14:55 +01:00
Unknown W. Brackets
f777c872e6 Jit unaligned reads/writes. 
This mostly just improves perf on debug, not really on the map for release.
 2013-02-02 13:12:34 -08:00
Unknown W. Brackets
44b5adeaac Properly jit the break instruction. 
Otherwise, it just keeps on going past it.
We never want to hit this anyway, but it's good to know if we do.
 2013-02-01 00:49:14 -08:00
Henrik Rydgard
90b11bba37 Implement mult, multu, mflo/hi, mtlo/hi in x86 JIT 2013-01-29 00:48:42 +01:00
Unknown W. Brackets
a7b5433ba7 Make sure fastmem isn't confused by rs changing. 2013-01-26 23:18:50 -08:00
Unknown W. Brackets
a89d61463e Make the VFPU jit use far jumps for memory access. 2013-01-26 23:08:19 -08:00
Unknown W. Brackets
0e8e9697c5 Add lv.q/sv.q support to the x86 jit. 2013-01-26 10:09:18 -08:00
Unknown W. Brackets
b77ce99d01 Oops, no slow read for immediates usually. 2013-01-26 09:27:52 -08:00
Unknown W. Brackets
9cd5836b85 Rename WriteFinish() to Finish() is safe mem. 
It's nothing to do with writing.
 2013-01-26 09:09:47 -08:00
Unknown W. Brackets
3e419f513a Refactor jit safe memory reads without dup code. 
But, maybe too automagical...
 2013-01-26 08:42:34 -08:00
Henrik Rydgard
2738417040 VFPU JIT: start setting up infrastructure. very incomplete. vdot works if undisabled, but isn't complete. 2013-01-26 01:34:19 +01:00
Henrik Rydgard
68991511ee Split out the FPU reg cache into its own file too. 2013-01-26 01:34:19 +01:00
Henrik Rydgard
aabc0aa9ef Quick implementation of LV.Q and SV.Q in x86/x64 JIT 2013-01-25 19:50:30 +01:00
Henrik Rydgård
0f080aeaaa Merge pull request #492 from unknownbrackets/jit-minor 
ALU jit optimizations
 2013-01-25 01:01:34 -08:00
Unknown W. Brackets
ab9bea068c Jit reg+reg compile time, and avoid flushing EDX. 2013-01-25 00:16:55 -08:00
Unknown W. Brackets
2eba209f64 Move around the jit nice delay slot logic. 
Nice delay slots don't not save flags, they run before the CMP.
 2013-01-24 07:31:51 -08:00
Unknown W. Brackets
c324983340 Make the jit support bltzal and friends. 
Fixes problems with jit in games.  Android changes completely untested.
 2013-01-22 08:04:01 -08:00