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10,490 Commits 19 Branches 54 Tags 247 MiB
95881bdaac
Commit Graph

914 Commits

Author SHA1 Message Date
Sacha
95881bdaac Blackberry: Add simulator support. 2013-11-26 12:18:34 +10:00
Henrik Rydgard
e5e23f3ce1 ARM: Fix vsgn. Some vertex decoder tweaks. 2013-11-24 18:21:47 +01:00
Henrik Rydgard
030e6460cc ARM: NEON-optimize software skinning 2013-11-24 18:03:42 +01:00
Henrik Rydgard
f650b23c90 ARM: Add NEON widening and narrowing moves, and float/int convert. 
Experiment a little in the vertex decoder.
 2013-11-24 13:30:28 +01:00
Henrik Rydgard
db016f7001 ARMJIT: Disable vsgn, reported to break Miami Vice 2013-11-23 13:00:35 +01:00
Unknown W. Brackets
c50ab6d6aa armjit: Fix divu when divisor is a constant 1. 
Fixes #4539 and #4520.
 2013-11-19 13:24:15 -08:00
Henrik Rydgard
bd3a03ad1d Quick buildfix. Last commit was meant to go on a WIP branch but meh :) 2013-11-19 21:44:18 +01:00
Henrik Rydgard
ab3037112f Some scaffolding for a future VFPU-on-NEON implementation 2013-11-19 21:41:48 +01:00
Henrik Rydgard
99af10cb09 Get rid of bool disablePrefixes in ARM build (already gone in x86) 2013-11-19 21:41:48 +01:00
Henrik Rydgard
dca457e6df Optimize multiple sv.s and lv.s calls on ARM. Also some cleanup. 2013-11-19 21:41:47 +01:00
Henrik Rydgard
5bb3824dcf Implement vocp on ARM and x86. 2013-11-19 21:41:47 +01:00
Sacha
a41e3d3432 Qt: Remove controls. Undefine emit so that it is easier to use Qt headers in native files. 2013-11-20 01:25:59 +10:00
Henrik Rydgard
9f5402ce54 Use hardware half-to-float on ARM when available. 2013-11-17 14:17:13 +01:00
Unknown W. Brackets
5f3d7d5c97 Add support for fpu and vfpu regs in expressions. 
This way you can break based on the value.
 2013-11-17 02:15:15 -08:00
Kingcom
c44c99a5b7 Ignore changes to r0 2013-11-16 10:59:49 +01:00
Kingcom
a277706489 Workaround for symbols defined in .sym files 2013-11-16 10:53:47 +01:00
Henrik Rydgard
4e0520131a Tiny optimization 2013-11-15 20:32:23 +01:00
Henrik Rydgard
d17a5fefea ARM: Fix divide by 0 in software divide used on CPUs without HW divide. 2013-11-15 20:24:20 +01:00
Unknown W. Brackets
f165a15eff Fix a -unsigned warning. 
Looks ugly, but (u32)-(s32)val is what we really want here.

Also make a __FUNCTION__ redeclaration warning go away.
 2013-11-15 08:18:34 -08:00
Unknown W. Brackets
5128083d93 Mask out fcr31 bits that can't be set on a PSP. 2013-11-14 23:57:28 -08:00
Unknown W. Brackets
3c73d0d1f1 armjit: Read fpu control regs other than 0/31 as 0. 
Always seem to give zero, regardless of the value of fcr31, etc.
 2013-11-14 23:39:39 -08:00
Unknown W. Brackets
763eff181d Fix handling of jalr when delay slot changes rd. 2013-11-14 23:39:13 -08:00
Unknown W. Brackets
26f5922174 Return the correct value for fcr0/fir. 
This is what the PSP actually returns, it's read only.
 2013-11-14 23:39:08 -08:00
Unknown W. Brackets
98fb2e0402 armjit: Refer to R11 as MEMBASEREG for clarity. 2013-11-14 23:37:48 -08:00
Sacha
e3bdb3e09b Disable LitPool as it is causing crashes with Vertex Decoder JIT. Performance seems to be almost unaffected since the IMM changes. 2013-11-15 14:12:00 +10:00
Sacha
20e8a81268 Switch to compile-time ARMV7 define. 2013-11-15 11:20:39 +10:00
Henrik Rydgard
9a14d33372 Disable software divide that appears to be buggy, see #4539 2013-11-14 17:25:02 +01:00
Henrik Rydgård
ef8631c57f Cache VFPU_CTRL_CC in a register 2013-11-12 17:58:29 +01:00
Henrik Rydgard
df3765a320 Arm jit: optimize ES, NS conditions in vcmp. Bugfix TR. 2013-11-12 14:43:12 +01:00
Henrik Rydgard
a2e0a4d9bf x86 jit: Optimize ES, NS (is-nan-or-inf) conditions in vcmp 2013-11-12 14:07:48 +01:00
Henrik Rydgard
84f20a1cad Small optimizations 2013-11-12 14:05:50 +01:00
Unknown W. Brackets
f4b5e8a4c1 Merge pull request #4518 from hrydgard/fpcond 
ARMJIT: Cache fpcond in a register to avoid store/load between compare and branch
 2013-11-12 01:50:16 -08:00
Henrik Rydgård
17074f5a7f Cache fpcond in a register to avoid store/load between compare and branch 2013-11-12 10:33:38 +01:00
Unknown W. Brackets
a334aaf6ca x86jit: Refactor and skip flushes in branch cont. 
Still not faster, but at least the code isn't as messy.
 2013-11-12 00:45:28 -08:00
Unknown W. Brackets
32504ed46e armjit: Prioritize spilling regs not used soon. 
This may improve trashing.
 2013-11-12 00:03:39 -08:00
Unknown W. Brackets
1bfce12fdd armjit: Report some unexpected situations. 2013-11-11 23:41:18 -08:00
Unknown W. Brackets
ac5aacbd16 armjit: Spill an imm armreg back to an imm. 
We might be able to avoid the store or etc.
 2013-11-11 23:39:13 -08:00
Unknown W. Brackets
7e19933f64 x86jit: Try predicting branch continues. 
Still doesn't seem to work.  Something like a 4% gain in Star Ocean was
the best I saw...
 2013-11-10 22:50:23 -08:00
Unknown W. Brackets
bb960480c8 x86/armjit: Stop compiling on a jump to invalid. 2013-11-10 21:59:50 -08:00
Unknown W. Brackets
fd38b10ab6 x86jit: Rename imm funcs to match armjit. 2013-11-10 21:59:49 -08:00
Unknown W. Brackets
359110f010 x86/armjit: Add jump following (off by default.) 
Inlines function calls up to a certain extent.  Allows us to get
immediates all the way to a syscall, for example, usually.

Not sure if faster.
 2013-11-10 21:59:49 -08:00
Unknown W. Brackets
aacb31bc18 armjit: Copy over (disabled) immbranch optim. 
This does a little loop unrolling.  Costs a bit more cache space, but
avoids flushing regs for longer.

Not enabled.
 2013-11-10 21:59:48 -08:00
Unknown W. Brackets
92ecff4396 armjit: keep track of instructions in jitstate. 
To match x86.
 2013-11-10 21:59:48 -08:00
Unknown W. Brackets
8ceaafc159 armjit: Verify free space while compiling. 2013-11-10 21:59:48 -08:00
Unknown W. Brackets
ca7b2b554b armjit: fix major typo breaking mult/multu. 2013-11-10 21:54:44 -08:00
Unknown W. Brackets
e1fffdb37a armjit: Don't reload an armreg ptr marked noinit. 2013-11-10 16:43:38 -08:00
Unknown W. Brackets
67eaa2fd1c armjit: Optimize immediate load/stores in a row. 2013-11-10 16:32:48 -08:00
Unknown W. Brackets
bc0a846475 armjit: Optimize imm addresses (could do better...) 2013-11-10 16:30:20 -08:00
Unknown W. Brackets
c63560c0dd armjit: Try to find imms to optimize a reg load. 
This way we skip the MOVW/MOVT and go for one op only.
 2013-11-10 16:20:34 -08:00
Unknown W. Brackets
7e46ee0b0f armjit: Replace MOVI2R with using the regcache. 
So that it can optimize the value with existing imms.

Not actually optimizing yet.
 2013-11-10 15:50:45 -08:00