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7,638 Commits 19 Branches 54 Tags 247 MiB
97aa1a631e
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81 Commits

Author SHA1 Message Date
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97aa1a631e Improve typesafety in the x86 regalloc. 2013-08-24 19:41:10 -07:00
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6c97b66806 Cap imm branch instructions, reset compiling. 
Break and other delay slot ops could've set it to false.

It's actually sometimes faster now.
 2013-08-24 17:26:24 -07:00
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109ad17ac6 Use a typesafe struct for opcodes. 
Also, correctly read delayslots using Read_Instruction on ARM.
 2013-08-24 15:36:24 -07:00
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df32c99be6 Attempt to follow branches to a max # of ops. 
Seems to make it slower also.  Maybe taking the branch would be better...
hmmph.
 2013-08-16 01:07:11 -07:00
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defd2b6383 Attempt at doing branches with imm args. 2013-08-16 01:05:52 -07:00
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6b0b5145e5 Clean up some inconsistency in jit branches. 2013-08-16 00:44:23 -07:00
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64c2ea86c0 Add a method to save the gpr/fpr state in jit. 2013-08-16 00:12:49 -07:00
Henrik Rydgard
4e8958f42d A small optimization, a few jit stubs, and cross/quat product on x86. 2013-08-01 00:15:08 +02:00
Henrik Rydgard
0a8f85a919 Some JIT cleanup, implement VI2F on ARM. also disabled untested impl of viim for x86. 2013-07-31 17:27:04 +02:00
Henrik Rydgard
51596b636a Fix numerous ARM JIT bugs. Activate vmtvc and vscl, and vadd/vmul/vdiv/vsub for real this time. 2013-07-31 10:34:58 +02:00
Henrik Rydgard
d8294f025f More VFPU stuff (nothing new activated) 2013-07-30 01:09:11 +02:00
Henrik Rydgard
8feeaf2e7a Jit: Implement vidt in both, plus translate a couple easy ones to ARM. 2013-07-28 16:14:21 +02:00
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2d15eb2acd Re-enable lwl/lwr/swl/swr on the x86 jit. 
Now correctly handling ECX on x64.
 2013-07-06 01:21:52 -07:00
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662ae77214 Save regs before/after 3-arg func calls on x86. 
This fixes bugs only on x64 when ABI_CallFunctionACC and etc. were used.
This was breaking things since R8 was not being saved (arg 3.)
 2013-07-06 00:54:53 -07:00
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d823989330 Implement vmone/vmzero/vmidt for the x86 jit. 2013-07-04 18:16:57 -07:00
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e27ab6fa11 Add swl/swr to the x86 jit. 2013-07-04 17:34:56 -07:00
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203daf955b Implement lwl/lwr in the x86 jit. 2013-07-04 17:30:36 -07:00
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2d25d1eb05 Add a way to force alignment in JitSafeMem(). 2013-07-04 15:59:12 -07:00
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609f8d6340 Allow hitting Go on a breakpoint to continue. 
Doesn't work for branches though, because of delay slots.
 2013-06-29 11:23:24 -07:00
Henrik Rydgard
ce2c18d2fe Remove redundant vmov instructions (seen in wipeout) 2013-06-15 00:19:48 +02:00
Sacha
a26b48fc0b Stub wsbh/wsbw for x86. 2013-06-05 14:55:01 +10:00
Henrik Rydgard
1a1c161a0d Implement vmin/vmax in x86 jit, slots right into VecDo3 2013-04-27 20:52:42 +02:00
Henrik Rydgard
6f4ad05582 Remove some unused code, add some stubs to vfpu jit, some cleanup 2013-04-27 19:35:42 +02:00
Henrik Rydgard
9eace8a80e Combine the two JitCache implementations (x86, ARM) into one. 2013-04-27 01:32:03 +02:00
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3bb5651ca7 Initial x86 jit for vtfm/vhtfm. 2013-04-20 01:52:06 -07:00
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9245490b53 Initial / simple vmscl for x86 jit. 2013-04-20 01:34:16 -07:00
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29109d25af Non-optimal vmmul for x86 jit. 
It's faster than interpreter anyway, but it could be much better.
 2013-04-20 01:15:15 -07:00
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cfac7324d6 Implement vscl in the x86 jit. 2013-04-20 01:15:14 -07:00
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d051ea3106 Flush when checking for memcheck coreStates. 
Trouble is this has to be done outside the lock.  So, moved out.
 2013-03-09 02:41:50 -08:00
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d10bdd6938 Basic working imm mem breakpoints in x86 jit. 
Seems to work okay.  Doen't cover HLE of course.
 2013-03-09 02:41:48 -08:00
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6290b67984 Validate the full memory access is valid. 
Probably barely matters, but since we have the size now anyway...
 2013-03-09 02:41:47 -08:00
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2d6a730cac Add some basics for memory checks to x86 jit. 
Specifically, we will need to be able to bail in delayslots,
and we will need to know the size of the access (useful anyway.)
 2013-03-09 02:41:46 -08:00
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c4ab0855b4 Make sure interpreter and jit savestates match. 2013-03-08 08:49:21 -08:00
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313ffdb495 Add a stub for clz/clo in x86 jit. 2013-02-21 01:25:02 -08:00
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2db368c29a Add more imm handling for shifts in x86 jit. 
This is actually hit, and propagates more imms through.
 2013-02-21 01:25:00 -08:00
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a438791e7c Initial (very inefficient) vmmov for x86 jit. 
This makes #464 work (at least LittleBigPlanet), but only in x86 jit.
 2013-02-18 23:21:18 -08:00
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b8e2177591 Jit vzero/vone, which are easy and common (x86.) 2013-02-18 22:15:47 -08:00
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2dfdf3ffeb Implement Comp_VV2Op vfpu ops in the x86 jit. 
Also, some cleanup.  No need for this extra boilerplate, simplify...

This makes the Bink video issue slightly better, in jit only.
 2013-02-18 20:43:28 -08:00
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afb7c0b83c Assume prefixes start default until proven wrong. 
Currently this means nothing since the MIPSTables flags are wrong.
It will blow the cache once, after the first vfpu op.
 2013-02-18 01:14:57 -08:00
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8ea59990ab Make applying prefixes mostly automatic. 
And implement (hopefully) D prefixes.
 2013-02-18 00:11:57 -08:00
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27942606ad Use prefixD directly in jit, just like interp now. 2013-02-17 22:46:34 -08:00
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08a42a1aaf Preserve orig regs when applying vfpu prefixes. 2013-02-17 22:37:56 -08:00
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f532951331 Automatically eat prefixes in x86 jit. 
Simplifies the code and makes it easier to know they're eaten
even for ops not yet jitted.
 2013-02-17 17:53:53 -08:00
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2b441f1638 Initial implementation of jit vadd/vsub/vdiv/vmul. 2013-02-15 08:35:34 -08:00
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b9506c9568 Minor cleanup for vdot in x86 jit. 2013-02-15 08:35:34 -08:00
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ccad259ae5 Keep track of VFPU prefixes and flush them in jit. 2013-02-15 08:35:33 -08:00
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4eca76e0cc Check for s/t/d prefix reg changes in jit. 2013-02-14 00:27:09 -08:00
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19cc652a37 Correct NaN handling in fpu comparisons. 2013-02-13 01:54:07 -08:00
Henrik Rydgard
78923f5538 Jit a little more (vfpu single load/store, transfer instructions) 2013-02-10 12:14:55 +01:00
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f777c872e6 Jit unaligned reads/writes. 
This mostly just improves perf on debug, not really on the map for release.
 2013-02-02 13:12:34 -08:00