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460 Commits

Author SHA1 Message Date
Unknown W. Brackets
ead6983ad2 Don't lock armjit memory before aligning code. 2013-03-14 01:16:28 -07:00
Sacha
f88bf8bbff Attempt at fixing JIT on iOS. Can only have PROT_WRITE or PROT_EXEC enabled. So toggle between them as needed. 2013-03-14 14:40:01 +10:00
Sacha
529803e429 Sonic's ArmEmitter changes (cross-project merge from Dolphin) 2013-03-14 12:47:29 +10:00
Unknown W. Brackets
243c8c7a34 Clean up disasm immediates. 
They were still a bit wrong.
 2013-03-11 23:45:29 -07:00
Unknown W. Brackets
f7e476e72e Correct sign in disasm for immediates. 
Fixes #943.
 2013-03-11 08:55:33 -07:00
Unknown W. Brackets
ed76563973 Don't bother checking nice, just do it after. 2013-03-11 02:18:27 -07:00
Unknown W. Brackets
b5fe67eb3d If the out is RA, delay slot isn't nice for jal. 
Fixes Phantasy Star Portable 2 in jit.
 2013-03-11 02:14:38 -07:00
Henrik Rydgård
11c730890e Merge pull request #927 from hrydgard/armjit-opt 
ARMJIT: Optimize some common ops for immediates
 2013-03-10 00:30:14 -08:00
xsacha
1871c4e8bd Merge pull request #900 from xsacha/master 
Rounding Mode Handling
 2013-03-09 20:30:39 -08:00
Sacha
ac3f3099e1 Fix the conditional rounding for round to zero. Implement ctc1, cfc1. 2013-03-10 11:25:24 +10:00
Henrik Rydgard
216dc7ad65 Optimize some common ops for immediates 2013-03-10 00:48:44 +01:00
Unknown W. Brackets
a589361b82 Call GEtImm() before Map* in case of overlap. 2013-03-09 14:39:17 -08:00
Henrik Rydgård
b77d965e56 Merge pull request #917 from unknownbrackets/jit-memcheck 
Memory breakpoints (jit x86 only)
 2013-03-09 13:55:05 -08:00
Unknown W. Brackets
9100c4a5a2 armjit: Don't MapReg before checking for IsImm(). 2013-03-09 11:57:02 -08:00
Unknown W. Brackets
9cf2bcd06c Fix register memcheck to respect offset. 2013-03-09 09:01:23 -08:00
Unknown W. Brackets
d051ea3106 Flush when checking for memcheck coreStates. 
Trouble is this has to be done outside the lock.  So, moved out.
 2013-03-09 02:41:50 -08:00
Unknown W. Brackets
a926ef6776 Respect read/write only mem breakpoints in x86 jit. 2013-03-09 02:41:49 -08:00
Unknown W. Brackets
15ff927d4d And now the dynamic memory breakpoints in x86 jit. 
And add notes that this is interpreter/HLE only for now.
 2013-03-09 02:41:49 -08:00
Unknown W. Brackets
68aaac25c6 Use unsigned compares in slowmem x86 jit. 2013-03-09 02:41:48 -08:00
Unknown W. Brackets
d10bdd6938 Basic working imm mem breakpoints in x86 jit. 
Seems to work okay.  Doen't cover HLE of course.
 2013-03-09 02:41:48 -08:00
Unknown W. Brackets
6290b67984 Validate the full memory access is valid. 
Probably barely matters, but since we have the size now anyway...
 2013-03-09 02:41:47 -08:00
Unknown W. Brackets
4908fb8046 Don't trip in a delay slot for bad mem access. 
Could've done some tricky things... we don't jump correctly then.
 2013-03-09 02:41:47 -08:00
Unknown W. Brackets
2d6a730cac Add some basics for memory checks to x86 jit. 
Specifically, we will need to be able to bail in delayslots,
and we will need to know the size of the access (useful anyway.)
 2013-03-09 02:41:46 -08:00
Unknown W. Brackets
c4ab0855b4 Make sure interpreter and jit savestates match. 2013-03-08 08:49:21 -08:00
Sacha
7782be9a3e Try software rounding mode instead. Use conditionals for VFP functions. Note: Round to Zero not working for some reason? 2013-03-08 22:39:34 +10:00
Sacha
fbef590bed Add emitters for VMRS/VMSR. Undisable ceil, which works. Add stub for rounding mode handling. 2013-03-08 22:39:34 +10:00
Sacha
6adb6762f2 Enable instructions: ceil, ins (confirmed working). Buildfix for Qt platforms. 2013-03-08 12:36:04 +10:00
xsacha
9973f0456b Merge pull request #897 from unknownbrackets/jit-minor 
Some armjit sync
 2013-03-07 18:18:13 -08:00
Sacha
cc65b0add9 Fix rounding. Was disabling wrong rounding mode. Previous one wasn't merge-ready but should be OK now. Only tests that fail are VFPU now. 2013-03-07 22:34:20 +10:00
Sacha
b9ec281c55 Disable rounding methods that aren't working in hardware. Add some notes. Fix compare fall-through and choose right round method. 2013-03-07 21:33:30 +10:00
Unknown W. Brackets
cea396e901 armjit: Don't use R1 in the regcache. 
This way it can be used in swl/swr/ins as a temp reg.
Note: those instructions are currently DISABLEd, though.
 2013-03-07 02:09:13 -08:00
Unknown W. Brackets
925e4e42bd armjit: Disable ext for now, breaks Disgaea? 2013-03-07 02:08:45 -08:00
Unknown W. Brackets
d525abbcad Cleanup some indentation, more compares to 0. 2013-03-07 02:08:45 -08:00
Unknown W. Brackets
028e85dc92 Cleanup some differences between the two jits. 2013-03-07 02:08:44 -08:00
Unknown W. Brackets
669600bd8a Minor cleanup. 2013-03-07 02:08:44 -08:00
Sacha
2a9074d92f Fix FPU comp UEQ case. 2013-03-07 14:46:11 +10:00
Henrik Rydgard
6702f0c78c Tiny optimization and bugfix 2013-03-07 00:47:48 +01:00
Henrik Rydgard
963a6603fc Fix two armjit bugs the testrunner found. 2013-03-07 00:37:00 +01:00
Henrik Rydgard
a69b09a831 More work on TestRunner, now runs all the CPU tests. 2013-03-07 00:22:39 +01:00
Sacha
94a11ef3c0 Armjit: Implement movn, movz 2013-03-07 04:11:48 +10:00
Sacha
87de6be239 Fix the shift regs in ARM JIT that were causing graphical issues in some games. Set avoidload flag. 2013-03-07 02:39:28 +10:00
Sacha
d77632bfb0 Fix literal pools on games with very large code blocks (eg. Zero no Kieski). 
Was flushing after an offset of 4088 which did not take in to account that a single MIPS instruction can turn in to numerous ARM instructions. Chose a safer value of 4020.
Was insta-flushing after reaching this offset value. Some code blocks are over 8K in size. Use a partialFlushOffset to keep track of when the next flush is required.
Was protecting flush branch manually. Can use B_CC(CC_AL) for this instead.
 2013-03-07 02:25:27 +10:00
Sacha
8125d96ce1 Small update for shifted load/stores. Still disabled. 2013-03-07 01:04:41 +10:00
Sacha
a8b6fca61b Separate codepaths for shifted load/stores and normal load/stores. Fix dirty regs. 2013-03-07 00:59:07 +10:00
Sacha
ae3b881a7f Use correct args for Operand2(..) through armjit. Fix STR(..). 2013-03-07 00:59:07 +10:00
Sacha
268d16bd24 Use correct args for STR(..) throughout armjit. 2013-03-07 00:59:07 +10:00
Sacha
23fb88c5fe Enable optimisation codepath (left+right combines). 2013-03-07 00:59:07 +10:00
Henrik Rydgard
9f327985fc armjit: disable lwl/lwr/swl/swr 2013-03-05 23:09:26 +01:00
Sacha
5a134243a7 Armjit: Fix lwl, lwr and enable again. Thanks Sonic. 2013-03-06 03:28:28 +10:00
Sacha
7e67de3334 Armjit: Implement lwl, lwr, swl, swr in ARM JIT. lwr is currently disabled as it isn't working. 2013-03-06 02:11:36 +10:00