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decoder: Add ARM specification docs
Signed-off-by: Ronald Caesar <github43132@proton.me>
This commit is contained in:
Ronald Caesar
@@ -0,0 +1,539 @@
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<title>Sheet.18</title>
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<title>Signal 0.125</title>
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<title>Sheet.34</title>
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<title>Sheet.37</title>
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<title>Sheet.38</title>
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<title>Sheet.39</title>
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<desc>56</desc>
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<title>Sheet.45</title>
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<v:textRect cx="8.5037" cy="86.0393" width="17.01" height="11.3386"/>
|
||||
<rect x="0" y="80.37" width="17.0079" height="11.3386" class="st6"/>
|
||||
<text x="5.22" y="88.44" class="st3" v:langID="1033"><v:paragraph v:horizAlign="2"/><v:tabList/>Vd</text> </g>
|
||||
<g id="shape40-187" v:mID="40" v:groupContext="shape" transform="translate(227.272,-0.499999)">
|
||||
<title>Sheet.40</title>
|
||||
<desc>Vd</desc>
|
||||
<v:userDefs/>
|
||||
<v:textBlock v:margins="rect(0.999998,2,0.999998,0)" v:tabSpace="42.5196"/>
|
||||
<v:textRect cx="8.5037" cy="86.0393" width="17.01" height="11.3386"/>
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<rect x="0" y="80.37" width="17.0079" height="11.3386" class="st6"/>
|
||||
<text x="5.22" y="88.44" class="st3" v:langID="1033"><v:paragraph v:horizAlign="2"/><v:tabList/>Vd</text> </g>
|
||||
</g>
|
||||
</svg>
|
||||
|
After Width: | Height: | Size: 26 KiB |
158
spec/arm64_xml/abs.xml
Normal file
158
spec/arm64_xml/abs.xml
Normal file
@@ -0,0 +1,158 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ABS" title="ABS -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ABS" />
|
||||
</docvars>
|
||||
<heading>ABS</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Absolute value</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Absolute value computes the absolute value of the signed integer value in the source register, and writes the result to the destination register.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Integer" oneof="1" id="iclass_general" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ABS" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="ARMv8.9" feature="FEAT_CSSC" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/unary/abs">
|
||||
<box hibit="31" name="sf" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="30" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="29" name="S" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="8" settings="8">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="opcode2" settings="5">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="6" name="opcode" settings="6">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ABS_32_dp_1src" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ABS" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>ABS </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn" hover="32-bit general-purpose source register (field "Rn")"><Wn></a></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="ABS_64_dp_1src" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ABS" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>ABS </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn" hover="64-bit general-purpose source register (field "Rn")"><Xn></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/unary/abs" mylink="aarch64.instrs.integer.arithmetic.unary.abs" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveCSSC.0" file="shared_pseudocode.xml" hover="function: boolean HaveCSSC()">HaveCSSC</a>() then UNDEFINED;
|
||||
integer datasize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sf);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ABS_32_dp_1src" symboldefcount="1">
|
||||
<symbol link="sa_wd"><Wd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ABS_32_dp_1src" symboldefcount="1">
|
||||
<symbol link="sa_wn"><Wn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ABS_64_dp_1src" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ABS_64_dp_1src" symboldefcount="1">
|
||||
<symbol link="sa_xn"><Xn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/unary/abs" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) operand1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, datasize];
|
||||
integer result = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(<a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(operand1));
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result<datasize-1:0>;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
328
spec/arm64_xml/abs_advsimd.xml
Normal file
328
spec/arm64_xml/abs_advsimd.xml
Normal file
@@ -0,0 +1,328 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ABS_advsimd" title="ABS -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ABS" />
|
||||
</docvars>
|
||||
<heading>ABS</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Absolute value (vector)</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.</para>
|
||||
<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<classesintro count="2">
|
||||
<txt>It has encodings from 2 classes:</txt>
|
||||
<a href="#iclass_sisd">Scalar</a>
|
||||
<txt> and </txt>
|
||||
<a href="#iclass_simd">Vector</a>
|
||||
</classesintro>
|
||||
<iclass name="Scalar" oneof="2" id="iclass_sisd" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="advsimd-type" value="sisd" />
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ABS" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/unary/diff-neg/int/sisd" tworows="1">
|
||||
<box hibit="31" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="29" name="U" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" width="5" name="opcode" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="11" width="2" settings="2">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ABS_asisdmisc_R" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="advsimd-type" value="sisd" />
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ABS" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ABS </text><a link="sa_v" hover="Width specifier (field "size") [D]"><V></a><a link="sa_d" hover="SIMD&FP destination register number (field "Rd")"><d></a><text>, </text><a link="sa_v" hover="Width specifier (field "size") [D]"><V></a><a link="sa_n" hover="SIMD&FP source register number (field "Rn")"><n></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/arithmetic/unary/diff-neg/int/sisd" mylink="aarch64.instrs.vector.arithmetic.unary.diff-neg.int.sisd" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
|
||||
if size != '11' then UNDEFINED;
|
||||
integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer datasize = esize;
|
||||
integer elements = 1;
|
||||
boolean neg = (U == '1');</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
<iclass name="Vector" oneof="2" id="iclass_simd" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="advsimd-type" value="simd" />
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ABS" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/unary/diff-neg/int/simd" tworows="1">
|
||||
<box hibit="31" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="30" name="Q" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="29" name="U" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" width="5" name="opcode" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="11" width="2" settings="2">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ABS_asimdmisc_R" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="advsimd-type" value="simd" />
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ABS" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ABS </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [2D,2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_vn" hover="SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [2D,2S,4H,4S,8B,8H,16B]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/arithmetic/unary/diff-neg/int/simd" mylink="aarch64.instrs.vector.arithmetic.unary.diff-neg.int.simd" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
|
||||
if size:Q == '110' then UNDEFINED;
|
||||
integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer datasize = if Q == '1' then 128 else 64;
|
||||
integer elements = datasize DIV esize;
|
||||
boolean neg = (U == '1');</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ABS_asisdmisc_R" symboldefcount="1">
|
||||
<symbol link="sa_v"><V></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is a width specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><V></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">0x</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ABS_asisdmisc_R" symboldefcount="1">
|
||||
<symbol link="sa_d"><d></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the number of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ABS_asisdmisc_R" symboldefcount="1">
|
||||
<symbol link="sa_n"><n></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the number of the SIMD&FP source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ABS_asimdmisc_R" symboldefcount="1">
|
||||
<symbol link="sa_vd"><Vd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ABS_asimdmisc_R" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size:Q">
|
||||
<intro>Is an arrangement specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="3">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="bitfield">Q</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">8B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">16B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">4H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">8H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">2S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">4S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">2D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ABS_asimdmisc_R" symboldefcount="1">
|
||||
<symbol link="sa_vn"><Vn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the name of the SIMD&FP source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/arithmetic/unary/diff-neg/int/sisd" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
|
||||
bits(datasize) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
|
||||
bits(datasize) result;
|
||||
integer element;
|
||||
|
||||
for e = 0 to elements-1
|
||||
element = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
|
||||
if neg then
|
||||
element = -element;
|
||||
else
|
||||
element = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(element);
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element<esize-1:0>;
|
||||
|
||||
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
173
spec/arm64_xml/abs_z_p_z.xml
Normal file
173
spec/arm64_xml/abs_z_p_z.xml
Normal file
@@ -0,0 +1,173 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="abs_z_p_z" title="ABS" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ABS" />
|
||||
</docvars>
|
||||
<heading>ABS</heading>
|
||||
<desc>
|
||||
<brief>Absolute value (predicated)</brief>
|
||||
<description>
|
||||
<para>Compute the absolute value of the signed integer in each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>True</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<takes_movprfx>True</takes_movprfx>
|
||||
<takes_pred_movprfx>True</takes_pred_movprfx>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ABS" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ABS-Z.P.Z-_">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="18" width="2" name="opc<2:1>" settings="2">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="16" name="opc<0>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="3" settings="3">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="Pg" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="abs_z_p_z_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ABS" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ABS </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/M, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ABS-Z.P.Z-_" mylink="ABS-Z.P.Z-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="abs_z_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_zd"><Zd></symbol>
|
||||
<account encodedin="Zd">
|
||||
<intro>
|
||||
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="abs_z_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="abs_z_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_pg"><Pg></symbol>
|
||||
<account encodedin="Pg">
|
||||
<intro>
|
||||
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="abs_z_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ABS-Z.P.Z-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand = if <a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[d, VL];
|
||||
|
||||
for e = 0 to elements-1
|
||||
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
integer element = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize]);
|
||||
element = <a link="impl-shared.Abs.1" file="shared_pseudocode.xml" hover="function: integer Abs(integer x)">Abs</a>(element);
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element<esize-1:0>;
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
34
spec/arm64_xml/accounts.dtd
Normal file
34
spec/arm64_xml/accounts.dtd
Normal file
@@ -0,0 +1,34 @@
|
||||
<!--
|
||||
|
||||
XML language accounts for accounts.xml
|
||||
Copyright (c) 2011-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
|
||||
-->
|
||||
|
||||
<!ATTLIST arch_variant feature CDATA #REQUIRED>
|
||||
<!ELEMENT arch_variant EMPTY>
|
||||
<!ELEMENT arch_variants (arch_variant+)>
|
||||
|
||||
<!ELEMENT entry (#PCDATA | arch_variants)*>
|
||||
<!ATTLIST entry class CDATA #REQUIRED bitwidth CDATA #IMPLIED>
|
||||
<!ELEMENT row (entry+)>
|
||||
<!ELEMENT tbody (row+)>
|
||||
<!ELEMENT thead (row+)>
|
||||
<!ELEMENT tgroup (thead, tbody)>
|
||||
<!ATTLIST tgroup cols CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT table (tgroup+)>
|
||||
<!ATTLIST table class CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT encoding EMPTY>
|
||||
<!ATTLIST encoding encname CDATA #REQUIRED>
|
||||
<!ELEMENT encodings (encoding+)>
|
||||
<!ELEMENT orig (#PCDATA)>
|
||||
<!ELEMENT intro (#PCDATA)>
|
||||
<!ELEMENT after (#PCDATA)>
|
||||
<!ELEMENT definition (intro, table, after?)>
|
||||
<!ATTLIST definition encodedin CDATA #REQUIRED tabulatedwith CDATA #IMPLIED>
|
||||
<!ELEMENT account (encodings, orig, definition)>
|
||||
<!ATTLIST account iclass CDATA #REQUIRED symbol CDATA #REQUIRED iclass_long CDATA #REQUIRED>
|
||||
<!ELEMENT accounts (account+)>
|
||||
150
spec/arm64_xml/accounts.xsl
Normal file
150
spec/arm64_xml/accounts.xsl
Normal file
@@ -0,0 +1,150 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<xsl:stylesheet xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
|
||||
version="1.1" xmlns="http://www.w3.org/1999/xhtml">
|
||||
|
||||
<xsl:output doctype-public="-//W3C//DTD XHTML 1.1//EN"
|
||||
doctype-system="http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd"
|
||||
method="html" encoding="utf-8"/>
|
||||
|
||||
<xsl:template match="/accounts">
|
||||
<html>
|
||||
|
||||
<head>
|
||||
<link rel="stylesheet" type="text/css" href="insn.css"/>
|
||||
<meta name="generator" content="encodingindex.xsl"/>
|
||||
<title>Tabulated Instruction field options</title>
|
||||
</head>
|
||||
|
||||
<body>
|
||||
<table style="margin: 0 auto;">
|
||||
<tr>
|
||||
<!-- autogenerator: header/footer start -->
|
||||
<!-- autogenerated -->
|
||||
<td><div class="topbar"><a href="index.xml">Base Instructions</a></div></td>
|
||||
<td><div class="topbar"><a href="fpsimdindex.xml">SIMD&FP Instructions</a></div></td>
|
||||
<td><div class="topbar"><a href="sveindex.xml">SVE Instructions</a></div></td>
|
||||
<td><div class="topbar"><a href="mortlachindex.xml">SME Instructions</a></div></td>
|
||||
<td><div class="topbar"><a href="encodingindex.xml">Index by Encoding</a></div></td>
|
||||
<td><div class="topbar"><a href="shared_pseudocode.xml">Shared Pseudocode</a></div></td>
|
||||
<td><div class="topbar"><a href="notice.xml">Proprietary Notice</a></div></td>
|
||||
<!-- autogenerator: header/footer end -->
|
||||
</tr>
|
||||
</table>
|
||||
<hr/>
|
||||
<xsl:apply-templates/>
|
||||
<hr/>
|
||||
<table style="margin: 0 auto;">
|
||||
<tr>
|
||||
<!-- autogenerator: header/footer start -->
|
||||
<!-- autogenerated -->
|
||||
<td><div class="topbar"><a href="index.xml">Base Instructions</a></div></td>
|
||||
<td><div class="topbar"><a href="fpsimdindex.xml">SIMD&FP Instructions</a></div></td>
|
||||
<td><div class="topbar"><a href="sveindex.xml">SVE Instructions</a></div></td>
|
||||
<td><div class="topbar"><a href="mortlachindex.xml">SME Instructions</a></div></td>
|
||||
<td><div class="topbar"><a href="encodingindex.xml">Index by Encoding</a></div></td>
|
||||
<td><div class="topbar"><a href="shared_pseudocode.xml">Shared Pseudocode</a></div></td>
|
||||
<td><div class="topbar"><a href="notice.xml">Proprietary Notice</a></div></td>
|
||||
<!-- autogenerator: header/footer end -->
|
||||
</tr>
|
||||
</table>
|
||||
<!-- version footer -->
|
||||
<p class="versions">
|
||||
Internal version only: isa v33.59, AdvSIMD v29.12, pseudocode v2022-12_rel, sve v2022-12_relb
|
||||
; Build timestamp: 2022-12-14T22:29
|
||||
</p>
|
||||
<p class="copyconf">
|
||||
Copyright © 2010-2015 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p>
|
||||
</body>
|
||||
|
||||
</html>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="account">
|
||||
<h2>
|
||||
<xsl:value-of select="@iclass_long"/>
|
||||
<xsl:value-of select="@symbol"/>
|
||||
</h2>
|
||||
<xsl:apply-templates/>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="account/orig">
|
||||
<p class="accounts-orig">
|
||||
<strong>Original text</strong>: <xsl:value-of select="."/>
|
||||
</p>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="account/definition">
|
||||
<div class="explanations">
|
||||
<h4 class="encoding">Where:</h4>
|
||||
<table>
|
||||
<col class="asyn-l" />
|
||||
<col class="asyn-r" />
|
||||
<tr>
|
||||
<td>
|
||||
<xsl:value-of select="../@symbol"/>
|
||||
</td>
|
||||
<td>
|
||||
<xsl:apply-templates/>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="definition/intro">
|
||||
<xsl:value-of select="."/>
|
||||
encoded in
|
||||
<xsl:choose>
|
||||
<xsl:when test="../@tabulatedwith">
|
||||
<q><xsl:value-of select="../@encodedin"/></q>, based on
|
||||
<q><xsl:value-of select="../@tabulatedwith"/></q>:
|
||||
</xsl:when>
|
||||
<xsl:otherwise>
|
||||
<q><xsl:value-of select="../@encodedin"/></q>:
|
||||
</xsl:otherwise>
|
||||
</xsl:choose>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="definition/after">
|
||||
<xsl:value-of select="."/>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="table">
|
||||
<table class="{@class}">
|
||||
<xsl:apply-templates/>
|
||||
</table>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="thead">
|
||||
<thead>
|
||||
<xsl:apply-templates/>
|
||||
</thead>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="row">
|
||||
<tr>
|
||||
<xsl:apply-templates/>
|
||||
</tr>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="thead/row/entry">
|
||||
<th class="{@class}">
|
||||
<xsl:apply-templates/>
|
||||
</th>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="tbody">
|
||||
<tbody>
|
||||
<xsl:apply-templates/>
|
||||
</tbody>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="tbody/row/entry">
|
||||
<td class="{@class}">
|
||||
<xsl:apply-templates/>
|
||||
</td>
|
||||
</xsl:template>
|
||||
|
||||
</xsl:stylesheet>
|
||||
184
spec/arm64_xml/adc.xml
Normal file
184
spec/arm64_xml/adc.xml
Normal file
@@ -0,0 +1,184 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ADC" title="ADC -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADC" />
|
||||
</docvars>
|
||||
<heading>ADC</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Add with Carry</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Add with Carry adds two register values and the Carry flag value, and writes the result to the destination register.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Not setting the condition flags" oneof="1" id="iclass_no_s" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADC" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/add-sub/carry" tworows="1">
|
||||
<box hibit="31" name="sf" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="30" name="op" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="29" name="S" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="8" settings="8">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="6" settings="6">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ADC_32_addsub_carry" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADC" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>ADC </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn" hover="First 32-bit general-purpose source register (field "Rn")"><Wn></a><text>, </text><a link="sa_wm" hover="Second 32-bit general-purpose source register (field "Rm")"><Wm></a></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="ADC_64_addsub_carry" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADC" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>ADC </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn" hover="First 64-bit general-purpose source register (field "Rn")"><Xn></a><text>, </text><a link="sa_xm" hover="Second 64-bit general-purpose source register (field "Rm")"><Xm></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/add-sub/carry" mylink="aarch64.instrs.integer.arithmetic.add-sub.carry" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
integer datasize = if sf == '1' then 64 else 32;
|
||||
boolean sub_op = (op == '1');
|
||||
boolean setflags = (S == '1');</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ADC_32_addsub_carry" symboldefcount="1">
|
||||
<symbol link="sa_wd"><Wd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADC_32_addsub_carry" symboldefcount="1">
|
||||
<symbol link="sa_wn"><Wn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADC_32_addsub_carry" symboldefcount="1">
|
||||
<symbol link="sa_wm"><Wm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADC_64_addsub_carry" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADC_64_addsub_carry" symboldefcount="1">
|
||||
<symbol link="sa_xn"><Xn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADC_64_addsub_carry" symboldefcount="1">
|
||||
<symbol link="sa_xm"><Xm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/add-sub/carry" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) result;
|
||||
bits(datasize) operand1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, datasize];
|
||||
bits(datasize) operand2 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[m, datasize];
|
||||
bits(4) nzcv;
|
||||
|
||||
if sub_op then
|
||||
operand2 = NOT(operand2);
|
||||
|
||||
(result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(operand1, operand2, PSTATE.C);
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = nzcv;
|
||||
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
167
spec/arm64_xml/adclb_z_zzz.xml
Normal file
167
spec/arm64_xml/adclb_z_zzz.xml
Normal file
@@ -0,0 +1,167 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="adclb_z_zzz" title="ADCLB" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADCLB" />
|
||||
</docvars>
|
||||
<heading>ADCLB</heading>
|
||||
<desc>
|
||||
<brief>Add with carry long (bottom)</brief>
|
||||
<description>
|
||||
<para>Add the even-numbered elements of the first source vector and the 1-bit carry from the least-significant bit of the odd-numbered elements of the second source vector to the even-numbered elements of the destination and accumulator vector. The 1-bit carry output is placed in the corresponding odd-numbered element of the destination vector.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<takes_movprfx>True</takes_movprfx>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADCLB" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ADCLB-Z.ZZZ-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="sz" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" name="T" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zda" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="adclb_z_zzz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADCLB" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADCLB </text><a link="sa_zda" hover="Third source and destination scalable vector register (field "Zda")"><Zda></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADCLB-Z.ZZZ-_" mylink="ADCLB-Z.ZZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer da = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zda);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="adclb_z_zzz_" symboldefcount="1">
|
||||
<symbol link="sa_zda"><Zda></symbol>
|
||||
<account encodedin="Zda">
|
||||
<intro>
|
||||
<para>Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="adclb_z_zzz_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="sz">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">sz</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="adclb_z_zzz_" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="adclb_z_zzz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADCLB-Z.ZZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer pairs = VL DIV (esize * 2);
|
||||
bits(VL) operand = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) carries = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[da, VL];
|
||||
|
||||
for p = 0 to pairs-1
|
||||
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, 2*p + 0, esize];
|
||||
bits(esize) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*p + 0, esize];
|
||||
bit carry_in = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[carries, 2*p + 1, esize]<0>;
|
||||
|
||||
(res, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(element1, element2, carry_in);
|
||||
carry_out = nzcv<1>;
|
||||
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p + 0, esize] = res;
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p + 1, esize] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(carry_out, esize);
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[da, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
167
spec/arm64_xml/adclt_z_zzz.xml
Normal file
167
spec/arm64_xml/adclt_z_zzz.xml
Normal file
@@ -0,0 +1,167 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="adclt_z_zzz" title="ADCLT" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADCLT" />
|
||||
</docvars>
|
||||
<heading>ADCLT</heading>
|
||||
<desc>
|
||||
<brief>Add with carry long (top)</brief>
|
||||
<description>
|
||||
<para>Add the odd-numbered elements of the first source vector and the 1-bit carry from the least-significant bit of the odd-numbered elements of the second source vector to the even-numbered elements of the destination and accumulator vector. The 1-bit carry output is placed in the corresponding odd-numbered element of the destination vector.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<takes_movprfx>True</takes_movprfx>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADCLT" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ADCLT-Z.ZZZ-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="sz" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" name="T" usename="1" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zda" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="adclt_z_zzz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADCLT" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADCLT </text><a link="sa_zda" hover="Third source and destination scalable vector register (field "Zda")"><Zda></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADCLT-Z.ZZZ-_" mylink="ADCLT-Z.ZZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer da = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zda);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="adclt_z_zzz_" symboldefcount="1">
|
||||
<symbol link="sa_zda"><Zda></symbol>
|
||||
<account encodedin="Zda">
|
||||
<intro>
|
||||
<para>Is the name of the third source and destination scalable vector register, encoded in the "Zda" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="adclt_z_zzz_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="sz">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">sz</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="adclt_z_zzz_" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="adclt_z_zzz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADCLT-Z.ZZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer pairs = VL DIV (esize * 2);
|
||||
bits(VL) operand = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) carries = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[da, VL];
|
||||
|
||||
for p = 0 to pairs-1
|
||||
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, 2*p + 0, esize];
|
||||
bits(esize) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, 2*p + 1, esize];
|
||||
bit carry_in = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[carries, 2*p + 1, esize]<0>;
|
||||
|
||||
(res, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(element1, element2, carry_in);
|
||||
carry_out = nzcv<1>;
|
||||
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p + 0, esize] = res;
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*p + 1, esize] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(carry_out, esize);
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[da, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
184
spec/arm64_xml/adcs.xml
Normal file
184
spec/arm64_xml/adcs.xml
Normal file
@@ -0,0 +1,184 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ADCS" title="ADCS -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADCS" />
|
||||
</docvars>
|
||||
<heading>ADCS</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Add with Carry, setting flags</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Add with Carry, setting flags, adds two register values and the Carry flag value, and writes the result to the destination register. It updates the condition flags based on the result.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Setting the condition flags" oneof="1" id="iclass_s" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADCS" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/add-sub/carry" tworows="1">
|
||||
<box hibit="31" name="sf" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="30" name="op" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="29" name="S" usename="1" settings="1" psbits="x">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="28" width="8" settings="8">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="6" settings="6">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ADCS_32_addsub_carry" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADCS" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>ADCS </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn" hover="First 32-bit general-purpose source register (field "Rn")"><Wn></a><text>, </text><a link="sa_wm" hover="Second 32-bit general-purpose source register (field "Rm")"><Wm></a></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="ADCS_64_addsub_carry" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADCS" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>ADCS </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn" hover="First 64-bit general-purpose source register (field "Rn")"><Xn></a><text>, </text><a link="sa_xm" hover="Second 64-bit general-purpose source register (field "Rm")"><Xm></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/add-sub/carry" mylink="aarch64.instrs.integer.arithmetic.add-sub.carry" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
integer datasize = if sf == '1' then 64 else 32;
|
||||
boolean sub_op = (op == '1');
|
||||
boolean setflags = (S == '1');</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ADCS_32_addsub_carry" symboldefcount="1">
|
||||
<symbol link="sa_wd"><Wd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADCS_32_addsub_carry" symboldefcount="1">
|
||||
<symbol link="sa_wn"><Wn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADCS_32_addsub_carry" symboldefcount="1">
|
||||
<symbol link="sa_wm"><Wm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADCS_64_addsub_carry" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADCS_64_addsub_carry" symboldefcount="1">
|
||||
<symbol link="sa_xn"><Xn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADCS_64_addsub_carry" symboldefcount="1">
|
||||
<symbol link="sa_xm"><Xm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/add-sub/carry" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) result;
|
||||
bits(datasize) operand1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, datasize];
|
||||
bits(datasize) operand2 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[m, datasize];
|
||||
bits(4) nzcv;
|
||||
|
||||
if sub_op then
|
||||
operand2 = NOT(operand2);
|
||||
|
||||
(result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(operand1, operand2, PSTATE.C);
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = nzcv;
|
||||
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
344
spec/arm64_xml/add_addsub_ext.xml
Normal file
344
spec/arm64_xml/add_addsub_ext.xml
Normal file
@@ -0,0 +1,344 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ADD_addsub_ext" title="ADD (extended register) -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<heading>ADD (extended register)</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Add (extended register)</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Add (extended register) adds a register value and a sign or zero-extended register value, followed by an optional left shift amount, and writes the result to the destination register. The argument that is extended from the <syntax><Rm></syntax> register can be a byte, halfword, word, or doubleword.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Not setting the condition flags" oneof="1" id="iclass_no_s" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/add-sub/extendedreg" tworows="1">
|
||||
<box hibit="31" name="sf" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="30" name="op" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="29" name="S" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="opt" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="3" name="option" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="imm3" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ADD_32_addsub_ext" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>ADD </text><a link="sa_wd_wsp" hover="32-bit destination general-purpose register or WSP (field "Rd")"><Wd|WSP></a><text>, </text><a link="sa_wn_wsp" hover="First 32-bit source general-purpose register or WSP (field "Rn")"><Wn|WSP></a><text>, </text><a link="sa_wm" hover="Second 32-bit general-purpose source register (field "Rm")"><Wm></a><text>{</text><text>, </text><a link="sa_extend" hover="Extension applied to second source operand (field "option") [LSL,SXTB,SXTH,SXTW,SXTX,UXTB,UXTH,UXTW,UXTX]"><extend></a><text> </text><text>{</text><text>#</text><a link="sa_amount" hover="Left shift amount applied after extension [0-4], default 0 (field "imm3")"><amount></a><text>}</text><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="ADD_64_addsub_ext" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>ADD </text><a link="sa_xd_sp" hover="64-bit destination general-purpose register or SP (field "Rd")"><Xd|SP></a><text>, </text><a link="sa_xn_sp" hover="First 64-bit source general-purpose register or SP (field "Rn")"><Xn|SP></a><text>, </text><a link="sa_r" hover="Width specifier (field "option") [W,X]"><R></a><a link="sa_m" hover="Second general-purpose source register number [0-30] or ZR (31) (field "Rm")"><m></a><text>{</text><text>, </text><a link="sa_extend_1" hover="Extension applied to second source operand (field "option") [LSL,SXTB,SXTH,SXTW,SXTX,UXTB,UXTH,UXTW,UXTX]"><extend></a><text> </text><text>{</text><text>#</text><a link="sa_amount" hover="Left shift amount applied after extension [0-4], default 0 (field "imm3")"><amount></a><text>}</text><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/add-sub/extendedreg" mylink="aarch64.instrs.integer.arithmetic.add-sub.extendedreg" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
integer datasize = if sf == '1' then 64 else 32;
|
||||
boolean sub_op = (op == '1');
|
||||
boolean setflags = (S == '1');
|
||||
<a link="ExtendType" file="shared_pseudocode.xml" hover="enumeration ExtendType {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType</a> extend_type = <a link="impl-aarch64.DecodeRegExtend.1" file="shared_pseudocode.xml" hover="function: ExtendType DecodeRegExtend(bits(3) op)">DecodeRegExtend</a>(option);
|
||||
integer shift = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm3);
|
||||
if shift > 4 then UNDEFINED;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ADD_32_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_wd_wsp"><Wd|WSP></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_32_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_wn_wsp"><Wn|WSP></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_32_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_wm"><Wm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_64_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_xd_sp"><Xd|SP></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_64_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_64_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_r"><R></symbol>
|
||||
<definition encodedin="option">
|
||||
<intro>Is a width specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">option</entry>
|
||||
<entry class="symbol"><R></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00x</entry>
|
||||
<entry class="symbol">W</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">010</entry>
|
||||
<entry class="symbol">W</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">x11</entry>
|
||||
<entry class="symbol">X</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10x</entry>
|
||||
<entry class="symbol">W</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">110</entry>
|
||||
<entry class="symbol">W</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_64_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_m"><m></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the number [0-30] of the second general-purpose source register or the name ZR (31), encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_32_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_extend"><extend></symbol>
|
||||
<definition encodedin="option">
|
||||
<intro>For the 32-bit variant: is the extension to be applied to the second source operand, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">option</entry>
|
||||
<entry class="symbol"><extend></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">000</entry>
|
||||
<entry class="symbol">UXTB</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">001</entry>
|
||||
<entry class="symbol">UXTH</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">010</entry>
|
||||
<entry class="symbol">LSL|UXTW</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">011</entry>
|
||||
<entry class="symbol">UXTX</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">100</entry>
|
||||
<entry class="symbol">SXTB</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">101</entry>
|
||||
<entry class="symbol">SXTH</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">110</entry>
|
||||
<entry class="symbol">SXTW</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">111</entry>
|
||||
<entry class="symbol">SXTX</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
<after>If "Rd" or "Rn" is '11111' (WSP) and "option" is '010' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTW when "option" is '010'.</after>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_64_addsub_ext" symboldefcount="2">
|
||||
<symbol link="sa_extend_1"><extend></symbol>
|
||||
<definition encodedin="option">
|
||||
<intro>For the 64-bit variant: is the extension to be applied to the second source operand, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">option</entry>
|
||||
<entry class="symbol"><extend></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">000</entry>
|
||||
<entry class="symbol">UXTB</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">001</entry>
|
||||
<entry class="symbol">UXTH</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">010</entry>
|
||||
<entry class="symbol">UXTW</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">011</entry>
|
||||
<entry class="symbol">LSL|UXTX</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">100</entry>
|
||||
<entry class="symbol">SXTB</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">101</entry>
|
||||
<entry class="symbol">SXTH</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">110</entry>
|
||||
<entry class="symbol">SXTW</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">111</entry>
|
||||
<entry class="symbol">SXTX</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
<after>If "Rd" or "Rn" is '11111' (SP) and "option" is '011' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTX when "option" is '011'.</after>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_32_addsub_ext, ADD_64_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_amount"><amount></symbol>
|
||||
<account encodedin="imm3">
|
||||
<intro>
|
||||
<para>Is the left shift amount to be applied after extension in the range 0 to 4, defaulting to 0, encoded in the "imm3" field. It must be absent when <extend> is absent, is required when <extend> is LSL, and is optional when <extend> is present but not LSL.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/add-sub/extendedreg" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) result;
|
||||
bits(datasize) operand1 = if n == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[]<datasize-1:0> else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, datasize];
|
||||
bits(datasize) operand2 = <a link="impl-aarch64.ExtendReg.4" file="shared_pseudocode.xml" hover="function: bits(N) ExtendReg(integer reg, ExtendType exttype, integer shift, integer N)">ExtendReg</a>(m, extend_type, shift, datasize);
|
||||
bits(4) nzcv;
|
||||
bit carry_in;
|
||||
|
||||
if sub_op then
|
||||
operand2 = NOT(operand2);
|
||||
carry_in = '1';
|
||||
else
|
||||
carry_in = '0';
|
||||
|
||||
(result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(operand1, operand2, carry_in);
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = nzcv;
|
||||
|
||||
if d == 31 && !setflags then
|
||||
<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(result, 64);
|
||||
else
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
222
spec/arm64_xml/add_addsub_imm.xml
Normal file
222
spec/arm64_xml/add_addsub_imm.xml
Normal file
@@ -0,0 +1,222 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ADD_addsub_imm" title="ADD (immediate) -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="immediate-type" value="imm12u" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<heading>ADD (immediate)</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Add (immediate)</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Add (immediate) adds a register value and an optionally-shifted immediate value, and writes the result to the destination register.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="1">
|
||||
<alias_list_intro>This instruction is used by the alias </alias_list_intro>
|
||||
<aliasref aliaspageid="MOV_ADD_addsub_imm" aliasfile="mov_add_addsub_imm.xml" hover="Move between register and stack pointer" punct=".">
|
||||
<text>MOV (to/from SP)</text>
|
||||
<aliaspref>sh == '0' && imm12 == '000000000000' && (Rd == '11111' || Rn == '11111')</aliaspref>
|
||||
</aliasref>
|
||||
<alias_list_outro>
|
||||
<text> See </text>
|
||||
<aliastablelink />
|
||||
<text> below for details of when the alias is preferred.</text>
|
||||
</alias_list_outro>
|
||||
</alias_list>
|
||||
<classes>
|
||||
<iclass name="Not setting the condition flags" oneof="1" id="iclass_no_s" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="immediate-type" value="imm12u" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/add-sub/immediate" tworows="1">
|
||||
<box hibit="31" name="sf" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="30" name="op" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="29" name="S" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="6" settings="6">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="sh" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="21" width="12" name="imm12" usename="1">
|
||||
<c colspan="12"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ADD_32_addsub_imm" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="immediate-type" value="imm12u" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>ADD </text><a link="sa_wd_wsp" hover="32-bit destination general-purpose register or WSP (field "Rd")"><Wd|WSP></a><text>, </text><a link="sa_wn_wsp" hover="32-bit source general-purpose register or WSP (field "Rn")"><Wn|WSP></a><text>, #</text><a link="sa_imm" hover="Unsigned immediate [0-4095] (field "imm12")"><imm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional left shift to apply to the immediate, default LSL #0 (field "sh") [LSL #0,LSL #12]"><shift></a><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="ADD_64_addsub_imm" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="immediate-type" value="imm12u" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>ADD </text><a link="sa_xd_sp" hover="64-bit destination general-purpose register or SP (field "Rd")"><Xd|SP></a><text>, </text><a link="sa_xn_sp" hover="64-bit source general-purpose register or SP (field "Rn")"><Xn|SP></a><text>, #</text><a link="sa_imm" hover="Unsigned immediate [0-4095] (field "imm12")"><imm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional left shift to apply to the immediate, default LSL #0 (field "sh") [LSL #0,LSL #12]"><shift></a><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/add-sub/immediate" mylink="aarch64.instrs.integer.arithmetic.add-sub.immediate" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer datasize = if sf == '1' then 64 else 32;
|
||||
boolean sub_op = (op == '1');
|
||||
boolean setflags = (S == '1');
|
||||
bits(datasize) imm;
|
||||
|
||||
case sh of
|
||||
when '0' imm = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, datasize);
|
||||
when '1' imm = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12), datasize);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ADD_32_addsub_imm" symboldefcount="1">
|
||||
<symbol link="sa_wd_wsp"><Wd|WSP></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_32_addsub_imm" symboldefcount="1">
|
||||
<symbol link="sa_wn_wsp"><Wn|WSP></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_64_addsub_imm" symboldefcount="1">
|
||||
<symbol link="sa_xd_sp"><Xd|SP></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_64_addsub_imm" symboldefcount="1">
|
||||
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_32_addsub_imm, ADD_64_addsub_imm" symboldefcount="1">
|
||||
<symbol link="sa_imm"><imm></symbol>
|
||||
<account encodedin="imm12">
|
||||
<intro>
|
||||
<para>Is an unsigned immediate, in the range 0 to 4095, encoded in the "imm12" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_32_addsub_imm, ADD_64_addsub_imm" symboldefcount="1">
|
||||
<symbol link="sa_shift"><shift></symbol>
|
||||
<definition encodedin="sh">
|
||||
<intro>Is the optional left shift to apply to the immediate, defaulting to LSL #0 and </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">sh</entry>
|
||||
<entry class="symbol"><shift></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">LSL #0</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">LSL #12</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/add-sub/immediate" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) result;
|
||||
bits(datasize) operand1 = if n == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[]<datasize-1:0> else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, datasize];
|
||||
bits(datasize) operand2 = imm;
|
||||
bits(4) nzcv;
|
||||
bit carry_in;
|
||||
|
||||
if sub_op then
|
||||
operand2 = NOT(operand2);
|
||||
carry_in = '1';
|
||||
else
|
||||
carry_in = '0';
|
||||
|
||||
(result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(operand1, operand2, carry_in);
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = nzcv;
|
||||
|
||||
if d == 31 && !setflags then
|
||||
<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(result, 64);
|
||||
else
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
248
spec/arm64_xml/add_addsub_shift.xml
Normal file
248
spec/arm64_xml/add_addsub_shift.xml
Normal file
@@ -0,0 +1,248 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ADD_addsub_shift" title="ADD (shifted register) -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<heading>ADD (shifted register)</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Add (shifted register)</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Add (shifted register) adds a register value and an optionally-shifted register value, and writes the result to the destination register.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Not setting the condition flags" oneof="1" id="iclass_no_s" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/add-sub/shiftedreg" tworows="1">
|
||||
<box hibit="31" name="sf" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="30" name="op" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="29" name="S" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="shift" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="6" name="imm6" usename="1">
|
||||
<c colspan="6"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ADD_32_addsub_shift" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>ADD </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn" hover="First 32-bit general-purpose source register (field "Rn")"><Wn></a><text>, </text><a link="sa_wm" hover="Second 32-bit general-purpose source register (field "Rm")"><Wm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift type applied to second source operand, default LSL (field "shift") [ASR,LSL,LSR]"><shift></a><text> #</text><a link="sa_amount" hover="Shift amount [0-31], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="ADD_64_addsub_shift" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>ADD </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn" hover="First 64-bit general-purpose source register (field "Rn")"><Xn></a><text>, </text><a link="sa_xm" hover="Second 64-bit general-purpose source register (field "Rm")"><Xm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift type applied to second source operand, default LSL (field "shift") [ASR,LSL,LSR]"><shift></a><text> #</text><a link="sa_amount_1" hover="Shift amount [0-63], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/add-sub/shiftedreg" mylink="aarch64.instrs.integer.arithmetic.add-sub.shiftedreg" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
integer datasize = if sf == '1' then 64 else 32;
|
||||
boolean sub_op = (op == '1');
|
||||
boolean setflags = (S == '1');
|
||||
|
||||
if shift == '11' then UNDEFINED;
|
||||
if sf == '0' && imm6<5> == '1' then UNDEFINED;
|
||||
|
||||
<a link="ShiftType" file="shared_pseudocode.xml" hover="enumeration ShiftType {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType</a> shift_type = <a link="impl-aarch64.DecodeShift.1" file="shared_pseudocode.xml" hover="function: ShiftType DecodeShift(bits(2) op)">DecodeShift</a>(shift);
|
||||
integer shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ADD_32_addsub_shift" symboldefcount="1">
|
||||
<symbol link="sa_wd"><Wd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_32_addsub_shift" symboldefcount="1">
|
||||
<symbol link="sa_wn"><Wn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_32_addsub_shift" symboldefcount="1">
|
||||
<symbol link="sa_wm"><Wm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_64_addsub_shift" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_64_addsub_shift" symboldefcount="1">
|
||||
<symbol link="sa_xn"><Xn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_64_addsub_shift" symboldefcount="1">
|
||||
<symbol link="sa_xm"><Xm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_32_addsub_shift, ADD_64_addsub_shift" symboldefcount="1">
|
||||
<symbol link="sa_shift"><shift></symbol>
|
||||
<definition encodedin="shift">
|
||||
<intro>Is the optional shift type to be applied to the second source operand, defaulting to LSL and </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">shift</entry>
|
||||
<entry class="symbol"><shift></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">LSL</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">LSR</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">ASR</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_32_addsub_shift" symboldefcount="1">
|
||||
<symbol link="sa_amount"><amount></symbol>
|
||||
<account encodedin="imm6">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="32" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 32-bit variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_64_addsub_shift" symboldefcount="2">
|
||||
<symbol link="sa_amount_1"><amount></symbol>
|
||||
<account encodedin="imm6">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="64" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 64-bit variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/add-sub/shiftedreg" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) result;
|
||||
bits(datasize) operand1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, datasize];
|
||||
bits(datasize) operand2 = <a link="impl-aarch64.ShiftReg.4" file="shared_pseudocode.xml" hover="function: bits(N) ShiftReg(integer reg, ShiftType shiftype, integer amount, integer N)">ShiftReg</a>(m, shift_type, shift_amount, datasize);
|
||||
bits(4) nzcv;
|
||||
bit carry_in;
|
||||
|
||||
if sub_op then
|
||||
operand2 = NOT(operand2);
|
||||
carry_in = '1';
|
||||
else
|
||||
carry_in = '0';
|
||||
|
||||
(result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(operand1, operand2, carry_in);
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = nzcv;
|
||||
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
344
spec/arm64_xml/add_advsimd.xml
Normal file
344
spec/arm64_xml/add_advsimd.xml
Normal file
@@ -0,0 +1,344 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ADD_advsimd" title="ADD (vector) -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<heading>ADD (vector)</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Add (vector)</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.</para>
|
||||
<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<classesintro count="2">
|
||||
<txt>It has encodings from 2 classes:</txt>
|
||||
<a href="#iclass_sisd">Scalar</a>
|
||||
<txt> and </txt>
|
||||
<a href="#iclass_simd">Vector</a>
|
||||
</classesintro>
|
||||
<iclass name="Scalar" oneof="2" id="iclass_sisd" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="advsimd-type" value="sisd" />
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/uniform/add/wrapping/single/sisd" tworows="1">
|
||||
<box hibit="31" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="29" name="U" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="5" name="opcode" settings="5">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ADD_asisdsame_only" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="advsimd-type" value="sisd" />
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADD </text><a link="sa_v" hover="Width specifier (field "size") [D]"><V></a><a link="sa_d" hover="SIMD&FP destination register number (field "Rd")"><d></a><text>, </text><a link="sa_v" hover="Width specifier (field "size") [D]"><V></a><a link="sa_n" hover="First SIMD&FP source register number (field "Rn")"><n></a><text>, </text><a link="sa_v" hover="Width specifier (field "size") [D]"><V></a><a link="sa_m" hover="Second SIMD&FP source register number (field "Rm")"><m></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/arithmetic/binary/uniform/add/wrapping/single/sisd" mylink="aarch64.instrs.vector.arithmetic.binary.uniform.add.wrapping.single.sisd" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
if size != '11' then UNDEFINED;
|
||||
integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer datasize = esize;
|
||||
integer elements = 1;
|
||||
boolean sub_op = (U == '1');</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
<iclass name="Vector" oneof="2" id="iclass_simd" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="advsimd-reguse" value="3reg-same" />
|
||||
<docvar key="advsimd-type" value="simd" />
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/uniform/add/wrapping/single/simd" tworows="1">
|
||||
<box hibit="31" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="30" name="Q" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="29" name="U" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="5" name="opcode" settings="5">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ADD_asimdsame_only" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="advsimd-reguse" value="3reg-same" />
|
||||
<docvar key="advsimd-type" value="simd" />
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADD </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [2D,2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_vn" hover="First SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [2D,2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_vm" hover="Second SIMD&FP source register (field "Rm")"><Vm></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [2D,2S,4H,4S,8B,8H,16B]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/arithmetic/binary/uniform/add/wrapping/single/simd" mylink="aarch64.instrs.vector.arithmetic.binary.uniform.add.wrapping.single.simd" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
if size:Q == '110' then UNDEFINED;
|
||||
integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer datasize = if Q == '1' then 128 else 64;
|
||||
integer elements = datasize DIV esize;
|
||||
boolean sub_op = (U == '1');</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ADD_asisdsame_only" symboldefcount="1">
|
||||
<symbol link="sa_v"><V></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is a width specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><V></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">0x</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_asisdsame_only" symboldefcount="1">
|
||||
<symbol link="sa_d"><d></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the number of the SIMD&FP destination register, in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_asisdsame_only" symboldefcount="1">
|
||||
<symbol link="sa_n"><n></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the number of the first SIMD&FP source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_asisdsame_only" symboldefcount="1">
|
||||
<symbol link="sa_m"><m></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the number of the second SIMD&FP source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_asimdsame_only" symboldefcount="1">
|
||||
<symbol link="sa_vd"><Vd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_asimdsame_only" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size:Q">
|
||||
<intro>Is an arrangement specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="3">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="bitfield">Q</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">8B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">16B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">4H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">8H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">2S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">4S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">2D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_asimdsame_only" symboldefcount="1">
|
||||
<symbol link="sa_vn"><Vn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADD_asimdsame_only" symboldefcount="1">
|
||||
<symbol link="sa_vm"><Vm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the name of the second SIMD&FP source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/arithmetic/binary/uniform/add/wrapping/single/sisd" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
|
||||
bits(datasize) operand1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
|
||||
bits(datasize) operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, datasize];
|
||||
bits(datasize) result;
|
||||
bits(esize) element1;
|
||||
bits(esize) element2;
|
||||
|
||||
for e = 0 to elements-1
|
||||
element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
|
||||
if sub_op then
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 - element2;
|
||||
else
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
|
||||
|
||||
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
281
spec/arm64_xml/add_mz_zzv.xml
Normal file
281
spec/arm64_xml/add_mz_zzv.xml
Normal file
@@ -0,0 +1,281 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="add_mz_zzv" title="ADD (to vector)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<heading>ADD (to vector)</heading>
|
||||
<desc>
|
||||
<brief>Add replicated single vector to multi-vector with multi-vector result</brief>
|
||||
<description>
|
||||
<para>Add elements of the second source vector to the corresponding elements of the two or four first source vectors and destructively place the results in the corresponding elements of the two or four first source vectors.</para>
|
||||
<para>This instruction is unpredicated.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<sm_policy>SM_1_only</sm_policy>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<classesintro count="2">
|
||||
<txt>It has encodings from 2 classes:</txt>
|
||||
<a href="#iclass_to_2reg">Two registers</a>
|
||||
<txt> and </txt>
|
||||
<a href="#iclass_to_4reg">Four registers</a>
|
||||
</classesintro>
|
||||
<iclass name="Two registers" oneof="2" id="iclass_to_2reg" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="ldstruct-regcount" value="to-2reg" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="ADD-MZ.ZZV-2x1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="2" settings="2">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="19" width="4" name="Zm" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
<box hibit="15" width="6" settings="6">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="4" width="4" name="Zdn" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
<box hibit="0" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="add_mz_zzv_2x1" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="ldstruct-regcount" value="to-2reg" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADD </text><text>{</text><text> </text><a link="sa_zdn1" hover="First scalable vector register of a multi-vector sequence (field Zdn)"><Zdn1></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>-</text><a link="sa_zdn2" hover="Second scalable vector register of a multi-vector sequence (field Zdn)"><Zdn2></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text> </text><text>}</text><text>, </text><text>{</text><text> </text><a link="sa_zdn1" hover="First scalable vector register of a multi-vector sequence (field Zdn)"><Zdn1></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>-</text><a link="sa_zdn2" hover="Second scalable vector register of a multi-vector sequence (field Zdn)"><Zdn2></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text> </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-MZ.ZZV-2x1" mylink="ADD-MZ.ZZV-2x1" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn:'0');
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
|
||||
constant integer nreg = 2;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
<iclass name="Four registers" oneof="2" id="iclass_to_4reg" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="ldstruct-regcount" value="to-4reg" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="ADD-MZ.ZZV-4x1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="2" settings="2">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="19" width="4" name="Zm" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
<box hibit="15" width="6" settings="6">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="4" width="3" name="Zdn" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="1" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="add_mz_zzv_4x1" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="ldstruct-regcount" value="to-4reg" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADD </text><text>{</text><text> </text><a link="sa_zdn1_1" hover="First scalable vector register of a multi-vector sequence (field Zdn)"><Zdn1></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>-</text><a link="sa_zdn4" hover="Fourth scalable vector register of a multi-vector sequence (field Zdn)"><Zdn4></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text> </text><text>}</text><text>, </text><text>{</text><text> </text><a link="sa_zdn1_1" hover="First scalable vector register of a multi-vector sequence (field Zdn)"><Zdn1></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>-</text><a link="sa_zdn4" hover="Fourth scalable vector register of a multi-vector sequence (field Zdn)"><Zdn4></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text> </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-MZ.ZZV-4x1" mylink="ADD-MZ.ZZV-4x1" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn:'00');
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
|
||||
constant integer nreg = 4;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="add_mz_zzv_2x1" symboldefcount="1">
|
||||
<symbol link="sa_zdn1"><Zdn1></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<docvars>
|
||||
<docvar key="ldstruct-regcount" value="to-2reg" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the two registers variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zdn" times 2.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_mz_zzv_4x1" symboldefcount="2">
|
||||
<symbol link="sa_zdn1_1"><Zdn1></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<docvars>
|
||||
<docvar key="ldstruct-regcount" value="to-4reg" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the four registers variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zdn" times 4.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_mz_zzv_2x1, add_mz_zzv_4x1" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="add_mz_zzv_4x1" symboldefcount="1">
|
||||
<symbol link="sa_zdn4"><Zdn4></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zdn" times 4 plus 3.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_mz_zzv_2x1" symboldefcount="1">
|
||||
<symbol link="sa_zdn2"><Zdn2></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zdn" times 2 plus 1.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_mz_zzv_2x1, add_mz_zzv_4x1" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-MZ.ZZV-2x1" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEEnabled()">CheckStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
array [0..3] of bits(VL) results;
|
||||
|
||||
for r = 0 to nreg-1
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn+r, VL];
|
||||
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(esize) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[results[r], e, esize] = element1 + element2;
|
||||
|
||||
for r = 0 to nreg-1
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn+r, VL] = results[r];</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
176
spec/arm64_xml/add_z_p_zz.xml
Normal file
176
spec/arm64_xml/add_z_p_zz.xml
Normal file
@@ -0,0 +1,176 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="add_z_p_zz" title="ADD (vectors, predicated)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<heading>ADD (vectors, predicated)</heading>
|
||||
<desc>
|
||||
<brief>Add vectors (predicated)</brief>
|
||||
<description>
|
||||
<para>Add active elements of the second source vector to corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>True</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<takes_movprfx>True</takes_movprfx>
|
||||
<takes_pred_movprfx>True</takes_pred_movprfx>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ADD-Z.P.ZZ-_">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="18" width="2" name="opc<2:1>" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" name="opc<0>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="Pg" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zdn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="add_z_p_zz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADD </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/M, </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-Z.P.ZZ-_" mylink="ADD-Z.P.ZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="add_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zdn"><Zdn></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="add_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_pg"><Pg></symbol>
|
||||
<account encodedin="Pg">
|
||||
<intro>
|
||||
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-Z.P.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = if <a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(esize) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
|
||||
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
|
||||
else
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
188
spec/arm64_xml/add_z_zi.xml
Normal file
188
spec/arm64_xml/add_z_zi.xml
Normal file
@@ -0,0 +1,188 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="add_z_zi" title="ADD (immediate)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<heading>ADD (immediate)</heading>
|
||||
<desc>
|
||||
<brief>Add immediate (unpredicated)</brief>
|
||||
<description>
|
||||
<para>Add an unsigned immediate to each element of the source vector, and destructively place the results in the corresponding elements of the source vector. This instruction is unpredicated.</para>
|
||||
<para>The immediate is an unsigned value in the range 0 to 255, and for element widths of 16 bits or higher it may also be a positive multiple of 256 in the range 256 to 65280.</para>
|
||||
<para>The immediate is encoded in 8 bits with an optional left shift by 8. The preferred disassembly when the shift option is specified is "<syntax>#<uimm8>, LSL #8</syntax>". However an assembler and disassembler may also allow use of the shifted 16-bit value unless the immediate is 0 and the shift amount is 8, which must be unambiguously described as "<syntax>#0, LSL #8</syntax>".</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<takes_movprfx>True</takes_movprfx>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ADD-Z.ZI-_">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="3" settings="3">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="18" width="2" name="opc<2:1>" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" name="opc<0>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="2" settings="2">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="13" name="sh" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="12" width="8" name="imm8" usename="1">
|
||||
<c colspan="8"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zdn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="add_z_zi_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADD </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, #</text><a link="sa_imm" hover="Unsigned immediate [0-255] (field "imm8")"><imm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional left shift to apply to the immediate, default LSL #0 (field "sh") [LSL #0,LSL #8]"><shift></a><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-Z.ZI-_" mylink="ADD-Z.ZI-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size:sh == '001' then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer imm = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm8);
|
||||
if sh == '1' then imm = imm << 8;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="add_z_zi_" symboldefcount="1">
|
||||
<symbol link="sa_zdn"><Zdn></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_z_zi_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="add_z_zi_" symboldefcount="1">
|
||||
<symbol link="sa_imm"><imm></symbol>
|
||||
<account encodedin="imm8">
|
||||
<intro>
|
||||
<para>Is an unsigned immediate in the range 0 to 255, encoded in the "imm8" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_z_zi_" symboldefcount="1">
|
||||
<symbol link="sa_shift"><shift></symbol>
|
||||
<definition encodedin="sh">
|
||||
<intro>Is the optional left shift to apply to the immediate, defaulting to LSL #0 and </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">sh</entry>
|
||||
<entry class="symbol"><shift></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">LSL #0</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">LSL #8</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-Z.ZI-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + imm;
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
167
spec/arm64_xml/add_z_zz.xml
Normal file
167
spec/arm64_xml/add_z_zz.xml
Normal file
@@ -0,0 +1,167 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="add_z_zz" title="ADD (vectors, unpredicated)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<heading>ADD (vectors, unpredicated)</heading>
|
||||
<desc>
|
||||
<brief>Add vectors (unpredicated)</brief>
|
||||
<description>
|
||||
<para>Add all elements of the second source vector to corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. This instruction is unpredicated.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ADD-Z.ZZ-_">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="12" width="2" name="opc<2:1>" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" name="opc<0>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="add_z_zz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADD </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-Z.ZZ-_" mylink="ADD-Z.ZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="add_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zd"><Zd></symbol>
|
||||
<account encodedin="Zd">
|
||||
<intro>
|
||||
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="add_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-Z.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(esize) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
297
spec/arm64_xml/add_za_zw.xml
Normal file
297
spec/arm64_xml/add_za_zw.xml
Normal file
@@ -0,0 +1,297 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="add_za_zw" title="ADD (array accumulators)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<heading>ADD (array accumulators)</heading>
|
||||
<desc>
|
||||
<brief>Add multi-vector to ZA array vector accumulators</brief>
|
||||
<description>
|
||||
<para>The instruction operates on two or four ZA single-vector groups.</para>
|
||||
<para>Destructively add all elements of the two or four source vectors to the corresponding elements of the two or four ZA single-vector groups. The vector numbers forming the single-vector group within each half or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo half or quarter the number of ZA array vectors.</para>
|
||||
<para>The <arm-defined-word>vector group</arm-defined-word> symbol, <syntax>VGx2</syntax> or <syntax>VGx4</syntax>, indicates that the ZA operand consists of two or four ZA single-vector groups respectively. The <arm-defined-word>vector group</arm-defined-word> symbol is preferred for disassembly, but optional in assembler source code.</para>
|
||||
<para>This instruction is unpredicated.</para>
|
||||
<para>ID_AA64SMFR0_EL1.I16I64 indicates whether the 64-bit integer variant is implemented.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<sm_policy>SM_1_only</sm_policy>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<classesintro count="2">
|
||||
<txt>It has encodings from 2 classes:</txt>
|
||||
<a href="#iclass_sme_vgx2_single">Two ZA single-vectors</a>
|
||||
<txt> and </txt>
|
||||
<a href="#iclass_sme_vgx4_single">Four ZA single-vectors</a>
|
||||
</classesintro>
|
||||
<iclass name="Two ZA single-vectors" oneof="2" id="iclass_sme_vgx2_single" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
<docvar key="sme-multireg" value="sme-vgx2-single" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="ADD-ZA.ZW-2x2" tworows="1">
|
||||
<box hibit="31" width="9" settings="9">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="22" name="sz" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="21" width="7" settings="7">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="14" width="2" name="Rv" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" settings="3">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="4" name="Zm" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
<box hibit="5" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="3" name="S" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="2" width="3" name="off3" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="add_za_zw_2x2" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
<docvar key="sme-multireg" value="sme-vgx2-single" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADD ZA.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field "off3")"><offs></a><a>{, VGx2}</a><text>], </text><text>{</text><text> </text><a link="sa_zm1" hover="First scalable vector register of a multi-vector sequence (field Zm)"><Zm1></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>-</text><a link="sa_zm2" hover="Second scalable vector register of a multi-vector sequence (field Zm)"><Zm2></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text> </text><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-ZA.ZW-2x2" mylink="ADD-ZA.ZW-2x2" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
|
||||
if sz == '1' && !<a link="impl-aarch64.HaveSMEI16I64.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>() then UNDEFINED;
|
||||
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
|
||||
constant integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm:'0');
|
||||
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
|
||||
constant integer nreg = 2;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
<iclass name="Four ZA single-vectors" oneof="2" id="iclass_sme_vgx4_single" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
<docvar key="sme-multireg" value="sme-vgx4-single" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="ADD-ZA.ZW-4x4" tworows="1">
|
||||
<box hibit="31" width="9" settings="9">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="22" name="sz" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="21" width="7" settings="7">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="14" width="2" name="Rv" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" settings="3">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="3" name="Zm" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="6" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="3" name="S" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="2" width="3" name="off3" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="add_za_zw_4x4" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
<docvar key="sme-multireg" value="sme-vgx4-single" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADD ZA.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field "off3")"><offs></a><a>{, VGx4}</a><text>], </text><text>{</text><text> </text><a link="sa_zm1_1" hover="First scalable vector register of a multi-vector sequence (field Zm)"><Zm1></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>-</text><a link="sa_zm4" hover="Fourth scalable vector register of a multi-vector sequence (field Zm)"><Zm4></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text> </text><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-ZA.ZW-4x4" mylink="ADD-ZA.ZW-4x4" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
|
||||
if sz == '1' && !<a link="impl-aarch64.HaveSMEI16I64.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>() then UNDEFINED;
|
||||
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
|
||||
constant integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm:'00');
|
||||
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
|
||||
constant integer nreg = 4;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="add_za_zw_2x2, add_za_zw_4x4" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="sz">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">sz</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zw_2x2, add_za_zw_4x4" symboldefcount="1">
|
||||
<symbol link="sa_wv"><Wv></symbol>
|
||||
<account encodedin="Rv">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zw_2x2, add_za_zw_4x4" symboldefcount="1">
|
||||
<symbol link="sa_offs"><offs></symbol>
|
||||
<account encodedin="off3">
|
||||
<intro>
|
||||
<para>Is the vector select offset, in the range 0 to 7, encoded in the "off3" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zw_2x2" symboldefcount="1">
|
||||
<symbol link="sa_zm1"><Zm1></symbol>
|
||||
<account encodedin="Zm">
|
||||
<docvars>
|
||||
<docvar key="sme-multireg" value="sme-vgx2-single" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the two ZA single-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zm" times 2.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zw_4x4" symboldefcount="2">
|
||||
<symbol link="sa_zm1_1"><Zm1></symbol>
|
||||
<account encodedin="Zm">
|
||||
<docvars>
|
||||
<docvar key="sme-multireg" value="sme-vgx4-single" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the four ZA single-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zm" times 4.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zw_4x4" symboldefcount="1">
|
||||
<symbol link="sa_zm4"><Zm4></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zm" times 4 plus 3.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zw_2x2" symboldefcount="1">
|
||||
<symbol link="sa_zm2"><Zm2></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zm" times 2 plus 1.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-ZA.ZW-2x2" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEAndZAEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
integer vectors = VL DIV 8;
|
||||
integer vstride = vectors DIV nreg;
|
||||
bits(32) vbase = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[v, 32];
|
||||
integer vec = (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vbase) + offset) MOD vstride;
|
||||
bits(VL) result;
|
||||
|
||||
for r = 0 to nreg-1
|
||||
bits(VL) operand1 = <a link="impl-aarch64.ZAvector.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAvector[integer index, integer width]">ZAvector</a>[vec, VL];
|
||||
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m+r, VL];
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(esize) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
|
||||
<a link="impl-aarch64.ZAvector.write.2" file="shared_pseudocode.xml" hover="accessor: ZAvector[integer index, integer width] = bits(width) value">ZAvector</a>[vec, VL] = result;
|
||||
vec = vec + vstride;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
292
spec/arm64_xml/add_za_zzv.xml
Normal file
292
spec/arm64_xml/add_za_zzv.xml
Normal file
@@ -0,0 +1,292 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="add_za_zzv" title="ADD (array results, multiple and single vector)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<heading>ADD (array results, multiple and single vector)</heading>
|
||||
<desc>
|
||||
<brief>Add replicated single vector to multi-vector with ZA array vector results</brief>
|
||||
<description>
|
||||
<para>The instruction operates on two or four ZA single-vector groups.</para>
|
||||
<para>Add all corresponding elements of the second source vector and the two or four first source vectors and place the results in the corresponding elements of the two or four ZA single-vector groups. The vector numbers forming the single-vector group within each half or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo half or quarter the number of ZA array vectors.</para>
|
||||
<para>The <arm-defined-word>vector group</arm-defined-word> symbol, <syntax>VGx2</syntax> or <syntax>VGx4</syntax>, indicates that the ZA operand consists of two or four ZA single-vector groups respectively. The <arm-defined-word>vector group</arm-defined-word> symbol is preferred for disassembly, but optional in assembler source code.</para>
|
||||
<para>This instruction is unpredicated.</para>
|
||||
<para>ID_AA64SMFR0_EL1.I16I64 indicates whether the 64-bit integer variant is implemented.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<sm_policy>SM_1_only</sm_policy>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<classesintro count="2">
|
||||
<txt>It has encodings from 2 classes:</txt>
|
||||
<a href="#iclass_sme_vgx2_single">Two ZA single-vectors</a>
|
||||
<txt> and </txt>
|
||||
<a href="#iclass_sme_vgx4_single">Four ZA single-vectors</a>
|
||||
</classesintro>
|
||||
<iclass name="Two ZA single-vectors" oneof="2" id="iclass_sme_vgx2_single" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
<docvar key="sme-multireg" value="sme-vgx2-single" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="ADD-ZA.ZZV-2x1" tworows="1">
|
||||
<box hibit="31" width="9" settings="9">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="sz" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="21" width="2" settings="2">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="19" width="4" name="Zm" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
<box hibit="15" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="14" width="2" name="Rv" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" settings="3">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="3" name="S" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="2" width="3" name="off3" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="add_za_zzv_2x1" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
<docvar key="sme-multireg" value="sme-vgx2-single" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADD ZA.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field "off3")"><offs></a><a>{, VGx2}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence, encoded as "Zn" (field Zn)"><Zn1></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>-</text><a link="sa_zn2" hover="Second scalable vector register of a multi-vector sequence (field Zn)"><Zn2></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text> </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-ZA.ZZV-2x1" mylink="ADD-ZA.ZZV-2x1" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
|
||||
if sz == '1' && !<a link="impl-aarch64.HaveSMEI16I64.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>() then UNDEFINED;
|
||||
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
|
||||
constant integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
|
||||
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
|
||||
constant integer nreg = 2;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
<iclass name="Four ZA single-vectors" oneof="2" id="iclass_sme_vgx4_single" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
<docvar key="sme-multireg" value="sme-vgx4-single" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="ADD-ZA.ZZV-4x1" tworows="1">
|
||||
<box hibit="31" width="9" settings="9">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="sz" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="21" width="2" settings="2">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="19" width="4" name="Zm" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
<box hibit="15" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="14" width="2" name="Rv" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" settings="3">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="3" name="S" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="2" width="3" name="off3" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="add_za_zzv_4x1" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
<docvar key="sme-multireg" value="sme-vgx4-single" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADD ZA.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field "off3")"><offs></a><a>{, VGx4}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence, encoded as "Zn" (field Zn)"><Zn1></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>-</text><a link="sa_zn4" hover="Fourth scalable vector register of a multi-vector sequence (field Zn)"><Zn4></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text> </text><text>}</text><text>, </text><a link="sa_zm" hover="Second source scalable vector register Z0-Z15 (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-ZA.ZZV-4x1" mylink="ADD-ZA.ZZV-4x1" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
|
||||
if sz == '1' && !<a link="impl-aarch64.HaveSMEI16I64.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>() then UNDEFINED;
|
||||
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
|
||||
constant integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('0':Zm);
|
||||
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
|
||||
constant integer nreg = 4;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="add_za_zzv_2x1, add_za_zzv_4x1" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="sz">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">sz</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zzv_2x1, add_za_zzv_4x1" symboldefcount="1">
|
||||
<symbol link="sa_wv"><Wv></symbol>
|
||||
<account encodedin="Rv">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zzv_2x1, add_za_zzv_4x1" symboldefcount="1">
|
||||
<symbol link="sa_offs"><offs></symbol>
|
||||
<account encodedin="off3">
|
||||
<intro>
|
||||
<para>Is the vector select offset, in the range 0 to 7, encoded in the "off3" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zzv_2x1, add_za_zzv_4x1" symboldefcount="1">
|
||||
<symbol link="sa_zn1"><Zn1></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn".</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zzv_4x1" symboldefcount="1">
|
||||
<symbol link="sa_zn4"><Zn4></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zn" plus 3 modulo 32.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zzv_2x1" symboldefcount="1">
|
||||
<symbol link="sa_zn2"><Zn2></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zn" plus 1 modulo 32.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zzv_2x1, add_za_zzv_4x1" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register Z0-Z15, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-ZA.ZZV-2x1" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEAndZAEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
integer vectors = VL DIV 8;
|
||||
integer vstride = vectors DIV nreg;
|
||||
bits(32) vbase = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[v, 32];
|
||||
integer vec = (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vbase) + offset) MOD vstride;
|
||||
bits(VL) result;
|
||||
|
||||
for r = 0 to nreg-1
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[(n+r) MOD 32, VL];
|
||||
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(esize) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
|
||||
<a link="impl-aarch64.ZAvector.write.2" file="shared_pseudocode.xml" hover="accessor: ZAvector[integer index, integer width] = bits(width) value">ZAvector</a>[vec, VL] = result;
|
||||
vec = vec + vstride;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
340
spec/arm64_xml/add_za_zzw.xml
Normal file
340
spec/arm64_xml/add_za_zzw.xml
Normal file
@@ -0,0 +1,340 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="add_za_zzw" title="ADD (array results, multiple vectors)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
</docvars>
|
||||
<heading>ADD (array results, multiple vectors)</heading>
|
||||
<desc>
|
||||
<brief>Add multi-vector to multi-vector with ZA array vector results</brief>
|
||||
<description>
|
||||
<para>The instruction operates on two or four ZA single-vector groups.</para>
|
||||
<para>Add all corresponding elements of the two or four second source vectors and first source vectors and place the results in the corresponding elements of the two or four ZA single-vector groups. The vector numbers forming the single-vector group within each half or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo half or quarter the number of ZA array vectors.</para>
|
||||
<para>The <arm-defined-word>vector group</arm-defined-word> symbol, <syntax>VGx2</syntax> or <syntax>VGx4</syntax>, indicates that the ZA operand consists of two or four ZA single-vector groups respectively. The <arm-defined-word>vector group</arm-defined-word> symbol is preferred for disassembly, but optional in assembler source code.</para>
|
||||
<para>This instruction is unpredicated.</para>
|
||||
<para>ID_AA64SMFR0_EL1.I16I64 indicates whether the 64-bit integer variant is implemented.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<sm_policy>SM_1_only</sm_policy>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<classesintro count="2">
|
||||
<txt>It has encodings from 2 classes:</txt>
|
||||
<a href="#iclass_sme_vgx2_single">Two ZA single-vectors</a>
|
||||
<txt> and </txt>
|
||||
<a href="#iclass_sme_vgx4_single">Four ZA single-vectors</a>
|
||||
</classesintro>
|
||||
<iclass name="Two ZA single-vectors" oneof="2" id="iclass_sme_vgx2_single" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
<docvar key="sme-multireg" value="sme-vgx2-single" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="ADD-ZA.ZZW-2x2" tworows="1">
|
||||
<box hibit="31" width="9" settings="9">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="22" name="sz" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="4" name="Zm" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
<box hibit="16" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="14" width="2" name="Rv" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" settings="3">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="4" name="Zn" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
<box hibit="5" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="3" name="S" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="2" width="3" name="off3" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="add_za_zzw_2x2" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
<docvar key="sme-multireg" value="sme-vgx2-single" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADD ZA.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field "off3")"><offs></a><a>{, VGx2}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1" hover="First scalable vector register of a multi-vector sequence (field Zn)"><Zn1></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>-</text><a link="sa_zn2" hover="Second scalable vector register of a multi-vector sequence (field Zn)"><Zn2></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text> </text><text>}</text><text>, </text><text>{</text><text> </text><a link="sa_zm1" hover="First scalable vector register of a multi-vector sequence (field Zm)"><Zm1></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>-</text><a link="sa_zm2" hover="Second scalable vector register of a multi-vector sequence (field Zm)"><Zm2></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text> </text><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-ZA.ZZW-2x2" mylink="ADD-ZA.ZZW-2x2" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
|
||||
if sz == '1' && !<a link="impl-aarch64.HaveSMEI16I64.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>() then UNDEFINED;
|
||||
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
|
||||
constant integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn:'0');
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm:'0');
|
||||
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
|
||||
constant integer nreg = 2;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
<iclass name="Four ZA single-vectors" oneof="2" id="iclass_sme_vgx4_single" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
<docvar key="sme-multireg" value="sme-vgx4-single" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SME2" feature="FEAT_SME2" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="ADD-ZA.ZZW-4x4" tworows="1">
|
||||
<box hibit="31" width="9" settings="9">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="22" name="sz" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="3" name="Zm" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="17" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="14" width="2" name="Rv" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" settings="3">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="3" name="Zn" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="6" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="3" name="S" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="2" width="3" name="off3" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="add_za_zzw_4x4" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADD" />
|
||||
<docvar key="sme-multireg" value="sme-vgx4-single" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADD ZA.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field "off3")"><offs></a><a>{, VGx4}</a><text>], </text><text>{</text><text> </text><a link="sa_zn1_1" hover="First scalable vector register of a multi-vector sequence (field Zn)"><Zn1></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>-</text><a link="sa_zn4" hover="Fourth scalable vector register of a multi-vector sequence (field Zn)"><Zn4></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text> </text><text>}</text><text>, </text><text>{</text><text> </text><a link="sa_zm1_1" hover="First scalable vector register of a multi-vector sequence (field Zm)"><Zm1></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>-</text><a link="sa_zm4" hover="Fourth scalable vector register of a multi-vector sequence (field Zm)"><Zm4></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text> </text><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-ZA.ZZW-4x4" mylink="ADD-ZA.ZZW-4x4" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2()">HaveSME2</a>() then UNDEFINED;
|
||||
if sz == '1' && !<a link="impl-aarch64.HaveSMEI16I64.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>() then UNDEFINED;
|
||||
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
|
||||
constant integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn:'00');
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm:'00');
|
||||
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
|
||||
constant integer nreg = 4;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="add_za_zzw_2x2, add_za_zzw_4x4" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="sz">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">sz</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zzw_2x2, add_za_zzw_4x4" symboldefcount="1">
|
||||
<symbol link="sa_wv"><Wv></symbol>
|
||||
<account encodedin="Rv">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zzw_2x2, add_za_zzw_4x4" symboldefcount="1">
|
||||
<symbol link="sa_offs"><offs></symbol>
|
||||
<account encodedin="off3">
|
||||
<intro>
|
||||
<para>Is the vector select offset, in the range 0 to 7, encoded in the "off3" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zzw_2x2" symboldefcount="1">
|
||||
<symbol link="sa_zn1"><Zn1></symbol>
|
||||
<account encodedin="Zn">
|
||||
<docvars>
|
||||
<docvar key="sme-multireg" value="sme-vgx2-single" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the two ZA single-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 2.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zzw_4x4" symboldefcount="2">
|
||||
<symbol link="sa_zn1_1"><Zn1></symbol>
|
||||
<account encodedin="Zn">
|
||||
<docvars>
|
||||
<docvar key="sme-multireg" value="sme-vgx4-single" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the four ZA single-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zn" times 4.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zzw_4x4" symboldefcount="1">
|
||||
<symbol link="sa_zn4"><Zn4></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zn" times 4 plus 3.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zzw_2x2" symboldefcount="1">
|
||||
<symbol link="sa_zn2"><Zn2></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zn" times 2 plus 1.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zzw_2x2" symboldefcount="1">
|
||||
<symbol link="sa_zm1"><Zm1></symbol>
|
||||
<account encodedin="Zm">
|
||||
<docvars>
|
||||
<docvar key="sme-multireg" value="sme-vgx2-single" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the two ZA single-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zm" times 2.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zzw_4x4" symboldefcount="2">
|
||||
<symbol link="sa_zm1_1"><Zm1></symbol>
|
||||
<account encodedin="Zm">
|
||||
<docvars>
|
||||
<docvar key="sme-multireg" value="sme-vgx4-single" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the four ZA single-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zm" times 4.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zzw_4x4" symboldefcount="1">
|
||||
<symbol link="sa_zm4"><Zm4></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zm" times 4 plus 3.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="add_za_zzw_2x2" symboldefcount="1">
|
||||
<symbol link="sa_zm2"><Zm2></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zm" times 2 plus 1.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADD-ZA.ZZW-2x2" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEAndZAEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
integer vectors = VL DIV 8;
|
||||
integer vstride = vectors DIV nreg;
|
||||
bits(32) vbase = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[v, 32];
|
||||
integer vec = (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vbase) + offset) MOD vstride;
|
||||
bits(VL) result;
|
||||
|
||||
for r = 0 to nreg-1
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n+r, VL];
|
||||
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m+r, VL];
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(esize) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
|
||||
<a link="impl-aarch64.ZAvector.write.2" file="shared_pseudocode.xml" hover="accessor: ZAvector[integer index, integer width] = bits(width) value">ZAvector</a>[vec, VL] = result;
|
||||
vec = vec + vstride;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
152
spec/arm64_xml/addg.xml
Normal file
152
spec/arm64_xml/addg.xml
Normal file
@@ -0,0 +1,152 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ADDG" title="ADDG -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDG" />
|
||||
</docvars>
|
||||
<heading>ADDG</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Add with Tag</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Add with Tag adds an immediate value scaled by the Tag granule to the address in the source register, modifies the Logical Address Tag of the address using an immediate value, and writes the result to the destination register. Tags specified in GCR_EL1.Exclude are excluded from the possible outputs when modifying the Logical Address Tag.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Integer" oneof="1" id="iclass_general" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDG" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="ARMv8.5" feature="FEAT_MTE" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/tags/mcaddtag" tworows="1">
|
||||
<box hibit="31" name="sf" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="30" name="op" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="29" name="S" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="6" settings="6">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="22" name="o2" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" width="6" name="uimm6" usename="1">
|
||||
<c colspan="6"></c>
|
||||
</box>
|
||||
<box hibit="15" width="2" name="op3" usename="1" settings="2" psbits="xx">
|
||||
<c>(0)</c>
|
||||
<c>(0)</c>
|
||||
</box>
|
||||
<box hibit="13" width="4" name="uimm4" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Xn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Xd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ADDG_64_addsub_immtags" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDG" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADDG </text><a link="sa_xd_sp" hover="64-bit destination general-purpose register or SP (field "Xd")"><Xd|SP></a><text>, </text><a link="sa_xn_sp" hover="64-bit source general-purpose register or SP (field "Xn")"><Xn|SP></a><text>, #</text><a link="sa_uimm6" hover="Unsigned immediate, multiple of 16 [0-1008] (field "uimm6")"><uimm6></a><text>, #</text><a link="sa_uimm4" hover="Unsigned immediate [0-15] (field "uimm4")"><uimm4></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/tags/mcaddtag" mylink="aarch64.instrs.integer.tags.mcaddtag" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveMTEExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveMTEExt()">HaveMTEExt</a>() then UNDEFINED;
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Xn);
|
||||
bits(4) tag_offset = uimm4;
|
||||
bits(64) offset = <a link="impl-shared.LSL.2" file="shared_pseudocode.xml" hover="function: bits(N) LSL(bits(N) x, integer shift)">LSL</a>(<a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(uimm6, 64), <a link="LOG2_TAG_GRANULE" file="shared_pseudocode.xml" hover="constant integer LOG2_TAG_GRANULE = 4">LOG2_TAG_GRANULE</a>);
|
||||
boolean ADD = TRUE;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ADDG_64_addsub_immtags" symboldefcount="1">
|
||||
<symbol link="sa_xd_sp"><Xd|SP></symbol>
|
||||
<account encodedin="Xd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Xd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDG_64_addsub_immtags" symboldefcount="1">
|
||||
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
||||
<account encodedin="Xn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Xn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDG_64_addsub_immtags" symboldefcount="1">
|
||||
<symbol link="sa_uimm6"><uimm6></symbol>
|
||||
<account encodedin="uimm6">
|
||||
<intro>
|
||||
<para>Is an unsigned immediate, a multiple of 16 in the range 0 to 1008, encoded in the "uimm6" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDG_64_addsub_immtags" symboldefcount="1">
|
||||
<symbol link="sa_uimm4"><uimm4></symbol>
|
||||
<account encodedin="uimm4">
|
||||
<intro>
|
||||
<para>Is an unsigned immediate, in the range 0 to 15, encoded in the "uimm4" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/tags/mcaddtag" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(64) operand1 = if n == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[] else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
||||
bits(4) start_tag = <a link="AArch64.AllocationTagFromAddress.1" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.AllocationTagFromAddress(bits(64) tagged_address)">AArch64.AllocationTagFromAddress</a>(operand1);
|
||||
bits(16) exclude = GCR_EL1.Exclude;
|
||||
bits(64) result;
|
||||
bits(4) rtag;
|
||||
|
||||
if <a link="AArch64.AllocationTagAccessIsEnabled.1" file="shared_pseudocode.xml" hover="function: boolean AArch64.AllocationTagAccessIsEnabled(bits(2) el)">AArch64.AllocationTagAccessIsEnabled</a>(PSTATE.EL) then
|
||||
rtag = <a link="AArch64.ChooseNonExcludedTag.3" file="shared_pseudocode.xml" hover="function: bits(4) AArch64.ChooseNonExcludedTag(bits(4) tag_in, bits(4) offset_in, bits(16) exclude)">AArch64.ChooseNonExcludedTag</a>(start_tag, tag_offset, exclude);
|
||||
else
|
||||
rtag = '0000';
|
||||
|
||||
if ADD then
|
||||
(result, -) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(operand1, offset, '0');
|
||||
else
|
||||
(result, -) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(operand1, NOT(offset), '1');
|
||||
|
||||
result = <a link="AArch64.AddressWithAllocationTag.2" file="shared_pseudocode.xml" hover="function: bits(64) AArch64.AddressWithAllocationTag(bits(64) address, bits(4) allocation_tag)">AArch64.AddressWithAllocationTag</a>(result, rtag);
|
||||
|
||||
if d == 31 then
|
||||
<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = result;
|
||||
else
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
266
spec/arm64_xml/addha_za_pp_z.xml
Normal file
266
spec/arm64_xml/addha_za_pp_z.xml
Normal file
@@ -0,0 +1,266 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="addha_za_pp_z" title="ADDHA" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDHA" />
|
||||
</docvars>
|
||||
<heading>ADDHA</heading>
|
||||
<desc>
|
||||
<brief>Add horizontally vector elements to ZA tile</brief>
|
||||
<description>
|
||||
<para>Add each element of the source vector to the corresponding active element of each horizontal slice of a ZA tile. The tile elements are predicated by a pair of governing predicates. An element of a horizontal slice is considered active if its corresponding element in the second governing predicate is TRUE and the element corresponding to its horizontal slice number in the first governing predicate is TRUE. Inactive elements in the destination tile remain unmodified.</para>
|
||||
<para>ID_AA64SMFR0_EL1.I16I64 indicates whether the 64-bit integer variant is implemented.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>True</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<sm_policy>SM_1_only</sm_policy>
|
||||
<is_gov_pred_pair>True</is_gov_pred_pair>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<classesintro count="2">
|
||||
<txt>It has encodings from 2 classes:</txt>
|
||||
<a href="#iclass_per_word">32-bit</a>
|
||||
<txt> and </txt>
|
||||
<a href="#iclass_per_doubleword">64-bit</a>
|
||||
</classesintro>
|
||||
<iclass name="32-bit" oneof="2" id="iclass_per_word" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="asimdimm-datatype" value="per-word" />
|
||||
<docvar key="instr-class" value="mortlach" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDHA" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SME" feature="FEAT_SME" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="ADDHA-ZA.PP.Z-32" tworows="1">
|
||||
<box hibit="31" width="2" settings="2">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="29" width="7" settings="7">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="22" name="op" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="19" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" name="V" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="3" name="Pm" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="Pn" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="3" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="2" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="1" width="2" name="ZAda" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="addha_za_pp_z_32" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="asimdimm-datatype" value="per-word" />
|
||||
<docvar key="instr-class" value="mortlach" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDHA" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADDHA </text><a link="sa_zada" hover="ZA tile ZA0-ZA3 (field "ZAda")"><ZAda></a><text>.S, </text><a link="sa_pn" hover="First governing scalable predicate register P0-P7 (field "Pn")"><Pn></a><text>/M, </text><a link="sa_pm" hover="Second governing scalable predicate register P0-P7 (field "Pm")"><Pm></a><text>/M, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>.S</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDHA-ZA.PP.Z-32" mylink="ADDHA-ZA.PP.Z-32" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 32;
|
||||
integer a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pn);
|
||||
integer b = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pm);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer da = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(ZAda);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
<iclass name="64-bit" oneof="2" id="iclass_per_doubleword" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="asimdimm-datatype" value="per-doubleword" />
|
||||
<docvar key="instr-class" value="mortlach" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDHA" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SME_I16I64" feature="FEAT_SME_I16I64" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="ADDHA-ZA.PP.Z-64" tworows="1">
|
||||
<box hibit="31" width="2" settings="2">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="29" width="7" settings="7">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="22" name="op" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="21" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" name="V" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="3" name="Pm" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="Pn" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="3" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="2" width="3" name="ZAda" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="addha_za_pp_z_64" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="asimdimm-datatype" value="per-doubleword" />
|
||||
<docvar key="instr-class" value="mortlach" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDHA" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADDHA </text><a link="sa_zada_1" hover="ZA tile ZA0-ZA7 (field "ZAda")"><ZAda></a><text>.D, </text><a link="sa_pn" hover="First governing scalable predicate register P0-P7 (field "Pn")"><Pn></a><text>/M, </text><a link="sa_pm" hover="Second governing scalable predicate register P0-P7 (field "Pm")"><Pm></a><text>/M, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>.D</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDHA-ZA.PP.Z-64" mylink="ADDHA-ZA.PP.Z-64" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSMEI16I64.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>() then UNDEFINED;
|
||||
constant integer esize = 64;
|
||||
integer a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pn);
|
||||
integer b = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pm);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer da = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(ZAda);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="addha_za_pp_z_32" symboldefcount="1">
|
||||
<symbol link="sa_zada"><ZAda></symbol>
|
||||
<account encodedin="ZAda">
|
||||
<docvars>
|
||||
<docvar key="asimdimm-datatype" value="per-word" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 32-bit variant: is the name of the ZA tile ZA0-ZA3, encoded in the "ZAda" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addha_za_pp_z_64" symboldefcount="2">
|
||||
<symbol link="sa_zada_1"><ZAda></symbol>
|
||||
<account encodedin="ZAda">
|
||||
<docvars>
|
||||
<docvar key="asimdimm-datatype" value="per-doubleword" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 64-bit variant: is the name of the ZA tile ZA0-ZA7, encoded in the "ZAda" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addha_za_pp_z_32, addha_za_pp_z_64" symboldefcount="1">
|
||||
<symbol link="sa_pn"><Pn></symbol>
|
||||
<account encodedin="Pn">
|
||||
<intro>
|
||||
<para>Is the name of the first governing scalable predicate register P0-P7, encoded in the "Pn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addha_za_pp_z_32, addha_za_pp_z_64" symboldefcount="1">
|
||||
<symbol link="sa_pm"><Pm></symbol>
|
||||
<account encodedin="Pm">
|
||||
<intro>
|
||||
<para>Is the name of the second governing scalable predicate register P0-P7, encoded in the "Pm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addha_za_pp_z_32, addha_za_pp_z_64" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDHA-ZA.PP.Z-32" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEAndZAEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer dim = VL DIV esize;
|
||||
bits(PL) mask1 = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[a, PL];
|
||||
bits(PL) mask2 = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[b, PL];
|
||||
bits(VL) operand_src = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(dim*dim*esize) operand_acc = <a link="impl-aarch64.ZAtile.read.3" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAtile[integer tile, integer esize, integer width]">ZAtile</a>[da, esize, dim*dim*esize];
|
||||
bits(dim*dim*esize) result;
|
||||
|
||||
for col = 0 to dim-1
|
||||
bits(esize) element = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand_src, col, esize];
|
||||
for row = 0 to dim-1
|
||||
bits(esize) res = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand_acc, row*dim+col, esize];
|
||||
if (<a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask1, row, esize) &&
|
||||
<a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask2, col, esize)) then
|
||||
res = res + element;
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, row*dim+col, esize] = res;
|
||||
|
||||
<a link="impl-aarch64.ZAtile.write.3" file="shared_pseudocode.xml" hover="accessor: ZAtile[integer tile, integer esize, integer width] = bits(width) value">ZAtile</a>[da, esize, dim*dim*esize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
284
spec/arm64_xml/addhn_advsimd.xml
Normal file
284
spec/arm64_xml/addhn_advsimd.xml
Normal file
@@ -0,0 +1,284 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ADDHN_advsimd" title="ADDHN, ADDHN2 -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="advsimd-reguse" value="3reg-diff" />
|
||||
<docvar key="advsimd-type" value="simd" />
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDHN" />
|
||||
</docvars>
|
||||
<heading>ADDHN, ADDHN2</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Add returning High Narrow</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.</para>
|
||||
<para>The results are truncated. For rounded results, see <xref linkend="A64.instructions.RADDHN_advsimd">RADDHN</xref>.</para>
|
||||
<para>The <instruction>ADDHN</instruction> instruction writes the vector to the lower half of the destination register and clears the upper half, while the <instruction>ADDHN2</instruction> instruction writes the vector to the upper half of the destination register without affecting the other bits of the register.</para>
|
||||
<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Three registers, not all the same type" oneof="1" id="iclass_3reg_diff" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="advsimd-reguse" value="3reg-diff" />
|
||||
<docvar key="advsimd-type" value="simd" />
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDHN" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/disparate/add-sub/narrow" tworows="1">
|
||||
<box hibit="31" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="30" name="Q" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="29" name="U" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="2" name="opcode[3:2]" settings="2">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="13" name="o1" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="12" name="opcode[0]" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="11" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ADDHN_asimddiff_N" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="advsimd-reguse" value="3reg-diff" />
|
||||
<docvar key="advsimd-type" value="simd" />
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDHN" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADDHN</text><a link="sa_2" hover="Second and upper half specifier (field "Q")">{2}</a><text> </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_tb" hover="Arrangement specifier (field "size:Q") [2S,4H,4S,8B,8H,16B]"><Tb></a><text>, </text><a link="sa_vn" hover="First SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "size") [2D,4S,8H]"><Ta></a><text>, </text><a link="sa_vm" hover="Second SIMD&FP source register (field "Rm")"><Vm></a><text>.</text><a link="sa_ta" hover="Arrangement specifier (field "size") [2D,4S,8H]"><Ta></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/arithmetic/binary/disparate/add-sub/narrow" mylink="aarch64.instrs.vector.arithmetic.binary.disparate.add-sub.narrow" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
|
||||
if size == '11' then UNDEFINED;
|
||||
integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer datasize = 64;
|
||||
integer part = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Q);
|
||||
integer elements = datasize DIV esize;
|
||||
|
||||
boolean sub_op = (o1 == '1');
|
||||
boolean round = (U == '1');</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ADDHN_asimddiff_N" symboldefcount="1">
|
||||
<symbol link="sa_2">2</symbol>
|
||||
<definition encodedin="Q">
|
||||
<intro>Is the second and upper half specifier. If present it causes the operation to be performed on the upper 64 bits of the registers holding the narrower elements, and is </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">Q</entry>
|
||||
<entry class="symbol">2</entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">[absent]</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">[present]</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ADDHN_asimddiff_N" symboldefcount="1">
|
||||
<symbol link="sa_vd"><Vd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDHN_asimddiff_N" symboldefcount="1">
|
||||
<symbol link="sa_tb"><Tb></symbol>
|
||||
<definition encodedin="size:Q">
|
||||
<intro>Is an arrangement specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="3">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="bitfield">Q</entry>
|
||||
<entry class="symbol"><Tb></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">8B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">16B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">4H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">8H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">2S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">4S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="bitfield">x</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ADDHN_asimddiff_N" symboldefcount="1">
|
||||
<symbol link="sa_vn"><Vn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDHN_asimddiff_N" symboldefcount="1">
|
||||
<symbol link="sa_ta"><Ta></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is an arrangement specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><Ta></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">8H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">4S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">2D</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ADDHN_asimddiff_N" symboldefcount="1">
|
||||
<symbol link="sa_vm"><Vm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the name of the second SIMD&FP source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/arithmetic/binary/disparate/add-sub/narrow" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
|
||||
bits(2*datasize) operand1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 2*datasize];
|
||||
bits(2*datasize) operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, 2*datasize];
|
||||
bits(datasize) result;
|
||||
integer round_const = if round then 1 << (esize - 1) else 0;
|
||||
bits(2*esize) element1;
|
||||
bits(2*esize) element2;
|
||||
bits(2*esize) sum;
|
||||
|
||||
for e = 0 to elements-1
|
||||
element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 2*esize];
|
||||
element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 2*esize];
|
||||
if sub_op then
|
||||
sum = element1 - element2;
|
||||
else
|
||||
sum = element1 + element2;
|
||||
sum = sum + round_const;
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = sum<2*esize-1:esize>;
|
||||
|
||||
<a link="impl-aarch64.Vpart.write.3" file="shared_pseudocode.xml" hover="accessor: Vpart[integer n, integer part, integer width] = bits(width) value">Vpart</a>[d, part, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
207
spec/arm64_xml/addhnb_z_zz.xml
Normal file
207
spec/arm64_xml/addhnb_z_zz.xml
Normal file
@@ -0,0 +1,207 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="addhnb_z_zz" title="ADDHNB" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDHNB" />
|
||||
</docvars>
|
||||
<heading>ADDHNB</heading>
|
||||
<desc>
|
||||
<brief>Add narrow high part (bottom)</brief>
|
||||
<description>
|
||||
<para>Add each vector element of the first source vector to the corresponding vector element of the second source vector, and place the most significant half of the result in the even-numbered half-width destination elements, while setting the odd-numbered elements to zero. This instruction is unpredicated.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDHNB" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ADDHNB-Z.ZZ-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="12" name="S" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="11" name="R" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" name="T" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="addhnb_z_zz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDHNB" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADDHNB </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,H,S]"><T></a><text>, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.</text><a link="sa_tb" hover="Size specifier (field "size") [D,H,S]"><Tb></a><text>, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.</text><a link="sa_tb" hover="Size specifier (field "size") [D,H,S]"><Tb></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDHNB-Z.ZZ-_" mylink="ADDHNB-Z.ZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '00' then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="addhnb_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zd"><Zd></symbol>
|
||||
<account encodedin="Zd">
|
||||
<intro>
|
||||
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addhnb_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="addhnb_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addhnb_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_tb"><Tb></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><Tb></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="addhnb_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDHNB-Z.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
constant integer halfesize = esize DIV 2;
|
||||
|
||||
for e = 0 to elements-1
|
||||
integer element1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
|
||||
integer element2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
|
||||
integer res = (element1 + element2) >> halfesize;
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*e + 0, halfesize] = res<halfesize-1:0>;
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*e + 1, halfesize] = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(halfesize);
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
206
spec/arm64_xml/addhnt_z_zz.xml
Normal file
206
spec/arm64_xml/addhnt_z_zz.xml
Normal file
@@ -0,0 +1,206 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="addhnt_z_zz" title="ADDHNT" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDHNT" />
|
||||
</docvars>
|
||||
<heading>ADDHNT</heading>
|
||||
<desc>
|
||||
<brief>Add narrow high part (top)</brief>
|
||||
<description>
|
||||
<para>Add each vector element of the first source vector to the corresponding vector element of the second source vector, and place the most significant half of the result in the odd-numbered half-width destination elements, leaving the even-numbered elements unchanged. This instruction is unpredicated.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDHNT" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ADDHNT-Z.ZZ-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="12" name="S" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="11" name="R" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" name="T" usename="1" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="addhnt_z_zz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDHNT" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADDHNT </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,H,S]"><T></a><text>, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.</text><a link="sa_tb" hover="Size specifier (field "size") [D,H,S]"><Tb></a><text>, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.</text><a link="sa_tb" hover="Size specifier (field "size") [D,H,S]"><Tb></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDHNT-Z.ZZ-_" mylink="ADDHNT-Z.ZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '00' then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="addhnt_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zd"><Zd></symbol>
|
||||
<account encodedin="Zd">
|
||||
<intro>
|
||||
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addhnt_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="addhnt_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addhnt_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_tb"><Tb></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><Tb></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="addhnt_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDHNT-Z.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[d, VL];
|
||||
constant integer halfesize = esize DIV 2;
|
||||
|
||||
for e = 0 to elements-1
|
||||
integer element1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
|
||||
integer element2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize]);
|
||||
integer res = (element1 + element2) >> halfesize;
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, 2*e + 1, halfesize] = res<halfesize-1:0>;
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
191
spec/arm64_xml/addp_advsimd_pair.xml
Normal file
191
spec/arm64_xml/addp_advsimd_pair.xml
Normal file
@@ -0,0 +1,191 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ADDP_advsimd_pair" title="ADDP (scalar) -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDP" />
|
||||
</docvars>
|
||||
<heading>ADDP (scalar)</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Add Pair of elements (scalar)</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Add Pair of elements (scalar). This instruction adds two vector elements in the source SIMD&FP register and writes the scalar result into the destination SIMD&FP register.</para>
|
||||
<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Advanced SIMD" oneof="1" id="iclass_advsimd" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDP" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/vector/reduce/add/sisd">
|
||||
<box hibit="31" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="29" name="U" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" width="5" name="opcode" settings="5">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="11" width="2" settings="2">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ADDP_asisdpair_only" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDP" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADDP </text><a link="sa_v" hover="Destination width specifier (field "size") [D]"><V></a><a link="sa_d" hover="SIMD&FP destination register number (field "Rd")"><d></a><text>, </text><a link="sa_vn" hover="SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_t" hover="Source arrangement specifier (field "size") [2D]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/reduce/add/sisd" mylink="aarch64.instrs.vector.reduce.add.sisd" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
|
||||
if size != '11' then UNDEFINED;
|
||||
|
||||
integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer datasize = esize * 2;
|
||||
integer elements = 2;
|
||||
|
||||
<a link="ReduceOp" file="shared_pseudocode.xml" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp</a> op = <a link="ReduceOp_ADD" file="shared_pseudocode.xml" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_ADD</a>;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ADDP_asisdpair_only" symboldefcount="1">
|
||||
<symbol link="sa_v"><V></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the destination width specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><V></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">0x</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ADDP_asisdpair_only" symboldefcount="1">
|
||||
<symbol link="sa_d"><d></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the number of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDP_asisdpair_only" symboldefcount="1">
|
||||
<symbol link="sa_vn"><Vn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the name of the SIMD&FP source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDP_asisdpair_only" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the source arrangement specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">0x</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">2D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/reduce/add/sisd" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
|
||||
bits(datasize) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
|
||||
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, esize] = <a link="impl-aarch64.Reduce.3" file="shared_pseudocode.xml" hover="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</a>(op, operand, esize);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
212
spec/arm64_xml/addp_advsimd_vec.xml
Normal file
212
spec/arm64_xml/addp_advsimd_vec.xml
Normal file
@@ -0,0 +1,212 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ADDP_advsimd_vec" title="ADDP (vector) -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="advsimd-reguse" value="3reg-same" />
|
||||
<docvar key="advsimd-type" value="simd" />
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDP" />
|
||||
</docvars>
|
||||
<heading>ADDP (vector)</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Add Pairwise (vector)</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.</para>
|
||||
<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Three registers of the same type" oneof="1" id="iclass_3reg_same" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="advsimd-reguse" value="3reg-same" />
|
||||
<docvar key="advsimd-type" value="simd" />
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDP" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/uniform/add/wrapping/pair">
|
||||
<box hibit="31" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="30" name="Q" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="29" name="U" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="5" name="opcode" settings="5">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="10" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ADDP_asimdsame_only" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="advsimd-reguse" value="3reg-same" />
|
||||
<docvar key="advsimd-type" value="simd" />
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDP" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADDP </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [2D,2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_vn" hover="First SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [2D,2S,4H,4S,8B,8H,16B]"><T></a><text>, </text><a link="sa_vm" hover="Second SIMD&FP source register (field "Rm")"><Vm></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [2D,2S,4H,4S,8B,8H,16B]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/arithmetic/binary/uniform/add/wrapping/pair" mylink="aarch64.instrs.vector.arithmetic.binary.uniform.add.wrapping.pair" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
if size:Q == '110' then UNDEFINED;
|
||||
integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer datasize = if Q == '1' then 128 else 64;
|
||||
integer elements = datasize DIV esize;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ADDP_asimdsame_only" symboldefcount="1">
|
||||
<symbol link="sa_vd"><Vd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDP_asimdsame_only" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size:Q">
|
||||
<intro>Is an arrangement specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="3">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="bitfield">Q</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">8B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">16B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">4H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">8H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">2S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">4S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">2D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ADDP_asimdsame_only" symboldefcount="1">
|
||||
<symbol link="sa_vn"><Vn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDP_asimdsame_only" symboldefcount="1">
|
||||
<symbol link="sa_vm"><Vm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the name of the second SIMD&FP source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/arithmetic/binary/uniform/add/wrapping/pair" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
|
||||
bits(datasize) operand1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
|
||||
bits(datasize) operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, datasize];
|
||||
bits(datasize) result;
|
||||
bits(2*datasize) concat = operand2:operand1;
|
||||
bits(esize) element1;
|
||||
bits(esize) element2;
|
||||
|
||||
for e = 0 to elements-1
|
||||
element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, 2*e, esize];
|
||||
element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[concat, (2*e)+1, esize];
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 + element2;
|
||||
|
||||
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
184
spec/arm64_xml/addp_z_p_zz.xml
Normal file
184
spec/arm64_xml/addp_z_p_zz.xml
Normal file
@@ -0,0 +1,184 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="addp_z_p_zz" title="ADDP" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDP" />
|
||||
</docvars>
|
||||
<heading>ADDP</heading>
|
||||
<desc>
|
||||
<brief>Add pairwise</brief>
|
||||
<description>
|
||||
<para>Add pairs of adjacent elements within each source vector, and interleave the results from corresponding lanes. The interleaved result values are destructively placed in the first source vector.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>True</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<takes_movprfx>True</takes_movprfx>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDP" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ADDP-Z.P.ZZ-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="18" name="opc<1>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="17" name="opc<0>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" name="U" usename="1" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="15" width="3" settings="3">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="Pg" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zdn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="addp_z_p_zz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDP" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADDP </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/M, </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDP-Z.P.ZZ-_" mylink="ADDP-Z.P.ZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="addp_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zdn"><Zdn></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addp_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="addp_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_pg"><Pg></symbol>
|
||||
<account encodedin="Pg">
|
||||
<intro>
|
||||
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addp_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDP-Z.P.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = if <a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result;
|
||||
integer element1;
|
||||
integer element2;
|
||||
|
||||
for e = 0 to elements-1
|
||||
if !<a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
else
|
||||
if <a link="impl-aarch64.IsEven.1" file="shared_pseudocode.xml" hover="function: boolean IsEven(integer val)">IsEven</a>(e) then
|
||||
element1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e + 0, esize]);
|
||||
element2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e + 1, esize]);
|
||||
else
|
||||
element1 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e - 1, esize]);
|
||||
element2 = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e + 0, esize]);
|
||||
integer res = element1 + element2;
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = res<esize-1:0>;
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
125
spec/arm64_xml/addpl_r_ri.xml
Normal file
125
spec/arm64_xml/addpl_r_ri.xml
Normal file
@@ -0,0 +1,125 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="addpl_r_ri" title="ADDPL" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDPL" />
|
||||
</docvars>
|
||||
<heading>ADDPL</heading>
|
||||
<desc>
|
||||
<brief>Add multiple of predicate register size to scalar register</brief>
|
||||
<description>
|
||||
<para>Add the current predicate register size in bytes multiplied by an immediate in the range -32 to 31 to the 64-bit source general-purpose register or current stack pointer and place the result in the 64-bit destination general-purpose register or current stack pointer.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDPL" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ADDPL-R.RI-_">
|
||||
<box hibit="31" width="9" settings="9">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="op" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" width="6" name="imm6" usename="1">
|
||||
<c colspan="6"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="addpl_r_ri_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDPL" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADDPL </text><a link="sa_xd_sp" hover="64-bit destination general-purpose register or SP (field "Rd")"><Xd|SP></a><text>, </text><a link="sa_xn_sp" hover="64-bit source general-purpose register or SP (field "Rn")"><Xn|SP></a><text>, #</text><a link="sa_imm" hover="Signed immediate operand [-32-31] (field "imm6")"><imm></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDPL-R.RI-_" mylink="ADDPL-R.RI-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer imm = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(imm6);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="addpl_r_ri_" symboldefcount="1">
|
||||
<symbol link="sa_xd_sp"><Xd|SP></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addpl_r_ri_" symboldefcount="1">
|
||||
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addpl_r_ri_" symboldefcount="1">
|
||||
<symbol link="sa_imm"><imm></symbol>
|
||||
<account encodedin="imm6">
|
||||
<intro>
|
||||
<para>Is the signed immediate operand, in the range -32 to 31, encoded in the "imm6" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDPL-R.RI-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
bits(64) operand1 = if n == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[] else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
||||
bits(64) result = operand1 + (imm * (PL DIV 8));
|
||||
|
||||
if d == 31 then
|
||||
<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = result;
|
||||
else
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
215
spec/arm64_xml/addqv_z_p_z.xml
Normal file
215
spec/arm64_xml/addqv_z_p_z.xml
Normal file
@@ -0,0 +1,215 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="addqv_z_p_z" title="ADDQV" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDQV" />
|
||||
</docvars>
|
||||
<heading>ADDQV</heading>
|
||||
<desc>
|
||||
<brief>Unsigned add reduction of quadword vector segments</brief>
|
||||
<description>
|
||||
<para>Unsigned addition of the same element numbers from each 128-bit source vector segment, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as zero.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>True</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDQV" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SVE2p1" feature="FEAT_SVE2p1" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="ADDQV-Z.P.Z-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="4" settings="4">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="17" name="op" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" name="U" usename="1" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="15" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="Pg" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Vd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="addqv_z_p_z_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDQV" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADDQV </text><a link="sa_vd" hover="Destination SIMD&FP register (field "Vd")"><Vd></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size") [2D,4S,8H,16B]"><T></a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>.</text><a link="sa_tb" hover="Size specifier (field "size") [B,D,H,S]"><Tb></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDQV-Z.P.Z-_" mylink="ADDQV-Z.P.Z-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE2p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2p1()">HaveSVE2p1</a>() && !<a link="impl-aarch64.HaveSME2p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2p1()">HaveSME2p1</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd);
|
||||
boolean unsigned = TRUE;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="addqv_z_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_vd"><Vd></symbol>
|
||||
<account encodedin="Vd">
|
||||
<intro>
|
||||
<para>Is the name of the destination SIMD&FP register, encoded in the "Vd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addqv_z_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is an arrangement specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">16B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">8H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">4S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">2D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="addqv_z_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_pg"><Pg></symbol>
|
||||
<account encodedin="Pg">
|
||||
<intro>
|
||||
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addqv_z_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addqv_z_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_tb"><Tb></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><Tb></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDQV-Z.P.Z-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer segments = VL DIV 128;
|
||||
constant integer elempersegment = 128 DIV esize;
|
||||
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand = if <a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(128) result = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(128);
|
||||
bits(128) stmp = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(128);
|
||||
|
||||
integer dtmp;
|
||||
|
||||
for e = 0 to elempersegment-1
|
||||
dtmp = 0;
|
||||
for s = 0 to segments-1
|
||||
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, s * elempersegment + e, esize) then
|
||||
stmp = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, s, 128];
|
||||
dtmp = dtmp + <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[stmp, e, esize]);
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = dtmp<esize-1:0>;
|
||||
|
||||
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
356
spec/arm64_xml/adds_addsub_ext.xml
Normal file
356
spec/arm64_xml/adds_addsub_ext.xml
Normal file
@@ -0,0 +1,356 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ADDS_addsub_ext" title="ADDS (extended register) -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDS" />
|
||||
</docvars>
|
||||
<heading>ADDS (extended register)</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Add (extended register), setting flags</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Add (extended register), setting flags, adds a register value and a sign or zero-extended register value, followed by an optional left shift amount, and writes the result to the destination register. The argument that is extended from the <syntax><Rm></syntax> register can be a byte, halfword, word, or doubleword. It updates the condition flags based on the result.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="1">
|
||||
<alias_list_intro>This instruction is used by the alias </alias_list_intro>
|
||||
<aliasref aliaspageid="CMN_ADDS_addsub_ext" aliasfile="cmn_adds_addsub_ext.xml" hover="Compare negative (extended register)" punct=".">
|
||||
<text>CMN (extended register)</text>
|
||||
<aliaspref>Rd == '11111'</aliaspref>
|
||||
</aliasref>
|
||||
<alias_list_outro>
|
||||
<text> See </text>
|
||||
<aliastablelink />
|
||||
<text> below for details of when the alias is preferred.</text>
|
||||
</alias_list_outro>
|
||||
</alias_list>
|
||||
<classes>
|
||||
<iclass name="Setting the condition flags" oneof="1" id="iclass_s" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDS" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/add-sub/extendedreg" tworows="1">
|
||||
<box hibit="31" name="sf" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="30" name="op" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="29" name="S" usename="1" settings="1" psbits="x">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="28" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="opt" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="3" name="option" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="imm3" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ADDS_32S_addsub_ext" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDS" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>ADDS </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn_wsp" hover="First 32-bit source general-purpose register or WSP (field "Rn")"><Wn|WSP></a><text>, </text><a link="sa_wm" hover="Second 32-bit general-purpose source register (field "Rm")"><Wm></a><text>{</text><text>, </text><a link="sa_extend" hover="Extension applied to second source operand (field "option") [LSL,SXTB,SXTH,SXTW,SXTX,UXTB,UXTH,UXTW,UXTX]"><extend></a><text> </text><text>{</text><text>#</text><a link="sa_amount" hover="Left shift amount applied after extension [0-4], default 0 (field "imm3")"><amount></a><text>}</text><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="ADDS_64S_addsub_ext" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDS" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>ADDS </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn_sp" hover="First 64-bit source general-purpose register or SP (field "Rn")"><Xn|SP></a><text>, </text><a link="sa_r" hover="Width specifier (field "option") [W,X]"><R></a><a link="sa_m" hover="Second general-purpose source register number [0-30] or ZR (31) (field "Rm")"><m></a><text>{</text><text>, </text><a link="sa_extend_1" hover="Extension applied to second source operand (field "option") [LSL,SXTB,SXTH,SXTW,SXTX,UXTB,UXTH,UXTW,UXTX]"><extend></a><text> </text><text>{</text><text>#</text><a link="sa_amount" hover="Left shift amount applied after extension [0-4], default 0 (field "imm3")"><amount></a><text>}</text><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/add-sub/extendedreg" mylink="aarch64.instrs.integer.arithmetic.add-sub.extendedreg" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
integer datasize = if sf == '1' then 64 else 32;
|
||||
boolean sub_op = (op == '1');
|
||||
boolean setflags = (S == '1');
|
||||
<a link="ExtendType" file="shared_pseudocode.xml" hover="enumeration ExtendType {ExtendType_SXTB, ExtendType_SXTH, ExtendType_SXTW, ExtendType_SXTX, ExtendType_UXTB, ExtendType_UXTH, ExtendType_UXTW, ExtendType_UXTX}">ExtendType</a> extend_type = <a link="impl-aarch64.DecodeRegExtend.1" file="shared_pseudocode.xml" hover="function: ExtendType DecodeRegExtend(bits(3) op)">DecodeRegExtend</a>(option);
|
||||
integer shift = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm3);
|
||||
if shift > 4 then UNDEFINED;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ADDS_32S_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_wd"><Wd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_32S_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_wn_wsp"><Wn|WSP></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_32S_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_wm"><Wm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_64S_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_64S_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the first source general-purpose register or stack pointer, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_64S_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_r"><R></symbol>
|
||||
<definition encodedin="option">
|
||||
<intro>Is a width specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">option</entry>
|
||||
<entry class="symbol"><R></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00x</entry>
|
||||
<entry class="symbol">W</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">010</entry>
|
||||
<entry class="symbol">W</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">x11</entry>
|
||||
<entry class="symbol">X</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10x</entry>
|
||||
<entry class="symbol">W</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">110</entry>
|
||||
<entry class="symbol">W</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_64S_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_m"><m></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the number [0-30] of the second general-purpose source register or the name ZR (31), encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_32S_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_extend"><extend></symbol>
|
||||
<definition encodedin="option">
|
||||
<intro>For the 32-bit variant: is the extension to be applied to the second source operand, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">option</entry>
|
||||
<entry class="symbol"><extend></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">000</entry>
|
||||
<entry class="symbol">UXTB</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">001</entry>
|
||||
<entry class="symbol">UXTH</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">010</entry>
|
||||
<entry class="symbol">LSL|UXTW</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">011</entry>
|
||||
<entry class="symbol">UXTX</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">100</entry>
|
||||
<entry class="symbol">SXTB</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">101</entry>
|
||||
<entry class="symbol">SXTH</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">110</entry>
|
||||
<entry class="symbol">SXTW</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">111</entry>
|
||||
<entry class="symbol">SXTX</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
<after>If "Rn" is '11111' (WSP) and "option" is '010' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTW when "option" is '010'.</after>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_64S_addsub_ext" symboldefcount="2">
|
||||
<symbol link="sa_extend_1"><extend></symbol>
|
||||
<definition encodedin="option">
|
||||
<intro>For the 64-bit variant: is the extension to be applied to the second source operand, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">option</entry>
|
||||
<entry class="symbol"><extend></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">000</entry>
|
||||
<entry class="symbol">UXTB</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">001</entry>
|
||||
<entry class="symbol">UXTH</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">010</entry>
|
||||
<entry class="symbol">UXTW</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">011</entry>
|
||||
<entry class="symbol">LSL|UXTX</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">100</entry>
|
||||
<entry class="symbol">SXTB</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">101</entry>
|
||||
<entry class="symbol">SXTH</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">110</entry>
|
||||
<entry class="symbol">SXTW</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">111</entry>
|
||||
<entry class="symbol">SXTX</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
<after>If "Rn" is '11111' (SP) and "option" is '011' then LSL is preferred, but may be omitted when "imm3" is '000'. In all other cases <extend> is required and must be UXTX when "option" is '011'.</after>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_32S_addsub_ext, ADDS_64S_addsub_ext" symboldefcount="1">
|
||||
<symbol link="sa_amount"><amount></symbol>
|
||||
<account encodedin="imm3">
|
||||
<intro>
|
||||
<para>Is the left shift amount to be applied after extension in the range 0 to 4, defaulting to 0, encoded in the "imm3" field. It must be absent when <extend> is absent, is required when <extend> is LSL, and is optional when <extend> is present but not LSL.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/add-sub/extendedreg" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) result;
|
||||
bits(datasize) operand1 = if n == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[]<datasize-1:0> else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, datasize];
|
||||
bits(datasize) operand2 = <a link="impl-aarch64.ExtendReg.4" file="shared_pseudocode.xml" hover="function: bits(N) ExtendReg(integer reg, ExtendType exttype, integer shift, integer N)">ExtendReg</a>(m, extend_type, shift, datasize);
|
||||
bits(4) nzcv;
|
||||
bit carry_in;
|
||||
|
||||
if sub_op then
|
||||
operand2 = NOT(operand2);
|
||||
carry_in = '1';
|
||||
else
|
||||
carry_in = '0';
|
||||
|
||||
(result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(operand1, operand2, carry_in);
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = nzcv;
|
||||
|
||||
if d == 31 && !setflags then
|
||||
<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(result, 64);
|
||||
else
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
222
spec/arm64_xml/adds_addsub_imm.xml
Normal file
222
spec/arm64_xml/adds_addsub_imm.xml
Normal file
@@ -0,0 +1,222 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ADDS_addsub_imm" title="ADDS (immediate) -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="immediate-type" value="imm12u" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDS" />
|
||||
</docvars>
|
||||
<heading>ADDS (immediate)</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Add (immediate), setting flags</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Add (immediate), setting flags, adds a register value and an optionally-shifted immediate value, and writes the result to the destination register. It updates the condition flags based on the result.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="1">
|
||||
<alias_list_intro>This instruction is used by the alias </alias_list_intro>
|
||||
<aliasref aliaspageid="CMN_ADDS_addsub_imm" aliasfile="cmn_adds_addsub_imm.xml" hover="Compare negative (immediate)" punct=".">
|
||||
<text>CMN (immediate)</text>
|
||||
<aliaspref>Rd == '11111'</aliaspref>
|
||||
</aliasref>
|
||||
<alias_list_outro>
|
||||
<text> See </text>
|
||||
<aliastablelink />
|
||||
<text> below for details of when the alias is preferred.</text>
|
||||
</alias_list_outro>
|
||||
</alias_list>
|
||||
<classes>
|
||||
<iclass name="Setting the condition flags" oneof="1" id="iclass_s" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="immediate-type" value="imm12u" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDS" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/add-sub/immediate" tworows="1">
|
||||
<box hibit="31" name="sf" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="30" name="op" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="29" name="S" usename="1" settings="1" psbits="x">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="28" width="6" settings="6">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="sh" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="21" width="12" name="imm12" usename="1">
|
||||
<c colspan="12"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ADDS_32S_addsub_imm" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="immediate-type" value="imm12u" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDS" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>ADDS </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn_wsp" hover="32-bit source general-purpose register or WSP (field "Rn")"><Wn|WSP></a><text>, #</text><a link="sa_imm" hover="Unsigned immediate [0-4095] (field "imm12")"><imm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional left shift to apply to the immediate, default LSL #0 (field "sh") [LSL #0,LSL #12]"><shift></a><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="ADDS_64S_addsub_imm" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="immediate-type" value="imm12u" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDS" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>ADDS </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn_sp" hover="64-bit source general-purpose register or SP (field "Rn")"><Xn|SP></a><text>, #</text><a link="sa_imm" hover="Unsigned immediate [0-4095] (field "imm12")"><imm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional left shift to apply to the immediate, default LSL #0 (field "sh") [LSL #0,LSL #12]"><shift></a><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/add-sub/immediate" mylink="aarch64.instrs.integer.arithmetic.add-sub.immediate" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer datasize = if sf == '1' then 64 else 32;
|
||||
boolean sub_op = (op == '1');
|
||||
boolean setflags = (S == '1');
|
||||
bits(datasize) imm;
|
||||
|
||||
case sh of
|
||||
when '0' imm = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12, datasize);
|
||||
when '1' imm = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(imm12 : <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12), datasize);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ADDS_32S_addsub_imm" symboldefcount="1">
|
||||
<symbol link="sa_wd"><Wd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_32S_addsub_imm" symboldefcount="1">
|
||||
<symbol link="sa_wn_wsp"><Wn|WSP></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_64S_addsub_imm" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_64S_addsub_imm" symboldefcount="1">
|
||||
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_32S_addsub_imm, ADDS_64S_addsub_imm" symboldefcount="1">
|
||||
<symbol link="sa_imm"><imm></symbol>
|
||||
<account encodedin="imm12">
|
||||
<intro>
|
||||
<para>Is an unsigned immediate, in the range 0 to 4095, encoded in the "imm12" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_32S_addsub_imm, ADDS_64S_addsub_imm" symboldefcount="1">
|
||||
<symbol link="sa_shift"><shift></symbol>
|
||||
<definition encodedin="sh">
|
||||
<intro>Is the optional left shift to apply to the immediate, defaulting to LSL #0 and </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">sh</entry>
|
||||
<entry class="symbol"><shift></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">LSL #0</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">LSL #12</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/add-sub/immediate" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) result;
|
||||
bits(datasize) operand1 = if n == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[]<datasize-1:0> else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, datasize];
|
||||
bits(datasize) operand2 = imm;
|
||||
bits(4) nzcv;
|
||||
bit carry_in;
|
||||
|
||||
if sub_op then
|
||||
operand2 = NOT(operand2);
|
||||
carry_in = '1';
|
||||
else
|
||||
carry_in = '0';
|
||||
|
||||
(result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(operand1, operand2, carry_in);
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = nzcv;
|
||||
|
||||
if d == 31 && !setflags then
|
||||
<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(result, 64);
|
||||
else
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
260
spec/arm64_xml/adds_addsub_shift.xml
Normal file
260
spec/arm64_xml/adds_addsub_shift.xml
Normal file
@@ -0,0 +1,260 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ADDS_addsub_shift" title="ADDS (shifted register) -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDS" />
|
||||
</docvars>
|
||||
<heading>ADDS (shifted register)</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Add (shifted register), setting flags</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Add (shifted register), setting flags, adds a register value and an optionally-shifted register value, and writes the result to the destination register. It updates the condition flags based on the result.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="1">
|
||||
<alias_list_intro>This instruction is used by the alias </alias_list_intro>
|
||||
<aliasref aliaspageid="CMN_ADDS_addsub_shift" aliasfile="cmn_adds_addsub_shift.xml" hover="Compare negative (shifted register)" punct=".">
|
||||
<text>CMN (shifted register)</text>
|
||||
<aliaspref>Rd == '11111'</aliaspref>
|
||||
</aliasref>
|
||||
<alias_list_outro>
|
||||
<text> See </text>
|
||||
<aliastablelink />
|
||||
<text> below for details of when the alias is preferred.</text>
|
||||
</alias_list_outro>
|
||||
</alias_list>
|
||||
<classes>
|
||||
<iclass name="Setting the condition flags" oneof="1" id="iclass_s" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDS" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/add-sub/shiftedreg" tworows="1">
|
||||
<box hibit="31" name="sf" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="30" name="op" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="29" name="S" usename="1" settings="1" psbits="x">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="28" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="shift" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="6" name="imm6" usename="1">
|
||||
<c colspan="6"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ADDS_32_addsub_shift" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDS" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>ADDS </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn" hover="First 32-bit general-purpose source register (field "Rn")"><Wn></a><text>, </text><a link="sa_wm" hover="Second 32-bit general-purpose source register (field "Rm")"><Wm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift type applied to second source operand, default LSL (field "shift") [ASR,LSL,LSR]"><shift></a><text> #</text><a link="sa_amount" hover="Shift amount [0-31], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="ADDS_64_addsub_shift" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDS" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>ADDS </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn" hover="First 64-bit general-purpose source register (field "Rn")"><Xn></a><text>, </text><a link="sa_xm" hover="Second 64-bit general-purpose source register (field "Rm")"><Xm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift type applied to second source operand, default LSL (field "shift") [ASR,LSL,LSR]"><shift></a><text> #</text><a link="sa_amount_1" hover="Shift amount [0-63], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/add-sub/shiftedreg" mylink="aarch64.instrs.integer.arithmetic.add-sub.shiftedreg" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
integer datasize = if sf == '1' then 64 else 32;
|
||||
boolean sub_op = (op == '1');
|
||||
boolean setflags = (S == '1');
|
||||
|
||||
if shift == '11' then UNDEFINED;
|
||||
if sf == '0' && imm6<5> == '1' then UNDEFINED;
|
||||
|
||||
<a link="ShiftType" file="shared_pseudocode.xml" hover="enumeration ShiftType {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType</a> shift_type = <a link="impl-aarch64.DecodeShift.1" file="shared_pseudocode.xml" hover="function: ShiftType DecodeShift(bits(2) op)">DecodeShift</a>(shift);
|
||||
integer shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ADDS_32_addsub_shift" symboldefcount="1">
|
||||
<symbol link="sa_wd"><Wd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_32_addsub_shift" symboldefcount="1">
|
||||
<symbol link="sa_wn"><Wn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_32_addsub_shift" symboldefcount="1">
|
||||
<symbol link="sa_wm"><Wm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_64_addsub_shift" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_64_addsub_shift" symboldefcount="1">
|
||||
<symbol link="sa_xn"><Xn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_64_addsub_shift" symboldefcount="1">
|
||||
<symbol link="sa_xm"><Xm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_32_addsub_shift, ADDS_64_addsub_shift" symboldefcount="1">
|
||||
<symbol link="sa_shift"><shift></symbol>
|
||||
<definition encodedin="shift">
|
||||
<intro>Is the optional shift type to be applied to the second source operand, defaulting to LSL and </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">shift</entry>
|
||||
<entry class="symbol"><shift></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">LSL</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">LSR</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">ASR</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_32_addsub_shift" symboldefcount="1">
|
||||
<symbol link="sa_amount"><amount></symbol>
|
||||
<account encodedin="imm6">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="32" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 32-bit variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDS_64_addsub_shift" symboldefcount="2">
|
||||
<symbol link="sa_amount_1"><amount></symbol>
|
||||
<account encodedin="imm6">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="64" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 64-bit variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/add-sub/shiftedreg" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) result;
|
||||
bits(datasize) operand1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, datasize];
|
||||
bits(datasize) operand2 = <a link="impl-aarch64.ShiftReg.4" file="shared_pseudocode.xml" hover="function: bits(N) ShiftReg(integer reg, ShiftType shiftype, integer amount, integer N)">ShiftReg</a>(m, shift_type, shift_amount, datasize);
|
||||
bits(4) nzcv;
|
||||
bit carry_in;
|
||||
|
||||
if sub_op then
|
||||
operand2 = NOT(operand2);
|
||||
carry_in = '1';
|
||||
else
|
||||
carry_in = '0';
|
||||
|
||||
(result, nzcv) = <a link="impl-shared.AddWithCarry.3" file="shared_pseudocode.xml" hover="function: (bits(N), bits(4)) AddWithCarry(bits(N) x, bits(N) y, bit carry_in)">AddWithCarry</a>(operand1, operand2, carry_in);
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = nzcv;
|
||||
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
129
spec/arm64_xml/addspl_r_ri.xml
Normal file
129
spec/arm64_xml/addspl_r_ri.xml
Normal file
@@ -0,0 +1,129 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="addspl_r_ri" title="ADDSPL" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDSPL" />
|
||||
</docvars>
|
||||
<heading>ADDSPL</heading>
|
||||
<desc>
|
||||
<brief>Add multiple of Streaming SVE predicate register size to scalar register</brief>
|
||||
<description>
|
||||
<para>Add the Streaming SVE predicate register size in bytes multiplied by an immediate in the range -32 to 31 to the 64-bit source general-purpose register or current stack pointer and place the result in the 64-bit destination general-purpose register or current stack pointer.</para>
|
||||
<para>This instruction does not require the PE to be in Streaming SVE mode.</para>
|
||||
</description>
|
||||
<status>Amber</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SME" oneof="1" id="iclass_mortlach" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDSPL" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SME" feature="FEAT_SME" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="ADDSPL-R.RI-_">
|
||||
<box hibit="31" width="9" settings="9">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="op" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="10" width="6" name="imm6" usename="1">
|
||||
<c colspan="6"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="addspl_r_ri_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDSPL" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADDSPL </text><a link="sa_xd_sp" hover="64-bit destination general-purpose register or SP (field "Rd")"><Xd|SP></a><text>, </text><a link="sa_xn_sp" hover="64-bit source general-purpose register or SP (field "Rn")"><Xn|SP></a><text>, #</text><a link="sa_imm" hover="Signed immediate operand [-32-31] (field "imm6")"><imm></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDSPL-R.RI-_" mylink="ADDSPL-R.RI-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer imm = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(imm6);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="addspl_r_ri_" symboldefcount="1">
|
||||
<symbol link="sa_xd_sp"><Xd|SP></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addspl_r_ri_" symboldefcount="1">
|
||||
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addspl_r_ri_" symboldefcount="1">
|
||||
<symbol link="sa_imm"><imm></symbol>
|
||||
<account encodedin="imm6">
|
||||
<intro>
|
||||
<para>Is the signed immediate operand, in the range -32 to 31, encoded in the "imm6" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDSPL-R.RI-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSMEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSMEEnabled()">CheckSMEEnabled</a>();
|
||||
constant integer SVL = <a link="impl-aarch64.CurrentSVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentSVL">CurrentSVL</a>;
|
||||
integer len = imm * (SVL DIV 64);
|
||||
bits(64) operand1 = if n == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[] else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
||||
bits(64) result = operand1 + len;
|
||||
|
||||
if d == 31 then
|
||||
<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = result;
|
||||
else
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
129
spec/arm64_xml/addsvl_r_ri.xml
Normal file
129
spec/arm64_xml/addsvl_r_ri.xml
Normal file
@@ -0,0 +1,129 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="addsvl_r_ri" title="ADDSVL" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDSVL" />
|
||||
</docvars>
|
||||
<heading>ADDSVL</heading>
|
||||
<desc>
|
||||
<brief>Add multiple of Streaming SVE vector register size to scalar register</brief>
|
||||
<description>
|
||||
<para>Add the Streaming SVE vector register size in bytes multiplied by an immediate in the range -32 to 31 to the 64-bit source general-purpose register or current stack pointer, and place the result in the 64-bit destination general-purpose register or current stack pointer.</para>
|
||||
<para>This instruction does not require the PE to be in Streaming SVE mode.</para>
|
||||
</description>
|
||||
<status>Amber</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SME" oneof="1" id="iclass_mortlach" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDSVL" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SME" feature="FEAT_SME" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="ADDSVL-R.RI-_">
|
||||
<box hibit="31" width="9" settings="9">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="op" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="10" width="6" name="imm6" usename="1">
|
||||
<c colspan="6"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="addsvl_r_ri_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDSVL" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADDSVL </text><a link="sa_xd_sp" hover="64-bit destination general-purpose register or SP (field "Rd")"><Xd|SP></a><text>, </text><a link="sa_xn_sp" hover="64-bit source general-purpose register or SP (field "Rn")"><Xn|SP></a><text>, #</text><a link="sa_imm" hover="Signed immediate operand [-32-31] (field "imm6")"><imm></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDSVL-R.RI-_" mylink="ADDSVL-R.RI-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer imm = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(imm6);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="addsvl_r_ri_" symboldefcount="1">
|
||||
<symbol link="sa_xd_sp"><Xd|SP></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addsvl_r_ri_" symboldefcount="1">
|
||||
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addsvl_r_ri_" symboldefcount="1">
|
||||
<symbol link="sa_imm"><imm></symbol>
|
||||
<account encodedin="imm6">
|
||||
<intro>
|
||||
<para>Is the signed immediate operand, in the range -32 to 31, encoded in the "imm6" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDSVL-R.RI-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSMEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSMEEnabled()">CheckSMEEnabled</a>();
|
||||
constant integer SVL = <a link="impl-aarch64.CurrentSVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentSVL">CurrentSVL</a>;
|
||||
integer len = imm * (SVL DIV 8);
|
||||
bits(64) operand1 = if n == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[] else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
||||
bits(64) result = operand1 + len;
|
||||
|
||||
if d == 31 then
|
||||
<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = result;
|
||||
else
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
222
spec/arm64_xml/addv_advsimd.xml
Normal file
222
spec/arm64_xml/addv_advsimd.xml
Normal file
@@ -0,0 +1,222 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ADDV_advsimd" title="ADDV -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDV" />
|
||||
</docvars>
|
||||
<heading>ADDV</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Add across Vector</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.</para>
|
||||
<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Advanced SIMD" oneof="1" id="iclass_advsimd" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDV" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/vector/reduce/add/simd">
|
||||
<box hibit="31" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="30" name="Q" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="29" name="U" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" width="5" name="opcode" settings="5">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="11" width="2" settings="2">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ADDV_asimdall_only" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDV" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADDV </text><a link="sa_v" hover="Destination width specifier (field "size") [B,H,S]"><V></a><a link="sa_d" hover="SIMD&FP destination register number (field "Rd")"><d></a><text>, </text><a link="sa_vn" hover="SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size:Q") [4H,4S,8B,8H,16B]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/reduce/add/simd" mylink="aarch64.instrs.vector.reduce.add.simd" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
|
||||
if size:Q == '100' then UNDEFINED;
|
||||
if size == '11' then UNDEFINED;
|
||||
|
||||
integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer datasize = if Q == '1' then 128 else 64;
|
||||
integer elements = datasize DIV esize;
|
||||
|
||||
<a link="ReduceOp" file="shared_pseudocode.xml" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp</a> op = <a link="ReduceOp_ADD" file="shared_pseudocode.xml" hover="enumeration ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM, ReduceOp_FMIN, ReduceOp_FMAX, ReduceOp_FADD, ReduceOp_ADD}">ReduceOp_ADD</a>;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ADDV_asimdall_only" symboldefcount="1">
|
||||
<symbol link="sa_v"><V></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the destination width specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><V></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ADDV_asimdall_only" symboldefcount="1">
|
||||
<symbol link="sa_d"><d></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the number of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDV_asimdall_only" symboldefcount="1">
|
||||
<symbol link="sa_vn"><Vn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the name of the SIMD&FP source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADDV_asimdall_only" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size:Q">
|
||||
<intro>Is an arrangement specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="3">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="bitfield">Q</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">8B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">16B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">4H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">8H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">4S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="bitfield">x</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/reduce/add/simd" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
|
||||
bits(datasize) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
|
||||
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, esize] = <a link="impl-aarch64.Reduce.3" file="shared_pseudocode.xml" hover="function: bits(esize) Reduce(ReduceOp op, bits(N) input, integer esize)">Reduce</a>(op, operand, esize);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
266
spec/arm64_xml/addva_za_pp_z.xml
Normal file
266
spec/arm64_xml/addva_za_pp_z.xml
Normal file
@@ -0,0 +1,266 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="addva_za_pp_z" title="ADDVA" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDVA" />
|
||||
</docvars>
|
||||
<heading>ADDVA</heading>
|
||||
<desc>
|
||||
<brief>Add vertically vector elements to ZA tile</brief>
|
||||
<description>
|
||||
<para>Add each element of the source vector to the corresponding active element of each vertical slice of a ZA tile. The tile elements are predicated by a pair of governing predicates. An element of a vertical slice is considered active if its corresponding element in the first governing predicate is TRUE and the element corresponding to its vertical slice number in the second governing predicate is TRUE. Inactive elements in the destination tile remain unmodified.</para>
|
||||
<para>ID_AA64SMFR0_EL1.I16I64 indicates whether the 64-bit integer variant is implemented.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>True</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<sm_policy>SM_1_only</sm_policy>
|
||||
<is_gov_pred_pair>True</is_gov_pred_pair>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<classesintro count="2">
|
||||
<txt>It has encodings from 2 classes:</txt>
|
||||
<a href="#iclass_per_word">32-bit</a>
|
||||
<txt> and </txt>
|
||||
<a href="#iclass_per_doubleword">64-bit</a>
|
||||
</classesintro>
|
||||
<iclass name="32-bit" oneof="2" id="iclass_per_word" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="asimdimm-datatype" value="per-word" />
|
||||
<docvar key="instr-class" value="mortlach" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDVA" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SME" feature="FEAT_SME" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="ADDVA-ZA.PP.Z-32" tworows="1">
|
||||
<box hibit="31" width="2" settings="2">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="29" width="7" settings="7">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="22" name="op" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="19" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" name="V" usename="1" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="15" width="3" name="Pm" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="Pn" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="3" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="2" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="1" width="2" name="ZAda" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="addva_za_pp_z_32" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="asimdimm-datatype" value="per-word" />
|
||||
<docvar key="instr-class" value="mortlach" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDVA" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADDVA </text><a link="sa_zada" hover="ZA tile ZA0-ZA3 (field "ZAda")"><ZAda></a><text>.S, </text><a link="sa_pn" hover="First governing scalable predicate register P0-P7 (field "Pn")"><Pn></a><text>/M, </text><a link="sa_pm" hover="Second governing scalable predicate register P0-P7 (field "Pm")"><Pm></a><text>/M, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>.S</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDVA-ZA.PP.Z-32" mylink="ADDVA-ZA.PP.Z-32" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 32;
|
||||
integer a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pn);
|
||||
integer b = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pm);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer da = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(ZAda);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
<iclass name="64-bit" oneof="2" id="iclass_per_doubleword" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="asimdimm-datatype" value="per-doubleword" />
|
||||
<docvar key="instr-class" value="mortlach" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDVA" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SME_I16I64" feature="FEAT_SME_I16I64" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="ADDVA-ZA.PP.Z-64" tworows="1">
|
||||
<box hibit="31" width="2" settings="2">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="29" width="7" settings="7">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="22" name="op" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="21" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" name="V" usename="1" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="15" width="3" name="Pm" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="Pn" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="3" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="2" width="3" name="ZAda" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="addva_za_pp_z_64" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="asimdimm-datatype" value="per-doubleword" />
|
||||
<docvar key="instr-class" value="mortlach" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDVA" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADDVA </text><a link="sa_zada_1" hover="ZA tile ZA0-ZA7 (field "ZAda")"><ZAda></a><text>.D, </text><a link="sa_pn" hover="First governing scalable predicate register P0-P7 (field "Pn")"><Pn></a><text>/M, </text><a link="sa_pm" hover="Second governing scalable predicate register P0-P7 (field "Pm")"><Pm></a><text>/M, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>.D</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDVA-ZA.PP.Z-64" mylink="ADDVA-ZA.PP.Z-64" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSMEI16I64.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEI16I64()">HaveSMEI16I64</a>() then UNDEFINED;
|
||||
constant integer esize = 64;
|
||||
integer a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pn);
|
||||
integer b = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pm);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer da = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(ZAda);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="addva_za_pp_z_32" symboldefcount="1">
|
||||
<symbol link="sa_zada"><ZAda></symbol>
|
||||
<account encodedin="ZAda">
|
||||
<docvars>
|
||||
<docvar key="asimdimm-datatype" value="per-word" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 32-bit variant: is the name of the ZA tile ZA0-ZA3, encoded in the "ZAda" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addva_za_pp_z_64" symboldefcount="2">
|
||||
<symbol link="sa_zada_1"><ZAda></symbol>
|
||||
<account encodedin="ZAda">
|
||||
<docvars>
|
||||
<docvar key="asimdimm-datatype" value="per-doubleword" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 64-bit variant: is the name of the ZA tile ZA0-ZA7, encoded in the "ZAda" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addva_za_pp_z_32, addva_za_pp_z_64" symboldefcount="1">
|
||||
<symbol link="sa_pn"><Pn></symbol>
|
||||
<account encodedin="Pn">
|
||||
<intro>
|
||||
<para>Is the name of the first governing scalable predicate register P0-P7, encoded in the "Pn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addva_za_pp_z_32, addva_za_pp_z_64" symboldefcount="1">
|
||||
<symbol link="sa_pm"><Pm></symbol>
|
||||
<account encodedin="Pm">
|
||||
<intro>
|
||||
<para>Is the name of the second governing scalable predicate register P0-P7, encoded in the "Pm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addva_za_pp_z_32, addva_za_pp_z_64" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDVA-ZA.PP.Z-32" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEAndZAEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer dim = VL DIV esize;
|
||||
bits(PL) mask1 = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[a, PL];
|
||||
bits(PL) mask2 = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[b, PL];
|
||||
bits(VL) operand_src = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(dim*dim*esize) operand_acc = <a link="impl-aarch64.ZAtile.read.3" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAtile[integer tile, integer esize, integer width]">ZAtile</a>[da, esize, dim*dim*esize];
|
||||
bits(dim*dim*esize) result;
|
||||
|
||||
for row = 0 to dim-1
|
||||
bits(esize) element = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand_src, row, esize];
|
||||
for col = 0 to dim-1
|
||||
bits(esize) res = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand_acc, row*dim+col, esize];
|
||||
if (<a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask1, row, esize) &&
|
||||
<a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask2, col, esize)) then
|
||||
res = res + element;
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, row*dim+col, esize] = res;
|
||||
|
||||
<a link="impl-aarch64.ZAtile.write.3" file="shared_pseudocode.xml" hover="accessor: ZAtile[integer tile, integer esize, integer width] = bits(width) value">ZAtile</a>[da, esize, dim*dim*esize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
125
spec/arm64_xml/addvl_r_ri.xml
Normal file
125
spec/arm64_xml/addvl_r_ri.xml
Normal file
@@ -0,0 +1,125 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="addvl_r_ri" title="ADDVL" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDVL" />
|
||||
</docvars>
|
||||
<heading>ADDVL</heading>
|
||||
<desc>
|
||||
<brief>Add multiple of vector register size to scalar register</brief>
|
||||
<description>
|
||||
<para>Add the current vector register size in bytes multiplied by an immediate in the range -32 to 31 to the 64-bit source general-purpose register or current stack pointer, and place the result in the 64-bit destination general-purpose register or current stack pointer.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDVL" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ADDVL-R.RI-_">
|
||||
<box hibit="31" width="9" settings="9">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="op" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" width="6" name="imm6" usename="1">
|
||||
<c colspan="6"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="addvl_r_ri_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADDVL" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADDVL </text><a link="sa_xd_sp" hover="64-bit destination general-purpose register or SP (field "Rd")"><Xd|SP></a><text>, </text><a link="sa_xn_sp" hover="64-bit source general-purpose register or SP (field "Rn")"><Xn|SP></a><text>, #</text><a link="sa_imm" hover="Signed immediate operand [-32-31] (field "imm6")"><imm></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDVL-R.RI-_" mylink="ADDVL-R.RI-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer imm = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(imm6);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="addvl_r_ri_" symboldefcount="1">
|
||||
<symbol link="sa_xd_sp"><Xd|SP></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addvl_r_ri_" symboldefcount="1">
|
||||
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the source general-purpose register or stack pointer, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="addvl_r_ri_" symboldefcount="1">
|
||||
<symbol link="sa_imm"><imm></symbol>
|
||||
<account encodedin="imm6">
|
||||
<intro>
|
||||
<para>Is the signed immediate operand, in the range -32 to 31, encoded in the "imm6" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADDVL-R.RI-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
bits(64) operand1 = if n == 31 then <a link="impl-aarch64.SP.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) SP[]">SP</a>[] else <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, 64];
|
||||
bits(64) result = operand1 + (imm * (VL DIV 8));
|
||||
|
||||
if d == 31 then
|
||||
<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = result;
|
||||
else
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
108
spec/arm64_xml/adr.xml
Normal file
108
spec/arm64_xml/adr.xml
Normal file
@@ -0,0 +1,108 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ADR" title="ADR -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="address-form" value="literal" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADR" />
|
||||
<docvar key="offset-type" value="off19s" />
|
||||
</docvars>
|
||||
<heading>ADR</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Form PC-relative address</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Form PC-relative address adds an immediate value to the PC value to form a PC-relative address, and writes the result to the destination register.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Literal" oneof="1" id="iclass_literal" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="address-form" value="literal" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADR" />
|
||||
<docvar key="offset-type" value="off19s" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/address/pc-rel" tworows="1">
|
||||
<box hibit="31" name="op" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="30" width="2" name="immlo" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="28" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="19" name="immhi" usename="1">
|
||||
<c colspan="19"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ADR_only_pcreladdr" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="address-form" value="literal" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADR" />
|
||||
<docvar key="offset-type" value="off19s" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADR </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_label" hover="Label whose address is to be calculated (field "immhi:immlo")"><label></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/address/pc-rel" mylink="aarch64.instrs.integer.arithmetic.address.pc-rel" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
boolean page = (op == '1');
|
||||
bits(64) imm;
|
||||
|
||||
if page then
|
||||
imm = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(immhi:immlo:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12), 64);
|
||||
else
|
||||
imm = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(immhi:immlo, 64);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ADR_only_pcreladdr" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADR_only_pcreladdr" symboldefcount="1">
|
||||
<symbol link="sa_label"><label></symbol>
|
||||
<account encodedin="immhi:immlo">
|
||||
<intro>
|
||||
<para>Is the program label whose address is to be calculated. Its offset from the address of this instruction, in the range +/-1MB, is encoded in "immhi:immlo".</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/address/pc-rel" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(64) base = <a link="impl-aarch64.PC.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) PC[]">PC</a>[];
|
||||
|
||||
if page then
|
||||
base<11:0> = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12);
|
||||
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = base + imm;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
376
spec/arm64_xml/adr_z_az.xml
Normal file
376
spec/arm64_xml/adr_z_az.xml
Normal file
@@ -0,0 +1,376 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="adr_z_az" title="ADR" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADR" />
|
||||
</docvars>
|
||||
<heading>ADR</heading>
|
||||
<desc>
|
||||
<brief>Compute vector address</brief>
|
||||
<description>
|
||||
<para>Optionally sign or zero-extend the least significant 32-bits of each element from a vector of offsets or indices in the second source vector, scale each index by 2, 4 or 8, add to a vector of base addresses from the first source vector, and place the resulting addresses in the destination vector. This instruction is unpredicated.</para>
|
||||
<para>This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<sm_policy>SM_0_only</sm_policy>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<classesintro count="3">
|
||||
<txt>It has encodings from 3 classes:</txt>
|
||||
<a href="#iclass_off_pkd">Packed offsets</a>
|
||||
<txt>, </txt>
|
||||
<a href="#iclass_off_s_s32">Unpacked 32-bit signed offsets</a>
|
||||
<txt> and </txt>
|
||||
<a href="#iclass_off_s_u32">Unpacked 32-bit unsigned offsets</a>
|
||||
</classesintro>
|
||||
<iclass name="Packed offsets" oneof="3" id="iclass_off_pkd" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADR" />
|
||||
<docvar key="sve-offset-type" value="off_pkd" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ADR-Z.AZ-SD.same.scaled">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="22" name="sz" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="4" settings="4">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="11" width="2" name="msz" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="adr_z_az_sd_same_scaled" oneofinclass="1" oneof="3" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADR" />
|
||||
<docvar key="sve-offset-type" value="off_pkd" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADR </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>, [</text><a link="sa_zn" hover="Base scalable vector register (field "Zn")"><Zn></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>, </text><a link="sa_zm" hover="Offset scalable vector register (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "sz") [D,S]"><T></a><text>{</text><text>, </text><a link="sa_mod" hover="Index extend and shift specifier (field "msz")"><mod></a><text> </text><a link="sa_amount" hover="Index shift amount (field "msz")"><amount></a><text>}</text><text>]</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADR-Z.AZ-SD.same.scaled" mylink="ADR-Z.AZ-SD.same.scaled" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
|
||||
constant integer esize = 32 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(sz);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
|
||||
constant integer osize = esize;
|
||||
boolean unsigned = TRUE;
|
||||
integer mbytes = 1 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(msz);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
<iclass name="Unpacked 32-bit signed offsets" oneof="3" id="iclass_off_s_s32" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADR" />
|
||||
<docvar key="sve-offset-type" value="off_s_s32" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ADR-Z.AZ-D.s32.scaled">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" name="opc<1>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="opc<0>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="4" settings="4">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="11" width="2" name="msz" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="adr_z_az_d_s32_scaled" oneofinclass="1" oneof="3" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADR" />
|
||||
<docvar key="sve-offset-type" value="off_s_s32" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADR </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.D, [</text><a link="sa_zn" hover="Base scalable vector register (field "Zn")"><Zn></a><text>.D, </text><a link="sa_zm" hover="Offset scalable vector register (field "Zm")"><Zm></a><text>.D, SXTW</text><text>{</text><text> </text><a link="sa_amount" hover="Index shift amount (field "msz")"><amount></a><text>}</text><text>]</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADR-Z.AZ-D.s32.scaled" mylink="ADR-Z.AZ-D.s32.scaled" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
|
||||
constant integer esize = 64;
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
|
||||
constant integer osize = 32;
|
||||
boolean unsigned = FALSE;
|
||||
integer mbytes = 1 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(msz);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
<iclass name="Unpacked 32-bit unsigned offsets" oneof="3" id="iclass_off_s_u32" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADR" />
|
||||
<docvar key="sve-offset-type" value="off_s_u32" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ADR-Z.AZ-D.u32.scaled">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" name="opc<1>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="opc<0>" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="4" settings="4">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="11" width="2" name="msz" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="adr_z_az_d_u32_scaled" oneofinclass="1" oneof="3" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADR" />
|
||||
<docvar key="sve-offset-type" value="off_s_u32" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADR </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.D, [</text><a link="sa_zn" hover="Base scalable vector register (field "Zn")"><Zn></a><text>.D, </text><a link="sa_zm" hover="Offset scalable vector register (field "Zm")"><Zm></a><text>.D, UXTW</text><text>{</text><text> </text><a link="sa_amount" hover="Index shift amount (field "msz")"><amount></a><text>}</text><text>]</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADR-Z.AZ-D.u32.scaled" mylink="ADR-Z.AZ-D.u32.scaled" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() then UNDEFINED;
|
||||
constant integer esize = 64;
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
|
||||
constant integer osize = 32;
|
||||
boolean unsigned = TRUE;
|
||||
integer mbytes = 1 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(msz);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="adr_z_az_d_s32_scaled, adr_z_az_d_u32_scaled, adr_z_az_sd_same_scaled" symboldefcount="1">
|
||||
<symbol link="sa_zd"><Zd></symbol>
|
||||
<account encodedin="Zd">
|
||||
<intro>
|
||||
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="adr_z_az_sd_same_scaled" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="sz">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">sz</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="adr_z_az_d_s32_scaled, adr_z_az_d_u32_scaled, adr_z_az_sd_same_scaled" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the base scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="adr_z_az_d_s32_scaled, adr_z_az_d_u32_scaled, adr_z_az_sd_same_scaled" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the offset scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="adr_z_az_sd_same_scaled" symboldefcount="1">
|
||||
<symbol link="sa_mod"><mod></symbol>
|
||||
<definition encodedin="msz">
|
||||
<intro>Is the index extend and shift specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">msz</entry>
|
||||
<entry class="symbol"><mod></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">[absent]</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">x1</entry>
|
||||
<entry class="symbol">LSL</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">LSL</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="adr_z_az_d_s32_scaled, adr_z_az_d_u32_scaled, adr_z_az_sd_same_scaled" symboldefcount="1">
|
||||
<symbol link="sa_amount"><amount></symbol>
|
||||
<definition encodedin="msz">
|
||||
<intro>Is the index shift amount, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">msz</entry>
|
||||
<entry class="symbol"><amount></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">[absent]</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">#1</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">#2</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">#3</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ADR-Z.AZ-SD.same.scaled" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckNonStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) base = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) offs = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) addr = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[base, e, esize];
|
||||
integer offset = <a link="impl-shared.Int.2" file="shared_pseudocode.xml" hover="function: integer Int(bits(N) x, boolean unsigned)">Int</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[offs, e, esize]<osize-1:0>, unsigned);
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = addr + (offset * mbytes);
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
108
spec/arm64_xml/adrp.xml
Normal file
108
spec/arm64_xml/adrp.xml
Normal file
@@ -0,0 +1,108 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ADRP" title="ADRP -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="address-form" value="literal" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADRP" />
|
||||
<docvar key="offset-type" value="off19s" />
|
||||
</docvars>
|
||||
<heading>ADRP</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Form PC-relative address to 4KB page</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Form PC-relative address to 4KB page adds an immediate value that is shifted left by 12 bits, to the PC value to form a PC-relative address, with the bottom 12 bits masked out, and writes the result to the destination register.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Literal" oneof="1" id="iclass_literal" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="address-form" value="literal" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADRP" />
|
||||
<docvar key="offset-type" value="off19s" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/arithmetic/address/pc-rel" tworows="1">
|
||||
<box hibit="31" name="op" usename="1" settings="1" psbits="x">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="30" width="2" name="immlo" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="28" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="19" name="immhi" usename="1">
|
||||
<c colspan="19"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ADRP_only_pcreladdr" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="address-form" value="literal" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ADRP" />
|
||||
<docvar key="offset-type" value="off19s" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ADRP </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_label" hover="Label whose 4KB page address is to be calculated (field immhi:immlo)"><label></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/address/pc-rel" mylink="aarch64.instrs.integer.arithmetic.address.pc-rel" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
boolean page = (op == '1');
|
||||
bits(64) imm;
|
||||
|
||||
if page then
|
||||
imm = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(immhi:immlo:<a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12), 64);
|
||||
else
|
||||
imm = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(immhi:immlo, 64);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ADRP_only_pcreladdr" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ADRP_only_pcreladdr" symboldefcount="1">
|
||||
<symbol link="sa_label"><label></symbol>
|
||||
<account encodedin="immhi:immlo">
|
||||
<intro>
|
||||
<para>Is the program label whose 4KB page address is to be calculated. Its offset from the page address of this instruction, in the range +/-4GB, is encoded as "immhi:immlo" times 4096.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/arithmetic/address/pc-rel" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(64) base = <a link="impl-aarch64.PC.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) PC[]">PC</a>[];
|
||||
|
||||
if page then
|
||||
base<11:0> = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(12);
|
||||
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = base + imm;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
135
spec/arm64_xml/aesd_advsimd.xml
Normal file
135
spec/arm64_xml/aesd_advsimd.xml
Normal file
@@ -0,0 +1,135 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="AESD_advsimd" title="AESD -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESD" />
|
||||
</docvars>
|
||||
<heading>AESD</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>AES single round decryption</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>AES single round decryption.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Advanced SIMD" oneof="1" id="iclass_advsimd" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESD" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="ARMv8.0" feature="FEAT_AES" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="aarch64/instrs/vector/crypto/aes/round" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" width="4" name="opcode[4:1]" settings="4">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="12" name="D" usename="1" settings="1" psbits="x">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="11" width="2" settings="2">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="AESD_B_cryptoaes" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESD" />
|
||||
</docvars>
|
||||
<asmtemplate><text>AESD </text><a link="sa_vd" hover="SIMD&FP source and destination register (field "Rd")"><Vd></a><text>.16B, </text><a link="sa_vn" hover="Second SIMD&FP source register (field "Rn")"><Vn></a><text>.16B</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/crypto/aes/round" mylink="aarch64.instrs.vector.crypto.aes.round" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
if !<a link="impl-shared.HaveAESExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAESExt()">HaveAESExt</a>() then UNDEFINED;
|
||||
boolean decrypt = (D == '1');</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="AESD_B_cryptoaes" symboldefcount="1">
|
||||
<symbol link="sa_vd"><Vd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AESD_B_cryptoaes" symboldefcount="1">
|
||||
<symbol link="sa_vn"><Vn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the name of the second SIMD&FP source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/crypto/aes/round" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="AArch64.CheckFPAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
|
||||
|
||||
bits(128) operand1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, 128];
|
||||
bits(128) operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128];
|
||||
bits(128) result;
|
||||
result = operand1 EOR operand2;
|
||||
if decrypt then
|
||||
result = <a link="impl-shared.AESInvSubBytes.1" file="shared_pseudocode.xml" hover="function: bits(128) AESInvSubBytes(bits(128) op)">AESInvSubBytes</a>(<a link="impl-shared.AESInvShiftRows.1" file="shared_pseudocode.xml" hover="function: bits(128) AESInvShiftRows(bits(128) op)">AESInvShiftRows</a>(result));
|
||||
else
|
||||
result = <a link="impl-shared.AESSubBytes.1" file="shared_pseudocode.xml" hover="function: bits(128) AESSubBytes(bits(128) op)">AESSubBytes</a>(<a link="impl-shared.AESShiftRows.1" file="shared_pseudocode.xml" hover="function: bits(128) AESShiftRows(bits(128) op)">AESShiftRows</a>(result));
|
||||
|
||||
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
133
spec/arm64_xml/aesd_z_zz.xml
Normal file
133
spec/arm64_xml/aesd_z_zz.xml
Normal file
@@ -0,0 +1,133 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="aesd_z_zz" title="AESD" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESD" />
|
||||
</docvars>
|
||||
<heading>AESD</heading>
|
||||
<desc>
|
||||
<brief>AES single round decryption</brief>
|
||||
<description>
|
||||
<para>The <instruction>AESD</instruction> instruction reads a 16-byte state array from each 128-bit segment of the first source vector, together with a round key from the corresponding 128-bit segment of the second source vector. Each state array undergoes a single round of the <arm-defined-word>AddRoundKey()</arm-defined-word>, <arm-defined-word>InvSubBytes()</arm-defined-word> and <arm-defined-word>InvShiftRows()</arm-defined-word> transformations in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. This instruction is unpredicated.</para>
|
||||
<para>ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented.</para>
|
||||
<para>This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<sm_policy>SM_0_only</sm_policy>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESD" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SVE_AES" feature="FEAT_SVE_AES" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="AESD-Z.ZZ-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" name="size<1>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="size<0>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="16" name="op" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" name="o2" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zdn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="aesd_z_zz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESD" />
|
||||
</docvars>
|
||||
<asmtemplate><text>AESD </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.B, </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.B, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.B</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="AESD-Z.ZZ-_" mylink="AESD-Z.ZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() || !<a link="impl-aarch64.HaveSVE2AES.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2AES()">HaveSVE2AES</a>() then UNDEFINED;
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="aesd_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zdn"><Zdn></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="aesd_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="AESD-Z.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckNonStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer segments = VL DIV 128;
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
|
||||
result = operand1 EOR operand2;
|
||||
for s = 0 to segments-1
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, s, 128] = <a link="impl-shared.AESInvSubBytes.1" file="shared_pseudocode.xml" hover="function: bits(128) AESInvSubBytes(bits(128) op)">AESInvSubBytes</a>(<a link="impl-shared.AESInvShiftRows.1" file="shared_pseudocode.xml" hover="function: bits(128) AESInvShiftRows(bits(128) op)">AESInvShiftRows</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, s, 128]));
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
135
spec/arm64_xml/aese_advsimd.xml
Normal file
135
spec/arm64_xml/aese_advsimd.xml
Normal file
@@ -0,0 +1,135 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="AESE_advsimd" title="AESE -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESE" />
|
||||
</docvars>
|
||||
<heading>AESE</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>AES single round encryption</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>AES single round encryption.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Advanced SIMD" oneof="1" id="iclass_advsimd" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESE" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="ARMv8.0" feature="FEAT_AES" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="aarch64/instrs/vector/crypto/aes/round" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" width="4" name="opcode[4:1]" settings="4">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="12" name="D" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="11" width="2" settings="2">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="AESE_B_cryptoaes" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESE" />
|
||||
</docvars>
|
||||
<asmtemplate><text>AESE </text><a link="sa_vd" hover="SIMD&FP source and destination register (field "Rd")"><Vd></a><text>.16B, </text><a link="sa_vn" hover="Second SIMD&FP source register (field "Rn")"><Vn></a><text>.16B</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/crypto/aes/round" mylink="aarch64.instrs.vector.crypto.aes.round" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
if !<a link="impl-shared.HaveAESExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAESExt()">HaveAESExt</a>() then UNDEFINED;
|
||||
boolean decrypt = (D == '1');</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="AESE_B_cryptoaes" symboldefcount="1">
|
||||
<symbol link="sa_vd"><Vd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the name of the SIMD&FP source and destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AESE_B_cryptoaes" symboldefcount="1">
|
||||
<symbol link="sa_vn"><Vn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the name of the second SIMD&FP source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/crypto/aes/round" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="AArch64.CheckFPAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
|
||||
|
||||
bits(128) operand1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[d, 128];
|
||||
bits(128) operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128];
|
||||
bits(128) result;
|
||||
result = operand1 EOR operand2;
|
||||
if decrypt then
|
||||
result = <a link="impl-shared.AESInvSubBytes.1" file="shared_pseudocode.xml" hover="function: bits(128) AESInvSubBytes(bits(128) op)">AESInvSubBytes</a>(<a link="impl-shared.AESInvShiftRows.1" file="shared_pseudocode.xml" hover="function: bits(128) AESInvShiftRows(bits(128) op)">AESInvShiftRows</a>(result));
|
||||
else
|
||||
result = <a link="impl-shared.AESSubBytes.1" file="shared_pseudocode.xml" hover="function: bits(128) AESSubBytes(bits(128) op)">AESSubBytes</a>(<a link="impl-shared.AESShiftRows.1" file="shared_pseudocode.xml" hover="function: bits(128) AESShiftRows(bits(128) op)">AESShiftRows</a>(result));
|
||||
|
||||
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
133
spec/arm64_xml/aese_z_zz.xml
Normal file
133
spec/arm64_xml/aese_z_zz.xml
Normal file
@@ -0,0 +1,133 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="aese_z_zz" title="AESE" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESE" />
|
||||
</docvars>
|
||||
<heading>AESE</heading>
|
||||
<desc>
|
||||
<brief>AES single round encryption</brief>
|
||||
<description>
|
||||
<para>The <instruction>AESE</instruction> instruction reads a 16-byte state array from each 128-bit segment of the first source vector together with a round key from the corresponding 128-bit segment of the second source vector. Each state array undergoes a single round of the <arm-defined-word>AddRoundKey()</arm-defined-word>, <arm-defined-word>SubBytes()</arm-defined-word> and <arm-defined-word>ShiftRows()</arm-defined-word> transformations in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. This instruction is unpredicated.</para>
|
||||
<para>ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented.</para>
|
||||
<para>This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<sm_policy>SM_0_only</sm_policy>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESE" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SVE_AES" feature="FEAT_SVE_AES" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="AESE-Z.ZZ-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" name="size<1>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="size<0>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="16" name="op" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" name="o2" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zdn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="aese_z_zz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESE" />
|
||||
</docvars>
|
||||
<asmtemplate><text>AESE </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.B, </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.B, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.B</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="AESE-Z.ZZ-_" mylink="AESE-Z.ZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() || !<a link="impl-aarch64.HaveSVE2AES.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2AES()">HaveSVE2AES</a>() then UNDEFINED;
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="aese_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zdn"><Zdn></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="aese_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="AESE-Z.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckNonStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer segments = VL DIV 128;
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
|
||||
result = operand1 EOR operand2;
|
||||
for s = 0 to segments-1
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, s, 128] = <a link="impl-shared.AESSubBytes.1" file="shared_pseudocode.xml" hover="function: bits(128) AESSubBytes(bits(128) op)">AESSubBytes</a>(<a link="impl-shared.AESShiftRows.1" file="shared_pseudocode.xml" hover="function: bits(128) AESShiftRows(bits(128) op)">AESShiftRows</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[result, s, 128]));
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
132
spec/arm64_xml/aesimc_advsimd.xml
Normal file
132
spec/arm64_xml/aesimc_advsimd.xml
Normal file
@@ -0,0 +1,132 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="AESIMC_advsimd" title="AESIMC -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESIMC" />
|
||||
</docvars>
|
||||
<heading>AESIMC</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>AES inverse mix columns</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>AES inverse mix columns.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Advanced SIMD" oneof="1" id="iclass_advsimd" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESIMC" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="ARMv8.0" feature="FEAT_AES" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="aarch64/instrs/vector/crypto/aes/mix" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" width="4" name="opcode[4:1]" settings="4">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="12" name="D" usename="1" settings="1" psbits="x">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="11" width="2" settings="2">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="AESIMC_B_cryptoaes" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESIMC" />
|
||||
</docvars>
|
||||
<asmtemplate><text>AESIMC </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.16B, </text><a link="sa_vn" hover="SIMD&FP source register (field "Rn")"><Vn></a><text>.16B</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/crypto/aes/mix" mylink="aarch64.instrs.vector.crypto.aes.mix" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
if !<a link="impl-shared.HaveAESExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAESExt()">HaveAESExt</a>() then UNDEFINED;
|
||||
boolean decrypt = (D == '1');</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="AESIMC_B_cryptoaes" symboldefcount="1">
|
||||
<symbol link="sa_vd"><Vd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AESIMC_B_cryptoaes" symboldefcount="1">
|
||||
<symbol link="sa_vn"><Vn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the name of the SIMD&FP source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/crypto/aes/mix" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="AArch64.CheckFPAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
|
||||
|
||||
bits(128) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128];
|
||||
bits(128) result;
|
||||
if decrypt then
|
||||
result = <a link="impl-shared.AESInvMixColumns.1" file="shared_pseudocode.xml" hover="function: bits(128) AESInvMixColumns(bits (128) op)">AESInvMixColumns</a>(operand);
|
||||
else
|
||||
result = <a link="impl-shared.AESMixColumns.1" file="shared_pseudocode.xml" hover="function: bits(128) AESMixColumns(bits (128) op)">AESMixColumns</a>(operand);
|
||||
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
122
spec/arm64_xml/aesimc_z_z.xml
Normal file
122
spec/arm64_xml/aesimc_z_z.xml
Normal file
@@ -0,0 +1,122 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="aesimc_z_z" title="AESIMC" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESIMC" />
|
||||
</docvars>
|
||||
<heading>AESIMC</heading>
|
||||
<desc>
|
||||
<brief>AES inverse mix columns</brief>
|
||||
<description>
|
||||
<para>The <instruction>AESIMC</instruction> instruction reads a 16-byte state array from each 128-bit segment of the source register, and performs a single round of the <arm-defined-word>InvMixColumns()</arm-defined-word> transformation on each state array in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. This instruction is unpredicated.</para>
|
||||
<para>ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented.</para>
|
||||
<para>This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<sm_policy>SM_0_only</sm_policy>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESIMC" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SVE_AES" feature="FEAT_SVE_AES" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="AESIMC-Z.Z-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" name="size<1>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="size<0>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" width="11" settings="11">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" name="op" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zdn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="aesimc_z_z_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESIMC" />
|
||||
</docvars>
|
||||
<asmtemplate><text>AESIMC </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.B, </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.B</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="AESIMC-Z.Z-_" mylink="AESIMC-Z.Z-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() || !<a link="impl-aarch64.HaveSVE2AES.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2AES()">HaveSVE2AES</a>() then UNDEFINED;
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="aesimc_z_z_" symboldefcount="1">
|
||||
<symbol link="sa_zdn"><Zdn></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="AESIMC-Z.Z-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckNonStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer segments = VL DIV 128;
|
||||
bits(VL) operand = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for s = 0 to segments-1
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, s, 128] = <a link="impl-shared.AESInvMixColumns.1" file="shared_pseudocode.xml" hover="function: bits(128) AESInvMixColumns(bits (128) op)">AESInvMixColumns</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, s, 128]);
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
132
spec/arm64_xml/aesmc_advsimd.xml
Normal file
132
spec/arm64_xml/aesmc_advsimd.xml
Normal file
@@ -0,0 +1,132 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="AESMC_advsimd" title="AESMC -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESMC" />
|
||||
</docvars>
|
||||
<heading>AESMC</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>AES mix columns</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>AES mix columns.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Advanced SIMD" oneof="1" id="iclass_advsimd" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESMC" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="ARMv8.0" feature="FEAT_AES" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="aarch64/instrs/vector/crypto/aes/mix" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" width="5" settings="5">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" width="4" name="opcode[4:1]" settings="4">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="12" name="D" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="11" width="2" settings="2">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="AESMC_B_cryptoaes" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESMC" />
|
||||
</docvars>
|
||||
<asmtemplate><text>AESMC </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.16B, </text><a link="sa_vn" hover="SIMD&FP source register (field "Rn")"><Vn></a><text>.16B</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/crypto/aes/mix" mylink="aarch64.instrs.vector.crypto.aes.mix" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
if !<a link="impl-shared.HaveAESExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveAESExt()">HaveAESExt</a>() then UNDEFINED;
|
||||
boolean decrypt = (D == '1');</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="AESMC_B_cryptoaes" symboldefcount="1">
|
||||
<symbol link="sa_vd"><Vd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AESMC_B_cryptoaes" symboldefcount="1">
|
||||
<symbol link="sa_vn"><Vn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the name of the SIMD&FP source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/crypto/aes/mix" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="AArch64.CheckFPAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
|
||||
|
||||
bits(128) operand = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128];
|
||||
bits(128) result;
|
||||
if decrypt then
|
||||
result = <a link="impl-shared.AESInvMixColumns.1" file="shared_pseudocode.xml" hover="function: bits(128) AESInvMixColumns(bits (128) op)">AESInvMixColumns</a>(operand);
|
||||
else
|
||||
result = <a link="impl-shared.AESMixColumns.1" file="shared_pseudocode.xml" hover="function: bits(128) AESMixColumns(bits (128) op)">AESMixColumns</a>(operand);
|
||||
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
122
spec/arm64_xml/aesmc_z_z.xml
Normal file
122
spec/arm64_xml/aesmc_z_z.xml
Normal file
@@ -0,0 +1,122 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="aesmc_z_z" title="AESMC" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESMC" />
|
||||
</docvars>
|
||||
<heading>AESMC</heading>
|
||||
<desc>
|
||||
<brief>AES mix columns</brief>
|
||||
<description>
|
||||
<para>The <instruction>AESMC</instruction> instruction reads a 16-byte state array from each 128-bit segment of the source register, and performs a single round of the <arm-defined-word>MixColumns()</arm-defined-word> transformation on each state array in accordance with the AES standard. Each updated state array is destructively placed in the corresponding segment of the first source vector. This instruction is unpredicated.</para>
|
||||
<para>ID_AA64ZFR0_EL1.AES indicates whether this instruction is implemented.</para>
|
||||
<para>This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<sm_policy>SM_0_only</sm_policy>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESMC" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SVE_AES" feature="FEAT_SVE_AES" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="AESMC-Z.Z-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" name="size<1>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="size<0>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" width="11" settings="11">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" name="op" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zdn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="aesmc_z_z_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AESMC" />
|
||||
</docvars>
|
||||
<asmtemplate><text>AESMC </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.B, </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.B</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="AESMC-Z.Z-_" mylink="AESMC-Z.Z-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() || !<a link="impl-aarch64.HaveSVE2AES.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2AES()">HaveSVE2AES</a>() then UNDEFINED;
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="aesmc_z_z_" symboldefcount="1">
|
||||
<symbol link="sa_zdn"><Zdn></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="AESMC-Z.Z-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckNonStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer segments = VL DIV 128;
|
||||
bits(VL) operand = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for s = 0 to segments-1
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, s, 128] = <a link="impl-shared.AESMixColumns.1" file="shared_pseudocode.xml" hover="function: bits(128) AESMixColumns(bits (128) op)">AESMixColumns</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, s, 128]);
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
293
spec/arm64_xml/allinstrs.dtd
Normal file
293
spec/arm64_xml/allinstrs.dtd
Normal file
@@ -0,0 +1,293 @@
|
||||
<!--
|
||||
|
||||
XML language allinstrs for one big file
|
||||
Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
|
||||
-->
|
||||
|
||||
<!ENTITY % TEXT "(#PCDATA|a)*">
|
||||
<!ENTITY % formatted_words "asm-code|instruction|literal|xref|b|arm-defined-word|parameter|sup|sub|binarynumber|hexnumber|syntax|field|value|function|enum|enumvalue|url">
|
||||
<!ENTITY % formatted_text "(#PCDATA|para|note|list|%formatted_words;)*">
|
||||
<!ENTITY % inline "#PCDATA | a | anchor | txt">
|
||||
|
||||
<!ELEMENT arm-defined-word (#PCDATA)*>
|
||||
<!ELEMENT asm-code (#PCDATA)*>
|
||||
<!ELEMENT binarynumber (#PCDATA)*>
|
||||
<!ELEMENT enumvalue (#PCDATA)*>
|
||||
<!ELEMENT field (#PCDATA)*>
|
||||
<!ELEMENT function (#PCDATA)*>
|
||||
<!ELEMENT hexnumber (#PCDATA)*>
|
||||
<!ELEMENT instruction (#PCDATA)*>
|
||||
<!ELEMENT sup (#PCDATA)*>
|
||||
<!ELEMENT sub (#PCDATA)*>
|
||||
<!ELEMENT syntax (#PCDATA)*>
|
||||
<!ELEMENT value (#PCDATA)*>
|
||||
<!ELEMENT xref (#PCDATA)*>
|
||||
<!ATTLIST xref linkend CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT a (#PCDATA)>
|
||||
<!ELEMENT account (docvars?, intro)>
|
||||
<!ATTLIST account encodedin CDATA #IMPLIED>
|
||||
<!ELEMENT intro %formatted_text;>
|
||||
<!ATTLIST a href CDATA #IMPLIED class CDATA #IMPLIED link CDATA #IMPLIED
|
||||
file CDATA #IMPLIED hover CDATA #IMPLIED classid CDATA #IMPLIED>
|
||||
|
||||
<!ELEMENT allinstrs (title, (para | file | sect1)+)>
|
||||
<!ELEMENT file (alphaindex | encodingindex | instructionsection | constraint_text_mappings)>
|
||||
<!ATTLIST file type CDATA #REQUIRED file CDATA #REQUIRED>
|
||||
<!ATTLIST allinstrs id CDATA #REQUIRED xreflabel CDATA #REQUIRED>
|
||||
<!ELEMENT alphaindex (toptitle, iforms)>
|
||||
<!-- text: wrap PCDATA to avoid mixed mode. Deprecated -->
|
||||
<!ELEMENT text (#PCDATA)>
|
||||
<!ELEMENT asmtemplate (#PCDATA | text | a)*>
|
||||
<!ATTLIST asmtemplate class CDATA #IMPLIED
|
||||
role (alias_prototype | alias_equivalent_to) #IMPLIED>
|
||||
<!ELEMENT box (c*)>
|
||||
<!ATTLIST box hibit CDATA #IMPLIED name CDATA #IMPLIED
|
||||
usename CDATA #IMPLIED width CDATA #IMPLIED
|
||||
constraint CDATA #IMPLIED
|
||||
settings CDATA #IMPLIED
|
||||
psbits CDATA #IMPLIED>
|
||||
<!ELEMENT c (#PCDATA)>
|
||||
<!ATTLIST c colspan CDATA #IMPLIED href CDATA #IMPLIED>
|
||||
<!ELEMENT desc (brief, authored?, description?, encodingnotes?, syntaxnotes?, alg*, (longer, alg*)?, status?, predicated?, uses_dit?, takes_movprfx?, is_wide_zm?)>
|
||||
<!ELEMENT description (#PCDATA|list|para|%formatted_words;)*>
|
||||
<!ELEMENT status (#PCDATA)>
|
||||
<!ELEMENT syntaxnotes %formatted_text;>
|
||||
<!ELEMENT encodingnotes %formatted_text;>
|
||||
<!ELEMENT predicated (#PCDATA)>
|
||||
<!ELEMENT uses_dit (#PCDATA)>
|
||||
<!ELEMENT takes_movprfx (#PCDATA)>
|
||||
<!ELEMENT is_wide_zm (#PCDATA)>
|
||||
|
||||
<!ELEMENT brief %formatted_text;>
|
||||
<!ATTLIST brief enclist CDATA #IMPLIED
|
||||
checked (yes) #IMPLIED
|
||||
synth (single|multiple) #IMPLIED>
|
||||
<!ELEMENT authored %formatted_text;>
|
||||
<!ELEMENT alg %TEXT;>
|
||||
<!ATTLIST alg howmany CDATA #IMPLIED>
|
||||
<!ELEMENT longer %TEXT;>
|
||||
|
||||
<!ELEMENT encoding (docvars?, arch_variants?, box*, asmtemplate+, equivalent_to?)>
|
||||
<!ATTLIST encoding name CDATA #REQUIRED oneofinclass CDATA #REQUIRED
|
||||
oneof CDATA #REQUIRED label CDATA #REQUIRED
|
||||
bitdiffs CDATA #IMPLIED
|
||||
tags CDATA #IMPLIED>
|
||||
<!ELEMENT equivalent_to (asmtemplate, aliascond)>
|
||||
<!ELEMENT aliascond (%inline;)*>
|
||||
|
||||
<!ELEMENT encodingindex (hierarchy, groups?, maintable,
|
||||
(funcgroupheader?, iclass_sect+)+)>
|
||||
<!ATTLIST encodingindex instructionset CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT hierarchy (regdiagram, node+)>
|
||||
<!ELEMENT node (header, decode, regdiagram?, node*)>
|
||||
<!ATTLIST node groupname CDATA #IMPLIED iclass CDATA #IMPLIED unallocated CDATA #IMPLIED>
|
||||
<!ELEMENT header (#PCDATA)>
|
||||
|
||||
<!ELEMENT groups (maintable)>
|
||||
<!ATTLIST groups heading CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT funcgroupheader (#PCDATA)>
|
||||
<!ATTLIST funcgroupheader id CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT entry (%inline; | arch_variants)*>
|
||||
<!ATTLIST entry class CDATA #REQUIRED iclasslink CDATA #IMPLIED
|
||||
iclasslinkfile CDATA #IMPLIED>
|
||||
<!ELEMENT row (entry+)>
|
||||
<!ELEMENT tbody (row+ | tr+)>
|
||||
<!ELEMENT thead (row+ | tr+)>
|
||||
<!ATTLIST thead class CDATA #IMPLIED>
|
||||
<!ELEMENT tgroup (thead, tbody)>
|
||||
<!ATTLIST tgroup cols CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT list (listitem+)>
|
||||
<!ATTLIST list
|
||||
type (ordered|unordered|var|param) #REQUIRED
|
||||
role (standard|compressed|break|wide) #IMPLIED
|
||||
language CDATA #IMPLIED>
|
||||
<!ELEMENT listitem ((term*|param*), content)>
|
||||
<!ELEMENT term (#PCDATA|%formatted_words;)*>
|
||||
<!ELEMENT param (#PCDATA|%formatted_words;)*>
|
||||
<!ELEMENT content (#PCDATA|list|para|%formatted_words;)*>
|
||||
|
||||
<!ELEMENT table (tgroup+)>
|
||||
<!ATTLIST table class CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT after (#PCDATA)>
|
||||
<!ELEMENT definition (intro, table, after?)>
|
||||
<!ATTLIST definition encodedin CDATA #REQUIRED tabulatedwith CDATA #IMPLIED>
|
||||
|
||||
<!ELEMENT explanation_intro (#PCDATA | a)*>
|
||||
<!ATTLIST explanation_intro headingsabove CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT explanations (explanation_intro?, explanation*)>
|
||||
<!ATTLIST explanations scope CDATA #REQUIRED>
|
||||
<!ELEMENT explanation (symbol, (account | definition), arch_variants?)>
|
||||
<!ATTLIST explanation enclist CDATA #REQUIRED
|
||||
tags CDATA #IMPLIED
|
||||
symboldefcount CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT aliasmnem (desc?, (alias+ | aliases+))>
|
||||
<!ATTLIST aliasmnem mnemonic CDATA #REQUIRED id CDATA #REQUIRED heading CDATA #IMPLIED>
|
||||
|
||||
<!ELEMENT aliases (alias+)>
|
||||
<!ATTLIST aliases conditions CDATA #IMPLIED>
|
||||
|
||||
<!ELEMENT alias (#PCDATA | asmtemplate)*>
|
||||
<!ATTLIST alias enctag CDATA #IMPLIED encname CDATA #REQUIRED
|
||||
equivalent_to CDATA #REQUIRED
|
||||
assembler_prototype CDATA #REQUIRED
|
||||
conditions CDATA #IMPLIED
|
||||
description CDATA #IMPLIED>
|
||||
|
||||
<!ELEMENT heading %TEXT;>
|
||||
<!ELEMENT instructiontable (col+, thead, tbody)>
|
||||
<!ATTLIST instructiontable cols CDATA #REQUIRED iclass CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT iclass_sect (regdiagram, decode_constraints?, instructiontable)>
|
||||
<!ATTLIST iclass_sect id CDATA #REQUIRED title CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT decode_constraints (decode_constraint+)>
|
||||
<!ELEMENT decode_constraint EMPTY>
|
||||
<!ATTLIST decode_constraint name CDATA #REQUIRED op CDATA #REQUIRED val CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT iclass (docvars?, iclassintro?, arch_variants?, regdiagram, encoding+, ps_section?, constrained_unpredictables?)>
|
||||
<!ATTLIST iclass name CDATA #REQUIRED
|
||||
id CDATA #REQUIRED
|
||||
oneof CDATA #REQUIRED
|
||||
no_encodings CDATA #REQUIRED
|
||||
isa CDATA #REQUIRED>
|
||||
<!ELEMENT iclassintro (txt|a)*>
|
||||
<!ATTLIST iclassintro count CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT arch_variants (arch_variant*)>
|
||||
<!ELEMENT arch_variant EMPTY>
|
||||
<!ATTLIST arch_variant name CDATA #IMPLIED
|
||||
feature CDATA #IMPLIED>
|
||||
<!ELEMENT txt (#PCDATA)>
|
||||
|
||||
<!ELEMENT iform (#PCDATA)>
|
||||
<!ATTLIST iform id CDATA #REQUIRED iformfile CDATA #REQUIRED heading CDATA #REQUIRED>
|
||||
<!ELEMENT iforms (iform+)>
|
||||
<!ATTLIST iforms title CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT docvars (docvar+)>
|
||||
<!ELEMENT docvar EMPTY>
|
||||
<!ATTLIST docvar key CDATA #REQUIRED value CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT instructionsection (docvars?, heading, desc, operationalnotes?,
|
||||
(alias_list | aliasto)?,
|
||||
classes?, aliasmnem*, explanations?,
|
||||
aliastablehook?,
|
||||
ps_section*, exceptions?)>
|
||||
<!ATTLIST instructionsection id CDATA #REQUIRED
|
||||
title CDATA #REQUIRED
|
||||
tags CDATA #IMPLIED
|
||||
type (instruction|alias|pseudocode) #REQUIRED>
|
||||
|
||||
|
||||
<!--
|
||||
<operationalnotes>:
|
||||
-->
|
||||
<!ELEMENT operationalnotes %formatted_text;>
|
||||
|
||||
<!ELEMENT constraint_text_mappings (constraint_text_mapping*)>
|
||||
<!ELEMENT constraint_text_mapping (constraint_id, constraint_text)>
|
||||
<!ELEMENT constraint_id (#PCDATA)>
|
||||
<!ELEMENT constraint_text (#PCDATA|%formatted_words;)*>
|
||||
|
||||
<!ELEMENT classes (classesintro?, iclass+)>
|
||||
<!ELEMENT classesintro (txt | a)*>
|
||||
<!ATTLIST classesintro count CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT alias_list (alias_list_intro?, aliasref*, alias_list_outro?)>
|
||||
<!ATTLIST alias_list howmany CDATA #REQUIRED>
|
||||
<!ELEMENT alias_list_intro (#PCDATA)>
|
||||
<!ELEMENT aliasref (text, aliaspref+)>
|
||||
<!ATTLIST aliasref aliaspageid CDATA #REQUIRED
|
||||
aliasfile CDATA #REQUIRED
|
||||
hover CDATA #IMPLIED
|
||||
punct CDATA #REQUIRED>
|
||||
<!ELEMENT aliaspref (%inline;)*>
|
||||
<!ATTLIST aliaspref labels CDATA #IMPLIED>
|
||||
<!ELEMENT alias_list_outro (#PCDATA | text | aliastablelink)*>
|
||||
<!ELEMENT aliastablelink EMPTY>
|
||||
<!ELEMENT aliasto (#PCDATA)>
|
||||
<!ATTLIST aliasto refiform CDATA #REQUIRED
|
||||
iformid CDATA #REQUIRED>
|
||||
<!ELEMENT aliastablehook (#PCDATA)>
|
||||
<!ATTLIST aliastablehook anchor CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT col EMPTY>
|
||||
<!ATTLIST col bitno CDATA #IMPLIED colno CDATA #REQUIRED printwidth CDATA #IMPLIED>
|
||||
<!ELEMENT maintable (col*, tableheader, tablebody)>
|
||||
<!ATTLIST maintable size (16x2 | 32) #IMPLIED
|
||||
howmanybits CDATA #IMPLIED
|
||||
class (grouptable|allclasses) #IMPLIED>
|
||||
<!ELEMENT maintablesect EMPTY>
|
||||
<!ATTLIST maintablesect sect CDATA #REQUIRED
|
||||
linkref CDATA #IMPLIED>
|
||||
|
||||
<!ELEMENT para (#PCDATA|%formatted_words;|image)*>
|
||||
<!ELEMENT image EMPTY>
|
||||
<!ATTLIST image file CDATA #REQUIRED label CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT note (para|list|%formatted_words;)*>
|
||||
|
||||
<!ELEMENT decode (box*)>
|
||||
<!ELEMENT regdiagram (box*)>
|
||||
<!ATTLIST regdiagram form (16x2 | 32) #REQUIRED tworows CDATA #IMPLIED
|
||||
encname CDATA #IMPLIED psname CDATA #IMPLIED>
|
||||
<!ELEMENT sect1 (file | (title, para, file+))>
|
||||
<!ATTLIST sect1 id ID #REQUIRED>
|
||||
<!ELEMENT symbol (#PCDATA | a)*>
|
||||
<!ATTLIST symbol link CDATA #IMPLIED>
|
||||
<!ELEMENT tablebody (maintablesect*, tr+)*>
|
||||
<!ELEMENT tableheader (tr+)>
|
||||
<!ELEMENT td %TEXT;>
|
||||
<!ATTLIST td colspan CDATA #IMPLIED rowspan CDATA #IMPLIED
|
||||
class CDATA #IMPLIED iformid CDATA #IMPLIED
|
||||
bitwidth CDATA #IMPLIED note CDATA #IMPLIED
|
||||
ingroup (1) #IMPLIED
|
||||
bg CDATA #IMPLIED>
|
||||
<!ELEMENT th (#PCDATA)>
|
||||
<!ATTLIST th colno CDATA #IMPLIED colspan CDATA #IMPLIED rowspan CDATA #IMPLIED
|
||||
class CDATA #IMPLIED bitwidth CDATA #IMPLIED>
|
||||
<!ELEMENT title %TEXT;>
|
||||
<!ELEMENT toptitle EMPTY>
|
||||
<!ATTLIST toptitle instructionset CDATA #REQUIRED>
|
||||
<!ELEMENT tr (th+ | td+)>
|
||||
<!ATTLIST tr class CDATA #IMPLIED iclass CDATA #IMPLIED id CDATA #IMPLIED
|
||||
encname CDATA #IMPLIED first CDATA #IMPLIED last CDATA #IMPLIED
|
||||
iformfile CDATA #IMPLIED oneofthismnem CDATA #IMPLIED
|
||||
label CDATA #IMPLIED size CDATA #IMPLIED
|
||||
undef (1) #IMPLIED arch_version CDATA #IMPLIED
|
||||
groupid CDATA #IMPLIED groupname CDATA #IMPLIED>
|
||||
|
||||
<!ELEMENT anchor (#PCDATA)>
|
||||
<!ATTLIST anchor link CDATA #REQUIRED file CDATA #IMPLIED
|
||||
hover CDATA #IMPLIED>
|
||||
|
||||
<!ELEMENT pstext (line*)>
|
||||
<!ATTLIST pstext section CDATA #REQUIRED
|
||||
rep_section CDATA #IMPLIED
|
||||
mayhavelinks (1) #IMPLIED>
|
||||
|
||||
<!ELEMENT line (#PCDATA | a | anchor)*>
|
||||
<!ATTLIST line indent CDATA #IMPLIED link CDATA #IMPLIED
|
||||
file CDATA #IMPLIED hover CDATA #IMPLIED
|
||||
conts CDATA #IMPLIED>
|
||||
|
||||
<!ELEMENT ps (pstext)>
|
||||
<!ATTLIST ps name CDATA #REQUIRED
|
||||
mylink CDATA #IMPLIED
|
||||
enclabels CDATA #IMPLIED
|
||||
sections CDATA #REQUIRED
|
||||
secttype CDATA #IMPLIED>
|
||||
|
||||
<!ELEMENT ps_section (ps+)>
|
||||
<!ATTLIST ps_section howmany CDATA #REQUIRED>
|
||||
|
||||
16
spec/arm64_xml/alphaindex.dtd
Normal file
16
spec/arm64_xml/alphaindex.dtd
Normal file
@@ -0,0 +1,16 @@
|
||||
<!--
|
||||
|
||||
XML language accounts for alphaindex.xml
|
||||
Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
|
||||
-->
|
||||
|
||||
<!ELEMENT toptitle EMPTY>
|
||||
<!ATTLIST toptitle instructionset CDATA #REQUIRED>
|
||||
|
||||
<!ELEMENT iform (#PCDATA)>
|
||||
<!ATTLIST iform id CDATA #REQUIRED heading CDATA #REQUIRED iformfile CDATA #REQUIRED>
|
||||
<!ELEMENT iforms (iform+)>
|
||||
<!ATTLIST iforms title CDATA #REQUIRED>
|
||||
<!ELEMENT alphaindex (toptitle, iforms)>
|
||||
90
spec/arm64_xml/alphaindex.xsl
Normal file
90
spec/arm64_xml/alphaindex.xsl
Normal file
@@ -0,0 +1,90 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<xsl:stylesheet xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
|
||||
version="1.0" xmlns="http://www.w3.org/1999/xhtml">
|
||||
<xsl:output doctype-public="-//W3C//DTD XHTML 1.1//EN"
|
||||
doctype-system="http://www.w3.org/TR/xhtml11/DTD/xhtml11.dtd"
|
||||
method="html" encoding="utf-8"/>
|
||||
|
||||
<xsl:template match="/alphaindex">
|
||||
<html>
|
||||
<xsl:apply-templates />
|
||||
</html>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="/alphaindex/toptitle">
|
||||
<head>
|
||||
<title><xsl:value-of select="@instructionset"/></title>
|
||||
<link rel="stylesheet" type="text/css" href="insn.css"/>
|
||||
</head>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="/alphaindex/iforms">
|
||||
<body>
|
||||
<table style="margin: 0 auto;">
|
||||
<tr>
|
||||
<!-- autogenerator: header/footer start -->
|
||||
<!-- autogenerated -->
|
||||
<td><div class="topbar"><a href="index.xml">Base Instructions</a></div></td>
|
||||
<td><div class="topbar"><a href="fpsimdindex.xml">SIMD&FP Instructions</a></div></td>
|
||||
<td><div class="topbar"><a href="sveindex.xml">SVE Instructions</a></div></td>
|
||||
<td><div class="topbar"><a href="mortlachindex.xml">SME Instructions</a></div></td>
|
||||
<td><div class="topbar"><a href="encodingindex.xml">Index by Encoding</a></div></td>
|
||||
<td><div class="topbar"><a href="shared_pseudocode.xml">Shared Pseudocode</a></div></td>
|
||||
<td><div class="topbar"><a href="notice.xml">Proprietary Notice</a></div></td>
|
||||
<!-- autogenerator: header/footer end -->
|
||||
</tr>
|
||||
</table>
|
||||
<hr/>
|
||||
<h1 class="alphindextitle"><xsl:value-of select="@title"/></h1>
|
||||
<xsl:apply-templates />
|
||||
<hr/>
|
||||
<table style="margin: 0 auto;">
|
||||
<tr>
|
||||
<!-- autogenerator: header/footer start -->
|
||||
<!-- autogenerated -->
|
||||
<td><div class="topbar"><a href="index.xml">Base Instructions</a></div></td>
|
||||
<td><div class="topbar"><a href="fpsimdindex.xml">SIMD&FP Instructions</a></div></td>
|
||||
<td><div class="topbar"><a href="sveindex.xml">SVE Instructions</a></div></td>
|
||||
<td><div class="topbar"><a href="mortlachindex.xml">SME Instructions</a></div></td>
|
||||
<td><div class="topbar"><a href="encodingindex.xml">Index by Encoding</a></div></td>
|
||||
<td><div class="topbar"><a href="shared_pseudocode.xml">Shared Pseudocode</a></div></td>
|
||||
<td><div class="topbar"><a href="notice.xml">Proprietary Notice</a></div></td>
|
||||
<!-- autogenerator: header/footer end -->
|
||||
</tr>
|
||||
</table>
|
||||
<!-- version footer -->
|
||||
<p class="versions">
|
||||
Internal version only: isa v33.59, AdvSIMD v29.12, pseudocode v2022-12_rel, sve v2022-12_relb
|
||||
; Build timestamp: 2022-12-14T22:29
|
||||
</p>
|
||||
<p class="copyconf">
|
||||
Copyright © 2010-2022 Arm Limited or its affiliates. All rights reserved.
|
||||
This document is Non-Confidential.
|
||||
</p>
|
||||
</body>
|
||||
</xsl:template>
|
||||
|
||||
<xsl:template match="/alphaindex/iforms/iform">
|
||||
<div class="iformindex">
|
||||
<p class="iformindex">
|
||||
<span class="insnheading">
|
||||
<a>
|
||||
<xsl:attribute name="href">
|
||||
<xsl:choose>
|
||||
<xsl:when test="@id = ''">
|
||||
<xsl:value-of select="@href"/>
|
||||
</xsl:when>
|
||||
<xsl:otherwise>
|
||||
<xsl:value-of select="@iformfile"/>
|
||||
</xsl:otherwise>
|
||||
</xsl:choose>
|
||||
</xsl:attribute>
|
||||
<xsl:value-of select="@heading"/>
|
||||
</a>:
|
||||
<xsl:value-of select="."/>
|
||||
</span>
|
||||
</p>
|
||||
</div>
|
||||
</xsl:template>
|
||||
|
||||
</xsl:stylesheet>
|
||||
182
spec/arm64_xml/and_advsimd.xml
Normal file
182
spec/arm64_xml/and_advsimd.xml
Normal file
@@ -0,0 +1,182 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="AND_advsimd" title="AND (vector) -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="advsimd-reguse" value="3reg-same" />
|
||||
<docvar key="advsimd-type" value="simd" />
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<heading>AND (vector)</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Bitwise AND (vector)</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.</para>
|
||||
<para>Depending on the settings in the <xref linkend="AArch64.cpacr_el1">CPACR_EL1</xref>, <xref linkend="AArch64.cptr_el2">CPTR_EL2</xref>, and <xref linkend="AArch64.cptr_el3">CPTR_EL3</xref> registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Three registers of the same type" oneof="1" id="iclass_3reg_same" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="advsimd-reguse" value="3reg-same" />
|
||||
<docvar key="advsimd-type" value="simd" />
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/vector/arithmetic/binary/uniform/logical/and-orr" tworows="1">
|
||||
<box hibit="31" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="30" name="Q" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="29" name="U" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1" settings="2" psbits="xx">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="5" name="opcode" settings="5">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="10" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="AND_asimdsame_only" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="advsimd-reguse" value="3reg-same" />
|
||||
<docvar key="advsimd-type" value="simd" />
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<asmtemplate><text>AND </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "Q") [8B,16B]"><T></a><text>, </text><a link="sa_vn" hover="First SIMD&FP source register (field "Rn")"><Vn></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "Q") [8B,16B]"><T></a><text>, </text><a link="sa_vm" hover="Second SIMD&FP source register (field "Rm")"><Vm></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "Q") [8B,16B]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/arithmetic/binary/uniform/logical/and-orr" mylink="aarch64.instrs.vector.arithmetic.binary.uniform.logical.and-orr" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
integer esize = 8;
|
||||
integer datasize = if Q == '1' then 128 else 64;
|
||||
integer elements = datasize DIV esize;
|
||||
|
||||
boolean invert = (size<0> == '1');
|
||||
<a link="LogicalOp" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp</a> op = if size<1> == '1' then <a link="LogicalOp_ORR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_ORR</a> else <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a>;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="AND_asimdsame_only" symboldefcount="1">
|
||||
<symbol link="sa_vd"><Vd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AND_asimdsame_only" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="Q">
|
||||
<intro>Is an arrangement specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">Q</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="symbol">8B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="symbol">16B</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="AND_asimdsame_only" symboldefcount="1">
|
||||
<symbol link="sa_vn"><Vn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AND_asimdsame_only" symboldefcount="1">
|
||||
<symbol link="sa_vm"><Vm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the name of the second SIMD&FP source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/arithmetic/binary/uniform/logical/and-orr" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckFPAdvSIMDEnabled64.0" file="shared_pseudocode.xml" hover="function: CheckFPAdvSIMDEnabled64()">CheckFPAdvSIMDEnabled64</a>();
|
||||
bits(datasize) operand1 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, datasize];
|
||||
bits(datasize) operand2 = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, datasize];
|
||||
bits(datasize) result;
|
||||
|
||||
if invert then operand2 = NOT(operand2);
|
||||
|
||||
case op of
|
||||
when <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a>
|
||||
result = operand1 AND operand2;
|
||||
when <a link="LogicalOp_ORR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_ORR</a>
|
||||
result = operand1 OR operand2;
|
||||
|
||||
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
201
spec/arm64_xml/and_log_imm.xml
Normal file
201
spec/arm64_xml/and_log_imm.xml
Normal file
@@ -0,0 +1,201 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="AND_log_imm" title="AND (immediate) -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="immediate-type" value="imm12-bitfield" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<heading>AND (immediate)</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Bitwise AND (immediate)</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Bitwise AND (immediate) performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Not setting the condition flags" oneof="1" id="iclass_no_s" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="immediate-type" value="imm12-bitfield" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/logical/immediate" tworows="1">
|
||||
<box hibit="31" name="sf" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="30" width="2" name="opc" usename="1" settings="2" psbits="xx">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="6" settings="6">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="N" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="21" width="6" name="immr" usename="1">
|
||||
<c colspan="6"></c>
|
||||
</box>
|
||||
<box hibit="15" width="6" name="imms" usename="1">
|
||||
<c colspan="6"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="AND_32_log_imm" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0 && N == 0">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="immediate-type" value="imm12-bitfield" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" width="1" name="N">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>AND </text><a link="sa_wd_wsp" hover="32-bit destination general-purpose register or WSP (field "Rd")"><Wd|WSP></a><text>, </text><a link="sa_wn" hover="32-bit general-purpose source register (field "Rn")"><Wn></a><text>, #</text><a link="sa_imm" hover="Bitmask immediate (field "imms:immr")"><imm></a></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="AND_64_log_imm" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="immediate-type" value="imm12-bitfield" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>AND </text><a link="sa_xd_sp" hover="64-bit destination general-purpose register or SP (field "Rd")"><Xd|SP></a><text>, </text><a link="sa_xn" hover="64-bit general-purpose source register (field "Rn")"><Xn></a><text>, #</text><a link="sa_imm_1" hover="Bitmask immediate (field "N:imms:immr")"><imm></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/logical/immediate" mylink="aarch64.instrs.integer.logical.immediate" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer datasize = if sf == '1' then 64 else 32;
|
||||
boolean setflags;
|
||||
<a link="LogicalOp" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp</a> op;
|
||||
case opc of
|
||||
when '00' op = <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a>; setflags = FALSE;
|
||||
when '01' op = <a link="LogicalOp_ORR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_ORR</a>; setflags = FALSE;
|
||||
when '10' op = <a link="LogicalOp_EOR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_EOR</a>; setflags = FALSE;
|
||||
when '11' op = <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a>; setflags = TRUE;
|
||||
|
||||
bits(datasize) imm;
|
||||
if sf == '0' && N != '0' then UNDEFINED;
|
||||
(imm, -) = <a link="impl-aarch64.DecodeBitMasks.5" file="shared_pseudocode.xml" hover="function: (bits(M), bits(M)) DecodeBitMasks(bit immN, bits(6) imms, bits(6) immr, boolean immediate, integer M)">DecodeBitMasks</a>(N, imms, immr, TRUE, datasize);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="AND_32_log_imm" symboldefcount="1">
|
||||
<symbol link="sa_wd_wsp"><Wd|WSP></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AND_32_log_imm" symboldefcount="1">
|
||||
<symbol link="sa_wn"><Wn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AND_64_log_imm" symboldefcount="1">
|
||||
<symbol link="sa_xd_sp"><Xd|SP></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the destination general-purpose register or stack pointer, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AND_64_log_imm" symboldefcount="1">
|
||||
<symbol link="sa_xn"><Xn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AND_32_log_imm" symboldefcount="1">
|
||||
<symbol link="sa_imm"><imm></symbol>
|
||||
<account encodedin="immr:imms">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="32" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 32-bit variant: is the bitmask immediate, encoded in "imms:immr".</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AND_64_log_imm" symboldefcount="2">
|
||||
<symbol link="sa_imm_1"><imm></symbol>
|
||||
<account encodedin="N:immr:imms">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="64" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 64-bit variant: is the bitmask immediate, encoded in "N:imms:immr".</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/logical/immediate" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) result;
|
||||
bits(datasize) operand1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, datasize];
|
||||
bits(datasize) operand2 = imm;
|
||||
|
||||
case op of
|
||||
when <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a> result = operand1 AND operand2;
|
||||
when <a link="LogicalOp_ORR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_ORR</a> result = operand1 OR operand2;
|
||||
when <a link="LogicalOp_EOR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_EOR</a> result = operand1 EOR operand2;
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = result<datasize-1>:<a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result):'00';
|
||||
|
||||
if d == 31 && !setflags then
|
||||
<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(result, 64);
|
||||
else
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
256
spec/arm64_xml/and_log_shift.xml
Normal file
256
spec/arm64_xml/and_log_shift.xml
Normal file
@@ -0,0 +1,256 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="AND_log_shift" title="AND (shifted register) -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
<docvar key="reguse" value="shifted-reg" />
|
||||
</docvars>
|
||||
<heading>AND (shifted register)</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Bitwise AND (shifted register)</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Bitwise AND (shifted register) performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Not setting the condition flags" oneof="1" id="iclass_no_s" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
<docvar key="reguse" value="shifted-reg" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/logical/shiftedreg" tworows="1">
|
||||
<box hibit="31" name="sf" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="30" width="2" name="opc" usename="1" settings="2" psbits="xx">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="shift" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" name="N" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="6" name="imm6" usename="1">
|
||||
<c colspan="6"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="AND_32_log_shift" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="datatype-reguse" value="32-shifted-reg" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
<docvar key="reguse" value="shifted-reg" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>AND </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn" hover="First 32-bit general-purpose source register (field "Rn")"><Wn></a><text>, </text><a link="sa_wm" hover="Second 32-bit general-purpose source register (field "Rm")"><Wm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift applied to final source, default LSL (field "shift") [ASR,LSL,LSR,ROR]"><shift></a><text> #</text><a link="sa_amount" hover="Shift amount [0-31], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="AND_64_log_shift" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="datatype-reguse" value="64-shifted-reg" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
<docvar key="reguse" value="shifted-reg" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>AND </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn" hover="First 64-bit general-purpose source register (field "Rn")"><Xn></a><text>, </text><a link="sa_xm" hover="Second 64-bit general-purpose source register (field "Rm")"><Xm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift applied to final source, default LSL (field "shift") [ASR,LSL,LSR,ROR]"><shift></a><text> #</text><a link="sa_amount_1" hover="Shift amount [0-63], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/logical/shiftedreg" mylink="aarch64.instrs.integer.logical.shiftedreg" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
integer datasize = if sf == '1' then 64 else 32;
|
||||
boolean setflags;
|
||||
<a link="LogicalOp" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp</a> op;
|
||||
case opc of
|
||||
when '00' op = <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a>; setflags = FALSE;
|
||||
when '01' op = <a link="LogicalOp_ORR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_ORR</a>; setflags = FALSE;
|
||||
when '10' op = <a link="LogicalOp_EOR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_EOR</a>; setflags = FALSE;
|
||||
when '11' op = <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a>; setflags = TRUE;
|
||||
|
||||
if sf == '0' && imm6<5> == '1' then UNDEFINED;
|
||||
|
||||
<a link="ShiftType" file="shared_pseudocode.xml" hover="enumeration ShiftType {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType</a> shift_type = <a link="impl-aarch64.DecodeShift.1" file="shared_pseudocode.xml" hover="function: ShiftType DecodeShift(bits(2) op)">DecodeShift</a>(shift);
|
||||
integer shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);
|
||||
boolean invert = (N == '1');</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="AND_32_log_shift" symboldefcount="1">
|
||||
<symbol link="sa_wd"><Wd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AND_32_log_shift" symboldefcount="1">
|
||||
<symbol link="sa_wn"><Wn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AND_32_log_shift" symboldefcount="1">
|
||||
<symbol link="sa_wm"><Wm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AND_64_log_shift" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AND_64_log_shift" symboldefcount="1">
|
||||
<symbol link="sa_xn"><Xn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AND_64_log_shift" symboldefcount="1">
|
||||
<symbol link="sa_xm"><Xm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AND_32_log_shift, AND_64_log_shift" symboldefcount="1">
|
||||
<symbol link="sa_shift"><shift></symbol>
|
||||
<definition encodedin="shift">
|
||||
<intro>Is the optional shift to be applied to the final source, defaulting to LSL and </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">shift</entry>
|
||||
<entry class="symbol"><shift></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">LSL</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">LSR</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">ASR</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">ROR</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="AND_32_log_shift" symboldefcount="1">
|
||||
<symbol link="sa_amount"><amount></symbol>
|
||||
<account encodedin="imm6">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="datatype-reguse" value="32-shifted-reg" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 32-bit variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AND_64_log_shift" symboldefcount="2">
|
||||
<symbol link="sa_amount_1"><amount></symbol>
|
||||
<account encodedin="imm6">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="datatype-reguse" value="64-shifted-reg" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 64-bit variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field,</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/logical/shiftedreg" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) operand1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, datasize];
|
||||
bits(datasize) operand2 = <a link="impl-aarch64.ShiftReg.4" file="shared_pseudocode.xml" hover="function: bits(N) ShiftReg(integer reg, ShiftType shiftype, integer amount, integer N)">ShiftReg</a>(m, shift_type, shift_amount, datasize);
|
||||
bits(datasize) result;
|
||||
|
||||
if invert then operand2 = NOT(operand2);
|
||||
|
||||
case op of
|
||||
when <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a> result = operand1 AND operand2;
|
||||
when <a link="LogicalOp_ORR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_ORR</a> result = operand1 OR operand2;
|
||||
when <a link="LogicalOp_EOR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_EOR</a> result = operand1 EOR operand2;
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = result<datasize-1>:<a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result):'00';
|
||||
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
171
spec/arm64_xml/and_p_p_pp.xml
Normal file
171
spec/arm64_xml/and_p_p_pp.xml
Normal file
@@ -0,0 +1,171 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="and_p_p_pp" title="AND (predicates)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<heading>AND (predicates)</heading>
|
||||
<desc>
|
||||
<brief>Bitwise AND predicates</brief>
|
||||
<description>
|
||||
<para>Bitwise AND active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Does not set the condition flags.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>True</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
</desc>
|
||||
<alias_list howmany="1">
|
||||
<alias_list_intro>This instruction is used by the alias </alias_list_intro>
|
||||
<aliasref aliaspageid="MOV_and_p_p_pp" aliasfile="mov_and_p_p_pp.xml" hover="Move predicates (zeroing)" punct=".">
|
||||
<text>MOV (predicate, predicated, zeroing)</text>
|
||||
<aliaspref>S == '0' && Pn == Pm</aliaspref>
|
||||
</aliasref>
|
||||
<alias_list_outro>
|
||||
<text> See </text>
|
||||
<aliastablelink />
|
||||
<text> below for details of when the alias is preferred.</text>
|
||||
</alias_list_outro>
|
||||
</alias_list>
|
||||
<classes>
|
||||
<iclass name="Not setting the condition flags" oneof="1" id="iclass_no_s" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="AND-P.P.PP-Z" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" name="op" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="S" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="19" width="4" name="Pm" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
<box hibit="15" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="13" width="4" name="Pg" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
<box hibit="9" name="o2" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="8" width="4" name="Pn" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
<box hibit="4" name="o3" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="3" width="4" name="Pd" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="and_p_p_pp_z" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="no-s" />
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<asmtemplate><text>AND </text><a link="sa_pd" hover="Destination scalable predicate register (field "Pd")"><Pd></a><text>.B, </text><a link="sa_pg" hover="Governing scalable predicate register (field "Pg")"><Pg></a><text>/Z, </text><a link="sa_pn" hover="First source scalable predicate register (field "Pn")"><Pn></a><text>.B, </text><a link="sa_pm" hover="Second source scalable predicate register (field "Pm")"><Pm></a><text>.B</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="AND-P.P.PP-Z" mylink="AND-P.P.PP-Z" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8;
|
||||
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pm);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
boolean setflags = FALSE;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="and_p_p_pp_z" symboldefcount="1">
|
||||
<symbol link="sa_pd"><Pd></symbol>
|
||||
<account encodedin="Pd">
|
||||
<intro>
|
||||
<para>Is the name of the destination scalable predicate register, encoded in the "Pd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="and_p_p_pp_z" symboldefcount="1">
|
||||
<symbol link="sa_pg"><Pg></symbol>
|
||||
<account encodedin="Pg">
|
||||
<intro>
|
||||
<para>Is the name of the governing scalable predicate register, encoded in the "Pg" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="and_p_p_pp_z" symboldefcount="1">
|
||||
<symbol link="sa_pn"><Pn></symbol>
|
||||
<account encodedin="Pn">
|
||||
<intro>
|
||||
<para>Is the name of the first source scalable predicate register, encoded in the "Pn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="and_p_p_pp_z" symboldefcount="1">
|
||||
<symbol link="sa_pm"><Pm></symbol>
|
||||
<account encodedin="Pm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable predicate register, encoded in the "Pm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
|
||||
<ps_section howmany="1">
|
||||
<ps name="AND-P.P.PP-Z" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(PL) operand1 = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[n, PL];
|
||||
bits(PL) operand2 = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[m, PL];
|
||||
bits(PL) result;
|
||||
constant integer psize = esize DIV 8;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bit element1 = <a link="impl-aarch64.PredicateElement.3" file="shared_pseudocode.xml" hover="function: bit PredicateElement(bits(N) pred, integer e, integer esize)">PredicateElement</a>(operand1, e, esize);
|
||||
bit element2 = <a link="impl-aarch64.PredicateElement.3" file="shared_pseudocode.xml" hover="function: bit PredicateElement(bits(N) pred, integer e, integer esize)">PredicateElement</a>(operand2, e, esize);
|
||||
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(element1 AND element2, psize);
|
||||
else
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', psize);
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = <a link="impl-aarch64.PredTest.3" file="shared_pseudocode.xml" hover="function: bits(4) PredTest(bits(N) mask, bits(N) result, integer esize)">PredTest</a>(mask, result, esize);
|
||||
<a link="impl-aarch64.P.write.2" file="shared_pseudocode.xml" hover="accessor: P[integer n, integer width] = bits(width) value">P</a>[d, PL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
176
spec/arm64_xml/and_z_p_zz.xml
Normal file
176
spec/arm64_xml/and_z_p_zz.xml
Normal file
@@ -0,0 +1,176 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="and_z_p_zz" title="AND (vectors, predicated)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<heading>AND (vectors, predicated)</heading>
|
||||
<desc>
|
||||
<brief>Bitwise AND vectors (predicated)</brief>
|
||||
<description>
|
||||
<para>Bitwise AND active elements of the second source vector with corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>True</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<takes_movprfx>True</takes_movprfx>
|
||||
<takes_pred_movprfx>True</takes_pred_movprfx>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="AND-Z.P.ZZ-_">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="18" width="2" name="opc<2:1>" settings="2">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="16" name="opc<0>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="Pg" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zdn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="and_z_p_zz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<asmtemplate><text>AND </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/M, </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="AND-Z.P.ZZ-_" mylink="AND-Z.P.ZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="and_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zdn"><Zdn></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="and_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="and_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_pg"><Pg></symbol>
|
||||
<account encodedin="Pg">
|
||||
<intro>
|
||||
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="and_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="AND-Z.P.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = if <a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(esize) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
|
||||
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = element1 AND element2;
|
||||
else
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
186
spec/arm64_xml/and_z_zi.xml
Normal file
186
spec/arm64_xml/and_z_zi.xml
Normal file
@@ -0,0 +1,186 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="and_z_zi" title="AND (immediate)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<heading>AND (immediate)</heading>
|
||||
<desc>
|
||||
<brief>Bitwise AND with immediate (unpredicated)</brief>
|
||||
<description>
|
||||
<para>Bitwise AND an immediate with each 64-bit element of the source vector, and destructively place the results in the corresponding elements of the source vector. The immediate is a 64-bit value consisting of a single run of ones or zeros repeating every 2, 4, 8, 16, 32 or 64 bits. This instruction is unpredicated.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<takes_movprfx>True</takes_movprfx>
|
||||
</desc>
|
||||
<alias_list howmany="1">
|
||||
<alias_list_intro>This instruction is used by the alias </alias_list_intro>
|
||||
<aliasref aliaspageid="BIC_and_z_zi" aliasfile="bic_and_z_zi.xml" hover="Bitwise clear bits using immediate (unpredicated)" punct=".">
|
||||
<text>BIC (immediate)</text>
|
||||
<aliaspref>Never</aliaspref>
|
||||
</aliasref>
|
||||
<alias_list_outro>
|
||||
<text> See </text>
|
||||
<aliastablelink />
|
||||
<text> below for details of when the alias is preferred.</text>
|
||||
</alias_list_outro>
|
||||
</alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="AND-Z.ZI-_">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" name="opc<1>" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="22" name="opc" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" width="4" settings="4">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="17" width="13" name="imm13" usename="1">
|
||||
<c colspan="13"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zdn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="and_z_zi_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<asmtemplate><text>AND </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "imm13<12>:imm13<5:0>") [B,D,H,S]"><T></a><text>, </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "imm13<12>:imm13<5:0>") [B,D,H,S]"><T></a><text>, #</text><a link="sa_const" hover="64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits (field "imm13")"><const></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="AND-Z.ZI-_" mylink="AND-Z.ZI-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
bits(64) imm;
|
||||
(imm, -) = <a link="impl-aarch64.DecodeBitMasks.5" file="shared_pseudocode.xml" hover="function: (bits(M), bits(M)) DecodeBitMasks(bit immN, bits(6) imms, bits(6) immr, boolean immediate, integer M)">DecodeBitMasks</a>(imm13<12>, imm13<5:0>, imm13<11:6>, TRUE, 64);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="and_z_zi_" symboldefcount="1">
|
||||
<symbol link="sa_zdn"><Zdn></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="and_z_zi_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="imm13<12>:imm13<5:0>">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="3">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">imm13<12></entry>
|
||||
<entry class="bitfield">imm13<5:0></entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">0xxxxx</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">10xxxx</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">110xxx</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">1110xx</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">11110x</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">111110</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">111111</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="bitfield">xxxxxx</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="and_z_zi_" symboldefcount="1">
|
||||
<symbol link="sa_const"><const></symbol>
|
||||
<account encodedin="imm13">
|
||||
<intro>
|
||||
<para>Is a 64, 32, 16 or 8-bit bitmask consisting of replicated 2, 4, 8, 16, 32 or 64 bit fields, each field containing a rotated run of non-zero bits, encoded in the "imm13" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
|
||||
<ps_section howmany="1">
|
||||
<ps name="AND-Z.ZI-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV 64;
|
||||
bits(VL) operand = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(64) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, 64];
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 64] = element1 AND imm;
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
124
spec/arm64_xml/and_z_zz.xml
Normal file
124
spec/arm64_xml/and_z_zz.xml
Normal file
@@ -0,0 +1,124 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="and_z_zz" title="AND (vectors, unpredicated)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<heading>AND (vectors, unpredicated)</heading>
|
||||
<desc>
|
||||
<brief>Bitwise AND vectors (unpredicated)</brief>
|
||||
<description>
|
||||
<para>Bitwise AND all elements of the second source vector with corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector. This instruction is unpredicated.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="AND-Z.ZZ-_">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" name="opc<1>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="opc<0>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="6" settings="6">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="and_z_zz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AND" />
|
||||
</docvars>
|
||||
<asmtemplate><text>AND </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.D, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.D, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.D</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="AND-Z.ZZ-_" mylink="AND-Z.ZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="and_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zd"><Zd></symbol>
|
||||
<account encodedin="Zd">
|
||||
<intro>
|
||||
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="and_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="and_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="AND-Z.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = operand1 AND operand2;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
214
spec/arm64_xml/andqv_z_p_z.xml
Normal file
214
spec/arm64_xml/andqv_z_p_z.xml
Normal file
@@ -0,0 +1,214 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="andqv_z_p_z" title="ANDQV" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ANDQV" />
|
||||
</docvars>
|
||||
<heading>ANDQV</heading>
|
||||
<desc>
|
||||
<brief>Bitwise AND reduction of quadword vector segments</brief>
|
||||
<description>
|
||||
<para>Bitwise AND of the same element numbers from each 128-bit source vector segment, placing each result into the corresponding element number of the 128-bit SIMD&FP destination register. Inactive elements in the source vector are treated as all ones.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>True</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ANDQV" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SVE2p1" feature="FEAT_SVE2p1" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="ANDQV-Z.P.Z-_">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="4" settings="4">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="17" name="opc<1>" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="16" name="opc<0>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="Pg" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Vd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="andqv_z_p_z_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ANDQV" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ANDQV </text><a link="sa_vd" hover="Destination SIMD&FP register (field "Vd")"><Vd></a><text>.</text><a link="sa_t" hover="Arrangement specifier (field "size") [2D,4S,8H,16B]"><T></a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>.</text><a link="sa_tb" hover="Size specifier (field "size") [B,D,H,S]"><Tb></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ANDQV-Z.P.Z-_" mylink="ANDQV-Z.P.Z-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE2p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2p1()">HaveSVE2p1</a>() && !<a link="impl-aarch64.HaveSME2p1.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME2p1()">HaveSME2p1</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="andqv_z_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_vd"><Vd></symbol>
|
||||
<account encodedin="Vd">
|
||||
<intro>
|
||||
<para>Is the name of the destination SIMD&FP register, encoded in the "Vd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="andqv_z_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is an arrangement specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">16B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">8H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">4S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">2D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="andqv_z_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_pg"><Pg></symbol>
|
||||
<account encodedin="Pg">
|
||||
<intro>
|
||||
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="andqv_z_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="andqv_z_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_tb"><Tb></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><Tb></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ANDQV-Z.P.Z-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer segments = VL DIV 128;
|
||||
constant integer elempersegment = 128 DIV esize;
|
||||
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand = if <a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(128) result = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(128);
|
||||
bits(128) stmp = <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(128);
|
||||
|
||||
bits(esize) dtmp;
|
||||
|
||||
for e = 0 to elempersegment-1
|
||||
dtmp = <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize);
|
||||
for s = 0 to segments-1
|
||||
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, s * elempersegment + e, esize) then
|
||||
stmp = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, s, 128];
|
||||
dtmp = dtmp AND <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[stmp, e, esize];
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = dtmp<esize-1:0>;
|
||||
|
||||
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
213
spec/arm64_xml/ands_log_imm.xml
Normal file
213
spec/arm64_xml/ands_log_imm.xml
Normal file
@@ -0,0 +1,213 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ANDS_log_imm" title="ANDS (immediate) -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="immediate-type" value="imm12-bitfield" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ANDS" />
|
||||
</docvars>
|
||||
<heading>ANDS (immediate)</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Bitwise AND (immediate), setting flags</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Bitwise AND (immediate), setting flags, performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register. It updates the condition flags based on the result.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="1">
|
||||
<alias_list_intro>This instruction is used by the alias </alias_list_intro>
|
||||
<aliasref aliaspageid="TST_ANDS_log_imm" aliasfile="tst_ands_log_imm.xml" hover="Test bits (immediate)" punct=".">
|
||||
<text>TST (immediate)</text>
|
||||
<aliaspref>Rd == '11111'</aliaspref>
|
||||
</aliasref>
|
||||
<alias_list_outro>
|
||||
<text> See </text>
|
||||
<aliastablelink />
|
||||
<text> below for details of when the alias is preferred.</text>
|
||||
</alias_list_outro>
|
||||
</alias_list>
|
||||
<classes>
|
||||
<iclass name="Setting the condition flags" oneof="1" id="iclass_s" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="immediate-type" value="imm12-bitfield" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ANDS" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/logical/immediate" tworows="1">
|
||||
<box hibit="31" name="sf" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="30" width="2" name="opc" usename="1" settings="2" psbits="xx">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="28" width="6" settings="6">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="N" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="21" width="6" name="immr" usename="1">
|
||||
<c colspan="6"></c>
|
||||
</box>
|
||||
<box hibit="15" width="6" name="imms" usename="1">
|
||||
<c colspan="6"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ANDS_32S_log_imm" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0 && N == 0">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="immediate-type" value="imm12-bitfield" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ANDS" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" width="1" name="N">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>ANDS </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn" hover="32-bit general-purpose source register (field "Rn")"><Wn></a><text>, #</text><a link="sa_imm" hover="Bitmask immediate (field "imms:immr")"><imm></a></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="ANDS_64S_log_imm" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="immediate-type" value="imm12-bitfield" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ANDS" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>ANDS </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn" hover="64-bit general-purpose source register (field "Rn")"><Xn></a><text>, #</text><a link="sa_imm_1" hover="Bitmask immediate (field "N:imms:immr")"><imm></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/logical/immediate" mylink="aarch64.instrs.integer.logical.immediate" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer datasize = if sf == '1' then 64 else 32;
|
||||
boolean setflags;
|
||||
<a link="LogicalOp" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp</a> op;
|
||||
case opc of
|
||||
when '00' op = <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a>; setflags = FALSE;
|
||||
when '01' op = <a link="LogicalOp_ORR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_ORR</a>; setflags = FALSE;
|
||||
when '10' op = <a link="LogicalOp_EOR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_EOR</a>; setflags = FALSE;
|
||||
when '11' op = <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a>; setflags = TRUE;
|
||||
|
||||
bits(datasize) imm;
|
||||
if sf == '0' && N != '0' then UNDEFINED;
|
||||
(imm, -) = <a link="impl-aarch64.DecodeBitMasks.5" file="shared_pseudocode.xml" hover="function: (bits(M), bits(M)) DecodeBitMasks(bit immN, bits(6) imms, bits(6) immr, boolean immediate, integer M)">DecodeBitMasks</a>(N, imms, immr, TRUE, datasize);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ANDS_32S_log_imm" symboldefcount="1">
|
||||
<symbol link="sa_wd"><Wd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ANDS_32S_log_imm" symboldefcount="1">
|
||||
<symbol link="sa_wn"><Wn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ANDS_64S_log_imm" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ANDS_64S_log_imm" symboldefcount="1">
|
||||
<symbol link="sa_xn"><Xn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ANDS_32S_log_imm" symboldefcount="1">
|
||||
<symbol link="sa_imm"><imm></symbol>
|
||||
<account encodedin="immr:imms">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="32" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 32-bit variant: is the bitmask immediate, encoded in "imms:immr".</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ANDS_64S_log_imm" symboldefcount="2">
|
||||
<symbol link="sa_imm_1"><imm></symbol>
|
||||
<account encodedin="N:immr:imms">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="64" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 64-bit variant: is the bitmask immediate, encoded in "N:imms:immr".</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/logical/immediate" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) result;
|
||||
bits(datasize) operand1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, datasize];
|
||||
bits(datasize) operand2 = imm;
|
||||
|
||||
case op of
|
||||
when <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a> result = operand1 AND operand2;
|
||||
when <a link="LogicalOp_ORR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_ORR</a> result = operand1 OR operand2;
|
||||
when <a link="LogicalOp_EOR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_EOR</a> result = operand1 EOR operand2;
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = result<datasize-1>:<a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result):'00';
|
||||
|
||||
if d == 31 && !setflags then
|
||||
<a link="impl-aarch64.SP.write.0" file="shared_pseudocode.xml" hover="accessor: SP[] = bits(64) value">SP</a>[] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(result, 64);
|
||||
else
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
268
spec/arm64_xml/ands_log_shift.xml
Normal file
268
spec/arm64_xml/ands_log_shift.xml
Normal file
@@ -0,0 +1,268 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ANDS_log_shift" title="ANDS (shifted register) -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ANDS" />
|
||||
<docvar key="reguse" value="shifted-reg" />
|
||||
</docvars>
|
||||
<heading>ANDS (shifted register)</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Bitwise AND (shifted register), setting flags</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Bitwise AND (shifted register), setting flags, performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register. It updates the condition flags based on the result.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="1">
|
||||
<alias_list_intro>This instruction is used by the alias </alias_list_intro>
|
||||
<aliasref aliaspageid="TST_ANDS_log_shift" aliasfile="tst_ands_log_shift.xml" hover="Test bits (shifted register)" punct=".">
|
||||
<text>TST (shifted register)</text>
|
||||
<aliaspref>Rd == '11111'</aliaspref>
|
||||
</aliasref>
|
||||
<alias_list_outro>
|
||||
<text> See </text>
|
||||
<aliastablelink />
|
||||
<text> below for details of when the alias is preferred.</text>
|
||||
</alias_list_outro>
|
||||
</alias_list>
|
||||
<classes>
|
||||
<iclass name="Setting the condition flags" oneof="1" id="iclass_s" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ANDS" />
|
||||
<docvar key="reguse" value="shifted-reg" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/logical/shiftedreg" tworows="1">
|
||||
<box hibit="31" name="sf" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="30" width="2" name="opc" usename="1" settings="2" psbits="xx">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="28" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="shift" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" name="N" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="6" name="imm6" usename="1">
|
||||
<c colspan="6"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ANDS_32_log_shift" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="datatype-reguse" value="32-shifted-reg" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ANDS" />
|
||||
<docvar key="reguse" value="shifted-reg" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>ANDS </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn" hover="First 32-bit general-purpose source register (field "Rn")"><Wn></a><text>, </text><a link="sa_wm" hover="Second 32-bit general-purpose source register (field "Rm")"><Wm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift applied to final source, default LSL (field "shift") [ASR,LSL,LSR,ROR]"><shift></a><text> #</text><a link="sa_amount" hover="Shift amount [0-31], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="ANDS_64_log_shift" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="S" />
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="datatype-reguse" value="64-shifted-reg" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ANDS" />
|
||||
<docvar key="reguse" value="shifted-reg" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>ANDS </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn" hover="First 64-bit general-purpose source register (field "Rn")"><Xn></a><text>, </text><a link="sa_xm" hover="Second 64-bit general-purpose source register (field "Rm")"><Xm></a><text>{</text><text>, </text><a link="sa_shift" hover="Optional shift applied to final source, default LSL (field "shift") [ASR,LSL,LSR,ROR]"><shift></a><text> #</text><a link="sa_amount_1" hover="Shift amount [0-63], default 0 (field "imm6")"><amount></a><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/logical/shiftedreg" mylink="aarch64.instrs.integer.logical.shiftedreg" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
integer datasize = if sf == '1' then 64 else 32;
|
||||
boolean setflags;
|
||||
<a link="LogicalOp" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp</a> op;
|
||||
case opc of
|
||||
when '00' op = <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a>; setflags = FALSE;
|
||||
when '01' op = <a link="LogicalOp_ORR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_ORR</a>; setflags = FALSE;
|
||||
when '10' op = <a link="LogicalOp_EOR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_EOR</a>; setflags = FALSE;
|
||||
when '11' op = <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a>; setflags = TRUE;
|
||||
|
||||
if sf == '0' && imm6<5> == '1' then UNDEFINED;
|
||||
|
||||
<a link="ShiftType" file="shared_pseudocode.xml" hover="enumeration ShiftType {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType</a> shift_type = <a link="impl-aarch64.DecodeShift.1" file="shared_pseudocode.xml" hover="function: ShiftType DecodeShift(bits(2) op)">DecodeShift</a>(shift);
|
||||
integer shift_amount = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imm6);
|
||||
boolean invert = (N == '1');</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ANDS_32_log_shift" symboldefcount="1">
|
||||
<symbol link="sa_wd"><Wd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ANDS_32_log_shift" symboldefcount="1">
|
||||
<symbol link="sa_wn"><Wn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ANDS_32_log_shift" symboldefcount="1">
|
||||
<symbol link="sa_wm"><Wm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ANDS_64_log_shift" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ANDS_64_log_shift" symboldefcount="1">
|
||||
<symbol link="sa_xn"><Xn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ANDS_64_log_shift" symboldefcount="1">
|
||||
<symbol link="sa_xm"><Xm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the second general-purpose source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ANDS_32_log_shift, ANDS_64_log_shift" symboldefcount="1">
|
||||
<symbol link="sa_shift"><shift></symbol>
|
||||
<definition encodedin="shift">
|
||||
<intro>Is the optional shift to be applied to the final source, defaulting to LSL and </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">shift</entry>
|
||||
<entry class="symbol"><shift></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">LSL</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">LSR</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">ASR</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">ROR</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="ANDS_32_log_shift" symboldefcount="1">
|
||||
<symbol link="sa_amount"><amount></symbol>
|
||||
<account encodedin="imm6">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="datatype-reguse" value="32-shifted-reg" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 32-bit variant: is the shift amount, in the range 0 to 31, defaulting to 0 and encoded in the "imm6" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ANDS_64_log_shift" symboldefcount="2">
|
||||
<symbol link="sa_amount_1"><amount></symbol>
|
||||
<account encodedin="imm6">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="datatype-reguse" value="64-shifted-reg" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 64-bit variant: is the shift amount, in the range 0 to 63, defaulting to 0 and encoded in the "imm6" field,</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/logical/shiftedreg" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) operand1 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[n, datasize];
|
||||
bits(datasize) operand2 = <a link="impl-aarch64.ShiftReg.4" file="shared_pseudocode.xml" hover="function: bits(N) ShiftReg(integer reg, ShiftType shiftype, integer amount, integer N)">ShiftReg</a>(m, shift_type, shift_amount, datasize);
|
||||
bits(datasize) result;
|
||||
|
||||
if invert then operand2 = NOT(operand2);
|
||||
|
||||
case op of
|
||||
when <a link="LogicalOp_AND" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_AND</a> result = operand1 AND operand2;
|
||||
when <a link="LogicalOp_ORR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_ORR</a> result = operand1 OR operand2;
|
||||
when <a link="LogicalOp_EOR" file="shared_pseudocode.xml" hover="enumeration LogicalOp {LogicalOp_AND, LogicalOp_EOR, LogicalOp_ORR}">LogicalOp_EOR</a> result = operand1 EOR operand2;
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = result<datasize-1>:<a link="impl-shared.IsZeroBit.1" file="shared_pseudocode.xml" hover="function: bit IsZeroBit(bits(N) x)">IsZeroBit</a>(result):'00';
|
||||
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
172
spec/arm64_xml/ands_p_p_pp.xml
Normal file
172
spec/arm64_xml/ands_p_p_pp.xml
Normal file
@@ -0,0 +1,172 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ands_p_p_pp" title="ANDS" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="s" />
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ANDS" />
|
||||
</docvars>
|
||||
<heading>ANDS</heading>
|
||||
<desc>
|
||||
<brief>Bitwise AND predicates, setting the condition flags</brief>
|
||||
<description>
|
||||
<para>Bitwise AND active elements of the second source predicate with corresponding elements of the first source predicate and place the results in the corresponding elements of the destination predicate. Inactive elements in the destination predicate register are set to zero. Sets the <arm-defined-word>First</arm-defined-word> (N), <arm-defined-word>None</arm-defined-word> (Z), <arm-defined-word>!Last</arm-defined-word> (C) condition flags based on the predicate result, and the V flag to zero.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>True</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<affected_by_sme output="NZCV condition flags" />
|
||||
</desc>
|
||||
<alias_list howmany="1">
|
||||
<alias_list_intro>This instruction is used by the alias </alias_list_intro>
|
||||
<aliasref aliaspageid="MOVS_ands_p_p_pp" aliasfile="movs_ands_p_p_pp.xml" hover="Move predicates (zeroing)" punct=".">
|
||||
<text>MOVS (predicated)</text>
|
||||
<aliaspref>S == '1' && Pn == Pm</aliaspref>
|
||||
</aliasref>
|
||||
<alias_list_outro>
|
||||
<text> See </text>
|
||||
<aliastablelink />
|
||||
<text> below for details of when the alias is preferred.</text>
|
||||
</alias_list_outro>
|
||||
</alias_list>
|
||||
<classes>
|
||||
<iclass name="Setting the condition flags" oneof="1" id="iclass_s" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="s" />
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ANDS" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ANDS-P.P.PP-Z" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" name="op" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="S" usename="1" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="21" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="19" width="4" name="Pm" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
<box hibit="15" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="13" width="4" name="Pg" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
<box hibit="9" name="o2" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="8" width="4" name="Pn" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
<box hibit="4" name="o3" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="3" width="4" name="Pd" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ands_p_p_pp_z" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="cond-setting" value="s" />
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ANDS" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ANDS </text><a link="sa_pd" hover="Destination scalable predicate register (field "Pd")"><Pd></a><text>.B, </text><a link="sa_pg" hover="Governing scalable predicate register (field "Pg")"><Pg></a><text>/Z, </text><a link="sa_pn" hover="First source scalable predicate register (field "Pn")"><Pn></a><text>.B, </text><a link="sa_pm" hover="Second source scalable predicate register (field "Pm")"><Pm></a><text>.B</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ANDS-P.P.PP-Z" mylink="ANDS-P.P.PP-Z" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8;
|
||||
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pm);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pd);
|
||||
boolean setflags = TRUE;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ands_p_p_pp_z" symboldefcount="1">
|
||||
<symbol link="sa_pd"><Pd></symbol>
|
||||
<account encodedin="Pd">
|
||||
<intro>
|
||||
<para>Is the name of the destination scalable predicate register, encoded in the "Pd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ands_p_p_pp_z" symboldefcount="1">
|
||||
<symbol link="sa_pg"><Pg></symbol>
|
||||
<account encodedin="Pg">
|
||||
<intro>
|
||||
<para>Is the name of the governing scalable predicate register, encoded in the "Pg" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ands_p_p_pp_z" symboldefcount="1">
|
||||
<symbol link="sa_pn"><Pn></symbol>
|
||||
<account encodedin="Pn">
|
||||
<intro>
|
||||
<para>Is the name of the first source scalable predicate register, encoded in the "Pn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ands_p_p_pp_z" symboldefcount="1">
|
||||
<symbol link="sa_pm"><Pm></symbol>
|
||||
<account encodedin="Pm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable predicate register, encoded in the "Pm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<aliastablehook anchor="aliasconditions">Alias Conditions</aliastablehook>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ANDS-P.P.PP-Z" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(PL) operand1 = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[n, PL];
|
||||
bits(PL) operand2 = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[m, PL];
|
||||
bits(PL) result;
|
||||
constant integer psize = esize DIV 8;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bit element1 = <a link="impl-aarch64.PredicateElement.3" file="shared_pseudocode.xml" hover="function: bit PredicateElement(bits(N) pred, integer e, integer esize)">PredicateElement</a>(operand1, e, esize);
|
||||
bit element2 = <a link="impl-aarch64.PredicateElement.3" file="shared_pseudocode.xml" hover="function: bit PredicateElement(bits(N) pred, integer e, integer esize)">PredicateElement</a>(operand2, e, esize);
|
||||
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>(element1 AND element2, psize);
|
||||
else
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, psize] = <a link="impl-shared.ZeroExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) ZeroExtend(bits(M) x, integer N)">ZeroExtend</a>('0', psize);
|
||||
|
||||
if setflags then
|
||||
PSTATE.<N,Z,C,V> = <a link="impl-aarch64.PredTest.3" file="shared_pseudocode.xml" hover="function: bits(4) PredTest(bits(N) mask, bits(N) result, integer esize)">PredTest</a>(mask, result, esize);
|
||||
<a link="impl-aarch64.P.write.2" file="shared_pseudocode.xml" hover="accessor: P[integer n, integer width] = bits(width) value">P</a>[d, PL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
203
spec/arm64_xml/andv_r_p_z.xml
Normal file
203
spec/arm64_xml/andv_r_p_z.xml
Normal file
@@ -0,0 +1,203 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="andv_r_p_z" title="ANDV" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ANDV" />
|
||||
</docvars>
|
||||
<heading>ANDV</heading>
|
||||
<desc>
|
||||
<brief>Bitwise AND reduction to scalar</brief>
|
||||
<description>
|
||||
<para>Bitwise AND horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as all ones.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>True</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ANDV" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ANDV-R.P.Z-_">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="4" settings="4">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="17" name="opc<1>" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="16" name="opc<0>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="Pg" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Vd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="andv_r_p_z_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ANDV" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ANDV </text><a link="sa_v" hover="Width specifier (field "size") [B,D,H,S]"><V></a><a link="sa_d" hover="Destination SIMD&FP register number [0-31] (field "Vd")"><d></a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ANDV-R.P.Z-_" mylink="ANDV-R.P.Z-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Vd);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="andv_r_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_v"><V></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is a width specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><V></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="andv_r_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_d"><d></symbol>
|
||||
<account encodedin="Vd">
|
||||
<intro>
|
||||
<para>Is the number [0-31] of the destination SIMD&FP register, encoded in the "Vd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="andv_r_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_pg"><Pg></symbol>
|
||||
<account encodedin="Pg">
|
||||
<intro>
|
||||
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="andv_r_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="andv_r_p_z_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ANDV-R.P.Z-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand = if <a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(esize) result = <a link="impl-shared.Ones.1" file="shared_pseudocode.xml" hover="function: bits(N) Ones(integer N)">Ones</a>(esize);
|
||||
|
||||
for e = 0 to elements-1
|
||||
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
result = result AND <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand, e, esize];
|
||||
|
||||
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, esize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
168
spec/arm64_xml/asr_asrv.xml
Normal file
168
spec/arm64_xml/asr_asrv.xml
Normal file
@@ -0,0 +1,168 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ASR_ASRV" title="ASR (register) -- A64" type="alias">
|
||||
<docvars>
|
||||
<docvar key="alias_mnemonic" value="ASR" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASRV" />
|
||||
<docvar key="source-type" value="src-is-register" />
|
||||
</docvars>
|
||||
<heading>ASR (register)</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Arithmetic Shift Right (register)</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The remainder obtained by dividing the second source register by the data size defines the number of bits by which the first source register is right-shifted.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<aliasto refiform="asrv.xml" iformid="ASRV">ASRV</aliasto>
|
||||
<classes>
|
||||
<iclass name="Integer" oneof="1" id="iclass_general" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASRV" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/shift/variable" tworows="1">
|
||||
<box hibit="31" name="sf" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="30" name="op" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="29" name="S" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="8" settings="8">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="4" name="opcode2[5:2]" settings="4">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="11" width="2" name="op2" usename="1" settings="2" psbits="xx">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ASR_ASRV_32_dp_2src" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
|
||||
<docvars>
|
||||
<docvar key="alias_mnemonic" value="ASR" />
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASRV" />
|
||||
<docvar key="source-type" value="src-is-register" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>ASR </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn" hover="First 32-bit general-purpose source register (field "Rn")"><Wn></a><text>, </text><a link="sa_wm" hover="Second 32-bit general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits (field "Rm")"><Wm></a></asmtemplate>
|
||||
<equivalent_to>
|
||||
<asmtemplate><a href="asrv.xml#ASRV_32_dp_2src">ASRV</a><text> </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn" hover="First 32-bit general-purpose source register (field "Rn")"><Wn></a><text>, </text><a link="sa_wm" hover="Second 32-bit general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits (field "Rm")"><Wm></a></asmtemplate>
|
||||
<aliascond>Unconditionally</aliascond>
|
||||
</equivalent_to>
|
||||
</encoding>
|
||||
<encoding name="ASR_ASRV_64_dp_2src" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
|
||||
<docvars>
|
||||
<docvar key="alias_mnemonic" value="ASR" />
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASRV" />
|
||||
<docvar key="source-type" value="src-is-register" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>ASR </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn" hover="First 64-bit general-purpose source register (field "Rn")"><Xn></a><text>, </text><a link="sa_xm" hover="Second 64-bit general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits (field "Rm")"><Xm></a></asmtemplate>
|
||||
<equivalent_to>
|
||||
<asmtemplate><a href="asrv.xml#ASRV_64_dp_2src">ASRV</a><text> </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn" hover="First 64-bit general-purpose source register (field "Rn")"><Xn></a><text>, </text><a link="sa_xm" hover="Second 64-bit general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits (field "Rm")"><Xm></a></asmtemplate>
|
||||
<aliascond>Unconditionally</aliascond>
|
||||
</equivalent_to>
|
||||
</encoding>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ASR_ASRV_32_dp_2src" symboldefcount="1">
|
||||
<symbol link="sa_wd"><Wd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ASR_ASRV_32_dp_2src" symboldefcount="1">
|
||||
<symbol link="sa_wn"><Wn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ASR_ASRV_32_dp_2src" symboldefcount="1">
|
||||
<symbol link="sa_wm"><Wm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the second general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ASR_ASRV_64_dp_2src" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ASR_ASRV_64_dp_2src" symboldefcount="1">
|
||||
<symbol link="sa_xn"><Xn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ASR_ASRV_64_dp_2src" symboldefcount="1">
|
||||
<symbol link="sa_xm"><Xm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the second general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
</instructionsection>
|
||||
197
spec/arm64_xml/asr_sbfm.xml
Normal file
197
spec/arm64_xml/asr_sbfm.xml
Normal file
@@ -0,0 +1,197 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ASR_SBFM" title="ASR (immediate) -- A64" type="alias">
|
||||
<docvars>
|
||||
<docvar key="alias_mnemonic" value="ASR" />
|
||||
<docvar key="bitfield-fill" value="signed-fill" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="SBFM" />
|
||||
<docvar key="source-type" value="src-is-immediate" />
|
||||
</docvars>
|
||||
<heading>ASR (immediate)</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Arithmetic Shift Right (immediate)</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of the sign bit in the upper bits and zeros in the lower bits, and writes the result to the destination register.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<aliasto refiform="sbfm.xml" iformid="SBFM">SBFM</aliasto>
|
||||
<classes>
|
||||
<iclass name="With sign replication to left and zeros to right" oneof="1" id="iclass_signed_fill" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="bitfield-fill" value="signed-fill" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="SBFM" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/bitfield" tworows="1">
|
||||
<box hibit="31" name="sf" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="30" width="2" name="opc" usename="1" settings="2" psbits="xx">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="6" settings="6">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="N" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="21" width="6" name="immr" usename="1">
|
||||
<c colspan="6"></c>
|
||||
</box>
|
||||
<box hibit="15" width="6" name="imms" usename="1" settings="5" psbits="xxxxxx">
|
||||
<c>x</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ASR_SBFM_32M_bitfield" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0 && N == 0 && imms == 011111">
|
||||
<docvars>
|
||||
<docvar key="alias_mnemonic" value="ASR" />
|
||||
<docvar key="bitfield-fill" value="signed-fill" />
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="SBFM" />
|
||||
<docvar key="source-type" value="src-is-immediate" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" width="1" name="N">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="6" name="imms">
|
||||
<c>0</c>
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c></c>
|
||||
</box>
|
||||
<asmtemplate><text>ASR </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn" hover="32-bit general-purpose source register (field "Rn")"><Wn></a><text>, #</text><a link="sa_shift" hover="Shift amount [0-31] (field "immr")"><shift></a></asmtemplate>
|
||||
<equivalent_to>
|
||||
<asmtemplate><a href="sbfm.xml#SBFM_32M_bitfield">SBFM</a><text> </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn" hover="32-bit general-purpose source register (field "Rn")"><Wn></a><text>, #</text><a link="sa_shift" hover="Shift amount [0-31] (field "immr")"><shift></a><text>, #31</text></asmtemplate>
|
||||
<aliascond>Unconditionally</aliascond>
|
||||
</equivalent_to>
|
||||
</encoding>
|
||||
<encoding name="ASR_SBFM_64M_bitfield" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1 && N == 1 && imms == 111111">
|
||||
<docvars>
|
||||
<docvar key="alias_mnemonic" value="ASR" />
|
||||
<docvar key="bitfield-fill" value="signed-fill" />
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="SBFM" />
|
||||
<docvar key="source-type" value="src-is-immediate" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="22" width="1" name="N">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="15" width="6" name="imms">
|
||||
<c>1</c>
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c></c>
|
||||
</box>
|
||||
<asmtemplate><text>ASR </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn" hover="64-bit general-purpose source register (field "Rn")"><Xn></a><text>, #</text><a link="sa_shift_1" hover="Shift amount [0-63] (field "immr")"><shift></a></asmtemplate>
|
||||
<equivalent_to>
|
||||
<asmtemplate><a href="sbfm.xml#SBFM_64M_bitfield">SBFM</a><text> </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn" hover="64-bit general-purpose source register (field "Rn")"><Xn></a><text>, #</text><a link="sa_shift_1" hover="Shift amount [0-63] (field "immr")"><shift></a><text>, #63</text></asmtemplate>
|
||||
<aliascond>Unconditionally</aliascond>
|
||||
</equivalent_to>
|
||||
</encoding>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ASR_SBFM_32M_bitfield" symboldefcount="1">
|
||||
<symbol link="sa_wd"><Wd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ASR_SBFM_32M_bitfield" symboldefcount="1">
|
||||
<symbol link="sa_wn"><Wn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ASR_SBFM_64M_bitfield" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ASR_SBFM_64M_bitfield" symboldefcount="1">
|
||||
<symbol link="sa_xn"><Xn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ASR_SBFM_32M_bitfield" symboldefcount="1">
|
||||
<symbol link="sa_shift"><shift></symbol>
|
||||
<account encodedin="immr">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="32" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 32-bit variant: is the shift amount, in the range 0 to 31, encoded in the "immr" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ASR_SBFM_64M_bitfield" symboldefcount="2">
|
||||
<symbol link="sa_shift_1"><shift></symbol>
|
||||
<account encodedin="immr">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="64" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 64-bit variant: is the shift amount, in the range 0 to 63, encoded in the "immr" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
</instructionsection>
|
||||
198
spec/arm64_xml/asr_z_p_zi.xml
Normal file
198
spec/arm64_xml/asr_z_p_zi.xml
Normal file
@@ -0,0 +1,198 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="asr_z_p_zi" title="ASR (immediate, predicated)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASR" />
|
||||
</docvars>
|
||||
<heading>ASR (immediate, predicated)</heading>
|
||||
<desc>
|
||||
<brief>Arithmetic shift right by immediate (predicated)</brief>
|
||||
<description>
|
||||
<para>Shift right by immediate, preserving the sign bit, each active element of the source vector, and destructively place the results in the corresponding elements of the source vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. Inactive elements in the destination vector register remain unmodified.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>True</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<takes_movprfx>True</takes_movprfx>
|
||||
<takes_pred_movprfx>True</takes_pred_movprfx>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASR" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ASR-Z.P.ZI-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="tszh" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="19" name="opc<1>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="18" name="opc<0>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="17" name="L" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" name="U" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="3" settings="3">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="Pg" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="2" name="tszl" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="7" width="3" name="imm3" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zdn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="asr_z_p_zi_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASR" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ASR </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "tszh:tszl") [B,D,H,S]"><T></a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/M, </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "tszh:tszl") [B,D,H,S]"><T></a><text>, #</text><a link="sa_const" hover="Immediate shift amount [1-number of bits per element] (field "tszh:tszl:imm3")"><const></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ASR-Z.P.ZI-_" mylink="ASR-Z.P.ZI-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
bits(4) tsize = tszh:tszl;
|
||||
integer esize;
|
||||
case tsize of
|
||||
when '0000' UNDEFINED;
|
||||
when '0001' esize = 8;
|
||||
when '001x' esize = 16;
|
||||
when '01xx' esize = 32;
|
||||
when '1xxx' esize = 64;
|
||||
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer shift = (2 * esize) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tsize:imm3);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="asr_z_p_zi_" symboldefcount="1">
|
||||
<symbol link="sa_zdn"><Zdn></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="asr_z_p_zi_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="tszh:tszl">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="3">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">tszh</entry>
|
||||
<entry class="bitfield">tszl</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">1x</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="bitfield">xx</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">1x</entry>
|
||||
<entry class="bitfield">xx</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="asr_z_p_zi_" symboldefcount="1">
|
||||
<symbol link="sa_pg"><Pg></symbol>
|
||||
<account encodedin="Pg">
|
||||
<intro>
|
||||
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="asr_z_p_zi_" symboldefcount="1">
|
||||
<symbol link="sa_const"><const></symbol>
|
||||
<account encodedin="imm3:tszh:tszl">
|
||||
<intro>
|
||||
<para>Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ASR-Z.P.ZI-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
constant integer PL = VL DIV 8;
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.ASR.2" file="shared_pseudocode.xml" hover="function: bits(N) ASR(bits(N) x, integer shift)">ASR</a>(element1, shift);
|
||||
else
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
181
spec/arm64_xml/asr_z_p_zw.xml
Normal file
181
spec/arm64_xml/asr_z_p_zw.xml
Normal file
@@ -0,0 +1,181 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="asr_z_p_zw" title="ASR (wide elements, predicated)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASR" />
|
||||
</docvars>
|
||||
<heading>ASR (wide elements, predicated)</heading>
|
||||
<desc>
|
||||
<brief>Arithmetic shift right by 64-bit wide elements (predicated)</brief>
|
||||
<description>
|
||||
<para>Shift right, preserving the sign bit, active elements of the first source vector by corresponding overlapping 64-bit elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. The shift amount is a vector of unsigned 64-bit doubleword elements in which all bits are significant, and not used modulo the destination element size. Inactive elements in the destination vector register remain unmodified.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>True</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<takes_movprfx>True</takes_movprfx>
|
||||
<takes_pred_movprfx>True</takes_pred_movprfx>
|
||||
<is_wide_zm>True</is_wide_zm>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASR" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ASR-Z.P.ZW-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="18" name="R" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="17" name="L" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" name="U" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="3" settings="3">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="Pg" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zdn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="asr_z_p_zw_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASR" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ASR </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,H,S]"><T></a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/M, </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,H,S]"><T></a><text>, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.D</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ASR-Z.P.ZW-_" mylink="ASR-Z.P.ZW-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '11' then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="asr_z_p_zw_" symboldefcount="1">
|
||||
<symbol link="sa_zdn"><Zdn></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="asr_z_p_zw_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="asr_z_p_zw_" symboldefcount="1">
|
||||
<symbol link="sa_pg"><Pg></symbol>
|
||||
<account encodedin="Pg">
|
||||
<intro>
|
||||
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="asr_z_p_zw_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ASR-Z.P.ZW-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = if <a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(64) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, (e * esize) DIV 64, 64];
|
||||
integer shift = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(element2), esize);
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.ASR.2" file="shared_pseudocode.xml" hover="function: bits(N) ASR(bits(N) x, integer shift)">ASR</a>(element1, shift);
|
||||
else
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
179
spec/arm64_xml/asr_z_p_zz.xml
Normal file
179
spec/arm64_xml/asr_z_p_zz.xml
Normal file
@@ -0,0 +1,179 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="asr_z_p_zz" title="ASR (vectors)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASR" />
|
||||
</docvars>
|
||||
<heading>ASR (vectors)</heading>
|
||||
<desc>
|
||||
<brief>Arithmetic shift right by vector (predicated)</brief>
|
||||
<description>
|
||||
<para>Shift right, preserving the sign bit, active elements of the first source vector by corresponding elements of the second source vector and destructively place the results in the corresponding elements of the first source vector. The shift amount operand is a vector of unsigned elements in which all bits are significant, and not used modulo the element size. Inactive elements in the destination vector register remain unmodified.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>True</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<takes_movprfx>True</takes_movprfx>
|
||||
<takes_pred_movprfx>True</takes_pred_movprfx>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASR" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ASR-Z.P.ZZ-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="18" name="R" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="17" name="L" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" name="U" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="3" settings="3">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="Pg" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zdn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="asr_z_p_zz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASR" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ASR </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/M, </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ASR-Z.P.ZZ-_" mylink="ASR-Z.P.ZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="asr_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zdn"><Zdn></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="asr_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="asr_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_pg"><Pg></symbol>
|
||||
<account encodedin="Pg">
|
||||
<intro>
|
||||
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="asr_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ASR-Z.P.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = if <a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(esize) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
|
||||
integer shift = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(element2), esize);
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.ASR.2" file="shared_pseudocode.xml" hover="function: bits(N) ASR(bits(N) x, integer shift)">ASR</a>(element1, shift);
|
||||
else
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
185
spec/arm64_xml/asr_z_zi.xml
Normal file
185
spec/arm64_xml/asr_z_zi.xml
Normal file
@@ -0,0 +1,185 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="asr_z_zi" title="ASR (immediate, unpredicated)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASR" />
|
||||
</docvars>
|
||||
<heading>ASR (immediate, unpredicated)</heading>
|
||||
<desc>
|
||||
<brief>Arithmetic shift right by immediate (unpredicated)</brief>
|
||||
<description>
|
||||
<para>Shift right by immediate, preserving the sign bit, each element of the source vector, and place the results in the corresponding elements of the destination vector. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. This instruction is unpredicated.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASR" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ASR-Z.ZI-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="tszh" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="2" name="tszl" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="18" width="3" name="imm3" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="15" width="4" settings="4">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="11" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" name="U" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="asr_z_zi_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASR" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ASR </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.</text><a link="sa_t" hover="Size specifier (field "tszh:tszl") [B,D,H,S]"><T></a><text>, </text><a link="sa_zn" hover="Source scalable vector register (field "Zn")"><Zn></a><text>.</text><a link="sa_t" hover="Size specifier (field "tszh:tszl") [B,D,H,S]"><T></a><text>, #</text><a link="sa_const" hover="Immediate shift amount [1-number of bits per element] (field "tszh:tszl:imm3")"><const></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ASR-Z.ZI-_" mylink="ASR-Z.ZI-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
bits(4) tsize = tszh:tszl;
|
||||
integer esize;
|
||||
case tsize of
|
||||
when '0000' UNDEFINED;
|
||||
when '0001' esize = 8;
|
||||
when '001x' esize = 16;
|
||||
when '01xx' esize = 32;
|
||||
when '1xxx' esize = 64;
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);
|
||||
integer shift = (2 * esize) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tsize:imm3);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="asr_z_zi_" symboldefcount="1">
|
||||
<symbol link="sa_zd"><Zd></symbol>
|
||||
<account encodedin="Zd">
|
||||
<intro>
|
||||
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="asr_z_zi_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="tszh:tszl">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="3">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">tszh</entry>
|
||||
<entry class="bitfield">tszl</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">1x</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="bitfield">xx</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">1x</entry>
|
||||
<entry class="bitfield">xx</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="asr_z_zi_" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="asr_z_zi_" symboldefcount="1">
|
||||
<symbol link="sa_const"><const></symbol>
|
||||
<account encodedin="imm3:tszh:tszl">
|
||||
<intro>
|
||||
<para>Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ASR-Z.ZI-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.ASR.2" file="shared_pseudocode.xml" hover="function: bits(N) ASR(bits(N) x, integer shift)">ASR</a>(element1, shift);
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
171
spec/arm64_xml/asr_z_zw.xml
Normal file
171
spec/arm64_xml/asr_z_zw.xml
Normal file
@@ -0,0 +1,171 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="asr_z_zw" title="ASR (wide elements, unpredicated)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASR" />
|
||||
</docvars>
|
||||
<heading>ASR (wide elements, unpredicated)</heading>
|
||||
<desc>
|
||||
<brief>Arithmetic shift right by 64-bit wide elements (unpredicated)</brief>
|
||||
<description>
|
||||
<para>Shift right, preserving the sign bit, all elements of the first source vector by corresponding overlapping 64-bit elements of the second source vector and place the first in the corresponding elements of the destination vector. The shift amount is a vector of unsigned 64-bit doubleword elements in which all bits are significant, and not used modulo the destination element size. This instruction is unpredicated.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<is_wide_zm>True</is_wide_zm>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASR" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ASR-Z.ZW-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="4" settings="4">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="11" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" name="U" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="asr_z_zw_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASR" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ASR </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,H,S]"><T></a><text>, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,H,S]"><T></a><text>, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.D</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ASR-Z.ZW-_" mylink="ASR-Z.ZW-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
if size == '11' then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="asr_z_zw_" symboldefcount="1">
|
||||
<symbol link="sa_zd"><Zd></symbol>
|
||||
<account encodedin="Zd">
|
||||
<intro>
|
||||
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="asr_z_zw_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="asr_z_zw_" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="asr_z_zw_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ASR-Z.ZW-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(64) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, (e * esize) DIV 64, 64];
|
||||
integer shift = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(element2), esize);
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.ASR.2" file="shared_pseudocode.xml" hover="function: bits(N) ASR(bits(N) x, integer shift)">ASR</a>(element1, shift);
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
200
spec/arm64_xml/asrd_z_p_zi.xml
Normal file
200
spec/arm64_xml/asrd_z_p_zi.xml
Normal file
@@ -0,0 +1,200 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="asrd_z_p_zi" title="ASRD" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASRD" />
|
||||
</docvars>
|
||||
<heading>ASRD</heading>
|
||||
<desc>
|
||||
<brief>Arithmetic shift right for divide by immediate (predicated)</brief>
|
||||
<description>
|
||||
<para>Shift right by immediate, preserving the sign bit, each active element of the source vector, and destructively place the results in the corresponding elements of the source vector. The result rounds toward zero as in a signed division. The immediate shift amount is an unsigned value in the range 1 to number of bits per element. Inactive elements in the destination vector register remain unmodified.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>True</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<takes_movprfx>True</takes_movprfx>
|
||||
<takes_pred_movprfx>True</takes_pred_movprfx>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASRD" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ASRD-Z.P.ZI-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="tszh" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="19" name="opc<1>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="18" name="opc<0>" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="17" name="L" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" name="U" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="3" settings="3">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="Pg" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="2" name="tszl" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="7" width="3" name="imm3" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zdn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="asrd_z_p_zi_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASRD" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ASRD </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "tszh:tszl") [B,D,H,S]"><T></a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/M, </text><a link="sa_zdn" hover="Source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "tszh:tszl") [B,D,H,S]"><T></a><text>, #</text><a link="sa_const" hover="Immediate shift amount [1-number of bits per element] (field "tszh:tszl:imm3")"><const></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ASRD-Z.P.ZI-_" mylink="ASRD-Z.P.ZI-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
bits(4) tsize = tszh:tszl;
|
||||
integer esize;
|
||||
case tsize of
|
||||
when '0000' UNDEFINED;
|
||||
when '0001' esize = 8;
|
||||
when '001x' esize = 16;
|
||||
when '01xx' esize = 32;
|
||||
when '1xxx' esize = 64;
|
||||
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer shift = (2 * esize) - <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(tsize:imm3);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="asrd_z_p_zi_" symboldefcount="1">
|
||||
<symbol link="sa_zdn"><Zdn></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the source and destination scalable vector register, encoded in the "Zdn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="asrd_z_p_zi_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="tszh:tszl">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="3">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">tszh</entry>
|
||||
<entry class="bitfield">tszl</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">RESERVED</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="bitfield">1x</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="bitfield">xx</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">1x</entry>
|
||||
<entry class="bitfield">xx</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="asrd_z_p_zi_" symboldefcount="1">
|
||||
<symbol link="sa_pg"><Pg></symbol>
|
||||
<account encodedin="Pg">
|
||||
<intro>
|
||||
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="asrd_z_p_zi_" symboldefcount="1">
|
||||
<symbol link="sa_const"><const></symbol>
|
||||
<account encodedin="imm3:tszh:tszl">
|
||||
<intro>
|
||||
<para>Is the immediate shift amount, in the range 1 to number of bits per element, encoded in "tszh:tszl:imm3".</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ASRD-Z.P.ZI-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
integer element1 = <a link="impl-shared.SInt.1" file="shared_pseudocode.xml" hover="function: integer SInt(bits(N) x)">SInt</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize]);
|
||||
if element1 < 0 then
|
||||
element1 = element1 + ((1 << shift) - 1);
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = (element1 >> shift)<esize-1:0>;
|
||||
else
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
179
spec/arm64_xml/asrr_z_p_zz.xml
Normal file
179
spec/arm64_xml/asrr_z_p_zz.xml
Normal file
@@ -0,0 +1,179 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="asrr_z_p_zz" title="ASRR" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASRR" />
|
||||
</docvars>
|
||||
<heading>ASRR</heading>
|
||||
<desc>
|
||||
<brief>Reversed arithmetic shift right by vector (predicated)</brief>
|
||||
<description>
|
||||
<para>Reversed shift right, preserving the sign bit, active elements of the second source vector by corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. The shift amount operand is a vector of unsigned elements in which all bits are significant, and not used modulo the element size. Inactive elements in the destination vector register remain unmodified.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>True</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<takes_movprfx>True</takes_movprfx>
|
||||
<takes_pred_movprfx>True</takes_pred_movprfx>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE" oneof="1" id="iclass_sve" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASRR" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="ASRR-Z.P.ZZ-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="18" name="R" usename="1" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="17" name="L" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" name="U" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="3" settings="3">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="Pg" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zdn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="asrr_z_p_zz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASRR" />
|
||||
</docvars>
|
||||
<asmtemplate><text>ASRR </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/M, </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ASRR-Z.P.ZZ-_" mylink="ASRR-Z.P.ZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="asrr_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zdn"><Zdn></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="asrr_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="asrr_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_pg"><Pg></symbol>
|
||||
<account encodedin="Pg">
|
||||
<intro>
|
||||
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="asrr_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="ASRR-Z.P.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = if <a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, esize) then <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, esize) then
|
||||
bits(esize) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
bits(esize) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, esize];
|
||||
integer shift = <a link="impl-shared.Min.2" file="shared_pseudocode.xml" hover="function: integer Min(integer a, integer b)">Min</a>(<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(element1), esize);
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.ASR.2" file="shared_pseudocode.xml" hover="function: bits(N) ASR(bits(N) x, integer shift)">ASR</a>(element2, shift);
|
||||
else
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, esize];
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
179
spec/arm64_xml/asrv.xml
Normal file
179
spec/arm64_xml/asrv.xml
Normal file
@@ -0,0 +1,179 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="ASRV" title="ASRV -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASRV" />
|
||||
</docvars>
|
||||
<heading>ASRV</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Arithmetic Shift Right Variable</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Arithmetic Shift Right Variable shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The remainder obtained by dividing the second source register by the data size defines the number of bits by which the first source register is right-shifted.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="1">
|
||||
<alias_list_intro>This instruction is used by the alias </alias_list_intro>
|
||||
<aliasref aliaspageid="ASR_ASRV" aliasfile="asr_asrv.xml" hover="Arithmetic shift right (register)" punct=".">
|
||||
<text>ASR (register)</text>
|
||||
<aliaspref>Unconditionally</aliaspref>
|
||||
</aliasref>
|
||||
<alias_list_outro> The alias is always the preferred disassembly.</alias_list_outro>
|
||||
</alias_list>
|
||||
<classes>
|
||||
<iclass name="Integer" oneof="1" id="iclass_general" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASRV" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/shift/variable" tworows="1">
|
||||
<box hibit="31" name="sf" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="30" name="op" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="29" name="S" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="8" settings="8">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="4" name="opcode2[5:2]" settings="4">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="11" width="2" name="op2" usename="1" settings="2" psbits="xx">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="ASRV_32_dp_2src" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASRV" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>ASRV </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, </text><a link="sa_wn" hover="First 32-bit general-purpose source register (field "Rn")"><Wn></a><text>, </text><a link="sa_wm" hover="Second 32-bit general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits (field "Rm")"><Wm></a></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="ASRV_64_dp_2src" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="ASRV" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>ASRV </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn" hover="First 64-bit general-purpose source register (field "Rn")"><Xn></a><text>, </text><a link="sa_xm" hover="Second 64-bit general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits (field "Rm")"><Xm></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/shift/variable" mylink="aarch64.instrs.integer.shift.variable" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
integer datasize = if sf == '1' then 64 else 32;
|
||||
<a link="ShiftType" file="shared_pseudocode.xml" hover="enumeration ShiftType {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR}">ShiftType</a> shift_type = <a link="impl-aarch64.DecodeShift.1" file="shared_pseudocode.xml" hover="function: ShiftType DecodeShift(bits(2) op)">DecodeShift</a>(op2);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="ASRV_32_dp_2src" symboldefcount="1">
|
||||
<symbol link="sa_wd"><Wd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ASRV_32_dp_2src" symboldefcount="1">
|
||||
<symbol link="sa_wn"><Wn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ASRV_32_dp_2src" symboldefcount="1">
|
||||
<symbol link="sa_wm"><Wm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the second general-purpose source register holding a shift amount from 0 to 31 in its bottom 5 bits, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ASRV_64_dp_2src" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ASRV_64_dp_2src" symboldefcount="1">
|
||||
<symbol link="sa_xn"><Xn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the first general-purpose source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="ASRV_64_dp_2src" symboldefcount="1">
|
||||
<symbol link="sa_xm"><Xm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the second general-purpose source register holding a shift amount from 0 to 63 in its bottom 6 bits, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/shift/variable" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bits(datasize) result;
|
||||
bits(datasize) operand2 = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[m, datasize];
|
||||
|
||||
result = <a link="impl-aarch64.ShiftReg.4" file="shared_pseudocode.xml" hover="function: bits(N) ShiftReg(integer reg, ShiftType shiftype, integer amount, integer N)">ShiftReg</a>(n, shift_type, <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(operand2) MOD datasize, datasize);
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, datasize] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
250
spec/arm64_xml/at_sys.xml
Normal file
250
spec/arm64_xml/at_sys.xml
Normal file
@@ -0,0 +1,250 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="AT_SYS" title="AT -- A64" type="alias">
|
||||
<docvars>
|
||||
<docvar key="alias_mnemonic" value="AT" />
|
||||
<docvar key="instr-class" value="system" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="SYS" />
|
||||
</docvars>
|
||||
<heading>AT</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Address Translate</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Address Translate. For more information, see <xref linkend="BABEJJJE">op0==0b01, cache maintenance, TLB maintenance, and address translation instructions</xref>.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<aliasto refiform="sys.xml" iformid="SYS">SYS</aliasto>
|
||||
<classes>
|
||||
<iclass name="System" oneof="1" id="iclass_system" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="system" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="SYS" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/system/sysops" tworows="1">
|
||||
<box hibit="31" width="10" settings="10">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" name="L" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="2" name="op0" settings="2">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="18" width="3" name="op1" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="15" width="4" name="CRn" usename="1" settings="4" psbits="xxxx">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="11" width="4" name="CRm" usename="1" settings="3" psbits="xxxx">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>x</c>
|
||||
</box>
|
||||
<box hibit="7" width="3" name="op2" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rt" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="AT_SYS_CR_systeminstrs" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="alias_mnemonic" value="AT" />
|
||||
<docvar key="instr-class" value="system" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="SYS" />
|
||||
</docvars>
|
||||
<asmtemplate><text>AT </text><a link="sa_at_op" hover="AT instruction name, as listed for AT system instruction group (field "op1:CRm<0>:op2") [S1E0R,S1E0W,S1E1R,S1E1RP (FEAT_PAN2),S1E1W,S1E1WP (FEAT_PAN2),S1E2R,S1E2W,S1E3R,S1E3W,S12E0R,S12E0W,S12E1R,S12E1W]"><at_op></a><text>, </text><a link="sa_xt_1" hover="64-bit general-purpose source register (field "Rt")"><Xt></a></asmtemplate>
|
||||
<equivalent_to>
|
||||
<asmtemplate><a href="sys.xml#SYS_CR_systeminstrs">SYS</a><text> #</text><a link="sa_op1" hover="3-bit unsigned immediate [0-7] (field "op1")"><op1></a><text>, C7, </text><a link="sa_cm" hover="Name 'Cm', with 'm' [0-15] (field "CRm")"><Cm></a><text>, #</text><a link="sa_op2" hover="3-bit unsigned immediate [0-7] (field "op2")"><op2></a><text>, </text><a link="sa_xt_1" hover="64-bit general-purpose source register (field "Rt")"><Xt></a></asmtemplate>
|
||||
<aliascond><a link="impl-aarch64.SysOp.4" file="shared_pseudocode.xml" hover="function: SystemOp SysOp(bits(3) op1, bits(4) CRn, bits(4) CRm, bits(3) op2)">SysOp</a>(op1,'0111',CRm,op2) == <a link="Sys_AT" file="shared_pseudocode.xml" hover="enumeration SystemOp {Sys_AT, Sys_BRB, Sys_DC, Sys_IC, Sys_TLBI, Sys_SYS}">Sys_AT</a></aliascond>
|
||||
</equivalent_to>
|
||||
</encoding>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="AT_SYS_CR_systeminstrs" symboldefcount="1">
|
||||
<symbol link="sa_at_op"><at_op></symbol>
|
||||
<definition encodedin="op1:CRm<0>:op2">
|
||||
<intro>Is an AT instruction name, as listed for the AT system instruction group, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="4">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">op1</entry>
|
||||
<entry class="bitfield">CRm<0></entry>
|
||||
<entry class="bitfield">op2</entry>
|
||||
<entry class="symbol"><at_op></entry>
|
||||
<entry class="symbol">Architectural Feature</entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">000</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">000</entry>
|
||||
<entry class="symbol">S1E1R</entry>
|
||||
<entry class="feature" />
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">000</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">001</entry>
|
||||
<entry class="symbol">S1E1W</entry>
|
||||
<entry class="feature" />
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">000</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">010</entry>
|
||||
<entry class="symbol">S1E0R</entry>
|
||||
<entry class="feature" />
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">000</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">011</entry>
|
||||
<entry class="symbol">S1E0W</entry>
|
||||
<entry class="feature" />
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">000</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="bitfield">000</entry>
|
||||
<entry class="symbol">S1E1RP</entry>
|
||||
<entry class="feature">
|
||||
<arch_variants>
|
||||
<arch_variant feature="FEAT_PAN2" />
|
||||
</arch_variants>
|
||||
</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">000</entry>
|
||||
<entry class="bitfield">1</entry>
|
||||
<entry class="bitfield">001</entry>
|
||||
<entry class="symbol">S1E1WP</entry>
|
||||
<entry class="feature">
|
||||
<arch_variants>
|
||||
<arch_variant feature="FEAT_PAN2" />
|
||||
</arch_variants>
|
||||
</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">100</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">000</entry>
|
||||
<entry class="symbol">S1E2R</entry>
|
||||
<entry class="feature" />
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">100</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">001</entry>
|
||||
<entry class="symbol">S1E2W</entry>
|
||||
<entry class="feature" />
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">100</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">100</entry>
|
||||
<entry class="symbol">S12E1R</entry>
|
||||
<entry class="feature" />
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">100</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">101</entry>
|
||||
<entry class="symbol">S12E1W</entry>
|
||||
<entry class="feature" />
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">100</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">110</entry>
|
||||
<entry class="symbol">S12E0R</entry>
|
||||
<entry class="feature" />
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">100</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">111</entry>
|
||||
<entry class="symbol">S12E0W</entry>
|
||||
<entry class="feature" />
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">110</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">000</entry>
|
||||
<entry class="symbol">S1E3R</entry>
|
||||
<entry class="feature" />
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">110</entry>
|
||||
<entry class="bitfield">0</entry>
|
||||
<entry class="bitfield">001</entry>
|
||||
<entry class="symbol">S1E3W</entry>
|
||||
<entry class="feature" />
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="AT_SYS_CR_systeminstrs" symboldefcount="1">
|
||||
<symbol link="sa_op1"><op1></symbol>
|
||||
<account encodedin="op1">
|
||||
<intro>
|
||||
<para>Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op1" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AT_SYS_CR_systeminstrs" symboldefcount="1">
|
||||
<symbol link="sa_cm"><Cm></symbol>
|
||||
<account encodedin="CRm">
|
||||
<intro>
|
||||
<para>Is a name 'Cm', with 'm' in the range 0 to 15, encoded in the "CRm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AT_SYS_CR_systeminstrs" symboldefcount="1">
|
||||
<symbol link="sa_op2"><op2></symbol>
|
||||
<account encodedin="op2">
|
||||
<intro>
|
||||
<para>Is a 3-bit unsigned immediate, in the range 0 to 7, encoded in the "op2" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AT_SYS_CR_systeminstrs" symboldefcount="1">
|
||||
<symbol link="sa_xt_1"><Xt></symbol>
|
||||
<account encodedin="Rt">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose source register, encoded in the "Rt" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
</instructionsection>
|
||||
162
spec/arm64_xml/autda.xml
Normal file
162
spec/arm64_xml/autda.xml
Normal file
@@ -0,0 +1,162 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="AUTDA" title="AUTDA, AUTDZA -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
</docvars>
|
||||
<heading>AUTDA, AUTDZA</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Authenticate Data address, using key A</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Authenticate Data address, using key A. This instruction authenticates a data address, using a modifier and key A.</para>
|
||||
<para>The address is in the general-purpose register that is specified by <syntax><Xd></syntax>.</para>
|
||||
<para>The modifier is:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>In the general-purpose register or stack pointer that is specified by <syntax><Xn|SP></syntax> for <instruction>AUTDA</instruction>.</content></listitem>
|
||||
<listitem><content>The value zero, for <instruction>AUTDZA</instruction>.</content></listitem>
|
||||
</list>
|
||||
<para>If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. For information on behavior if the authentication fails, see <xref>Faulting on pointer authentication</xref>.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Integer" oneof="1" id="iclass_general" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="ARMv8.3" feature="FEAT_PAuth" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/pac/autda/dp_1src">
|
||||
<box hibit="31" name="sf" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="30" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="29" name="S" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="8" settings="8">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="opcode2" settings="5">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="15" name="opcode[5]" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="14" name="opcode[4]" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="13" name="Z" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="opcode[2:0]" settings="3">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="AUTDA_64P_dp_1src" oneofinclass="2" oneof="2" label="AUTDA" bitdiffs="Z == 0">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AUTDA" />
|
||||
</docvars>
|
||||
<box hibit="13" width="1" name="Z">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>AUTDA </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn_sp" hover="64-bit general-purpose source register or SP (field "Rn")"><Xn|SP></a></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="AUTDZA_64Z_dp_1src" oneofinclass="2" oneof="2" label="AUTDZA" bitdiffs="Z == 1 && Rn == 11111">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AUTDZA" />
|
||||
</docvars>
|
||||
<box hibit="13" width="1" name="Z">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>AUTDZA </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/pac/autda/dp_1src" mylink="aarch64.instrs.integer.pac.autda.dp_1src" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">boolean source_is_sp = FALSE;
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
|
||||
if !<a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
UNDEFINED;
|
||||
|
||||
if Z == '0' then // AUTDA
|
||||
if n == 31 then source_is_sp = TRUE;
|
||||
else // AUTDZA
|
||||
if n != 31 then UNDEFINED;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="AUTDA_64P_dp_1src, AUTDZA_64Z_dp_1src" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AUTDA_64P_dp_1src" symboldefcount="1">
|
||||
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose source register or stack pointer, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/pac/autda/dp_1src" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">auth_then_branch = FALSE;
|
||||
|
||||
if <a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
if source_is_sp then
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = AuthDA(X[d, 64], SP[], auth_then_branch);
|
||||
else
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = AuthDA(X[d, 64], X[n, 64], auth_then_branch);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
162
spec/arm64_xml/autdb.xml
Normal file
162
spec/arm64_xml/autdb.xml
Normal file
@@ -0,0 +1,162 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="AUTDB" title="AUTDB, AUTDZB -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
</docvars>
|
||||
<heading>AUTDB, AUTDZB</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Authenticate Data address, using key B</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Authenticate Data address, using key B. This instruction authenticates a data address, using a modifier and key B.</para>
|
||||
<para>The address is in the general-purpose register that is specified by <syntax><Xd></syntax>.</para>
|
||||
<para>The modifier is:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>In the general-purpose register or stack pointer that is specified by <syntax><Xn|SP></syntax> for <instruction>AUTDB</instruction>.</content></listitem>
|
||||
<listitem><content>The value zero, for <instruction>AUTDZB</instruction>.</content></listitem>
|
||||
</list>
|
||||
<para>If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. For information on behavior if the authentication fails, see <xref>Faulting on pointer authentication</xref>.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Integer" oneof="1" id="iclass_general" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="ARMv8.3" feature="FEAT_PAuth" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/pac/autdb/dp_1src">
|
||||
<box hibit="31" name="sf" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="30" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="29" name="S" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="8" settings="8">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="opcode2" settings="5">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="15" name="opcode[5]" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="14" name="opcode[4]" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="13" name="Z" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="opcode[2:0]" settings="3">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="AUTDB_64P_dp_1src" oneofinclass="2" oneof="2" label="AUTDB" bitdiffs="Z == 0">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AUTDB" />
|
||||
</docvars>
|
||||
<box hibit="13" width="1" name="Z">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>AUTDB </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn_sp" hover="64-bit general-purpose source register or SP (field "Rn")"><Xn|SP></a></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="AUTDZB_64Z_dp_1src" oneofinclass="2" oneof="2" label="AUTDZB" bitdiffs="Z == 1 && Rn == 11111">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AUTDZB" />
|
||||
</docvars>
|
||||
<box hibit="13" width="1" name="Z">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>AUTDZB </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/pac/autdb/dp_1src" mylink="aarch64.instrs.integer.pac.autdb.dp_1src" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">boolean source_is_sp = FALSE;
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
|
||||
if !<a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
UNDEFINED;
|
||||
|
||||
if Z == '0' then // AUTDB
|
||||
if n == 31 then source_is_sp = TRUE;
|
||||
else // AUTDZB
|
||||
if n != 31 then UNDEFINED;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="AUTDB_64P_dp_1src, AUTDZB_64Z_dp_1src" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AUTDB_64P_dp_1src" symboldefcount="1">
|
||||
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose source register or stack pointer, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/pac/autdb/dp_1src" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">auth_then_branch = FALSE;
|
||||
|
||||
if <a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
if source_is_sp then
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = AuthDB(X[d, 64], SP[], auth_then_branch);
|
||||
else
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = AuthDB(X[d, 64], X[n, 64], auth_then_branch);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
317
spec/arm64_xml/autia.xml
Normal file
317
spec/arm64_xml/autia.xml
Normal file
@@ -0,0 +1,317 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="AUTIA" title="AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="isa" value="A64" />
|
||||
</docvars>
|
||||
<heading>AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Authenticate Instruction address, using key A</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Authenticate Instruction address, using key A. This instruction authenticates an instruction address, using a modifier and key A.</para>
|
||||
<para>The address is:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>In the general-purpose register that is specified by <syntax><Xd></syntax> for <instruction>AUTIA</instruction> and <instruction>AUTIZA</instruction>.</content></listitem>
|
||||
<listitem><content>In X17, for <instruction>AUTIA1716</instruction>.</content></listitem>
|
||||
<listitem><content>In X30, for <instruction>AUTIASP</instruction> and <instruction>AUTIAZ</instruction>.</content></listitem>
|
||||
</list>
|
||||
<para>The modifier is:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>In the general-purpose register or stack pointer that is specified by <syntax><Xn|SP></syntax> for <instruction>AUTIA</instruction>.</content></listitem>
|
||||
<listitem><content>The value zero, for <instruction>AUTIZA</instruction> and <instruction>AUTIAZ</instruction>.</content></listitem>
|
||||
<listitem><content>In X16, for <instruction>AUTIA1716</instruction>.</content></listitem>
|
||||
<listitem><content>In SP, for <instruction>AUTIASP</instruction>.</content></listitem>
|
||||
</list>
|
||||
<para>If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. For information on behavior if the authentication fails, see <xref>Faulting on pointer authentication</xref>.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<classesintro count="2">
|
||||
<txt>It has encodings from 2 classes:</txt>
|
||||
<a href="#iclass_general">Integer</a>
|
||||
<txt> and </txt>
|
||||
<a href="#iclass_system">System</a>
|
||||
</classesintro>
|
||||
<iclass name="Integer" oneof="2" id="iclass_general" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="ARMv8.3" feature="FEAT_PAuth" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/pac/autia/dp_1src">
|
||||
<box hibit="31" name="sf" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="30" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="29" name="S" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="8" settings="8">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="opcode2" settings="5">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="15" name="opcode[5]" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="14" name="opcode[4]" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="13" name="Z" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="opcode[2:0]" settings="3">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="AUTIA_64P_dp_1src" oneofinclass="2" oneof="5" label="AUTIA" bitdiffs="Z == 0">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AUTIA" />
|
||||
</docvars>
|
||||
<box hibit="13" width="1" name="Z">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>AUTIA </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn_sp" hover="64-bit general-purpose source register or SP (field "Rn")"><Xn|SP></a></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="AUTIZA_64Z_dp_1src" oneofinclass="2" oneof="5" label="AUTIZA" bitdiffs="Z == 1 && Rn == 11111">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AUTIZA" />
|
||||
</docvars>
|
||||
<box hibit="13" width="1" name="Z">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>AUTIZA </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/pac/autia/dp_1src" mylink="aarch64.instrs.integer.pac.autia.dp_1src" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">boolean source_is_sp = FALSE;
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
|
||||
if !<a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
UNDEFINED;
|
||||
|
||||
if Z == '0' then // AUTIA
|
||||
if n == 31 then source_is_sp = TRUE;
|
||||
else // AUTIZA
|
||||
if n != 31 then UNDEFINED;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
<iclass name="System" oneof="2" id="iclass_system" no_encodings="3" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="system" />
|
||||
<docvar key="isa" value="A64" />
|
||||
</docvars>
|
||||
<iclassintro count="3"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="ARMv8.3" feature="FEAT_PAuth" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/pac/autia/hint" tworows="1">
|
||||
<box hibit="31" width="10" settings="10">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" name="L" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="2" name="op0" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="18" width="3" name="op1" settings="3">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="15" width="4" name="CRn" settings="4">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="11" width="4" name="CRm" usename="1" settings="3" psbits="xxxx">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>x</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="7" width="3" name="op2" usename="1" settings="2" psbits="xxx">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>x</c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rt" settings="5">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="AUTIA1716_HI_hints" oneofinclass="3" oneof="5" label="AUTIA1716" bitdiffs="CRm == 0001 && op2 == 100">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="system" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AUTIA1716" />
|
||||
</docvars>
|
||||
<box hibit="11" width="4" name="CRm">
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c>0</c>
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="7" width="3" name="op2">
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>AUTIA1716</text></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="AUTIASP_HI_hints" oneofinclass="3" oneof="5" label="AUTIASP" bitdiffs="CRm == 0011 && op2 == 101">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="system" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AUTIASP" />
|
||||
</docvars>
|
||||
<box hibit="11" width="4" name="CRm">
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c>1</c>
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="7" width="3" name="op2">
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>AUTIASP</text></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="AUTIAZ_HI_hints" oneofinclass="3" oneof="5" label="AUTIAZ" bitdiffs="CRm == 0011 && op2 == 100">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="system" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AUTIAZ" />
|
||||
</docvars>
|
||||
<box hibit="11" width="4" name="CRm">
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c>1</c>
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="7" width="3" name="op2">
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>AUTIAZ</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/pac/autia/hint" mylink="aarch64.instrs.integer.pac.autia.hint" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d;
|
||||
integer n;
|
||||
boolean source_is_sp = FALSE;
|
||||
|
||||
case CRm:op2 of
|
||||
when '0011 100' // AUTIAZ
|
||||
d = 30;
|
||||
n = 31;
|
||||
when '0011 101' // AUTIASP
|
||||
d = 30;
|
||||
source_is_sp = TRUE;
|
||||
when '0001 100' // AUTIA1716
|
||||
d = 17;
|
||||
n = 16;
|
||||
when '0001 000' SEE "PACIA";
|
||||
when '0001 010' SEE "PACIB";
|
||||
when '0001 110' SEE "AUTIB";
|
||||
when '0011 00x' SEE "PACIA";
|
||||
when '0011 01x' SEE "PACIB";
|
||||
when '0011 11x' SEE "AUTIB";
|
||||
when '0000 111' SEE "XPACLRI";
|
||||
otherwise SEE "HINT";</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="AUTIA_64P_dp_1src, AUTIZA_64Z_dp_1src" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AUTIA_64P_dp_1src" symboldefcount="1">
|
||||
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose source register or stack pointer, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/pac/autia/dp_1src" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">auth_then_branch = FALSE;
|
||||
|
||||
if <a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
if source_is_sp then
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = AuthIA(X[d, 64], SP[], auth_then_branch);
|
||||
else
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = AuthIA(X[d, 64], X[n, 64], auth_then_branch);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
317
spec/arm64_xml/autib.xml
Normal file
317
spec/arm64_xml/autib.xml
Normal file
@@ -0,0 +1,317 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="AUTIB" title="AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="isa" value="A64" />
|
||||
</docvars>
|
||||
<heading>AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Authenticate Instruction address, using key B</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Authenticate Instruction address, using key B. This instruction authenticates an instruction address, using a modifier and key B.</para>
|
||||
<para>The address is:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>In the general-purpose register that is specified by <syntax><Xd></syntax> for <instruction>AUTIB</instruction> and <instruction>AUTIZB</instruction>.</content></listitem>
|
||||
<listitem><content>In X17, for <instruction>AUTIB1716</instruction>.</content></listitem>
|
||||
<listitem><content>In X30, for <instruction>AUTIBSP</instruction> and <instruction>AUTIBZ</instruction>.</content></listitem>
|
||||
</list>
|
||||
<para>The modifier is:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>In the general-purpose register or stack pointer that is specified by <syntax><Xn|SP></syntax> for <instruction>AUTIB</instruction>.</content></listitem>
|
||||
<listitem><content>The value zero, for <instruction>AUTIZB</instruction> and <instruction>AUTIBZ</instruction>.</content></listitem>
|
||||
<listitem><content>In X16, for <instruction>AUTIB1716</instruction>.</content></listitem>
|
||||
<listitem><content>In SP, for <instruction>AUTIBSP</instruction>.</content></listitem>
|
||||
</list>
|
||||
<para>If the authentication passes, the upper bits of the address are restored to enable subsequent use of the address. For information on behavior if the authentication fails, see <xref>Faulting on pointer authentication</xref>.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<classesintro count="2">
|
||||
<txt>It has encodings from 2 classes:</txt>
|
||||
<a href="#iclass_general">Integer</a>
|
||||
<txt> and </txt>
|
||||
<a href="#iclass_system">System</a>
|
||||
</classesintro>
|
||||
<iclass name="Integer" oneof="2" id="iclass_general" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="ARMv8.3" feature="FEAT_PAuth" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/pac/autib/dp_1src">
|
||||
<box hibit="31" name="sf" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="30" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="29" name="S" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="28" width="8" settings="8">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="opcode2" settings="5">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="15" name="opcode[5]" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="14" name="opcode[4]" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="13" name="Z" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="opcode[2:0]" settings="3">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="AUTIB_64P_dp_1src" oneofinclass="2" oneof="5" label="AUTIB" bitdiffs="Z == 0">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AUTIB" />
|
||||
</docvars>
|
||||
<box hibit="13" width="1" name="Z">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>AUTIB </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, </text><a link="sa_xn_sp" hover="64-bit general-purpose source register or SP (field "Rn")"><Xn|SP></a></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="AUTIZB_64Z_dp_1src" oneofinclass="2" oneof="5" label="AUTIZB" bitdiffs="Z == 1 && Rn == 11111">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AUTIZB" />
|
||||
</docvars>
|
||||
<box hibit="13" width="1" name="Z">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>AUTIZB </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/pac/autib/dp_1src" mylink="aarch64.instrs.integer.pac.autib.dp_1src" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">boolean source_is_sp = FALSE;
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
|
||||
if !<a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
UNDEFINED;
|
||||
|
||||
if Z == '0' then // AUTIB
|
||||
if n == 31 then source_is_sp = TRUE;
|
||||
else // AUTIZB
|
||||
if n != 31 then UNDEFINED;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
<iclass name="System" oneof="2" id="iclass_system" no_encodings="3" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="system" />
|
||||
<docvar key="isa" value="A64" />
|
||||
</docvars>
|
||||
<iclassintro count="3"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="ARMv8.3" feature="FEAT_PAuth" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/pac/autib/hint" tworows="1">
|
||||
<box hibit="31" width="10" settings="10">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" name="L" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="2" name="op0" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="18" width="3" name="op1" settings="3">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="15" width="4" name="CRn" settings="4">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="11" width="4" name="CRm" usename="1" settings="3" psbits="xxxx">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>x</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="7" width="3" name="op2" usename="1" settings="2" psbits="xxx">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>x</c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rt" settings="5">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="AUTIB1716_HI_hints" oneofinclass="3" oneof="5" label="AUTIB1716" bitdiffs="CRm == 0001 && op2 == 110">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="system" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AUTIB1716" />
|
||||
</docvars>
|
||||
<box hibit="11" width="4" name="CRm">
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c>0</c>
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="7" width="3" name="op2">
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>AUTIB1716</text></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="AUTIBSP_HI_hints" oneofinclass="3" oneof="5" label="AUTIBSP" bitdiffs="CRm == 0011 && op2 == 111">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="system" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AUTIBSP" />
|
||||
</docvars>
|
||||
<box hibit="11" width="4" name="CRm">
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c>1</c>
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="7" width="3" name="op2">
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>AUTIBSP</text></asmtemplate>
|
||||
</encoding>
|
||||
<encoding name="AUTIBZ_HI_hints" oneofinclass="3" oneof="5" label="AUTIBZ" bitdiffs="CRm == 0011 && op2 == 110">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="system" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AUTIBZ" />
|
||||
</docvars>
|
||||
<box hibit="11" width="4" name="CRm">
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c>1</c>
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="7" width="3" name="op2">
|
||||
<c></c>
|
||||
<c></c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>AUTIBZ</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/pac/autib/hint" mylink="aarch64.instrs.integer.pac.autib.hint" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">integer d;
|
||||
integer n;
|
||||
boolean source_is_sp = FALSE;
|
||||
|
||||
case CRm:op2 of
|
||||
when '0011 110' // AUTIBZ
|
||||
d = 30;
|
||||
n = 31;
|
||||
when '0011 111' // AUTIBSP
|
||||
d = 30;
|
||||
source_is_sp = TRUE;
|
||||
when '0001 110' // AUTIB1716
|
||||
d = 17;
|
||||
n = 16;
|
||||
when '0001 000' SEE "PACIA";
|
||||
when '0001 010' SEE "PACIB";
|
||||
when '0001 100' SEE "AUTIA";
|
||||
when '0011 00x' SEE "PACIA";
|
||||
when '0011 01x' SEE "PACIB";
|
||||
when '0011 10x' SEE "AUTIA";
|
||||
when '0000 111' SEE "XPACLRI";
|
||||
otherwise SEE "HINT";</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="AUTIB_64P_dp_1src, AUTIZB_64Z_dp_1src" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="AUTIB_64P_dp_1src" symboldefcount="1">
|
||||
<symbol link="sa_xn_sp"><Xn|SP></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose source register or stack pointer, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/pac/autib/dp_1src" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">auth_then_branch = FALSE;
|
||||
|
||||
if <a link="impl-aarch64.HavePACExt.0" file="shared_pseudocode.xml" hover="function: boolean HavePACExt()">HavePACExt</a>() then
|
||||
if source_is_sp then
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = AuthIB(X[d, 64], SP[], auth_then_branch);
|
||||
else
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[d, 64] = AuthIB(X[d, 64], X[n, 64], auth_then_branch);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
113
spec/arm64_xml/axflag.xml
Normal file
113
spec/arm64_xml/axflag.xml
Normal file
@@ -0,0 +1,113 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="AXFLAG" title="AXFLAG -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="system" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AXFLAG" />
|
||||
</docvars>
|
||||
<heading>AXFLAG</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Convert floating-point condition flags from Arm to external format</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Convert floating-point condition flags from Arm to external format. This instruction converts the state of the PSTATE.{N,Z,C,V} flags from a form representing the result of an Arm floating-point scalar compare instruction to an alternative representation required by some software.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="System" oneof="1" id="iclass_system" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="system" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AXFLAG" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="ARMv8.5" feature="FEAT_FlagM2" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/flags/axflag" tworows="1">
|
||||
<box hibit="31" width="10" settings="10">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" name="L" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="2" name="op0" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="18" width="3" name="op1" settings="3">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="4" name="CRn" settings="4">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="11" width="4" name="CRm" usename="1" settings="4" psbits="xxxx">
|
||||
<c>(0)</c>
|
||||
<c>(0)</c>
|
||||
<c>(0)</c>
|
||||
<c>(0)</c>
|
||||
</box>
|
||||
<box hibit="7" width="3" name="op2" settings="3">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rt" settings="5">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="AXFLAG_M_pstate" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="system" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="AXFLAG" />
|
||||
</docvars>
|
||||
<asmtemplate><text>AXFLAG</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/flags/axflag" mylink="aarch64.instrs.integer.flags.axflag" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFlagFormatExt.0" file="shared_pseudocode.xml" hover="function: boolean HaveFlagFormatExt()">HaveFlagFormatExt</a>() then UNDEFINED;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all"></explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/integer/flags/axflag" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">bit n = '0';
|
||||
bit z = PSTATE.Z OR PSTATE.V;
|
||||
bit c = PSTATE.C AND NOT(PSTATE.V);
|
||||
bit v = '0';
|
||||
|
||||
PSTATE.N = n;
|
||||
PSTATE.Z = z;
|
||||
PSTATE.C = c;
|
||||
PSTATE.V = v;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
103
spec/arm64_xml/b_cond.xml
Normal file
103
spec/arm64_xml/b_cond.xml
Normal file
@@ -0,0 +1,103 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="B_cond" title="B.cond -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="branch-offset" value="br19" />
|
||||
<docvar key="compare-with" value="cmp-cond" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="B" />
|
||||
</docvars>
|
||||
<heading>B.cond</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Branch conditionally</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Branch conditionally to a label at a PC-relative offset, with a hint that this is not a subroutine call or return.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="19-bit signed PC-relative branch offset" oneof="1" id="iclass_br19" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="branch-offset" value="br19" />
|
||||
<docvar key="compare-with" value="cmp-cond" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="B" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/branch/conditional/cond">
|
||||
<box hibit="31" width="7" settings="7">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="24" name="o1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="19" name="imm19" usename="1">
|
||||
<c colspan="19"></c>
|
||||
</box>
|
||||
<box hibit="4" name="o0" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="3" width="4" name="cond" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="B_only_condbranch" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="branch-offset" value="br19" />
|
||||
<docvar key="compare-with" value="cmp-cond" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="B" />
|
||||
</docvars>
|
||||
<asmtemplate><text>B.</text><a link="sa_cond" hover="Standard condition (field "cond")"><cond></a><text> </text><a link="sa_label" hover="Label to be conditionally branched to (field imm19)"><label></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/branch/conditional/cond" mylink="aarch64.instrs.branch.conditional.cond" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">bits(64) offset = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm19:'00', 64);
|
||||
bits(4) condition = cond;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="B_only_condbranch" symboldefcount="1">
|
||||
<symbol link="sa_cond"><cond></symbol>
|
||||
<account encodedin="cond">
|
||||
<intro>
|
||||
<para>Is one of the standard conditions, encoded in the "cond" field in the standard way.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="B_only_condbranch" symboldefcount="1">
|
||||
<symbol link="sa_label"><label></symbol>
|
||||
<account encodedin="imm19">
|
||||
<intro>
|
||||
<para>Is the program label to be conditionally branched to. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/branch/conditional/cond" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">boolean branch_conditional = TRUE;
|
||||
if <a link="impl-shared.ConditionHolds.1" file="shared_pseudocode.xml" hover="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</a>(condition) then
|
||||
<a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(<a link="impl-aarch64.PC.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) PC[]">PC</a>[] + offset, <a link="BranchType_DIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a>, branch_conditional);
|
||||
else
|
||||
<a link="impl-shared.BranchNotTaken.2" file="shared_pseudocode.xml" hover="function: BranchNotTaken(BranchType branchtype, boolean branch_conditional)">BranchNotTaken</a>(<a link="BranchType_DIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a>, branch_conditional);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
86
spec/arm64_xml/b_uncond.xml
Normal file
86
spec/arm64_xml/b_uncond.xml
Normal file
@@ -0,0 +1,86 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="B_uncond" title="B -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="branch-offset" value="br26" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="B" />
|
||||
</docvars>
|
||||
<heading>B</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Branch</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Branch causes an unconditional branch to a label at a PC-relative offset, with a hint that this is not a subroutine call or return.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="26-bit signed PC-relative branch offset" oneof="1" id="iclass_br26" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="branch-offset" value="br26" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="B" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="aarch64/instrs/branch/unconditional/immediate" tworows="1">
|
||||
<box hibit="31" name="op" usename="1" settings="1" psbits="x">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="30" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="25" width="26" name="imm26" usename="1">
|
||||
<c colspan="26"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="B_only_branch_imm" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="branch-offset" value="br26" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="B" />
|
||||
</docvars>
|
||||
<asmtemplate><text>B </text><a link="sa_label" hover="Label to be unconditionally branched to (field imm26)"><label></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/branch/unconditional/immediate" mylink="aarch64.instrs.branch.unconditional.immediate" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode"><a link="BranchType" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType</a> branch_type = if op == '1' then <a link="BranchType_DIRCALL" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIRCALL</a> else <a link="BranchType_DIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a>;
|
||||
bits(64) offset = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm26:'00', 64);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="B_only_branch_imm" symboldefcount="1">
|
||||
<symbol link="sa_label"><label></symbol>
|
||||
<account encodedin="imm26">
|
||||
<intro>
|
||||
<para>Is the program label to be unconditionally branched to. Its offset from the address of this instruction, in the range +/-128MB, is encoded as "imm26" times 4.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/branch/unconditional/immediate" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">if branch_type == <a link="BranchType_DIRCALL" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIRCALL</a> then
|
||||
if <a link="impl-shared.HaveGCS.0" file="shared_pseudocode.xml" hover="function: boolean HaveGCS()">HaveGCS</a>() && <a link="impl-aarch64.GCSPCREnabled.1" file="shared_pseudocode.xml" hover="function: boolean GCSPCREnabled(bits(2) el)">GCSPCREnabled</a>(PSTATE.EL) then
|
||||
<a link="impl-aarch64.AddGCSRecord.1" file="shared_pseudocode.xml" hover="function: AddGCSRecord(bits(64) vaddress)">AddGCSRecord</a>(<a link="impl-aarch64.PC.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) PC[]">PC</a>[] + 4);
|
||||
<a link="impl-aarch64.X.write.2" file="shared_pseudocode.xml" hover="accessor: X[integer n, integer width] = bits(width) value">X</a>[30, 64] = <a link="impl-aarch64.PC.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) PC[]">PC</a>[] + 4;
|
||||
|
||||
boolean branch_conditional = FALSE;
|
||||
<a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(<a link="impl-aarch64.PC.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) PC[]">PC</a>[] + offset, branch_type, branch_conditional);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
107
spec/arm64_xml/bc_cond.xml
Normal file
107
spec/arm64_xml/bc_cond.xml
Normal file
@@ -0,0 +1,107 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="BC_cond" title="BC.cond -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="branch-offset" value="br19" />
|
||||
<docvar key="compare-with" value="cmp-cond" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BC" />
|
||||
</docvars>
|
||||
<heading>BC.cond</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Branch Consistent conditionally</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Branch Consistent conditionally to a label at a PC-relative offset, with a hint that this branch will behave very consistently and is very unlikely to change direction.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="19-bit signed PC-relative branch offset" oneof="1" id="iclass_br19" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="branch-offset" value="br19" />
|
||||
<docvar key="compare-with" value="cmp-cond" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BC" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="ARMv8.8" feature="FEAT_HBC" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="aarch64/instrs/branch/conditional/hinted">
|
||||
<box hibit="31" width="7" settings="7">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="24" name="o1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" width="19" name="imm19" usename="1">
|
||||
<c colspan="19"></c>
|
||||
</box>
|
||||
<box hibit="4" name="o0" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="3" width="4" name="cond" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="BC_only_condbranch" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="branch-offset" value="br19" />
|
||||
<docvar key="compare-with" value="cmp-cond" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BC" />
|
||||
</docvars>
|
||||
<asmtemplate><text>BC.</text><a link="sa_cond" hover="Standard condition (field "cond")"><cond></a><text> </text><a link="sa_label" hover="Label to be conditionally branched to (field imm19)"><label></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/branch/conditional/hinted" mylink="aarch64.instrs.branch.conditional.hinted" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveFeatHBC.0" file="shared_pseudocode.xml" hover="function: boolean HaveFeatHBC()">HaveFeatHBC</a>() then UNDEFINED;
|
||||
bits(64) offset = <a link="impl-shared.SignExtend.2" file="shared_pseudocode.xml" hover="function: bits(N) SignExtend(bits(M) x, integer N)">SignExtend</a>(imm19:'00', 64);
|
||||
bits(4) condition = cond;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="BC_only_condbranch" symboldefcount="1">
|
||||
<symbol link="sa_cond"><cond></symbol>
|
||||
<account encodedin="cond">
|
||||
<intro>
|
||||
<para>Is one of the standard conditions, encoded in the "cond" field in the standard way.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="BC_only_condbranch" symboldefcount="1">
|
||||
<symbol link="sa_label"><label></symbol>
|
||||
<account encodedin="imm19">
|
||||
<intro>
|
||||
<para>Is the program label to be conditionally branched to. Its offset from the address of this instruction, in the range +/-1MB, is encoded as "imm19" times 4.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/branch/conditional/hinted" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute">boolean branch_conditional = TRUE;
|
||||
if <a link="impl-shared.ConditionHolds.1" file="shared_pseudocode.xml" hover="function: boolean ConditionHolds(bits(4) cond)">ConditionHolds</a>(condition) then
|
||||
<a link="impl-shared.BranchTo.3" file="shared_pseudocode.xml" hover="function: BranchTo(bits(N) target, BranchType branch_type, boolean branch_conditional)">BranchTo</a>(<a link="impl-aarch64.PC.read.0" file="shared_pseudocode.xml" hover="accessor: bits(64) PC[]">PC</a>[] + offset, <a link="BranchType_DIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a>, branch_conditional);
|
||||
else
|
||||
<a link="impl-shared.BranchNotTaken.2" file="shared_pseudocode.xml" hover="function: BranchNotTaken(BranchType branchtype, boolean branch_conditional)">BranchNotTaken</a>(<a link="BranchType_DIR" file="shared_pseudocode.xml" hover="enumeration BranchType { BranchType_DIRCALL, BranchType_INDCALL, BranchType_ERET, BranchType_DBGEXIT, BranchType_RET, BranchType_DIR, BranchType_INDIR, BranchType_EXCEPTION, BranchType_TMFAIL, BranchType_RESET, BranchType_UNKNOWN}">BranchType_DIR</a>, branch_conditional);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
137
spec/arm64_xml/bcax_advsimd.xml
Normal file
137
spec/arm64_xml/bcax_advsimd.xml
Normal file
@@ -0,0 +1,137 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="BCAX_advsimd" title="BCAX -- A64" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BCAX" />
|
||||
</docvars>
|
||||
<heading>BCAX</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Bit Clear and exclusive-OR</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Bit Clear and exclusive-OR performs a bitwise AND of the 128-bit vector in a source SIMD&FP register and the complement of the vector in another source SIMD&FP register, then performs a bitwise exclusive-OR of the resulting vector and the vector in a third source SIMD&FP register, and writes the result to the destination SIMD&FP register.</para>
|
||||
<para>This instruction is implemented only when <xref linkend="v8.2.SHA3">FEAT_SHA3</xref> is implemented.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="Advanced SIMD" oneof="1" id="iclass_advsimd" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BCAX" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="ARMv8.2" feature="FEAT_SHA3" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="aarch64/instrs/vector/crypto/sha3/bcax">
|
||||
<box hibit="31" width="9" settings="9">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" width="2" name="Op0" settings="2">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Rm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="14" width="5" name="Ra" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="BCAX_VVV16_crypto4" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="advsimd" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BCAX" />
|
||||
</docvars>
|
||||
<asmtemplate><text>BCAX </text><a link="sa_vd" hover="SIMD&FP destination register (field "Rd")"><Vd></a><text>.16B, </text><a link="sa_vn" hover="First SIMD&FP source register (field "Rn")"><Vn></a><text>.16B, </text><a link="sa_vm" hover="Second SIMD&FP source register (field "Rm")"><Vm></a><text>.16B, </text><a link="sa_va" hover="Third SIMD&FP source register (field "Ra")"><Va></a><text>.16B</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/crypto/sha3/bcax" mylink="aarch64.instrs.vector.crypto.sha3.bcax" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-shared.HaveSHA3Ext.0" file="shared_pseudocode.xml" hover="function: boolean HaveSHA3Ext()">HaveSHA3Ext</a>() then UNDEFINED;
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rd);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Rm);
|
||||
integer a = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Ra);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="BCAX_VVV16_crypto4" symboldefcount="1">
|
||||
<symbol link="sa_vd"><Vd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the name of the SIMD&FP destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="BCAX_VVV16_crypto4" symboldefcount="1">
|
||||
<symbol link="sa_vn"><Vn></symbol>
|
||||
<account encodedin="Rn">
|
||||
<intro>
|
||||
<para>Is the name of the first SIMD&FP source register, encoded in the "Rn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="BCAX_VVV16_crypto4" symboldefcount="1">
|
||||
<symbol link="sa_vm"><Vm></symbol>
|
||||
<account encodedin="Rm">
|
||||
<intro>
|
||||
<para>Is the name of the second SIMD&FP source register, encoded in the "Rm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="BCAX_VVV16_crypto4" symboldefcount="1">
|
||||
<symbol link="sa_va"><Va></symbol>
|
||||
<account encodedin="Ra">
|
||||
<intro>
|
||||
<para>Is the name of the third SIMD&FP source register, encoded in the "Ra" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="aarch64/instrs/vector/crypto/sha3/bcax" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="AArch64.CheckFPAdvSIMDEnabled.0" file="shared_pseudocode.xml" hover="function: AArch64.CheckFPAdvSIMDEnabled()">AArch64.CheckFPAdvSIMDEnabled</a>();
|
||||
|
||||
bits(128) Vm = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[m, 128];
|
||||
bits(128) Vn = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[n, 128];
|
||||
bits(128) Va = <a link="impl-aarch64.V.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) V[integer n, integer width]">V</a>[a, 128];
|
||||
<a link="impl-aarch64.V.write.2" file="shared_pseudocode.xml" hover="accessor: V[integer n, integer width] = bits(width) value">V</a>[d, 128] = Vn EOR (Vm AND NOT(Va));</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
128
spec/arm64_xml/bcax_z_zzz.xml
Normal file
128
spec/arm64_xml/bcax_z_zzz.xml
Normal file
@@ -0,0 +1,128 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="bcax_z_zzz" title="BCAX" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BCAX" />
|
||||
</docvars>
|
||||
<heading>BCAX</heading>
|
||||
<desc>
|
||||
<brief>Bitwise clear and exclusive OR</brief>
|
||||
<description>
|
||||
<para>Bitwise AND elements of the second source vector with the corresponding inverted elements of the third source vector, then exclusive OR the results with corresponding elements of the first source vector. The final results are destructively placed in the corresponding elements of the destination and first source vector. This instruction is unpredicated.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<takes_movprfx>True</takes_movprfx>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BCAX" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<regdiagram form="32" psname="BCAX-Z.ZZZ-_">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" name="opc<1>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="opc<0>" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="5" settings="5">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="10" name="o2" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zk" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zdn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="bcax_z_zzz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BCAX" />
|
||||
</docvars>
|
||||
<asmtemplate><text>BCAX </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.D, </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.D, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.D, </text><a link="sa_zk" hover="Third source scalable vector register (field "Zk")"><Zk></a><text>.D</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BCAX-Z.ZZZ-_" mylink="BCAX-Z.ZZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE2.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2()">HaveSVE2</a>() && !<a link="impl-aarch64.HaveSME.0" file="shared_pseudocode.xml" hover="function: boolean HaveSME()">HaveSME</a>() then UNDEFINED;
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer k = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zk);
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="bcax_z_zzz_" symboldefcount="1">
|
||||
<symbol link="sa_zdn"><Zdn></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bcax_z_zzz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bcax_z_zzz_" symboldefcount="1">
|
||||
<symbol link="sa_zk"><Zk></symbol>
|
||||
<account encodedin="Zk">
|
||||
<intro>
|
||||
<para>Is the name of the third source scalable vector register, encoded in the "Zk" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BCAX-Z.ZZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) operand3 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[k, VL];
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = operand1 EOR (operand2 AND NOT(operand3));</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
171
spec/arm64_xml/bdep_z_zz.xml
Normal file
171
spec/arm64_xml/bdep_z_zz.xml
Normal file
@@ -0,0 +1,171 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="bdep_z_zz" title="BDEP" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BDEP" />
|
||||
</docvars>
|
||||
<heading>BDEP</heading>
|
||||
<desc>
|
||||
<brief>Scatter lower bits into positions selected by bitmask</brief>
|
||||
<description>
|
||||
<para>This instruction scatters the lowest-numbered contiguous bits within each element of the first source vector to the bit positions indicated by non-zero bits in the corresponding mask element of the second source vector, preserving their order, and set the bits corresponding to a zero mask bit to zero. This instruction is unpredicated.</para>
|
||||
<para>ID_AA64ZFR0_EL1.BitPerm indicates whether this instruction is implemented.</para>
|
||||
<para>This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<sm_policy>SM_0_only</sm_policy>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BDEP" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SVE_BitPerm" feature="FEAT_SVE_BitPerm" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="BDEP-Z.ZZ-_">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="4" settings="4">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="11" name="opc<1>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" name="opc<0>" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="bdep_z_zz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BDEP" />
|
||||
</docvars>
|
||||
<asmtemplate><text>BDEP </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BDEP-Z.ZZ-_" mylink="BDEP-Z.ZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() || !<a link="impl-aarch64.HaveSVE2BitPerm.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2BitPerm()">HaveSVE2BitPerm</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="bdep_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zd"><Zd></symbol>
|
||||
<account encodedin="Zd">
|
||||
<intro>
|
||||
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bdep_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="bdep_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bdep_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BDEP-Z.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckNonStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) data = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) mask = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements - 1
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-aarch64.BitDeposit.2" file="shared_pseudocode.xml" hover="function: bits(N) BitDeposit (bits(N) data, bits(N) mask)">BitDeposit</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[data, e, esize], <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[mask, e, esize]);
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
171
spec/arm64_xml/bext_z_zz.xml
Normal file
171
spec/arm64_xml/bext_z_zz.xml
Normal file
@@ -0,0 +1,171 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="bext_z_zz" title="BEXT" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BEXT" />
|
||||
</docvars>
|
||||
<heading>BEXT</heading>
|
||||
<desc>
|
||||
<brief>Gather lower bits from positions selected by bitmask</brief>
|
||||
<description>
|
||||
<para>This instruction gathers bits in each element of the first source vector from the bit positions indicated by non-zero bits in the corresponding mask element of the second source vector to the lowest-numbered contiguous bits of the corresponding destination element, preserving their order, and sets the remaining higher-numbered bits to zero. This instruction is unpredicated.</para>
|
||||
<para>ID_AA64ZFR0_EL1.BitPerm indicates whether this instruction is implemented.</para>
|
||||
<para>This instruction is illegal when executed in Streaming SVE mode, unless FEAT_SME_FA64 is implemented and enabled.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<uses_dit condition="FEAT_SVE2 is implemented or FEAT_SME is implemented">True</uses_dit>
|
||||
<sm_policy>SM_0_only</sm_policy>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BEXT" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_SVE_BitPerm" feature="FEAT_SVE_BitPerm" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="BEXT-Z.ZZ-_">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" width="2" name="size" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="4" settings="4">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="11" name="opc<1>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" name="opc<0>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="bext_z_zz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BEXT" />
|
||||
</docvars>
|
||||
<asmtemplate><text>BEXT </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a><text>, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.</text><a link="sa_t" hover="Size specifier (field "size") [B,D,H,S]"><T></a></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BEXT-Z.ZZ-_" mylink="BEXT-Z.ZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVE.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE()">HaveSVE</a>() || !<a link="impl-aarch64.HaveSVE2BitPerm.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVE2BitPerm()">HaveSVE2BitPerm</a>() then UNDEFINED;
|
||||
constant integer esize = 8 << <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(size);
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="bext_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zd"><Zd></symbol>
|
||||
<account encodedin="Zd">
|
||||
<intro>
|
||||
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bext_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_t"><T></symbol>
|
||||
<definition encodedin="size">
|
||||
<intro>Is the size specifier, </intro>
|
||||
<table class="valuetable">
|
||||
<tgroup cols="2">
|
||||
<thead>
|
||||
<row>
|
||||
<entry class="bitfield">size</entry>
|
||||
<entry class="symbol"><T></entry>
|
||||
</row>
|
||||
</thead>
|
||||
<tbody>
|
||||
<row>
|
||||
<entry class="bitfield">00</entry>
|
||||
<entry class="symbol">B</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">01</entry>
|
||||
<entry class="symbol">H</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">10</entry>
|
||||
<entry class="symbol">S</entry>
|
||||
</row>
|
||||
<row>
|
||||
<entry class="bitfield">11</entry>
|
||||
<entry class="symbol">D</entry>
|
||||
</row>
|
||||
</tbody>
|
||||
</tgroup>
|
||||
</table>
|
||||
</definition>
|
||||
</explanation>
|
||||
<explanation enclist="bext_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bext_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BEXT-Z.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckNonStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckNonStreamingSVEEnabled()">CheckNonStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV esize;
|
||||
bits(VL) data = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) mask = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements - 1
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, esize] = <a link="impl-aarch64.BitExtract.2" file="shared_pseudocode.xml" hover="function: bits(N) BitExtract (bits(N) data, bits(N) mask)">BitExtract</a>(<a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[data, e, esize], <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[mask, e, esize]);
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
148
spec/arm64_xml/bfadd_z_p_zz.xml
Normal file
148
spec/arm64_xml/bfadd_z_p_zz.xml
Normal file
@@ -0,0 +1,148 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="bfadd_z_p_zz" title="BFADD (predicated)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFADD" />
|
||||
</docvars>
|
||||
<heading>BFADD (predicated)</heading>
|
||||
<desc>
|
||||
<brief>BFloat16 floating-point add vectors (predicated)</brief>
|
||||
<description>
|
||||
<para>Add active BFloat16 elements of the second source vector to corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.</para>
|
||||
<para>This instruction follows SVE2.1 non-widening BFloat16 numerical behaviors.</para>
|
||||
<para>ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>True</predicated>
|
||||
<takes_movprfx>True</takes_movprfx>
|
||||
<takes_pred_movprfx>True</takes_pred_movprfx>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFADD" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_B16B16" feature="FEAT_B16B16" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="BFADD-Z.P.ZZ-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" name="size<1>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="size<0>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="19" width="3" name="opc<3:1>" settings="3">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="16" name="opc<0>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="15" width="3" settings="3">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="12" width="3" name="Pg" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zdn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="bfadd_z_p_zz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFADD" />
|
||||
</docvars>
|
||||
<asmtemplate><text>BFADD </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.H, </text><a link="sa_pg" hover="Governing scalable predicate register P0-P7 (field "Pg")"><Pg></a><text>/M, </text><a link="sa_zdn" hover="First source and destination scalable vector register (field "Zdn")"><Zdn></a><text>.H, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.H</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BFADD-Z.P.ZZ-_" mylink="BFADD-Z.P.ZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVEB16B16.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVEB16B16()">HaveSVEB16B16</a>() then UNDEFINED;
|
||||
integer g = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Pg);
|
||||
integer dn = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zdn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="bfadd_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zdn"><Zdn></symbol>
|
||||
<account encodedin="Zdn">
|
||||
<intro>
|
||||
<para>Is the name of the first source and destination scalable vector register, encoded in the "Zdn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bfadd_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_pg"><Pg></symbol>
|
||||
<account encodedin="Pg">
|
||||
<intro>
|
||||
<para>Is the name of the governing scalable predicate register P0-P7, encoded in the "Pg" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bfadd_z_p_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BFADD-Z.P.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV 16;
|
||||
bits(PL) mask = <a link="impl-aarch64.P.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) P[integer n, integer width]">P</a>[g, PL];
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[dn, VL];
|
||||
bits(VL) operand2 = if <a link="impl-aarch64.AnyActiveElement.2" file="shared_pseudocode.xml" hover="function: boolean AnyActiveElement(bits(N) mask, integer esize)">AnyActiveElement</a>(mask, 16) then <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL] else <a link="impl-shared.Zeros.1" file="shared_pseudocode.xml" hover="function: bits(N) Zeros(integer N)">Zeros</a>(VL);
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(16) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 16];
|
||||
if <a link="impl-aarch64.ActivePredicateElement.3" file="shared_pseudocode.xml" hover="function: boolean ActivePredicateElement(bits(N) pred, integer e, integer esize)">ActivePredicateElement</a>(mask, e, 16) then
|
||||
bits(16) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 16];
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 16] = <a link="impl-shared.BFAdd.3" file="shared_pseudocode.xml" hover="function: bits(16) BFAdd(bits(16) op1, bits(16) op2, FPCRType fpcr)">BFAdd</a>(element1, element2, FPCR[]);
|
||||
else
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 16] = element1;
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[dn, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
140
spec/arm64_xml/bfadd_z_zz.xml
Normal file
140
spec/arm64_xml/bfadd_z_zz.xml
Normal file
@@ -0,0 +1,140 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="bfadd_z_zz" title="BFADD (unpredicated)" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFADD" />
|
||||
</docvars>
|
||||
<heading>BFADD (unpredicated)</heading>
|
||||
<desc>
|
||||
<brief>BFloat16 floating-point add vectors (unpredicated)</brief>
|
||||
<description>
|
||||
<para>Add all BFloat16 elements of the second source vector to corresponding elements of the first source vector and place the results in the corresponding elements of the destination vector.</para>
|
||||
<para>This instruction follows SVE2.1 non-widening BFloat16 numerical behaviors.</para>
|
||||
<para>This instruction is unpredicated.</para>
|
||||
<para>ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFADD" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_B16B16" feature="FEAT_B16B16" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="BFADD-Z.ZZ-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" name="size<1>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="size<0>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="12" width="2" name="opc<2:1>" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="10" name="opc<0>" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="bfadd_z_zz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFADD" />
|
||||
</docvars>
|
||||
<asmtemplate><text>BFADD </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.H, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.H, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.H</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BFADD-Z.ZZ-_" mylink="BFADD-Z.ZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVEB16B16.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVEB16B16()">HaveSVEB16B16</a>() then UNDEFINED;
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="bfadd_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zd"><Zd></symbol>
|
||||
<account encodedin="Zd">
|
||||
<intro>
|
||||
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bfadd_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bfadd_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BFADD-Z.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV 16;
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) result;
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(16) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 16];
|
||||
bits(16) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 16];
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 16] = <a link="impl-shared.BFAdd.3" file="shared_pseudocode.xml" hover="function: bits(16) BFAdd(bits(16) op1, bits(16) op2, FPCRType fpcr)">BFAdd</a>(element1, element2, FPCR[]);
|
||||
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
268
spec/arm64_xml/bfadd_za_zw.xml
Normal file
268
spec/arm64_xml/bfadd_za_zw.xml
Normal file
@@ -0,0 +1,268 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="bfadd_za_zw" title="BFADD" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFADD" />
|
||||
</docvars>
|
||||
<heading>BFADD</heading>
|
||||
<desc>
|
||||
<brief>BFloat16 floating-point add multi-vector to ZA array vector accumulators</brief>
|
||||
<description>
|
||||
<para>The instruction operates on two or four ZA single-vector groups.</para>
|
||||
<para>Destructively add all elements of the two or four source vectors to the corresponding BFloat16 elements of the two or four ZA single-vector groups. The vector numbers forming the single-vector group within each half or each quarter of the ZA array are selected by the sum of the vector select register and immediate offset, modulo half or quarter the number of ZA array vectors.</para>
|
||||
<para>The <arm-defined-word>vector group</arm-defined-word> symbol, <syntax>VGx2</syntax> or <syntax>VGx4</syntax>, indicates that the ZA operand consists of two or four ZA single-vector groups respectively. The <arm-defined-word>vector group</arm-defined-word> symbol is preferred for disassembly, but optional in assembler source code.</para>
|
||||
<para>This instruction follows SME2.1 ZA-targeting non-widening BFloat16 numerical behaviors.</para>
|
||||
<para>This instruction is unpredicated.</para>
|
||||
<para>ID_AA64SMFR0_EL1.B16B16 indicates whether this instruction is implemented.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<sm_policy>SM_1_only</sm_policy>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<classesintro count="2">
|
||||
<txt>It has encodings from 2 classes:</txt>
|
||||
<a href="#iclass_sme_vgx2_single">Two ZA single-vectors</a>
|
||||
<txt> and </txt>
|
||||
<a href="#iclass_sme_vgx4_single">Four ZA single-vectors</a>
|
||||
</classesintro>
|
||||
<iclass name="Two ZA single-vectors" oneof="2" id="iclass_sme_vgx2_single" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFADD" />
|
||||
<docvar key="sme-multireg" value="sme-vgx2-single" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_B16B16" feature="FEAT_B16B16" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="BFADD-ZA.ZW-2x2_16" tworows="1">
|
||||
<box hibit="31" width="9" settings="9">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="22" name="sz" usename="1" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="21" width="7" settings="7">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="14" width="2" name="Rv" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" settings="3">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="4" name="Zm" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
<box hibit="5" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="3" name="S" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="2" width="3" name="off3" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="bfadd_za_zw_2x2_16" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFADD" />
|
||||
<docvar key="sme-multireg" value="sme-vgx2-single" />
|
||||
</docvars>
|
||||
<asmtemplate><text>BFADD ZA.H[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field "off3")"><offs></a><a>{, VGx2}</a><text>], </text><text>{</text><text> </text><a link="sa_zm1" hover="First scalable vector register of a multi-vector sequence (field Zm)"><Zm1></a><text>.H-</text><a link="sa_zm2" hover="Second scalable vector register of a multi-vector sequence (field Zm)"><Zm2></a><text>.H </text><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BFADD-ZA.ZW-2x2_16" mylink="BFADD-ZA.ZW-2x2_16" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSMEB16B16.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEB16B16()">HaveSMEB16B16</a>() then UNDEFINED;
|
||||
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm:'0');
|
||||
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
|
||||
constant integer nreg = 2;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
<iclass name="Four ZA single-vectors" oneof="2" id="iclass_sme_vgx4_single" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFADD" />
|
||||
<docvar key="sme-multireg" value="sme-vgx4-single" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_B16B16" feature="FEAT_B16B16" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="BFADD-ZA.ZW-4x4_16" tworows="1">
|
||||
<box hibit="31" width="9" settings="9">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="22" name="sz" usename="1" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="21" width="7" settings="7">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="14" width="2" name="Rv" usename="1">
|
||||
<c colspan="2"></c>
|
||||
</box>
|
||||
<box hibit="12" width="3" settings="3">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="3" name="Zm" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="6" width="3" settings="3">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="3" name="S" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="2" width="3" name="off3" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="bfadd_za_zw_4x4_16" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFADD" />
|
||||
<docvar key="sme-multireg" value="sme-vgx4-single" />
|
||||
</docvars>
|
||||
<asmtemplate><text>BFADD ZA.H[</text><a link="sa_wv" hover="32-bit vector select register W8-W11 (field "Rv")"><Wv></a><text>, </text><a link="sa_offs" hover="Vector select offset [0-7] (field "off3")"><offs></a><a>{, VGx4}</a><text>], </text><text>{</text><text> </text><a link="sa_zm1_1" hover="First scalable vector register of a multi-vector sequence (field Zm)"><Zm1></a><text>.H-</text><a link="sa_zm4" hover="Fourth scalable vector register of a multi-vector sequence (field Zm)"><Zm4></a><text>.H </text><text>}</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BFADD-ZA.ZW-4x4_16" mylink="BFADD-ZA.ZW-4x4_16" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSMEB16B16.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEB16B16()">HaveSMEB16B16</a>() then UNDEFINED;
|
||||
integer v = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>('010':Rv);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm:'00');
|
||||
integer offset = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(off3);
|
||||
constant integer nreg = 4;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="bfadd_za_zw_2x2_16, bfadd_za_zw_4x4_16" symboldefcount="1">
|
||||
<symbol link="sa_wv"><Wv></symbol>
|
||||
<account encodedin="Rv">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the vector select register W8-W11, encoded in the "Rv" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bfadd_za_zw_2x2_16, bfadd_za_zw_4x4_16" symboldefcount="1">
|
||||
<symbol link="sa_offs"><offs></symbol>
|
||||
<account encodedin="off3">
|
||||
<intro>
|
||||
<para>Is the vector select offset, in the range 0 to 7, encoded in the "off3" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bfadd_za_zw_2x2_16" symboldefcount="1">
|
||||
<symbol link="sa_zm1"><Zm1></symbol>
|
||||
<account encodedin="Zm">
|
||||
<docvars>
|
||||
<docvar key="sme-multireg" value="sme-vgx2-single" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the two ZA single-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zm" times 2.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bfadd_za_zw_4x4_16" symboldefcount="2">
|
||||
<symbol link="sa_zm1_1"><Zm1></symbol>
|
||||
<account encodedin="Zm">
|
||||
<docvars>
|
||||
<docvar key="sme-multireg" value="sme-vgx4-single" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the four ZA single-vectors variant: is the name of the first scalable vector register of a multi-vector sequence, encoded as "Zm" times 4.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bfadd_za_zw_4x4_16" symboldefcount="1">
|
||||
<symbol link="sa_zm4"><Zm4></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the fourth scalable vector register of a multi-vector sequence, encoded as "Zm" times 4 plus 3.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bfadd_za_zw_2x2_16" symboldefcount="1">
|
||||
<symbol link="sa_zm2"><Zm2></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second scalable vector register of a multi-vector sequence, encoded as "Zm" times 2 plus 1.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BFADD-ZA.ZW-2x2_16" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEAndZAEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEAndZAEnabled()">CheckStreamingSVEAndZAEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV 16;
|
||||
integer vectors = VL DIV 8;
|
||||
integer vstride = vectors DIV nreg;
|
||||
bits(32) vbase = <a link="impl-aarch64.X.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) X[integer n, integer width]">X</a>[v, 32];
|
||||
integer vec = (<a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(vbase) + offset) MOD vstride;
|
||||
bits(VL) result;
|
||||
|
||||
for r = 0 to nreg-1
|
||||
bits(VL) operand1 = <a link="impl-aarch64.ZAvector.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) ZAvector[integer index, integer width]">ZAvector</a>[vec, VL];
|
||||
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m+r, VL];
|
||||
for e = 0 to elements-1
|
||||
bits(16) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 16];
|
||||
bits(16) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 16];
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 16] = <a link="impl-shared.BFAdd_ZA.3" file="shared_pseudocode.xml" hover="function: bits(16) BFAdd_ZA(bits(16) op1, bits(16) op2, FPCRType fpcr_in)">BFAdd_ZA</a>(element1, element2, FPCR[]);
|
||||
<a link="impl-aarch64.ZAvector.write.2" file="shared_pseudocode.xml" hover="accessor: ZAvector[integer index, integer width] = bits(width) value">ZAvector</a>[vec, VL] = result;
|
||||
vec = vec + vstride;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
189
spec/arm64_xml/bfc_bfm.xml
Normal file
189
spec/arm64_xml/bfc_bfm.xml
Normal file
@@ -0,0 +1,189 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="BFC_BFM" title="BFC -- A64" type="alias">
|
||||
<docvars>
|
||||
<docvar key="alias_mnemonic" value="BFC" />
|
||||
<docvar key="bitfield-fill" value="nofill" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFM" />
|
||||
<docvar key="source-type" value="src-is-immediate" />
|
||||
</docvars>
|
||||
<heading>BFC</heading>
|
||||
<desc>
|
||||
<brief>
|
||||
<para>Bitfield Clear</para>
|
||||
</brief>
|
||||
<authored>
|
||||
<para>Bitfield Clear sets a bitfield of <syntax><width></syntax> bits at bit position <syntax><lsb></syntax> of the destination register to zero, leaving the other destination bits unchanged.</para>
|
||||
</authored>
|
||||
</desc>
|
||||
<operationalnotes>
|
||||
<para>If PSTATE.DIT is 1:</para>
|
||||
<list type="unordered">
|
||||
<listitem><content>The execution time of this instruction is independent of:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
<listitem><content>The response of this instruction to asynchronous exceptions does not vary based on:<list type="unordered"><listitem><content>The values of the data supplied in any of its registers.</content></listitem><listitem><content>The values of the NZCV flags.</content></listitem></list></content></listitem>
|
||||
</list>
|
||||
</operationalnotes>
|
||||
<aliasto refiform="bfm.xml" iformid="BFM">BFM</aliasto>
|
||||
<classes>
|
||||
<iclass name="Leaving other bits unchanged" oneof="1" id="iclass_nofill" no_encodings="2" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="bitfield-fill" value="nofill" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFM" />
|
||||
</docvars>
|
||||
<iclassintro count="2"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="ARMv8.2" feature="FEAT_ASMv8p2" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="aarch64/instrs/integer/bitfield" tworows="1">
|
||||
<box hibit="31" name="sf" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="30" width="2" name="opc" usename="1" settings="2" psbits="xx">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="28" width="6" settings="6">
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="N" usename="1">
|
||||
<c></c>
|
||||
</box>
|
||||
<box hibit="21" width="6" name="immr" usename="1">
|
||||
<c colspan="6"></c>
|
||||
</box>
|
||||
<box hibit="15" width="6" name="imms" usename="1">
|
||||
<c colspan="6"></c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Rn" usename="1" settings="5" psbits="xxxxx">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Rd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="BFC_BFM_32M_bitfield" oneofinclass="2" oneof="2" label="32-bit" bitdiffs="sf == 0 && N == 0">
|
||||
<docvars>
|
||||
<docvar key="alias_mnemonic" value="BFC" />
|
||||
<docvar key="bitfield-fill" value="nofill" />
|
||||
<docvar key="datatype" value="32" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFM" />
|
||||
<docvar key="source-type" value="src-is-immediate" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" width="1" name="N">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<asmtemplate><text>BFC </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, #</text><a link="sa_lsb" hover="Bit number of lsb of the destination bitfield [0-31]"><lsb></a><text>, #</text><a link="sa_width" hover="Width of bitfield [1-32-<lsb>]"><width></a></asmtemplate>
|
||||
<equivalent_to>
|
||||
<asmtemplate><a href="bfm.xml#BFM_32M_bitfield">BFM</a><text> </text><a link="sa_wd" hover="32-bit general-purpose destination register (field "Rd")"><Wd></a><text>, WZR, #(-</text><a link="sa_lsb" hover="Bit number of lsb of the destination bitfield [0-31]"><lsb></a><text> MOD 32), #(</text><a link="sa_width" hover="Width of bitfield [1-32-<lsb>]"><width></a><text>-1)</text></asmtemplate>
|
||||
<aliascond><a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imms) < <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(immr)</aliascond>
|
||||
</equivalent_to>
|
||||
</encoding>
|
||||
<encoding name="BFC_BFM_64M_bitfield" oneofinclass="2" oneof="2" label="64-bit" bitdiffs="sf == 1 && N == 1">
|
||||
<docvars>
|
||||
<docvar key="alias_mnemonic" value="BFC" />
|
||||
<docvar key="bitfield-fill" value="nofill" />
|
||||
<docvar key="datatype" value="64" />
|
||||
<docvar key="instr-class" value="general" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFM" />
|
||||
<docvar key="source-type" value="src-is-immediate" />
|
||||
</docvars>
|
||||
<box hibit="31" width="1" name="sf">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="22" width="1" name="N">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<asmtemplate><text>BFC </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, #</text><a link="sa_lsb_2" hover="Bit number of lsb of the destination bitfield [0-63]"><lsb></a><text>, #</text><a link="sa_width_1" hover="Width of bitfield [1-64-<lsb>]"><width></a></asmtemplate>
|
||||
<equivalent_to>
|
||||
<asmtemplate><a href="bfm.xml#BFM_64M_bitfield">BFM</a><text> </text><a link="sa_xd" hover="64-bit general-purpose destination register (field "Rd")"><Xd></a><text>, XZR, #(-</text><a link="sa_lsb_2" hover="Bit number of lsb of the destination bitfield [0-63]"><lsb></a><text> MOD 64), #(</text><a link="sa_width_1" hover="Width of bitfield [1-64-<lsb>]"><width></a><text>-1)</text></asmtemplate>
|
||||
<aliascond><a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(imms) < <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(immr)</aliascond>
|
||||
</equivalent_to>
|
||||
</encoding>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="BFC_BFM_32M_bitfield" symboldefcount="1">
|
||||
<symbol link="sa_wd"><Wd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 32-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="BFC_BFM_64M_bitfield" symboldefcount="1">
|
||||
<symbol link="sa_xd"><Xd></symbol>
|
||||
<account encodedin="Rd">
|
||||
<intro>
|
||||
<para>Is the 64-bit name of the general-purpose destination register, encoded in the "Rd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="BFC_BFM_32M_bitfield" symboldefcount="1">
|
||||
<symbol link="sa_lsb"><lsb></symbol>
|
||||
<account encodedin="">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="32" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 32-bit variant: is the bit number of the lsb of the destination bitfield, in the range 0 to 31.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="BFC_BFM_64M_bitfield" symboldefcount="2">
|
||||
<symbol link="sa_lsb_2"><lsb></symbol>
|
||||
<account encodedin="">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="64" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 64-bit variant: is the bit number of the lsb of the destination bitfield, in the range 0 to 63.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="BFC_BFM_32M_bitfield" symboldefcount="1">
|
||||
<symbol link="sa_width"><width></symbol>
|
||||
<account encodedin="">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="32" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 32-bit variant: is the width of the bitfield, in the range 1 to 32-<lsb>.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="BFC_BFM_64M_bitfield" symboldefcount="2">
|
||||
<symbol link="sa_width_1"><width></symbol>
|
||||
<account encodedin="">
|
||||
<docvars>
|
||||
<docvar key="datatype" value="64" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the 64-bit variant: is the width of the bitfield, in the range 1 to 64-<lsb>.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
</instructionsection>
|
||||
255
spec/arm64_xml/bfclamp_mz_zz.xml
Normal file
255
spec/arm64_xml/bfclamp_mz_zz.xml
Normal file
@@ -0,0 +1,255 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="bfclamp_mz_zz" title="BFCLAMP" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFCLAMP" />
|
||||
</docvars>
|
||||
<heading>BFCLAMP</heading>
|
||||
<desc>
|
||||
<brief>Multi-vector BFloat16 floating-point clamp to minimum/maximum number</brief>
|
||||
<description>
|
||||
<para>Clamp each BFloat16 element in the two or four destination vectors to between the BFloat16 minimum value in the corresponding element of the first source vector and the BFloat16 maximum value in the corresponding element of the second source vector and destructively place the clamped results in the corresponding elements of the two or four destination vectors. If at least one element value contributing to a result is numeric and the other is either numeric or a quiet NaN, then the result is the numeric value.</para>
|
||||
<para>This instruction follows SME2.1 non-widening BFloat16 numerical behaviors corresponding to instructions that place their results in two or four SVE Z vectors.</para>
|
||||
<para>This instruction is unpredicated.</para>
|
||||
<para>ID_AA64SMFR0_EL1.B16B16 indicates whether this instruction is implemented.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<sm_policy>SM_1_only</sm_policy>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<classesintro count="2">
|
||||
<txt>It has encodings from 2 classes:</txt>
|
||||
<a href="#iclass_to_2reg">Two registers</a>
|
||||
<txt> and </txt>
|
||||
<a href="#iclass_to_4reg">Four registers</a>
|
||||
</classesintro>
|
||||
<iclass name="Two registers" oneof="2" id="iclass_to_2reg" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="ldstruct-regcount" value="to-2reg" />
|
||||
<docvar key="mnemonic" value="BFCLAMP" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_B16B16" feature="FEAT_B16B16" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="BFCLAMP-MZ.ZZ-2" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" name="size<1>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="size<0>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="6" settings="6">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="4" name="Zd" usename="1">
|
||||
<c colspan="4"></c>
|
||||
</box>
|
||||
<box hibit="0" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="bfclamp_mz_zz_2" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="ldstruct-regcount" value="to-2reg" />
|
||||
<docvar key="mnemonic" value="BFCLAMP" />
|
||||
</docvars>
|
||||
<asmtemplate><text>BFCLAMP </text><text>{</text><text> </text><a link="sa_zd1" hover="First destination scalable vector register of a multi-vector sequence (field Zd)"><Zd1></a><text>.H-</text><a link="sa_zd2" hover="Second destination scalable vector register of a multi-vector sequence (field Zd)"><Zd2></a><text>.H </text><text>}</text><text>, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.H, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.H</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BFCLAMP-MZ.ZZ-2" mylink="BFCLAMP-MZ.ZZ-2" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSMEB16B16.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEB16B16()">HaveSMEB16B16</a>() then UNDEFINED;
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd:'0');
|
||||
constant integer nreg = 2;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
<iclass name="Four registers" oneof="2" id="iclass_to_4reg" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="ldstruct-regcount" value="to-4reg" />
|
||||
<docvar key="mnemonic" value="BFCLAMP" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_B16B16" feature="FEAT_B16B16" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="BFCLAMP-MZ.ZZ-4" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="23" name="size<1>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="size<0>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="6" settings="6">
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="3" name="Zd" usename="1">
|
||||
<c colspan="3"></c>
|
||||
</box>
|
||||
<box hibit="1" width="2" settings="2">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="bfclamp_mz_zz_4" oneofinclass="1" oneof="2" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="mortlach2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="ldstruct-regcount" value="to-4reg" />
|
||||
<docvar key="mnemonic" value="BFCLAMP" />
|
||||
</docvars>
|
||||
<asmtemplate><text>BFCLAMP </text><text>{</text><text> </text><a link="sa_zd1_1" hover="First destination scalable vector register of a multi-vector sequence (field Zd)"><Zd1></a><text>.H-</text><a link="sa_zd4" hover="Fourth destination scalable vector register of a multi-vector sequence (field Zd)"><Zd4></a><text>.H </text><text>}</text><text>, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.H, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.H</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BFCLAMP-MZ.ZZ-4" mylink="BFCLAMP-MZ.ZZ-4" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSMEB16B16.0" file="shared_pseudocode.xml" hover="function: boolean HaveSMEB16B16()">HaveSMEB16B16</a>() then UNDEFINED;
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd:'00');
|
||||
constant integer nreg = 4;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="bfclamp_mz_zz_2" symboldefcount="1">
|
||||
<symbol link="sa_zd1"><Zd1></symbol>
|
||||
<account encodedin="Zd">
|
||||
<docvars>
|
||||
<docvar key="ldstruct-regcount" value="to-2reg" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the two registers variant: is the name of the first destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 2.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bfclamp_mz_zz_4" symboldefcount="2">
|
||||
<symbol link="sa_zd1_1"><Zd1></symbol>
|
||||
<account encodedin="Zd">
|
||||
<docvars>
|
||||
<docvar key="ldstruct-regcount" value="to-4reg" />
|
||||
</docvars>
|
||||
<intro>
|
||||
<para>For the four registers variant: is the name of the first destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 4.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bfclamp_mz_zz_4" symboldefcount="1">
|
||||
<symbol link="sa_zd4"><Zd4></symbol>
|
||||
<account encodedin="Zd">
|
||||
<intro>
|
||||
<para>Is the name of the fourth destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 4 plus 3.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bfclamp_mz_zz_2" symboldefcount="1">
|
||||
<symbol link="sa_zd2"><Zd2></symbol>
|
||||
<account encodedin="Zd">
|
||||
<intro>
|
||||
<para>Is the name of the second destination scalable vector register of a multi-vector sequence, encoded as "Zd" times 2 plus 1.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bfclamp_mz_zz_2, bfclamp_mz_zz_4" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bfclamp_mz_zz_2, bfclamp_mz_zz_4" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BFCLAMP-MZ.ZZ-2" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckStreamingSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckStreamingSVEEnabled()">CheckStreamingSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer elements = VL DIV 16;
|
||||
array [0..3] of bits(VL) results;
|
||||
|
||||
for r = 0 to nreg-1
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) operand3 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[d+r, VL];
|
||||
for e = 0 to elements-1
|
||||
bits(16) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 16];
|
||||
bits(16) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 16];
|
||||
bits(16) element3 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 16];
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[results[r], e, 16] = <a link="impl-shared.BFMinNum.3" file="shared_pseudocode.xml" hover="function: bits(16) BFMinNum(bits(16) op1_in, bits(16) op2_in, FPCRType fpcr)">BFMinNum</a>(<a link="impl-shared.BFMaxNum.3" file="shared_pseudocode.xml" hover="function: bits(16) BFMaxNum(bits(16) op1_in, bits(16) op2_in, FPCRType fpcr)">BFMaxNum</a>(element1, element3, FPCR[]), element2, FPCR[]);
|
||||
|
||||
for r = 0 to nreg-1
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d+r, VL] = results[r];</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
139
spec/arm64_xml/bfclamp_z_zz.xml
Normal file
139
spec/arm64_xml/bfclamp_z_zz.xml
Normal file
@@ -0,0 +1,139 @@
|
||||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<?xml-stylesheet type="text/xsl" encoding="UTF-8" href="iform.xsl" version="1.0"?>
|
||||
<!DOCTYPE instructionsection PUBLIC "-//ARM//DTD instructionsection //EN" "iform-p.dtd">
|
||||
<!-- Copyright (c) 2010-2022 Arm Limited or its affiliates. All rights reserved. -->
|
||||
<!-- This document is Non-Confidential. This document may only be used and distributed in accordance with the terms of the agreement entered into by Arm and the party that Arm delivered this document to. -->
|
||||
|
||||
<instructionsection id="bfclamp_z_zz" title="BFCLAMP" type="instruction">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFCLAMP" />
|
||||
</docvars>
|
||||
<heading>BFCLAMP</heading>
|
||||
<desc>
|
||||
<brief>BFloat16 floating-point clamp to minimum/maximum number</brief>
|
||||
<description>
|
||||
<para>Clamp each BFloat16 element in the destination vector to between the BFloat16 minimum value in the corresponding element of the first source vector and the BFloat16 maximum value in the corresponding element of the second source vector and destructively place the clamped results in the corresponding elements of the destination vector. If at least one element value contributing to a result is numeric and the others are either numeric or a quiet NaN, then the result is the numeric value.</para>
|
||||
<para>This instruction follows SVE2.1 non-widening BFloat16 numerical behaviors.</para>
|
||||
<para>This instruction is unpredicated.</para>
|
||||
<para>ID_AA64ZFR0_EL1.B16B16 indicates whether this instruction is implemented.</para>
|
||||
</description>
|
||||
<status>Green</status>
|
||||
<predicated>False</predicated>
|
||||
<takes_movprfx>True</takes_movprfx>
|
||||
</desc>
|
||||
<alias_list howmany="0"></alias_list>
|
||||
<classes>
|
||||
<iclass name="SVE2" oneof="1" id="iclass_sve2" no_encodings="1" isa="A64">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFCLAMP" />
|
||||
</docvars>
|
||||
<iclassintro count="1"></iclassintro>
|
||||
<arch_variants>
|
||||
<arch_variant name="FEAT_B16B16" feature="FEAT_B16B16" />
|
||||
</arch_variants>
|
||||
<regdiagram form="32" psname="BFCLAMP-Z.ZZ-_" tworows="1">
|
||||
<box hibit="31" width="8" settings="8">
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="23" name="size<1>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="22" name="size<0>" usename="1" settings="1">
|
||||
<c>0</c>
|
||||
</box>
|
||||
<box hibit="21" settings="1">
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="20" width="5" name="Zm" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="15" width="6" settings="6">
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
<c>0</c>
|
||||
<c>0</c>
|
||||
<c>1</c>
|
||||
</box>
|
||||
<box hibit="9" width="5" name="Zn" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
<box hibit="4" width="5" name="Zd" usename="1">
|
||||
<c colspan="5"></c>
|
||||
</box>
|
||||
</regdiagram>
|
||||
<encoding name="bfclamp_z_zz_" oneofinclass="1" oneof="1" label="">
|
||||
<docvars>
|
||||
<docvar key="instr-class" value="sve2" />
|
||||
<docvar key="isa" value="A64" />
|
||||
<docvar key="mnemonic" value="BFCLAMP" />
|
||||
</docvars>
|
||||
<asmtemplate><text>BFCLAMP </text><a link="sa_zd" hover="Destination scalable vector register (field "Zd")"><Zd></a><text>.H, </text><a link="sa_zn" hover="First source scalable vector register (field "Zn")"><Zn></a><text>.H, </text><a link="sa_zm" hover="Second source scalable vector register (field "Zm")"><Zm></a><text>.H</text></asmtemplate>
|
||||
</encoding>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BFCLAMP-Z.ZZ-_" mylink="BFCLAMP-Z.ZZ-_" enclabels="" sections="1" secttype="noheading">
|
||||
<pstext mayhavelinks="1" section="Decode" rep_section="decode">if !<a link="impl-aarch64.HaveSVEB16B16.0" file="shared_pseudocode.xml" hover="function: boolean HaveSVEB16B16()">HaveSVEB16B16</a>() then UNDEFINED;
|
||||
integer n = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zn);
|
||||
integer m = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zm);
|
||||
integer d = <a link="impl-shared.UInt.1" file="shared_pseudocode.xml" hover="function: integer UInt(bits(N) x)">UInt</a>(Zd);</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</iclass>
|
||||
</classes>
|
||||
<explanations scope="all">
|
||||
<explanation enclist="bfclamp_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zd"><Zd></symbol>
|
||||
<account encodedin="Zd">
|
||||
<intro>
|
||||
<para>Is the name of the destination scalable vector register, encoded in the "Zd" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bfclamp_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zn"><Zn></symbol>
|
||||
<account encodedin="Zn">
|
||||
<intro>
|
||||
<para>Is the name of the first source scalable vector register, encoded in the "Zn" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
<explanation enclist="bfclamp_z_zz_" symboldefcount="1">
|
||||
<symbol link="sa_zm"><Zm></symbol>
|
||||
<account encodedin="Zm">
|
||||
<intro>
|
||||
<para>Is the name of the second source scalable vector register, encoded in the "Zm" field.</para>
|
||||
</intro>
|
||||
</account>
|
||||
</explanation>
|
||||
</explanations>
|
||||
<ps_section howmany="1">
|
||||
<ps name="BFCLAMP-Z.ZZ-_" mylink="execute" enclabels="" sections="1" secttype="Operation">
|
||||
<pstext mayhavelinks="1" section="Execute" rep_section="execute"><a link="impl-aarch64.CheckSVEEnabled.0" file="shared_pseudocode.xml" hover="function: CheckSVEEnabled()">CheckSVEEnabled</a>();
|
||||
constant integer VL = <a link="impl-aarch64.CurrentVL.read.none" file="shared_pseudocode.xml" hover="accessor: integer CurrentVL">CurrentVL</a>;
|
||||
constant integer PL = VL DIV 8;
|
||||
constant integer elements = VL DIV 16;
|
||||
bits(VL) result;
|
||||
bits(VL) operand1 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[n, VL];
|
||||
bits(VL) operand2 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[m, VL];
|
||||
bits(VL) operand3 = <a link="impl-aarch64.Z.read.2" file="shared_pseudocode.xml" hover="accessor: bits(width) Z[integer n, integer width]">Z</a>[d, VL];
|
||||
|
||||
for e = 0 to elements-1
|
||||
bits(16) element1 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand1, e, 16];
|
||||
bits(16) element2 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand2, e, 16];
|
||||
bits(16) element3 = <a link="impl-shared.Elem.read.3" file="shared_pseudocode.xml" hover="accessor: bits(size) Elem[bits(N) vector, integer e, integer size]">Elem</a>[operand3, e, 16];
|
||||
<a link="impl-shared.Elem.write.3" file="shared_pseudocode.xml" hover="accessor: Elem[bits(N) &vector, integer e, integer size] = bits(size) value">Elem</a>[result, e, 16] = <a link="impl-shared.BFMinNum.3" file="shared_pseudocode.xml" hover="function: bits(16) BFMinNum(bits(16) op1_in, bits(16) op2_in, FPCRType fpcr)">BFMinNum</a>(<a link="impl-shared.BFMaxNum.3" file="shared_pseudocode.xml" hover="function: bits(16) BFMaxNum(bits(16) op1_in, bits(16) op2_in, FPCRType fpcr)">BFMaxNum</a>(element1, element3, FPCR[]), element2, FPCR[]);
|
||||
<a link="impl-aarch64.Z.write.2" file="shared_pseudocode.xml" hover="accessor: Z[integer n, integer width] = bits(width) value">Z</a>[d, VL] = result;</pstext>
|
||||
</ps>
|
||||
</ps_section>
|
||||
</instructionsection>
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user