Bumped version to v0.1.8

Fix pkgver in PKGBUILDS

.github/FUNDING.yml

@@ -0,0 +1,12 @@
+# These are supported funding model platforms
+
+github: ptitSeb
+patreon: # Replace with a single Patreon username
+open_collective: # Replace with a single Open Collective username
+ko_fi: # Replace with a single Ko-fi username
+tidelift: # Replace with a single Tidelift platform-name/package-name e.g., npm/babel
+community_bridge: # Replace with a single Community Bridge project-name e.g., cloud-foundry
+liberapay: # Replace with a single Liberapay username
+issuehunt: # Replace with a single IssueHunt username
+otechie: # Replace with a single Otechie username
+custom: paypal.me/0ptitSeb

.github/workflows/manual.yml

@@ -0,0 +1,95 @@
+### Manual build Box64 with Github Action
+name: Custom build Box64
+
+on:
+  workflow_dispatch:
+    inputs:
+      platform:
+        description: 'Target platform name'
+        required: true
+        default: 'GENERIC_ARM'
+        type: choice
+        options:
+        - X64
+        - GENERIC_ARM
+        - PHYTIUM
+        - RK3288
+        - RK3326
+        - RK3399
+        - RPI4ARM64
+        - SD845
+        - TEGRAX1
+      build_type:
+        description: 'Build type'
+        required: true
+        default: 'RelWithDebInfo'
+        type: choice
+        options:
+        - RelWithDebInfo
+        - Release
+        - Debug
+        - MinSizeRel
+      dynarec:
+        description: 'Enable dynarec'
+        required: false
+        default: 'true'
+        type: boolean
+      trace:
+        description: 'Enable trace'
+        required: false
+        default: 'false'
+        type: boolean
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    steps:
+      - name: "Checkout Box64 Repository"
+        uses: actions/checkout@v2
+
+      - name: "Environment preparation"
+        run: |
+          sudo apt-get update
+          if [[ ${{ github.event.inputs.platform }} != 'X64' && ${{ github.event.inputs.platform }} != 'GENERIC_ARM' ]]; then
+            echo "BOX64_PLATFORM_MARCRO=-D${{ github.event.inputs.platform }}=1" >> $GITHUB_ENV
+            echo "BOX64_COMPILER=aarch64-linux-gnu-gcc" >> $GITHUB_ENV
+            sudo apt-get -y install git gcc-aarch64-linux-gnu cmake make python3
+          else
+            if [[ ${{ github.event.inputs.platform }} == 'X64' ]]; then
+              echo "BOX64_PLATFORM_MARCRO=-DLD80BITS=1 -DNOALIGN=1" >> $GITHUB_ENV
+              echo "BOX64_COMPILER=gcc" >> $GITHUB_ENV
+              sudo apt-get -y install git cmake make python3
+            else
+              echo BOX64_PLATFORM_MARCRO="-DARM_DYNAREC=ON" >> $GITHUB_ENV
+              echo "BOX64_COMPILER=aarch64-linux-gnu-gcc" >> $GITHUB_ENV
+              sudo apt-get -y install git gcc-aarch64-linux-gnu cmake make python3
+            fi
+          fi
+
+      - name: "Display Build info"
+        run: |
+          echo "CMake Platform Macro: ${{ env.BOX64_PLATFORM_MARCRO }}"
+          echo "CMake C Compiler: ${{ env.BOX64_COMPILER }}"
+          echo "Build type: ${{ github.event.inputs.build_type }}"
+          echo "Dynarec Enabled: ${{ github.event.inputs.dynarec }}"
+          echo "Trace Enabled: ${{ github.event.inputs.trace }}"
+
+      - name: "Build Box64"
+        run: |
+          mkdir build
+          cd build
+          cmake .. -DCMAKE_C_COMPILER=${{ env.BOX64_COMPILER }} ${{ env.BOX64_PLATFORM_MARCRO }}\
+                   -DCMAKE_BUILD_TYPE=${{ github.event.inputs.build_type }}\
+                   -DARM_DYNAREC:BOOL=${{ github.event.inputs.dynarec }}\
+                   -DHAVE_TRACE:BOOL=${{ github.event.inputs.trace }}\
+                   -DCMAKE_VERBOSE_MAKEFILE:BOOL=ON
+          make -j$(nproc) VERBOSE=1
+
+      - name: "Upload Artifact"
+        uses: actions/upload-artifact@v2
+        with:
+          name: box64-${{ github.event.inputs.platform }}-${{ github.event.inputs.build_type }}
+          path: build/box64
+
+
+

.github/workflows/release.yml

@@ -0,0 +1,96 @@
+### Auto build Box64 and release its binary with Github Action
+name: Build and Release Box64
+
+on:
+  workflow_dispatch:
+  release:
+  push:
+    paths:
+      - "**/*.c"
+      - "**/*.h"
+      - "**/*.S"
+      - "**/*.py"
+      - "CMakeLists.txt"
+      - "**/*.yml"
+  pull_request:
+    types: [assigned, opened, synchronize, reopened]
+    paths:
+      - "**/*.c"
+      - "**/*.h"
+      - "**/*.S"
+      - "**/*.py"
+      - "CMakeLists.txt"
+      - "**/*.yml"
+
+jobs:
+  build:
+    strategy:
+      fail-fast: false
+      matrix:
+        platform: [X64, OTHER_ARM, RISCV, RPI4ARM64, RK3326, RK3399, RK3288, TEGRAX1, PHYTIUM, SD845]
+        type: [Release, Trace]
+
+    runs-on: ubuntu-latest
+    steps:
+      - name: "Checkout Box64 Repository"
+        uses: actions/checkout@v2
+
+      - name: "Environment preparation"
+        run: |
+          sudo apt-get update
+          if [[ ${{ matrix.platform }} != 'X64' && ${{ matrix.platform }} != 'OTHER_ARM' && ${{ matrix.platform }} != 'RISCV' ]]; then
+            echo "BOX64_PLATFORM_MARCRO=-D${{ matrix.platform }}=1" >> $GITHUB_ENV
+            echo "BOX64_COMPILER=aarch64-linux-gnu-gcc" >> $GITHUB_ENV
+            sudo apt-get -y install git gcc-aarch64-linux-gnu cmake make python3
+          else
+            if [[ ${{ matrix.platform }} == 'X64' ]]; then
+              echo "BOX64_PLATFORM_MARCRO=-DLD80BITS=1 -DNOALIGN=1" >> $GITHUB_ENV
+              echo "BOX64_COMPILER=gcc" >> $GITHUB_ENV
+              sudo apt-get -y install git cmake make python3
+            elif [[ ${{ matrix.platform }} == 'RISCV' ]]; then
+              echo BOX64_PLATFORM_MARCRO="-DRV64=ON" >> $GITHUB_ENV
+              echo "BOX64_COMPILER=riscv64-linux-gnu-gcc" >> $GITHUB_ENV
+              sudo apt-get -y install git gcc-riscv64-linux-gnu cmake make python3
+            else
+              echo BOX64_PLATFORM_MARCRO="-DARM_DYNAREC=ON" >> $GITHUB_ENV
+              echo "BOX64_COMPILER=aarch64-linux-gnu-gcc" >> $GITHUB_ENV
+              sudo apt-get -y install git gcc-aarch64-linux-gnu cmake make python3
+            fi
+          fi
+          if [[ ${{ matrix.type }} == 'Release' ]]; then
+            echo BOX64_BUILD_TYPE=Release >> $GITHUB_ENV
+            echo BOX64_HAVE_TRACE=0 >> $GITHUB_ENV
+          else
+            echo BOX64_BUILD_TYPE=RelWithDebInfo >> $GITHUB_ENV
+            echo BOX64_HAVE_TRACE=1 >> $GITHUB_ENV
+          fi
+
+      - name: "Display Build info"
+        run: |
+          echo "CMake Platform Macro: ${{ env.BOX64_PLATFORM_MARCRO }}"
+          echo "CMake C Compiler: ${{ env.BOX64_COMPILER }}"
+          echo "Build type: ${{ env.BOX64_BUILD_TYPE }}"
+          echo "Trace Enabled: ${{ env.BOX64_HAVE_TRACE }}"
+
+      - name: "Build Box64"
+        run: |
+          mkdir build
+          cd build
+          cmake .. -DCMAKE_C_COMPILER=${{ env.BOX64_COMPILER }}\
+                   ${{ env.BOX64_PLATFORM_MARCRO }}\
+                   -DCMAKE_BUILD_TYPE=${{ env.BOX64_BUILD_TYPE }}\
+                   -DHAVE_TRACE=${{ env.BOX64_HAVE_TRACE }}\
+                   -DCMAKE_VERBOSE_MAKEFILE:BOOL=ON
+          make -j$(nproc) VERBOSE=1
+
+      - name: "Test Box64"
+        if: ${{ matrix.platform == 'X64' }}
+        run: |
+          cd build
+          ctest -j$(nproc)
+
+      - name: "Upload Artifact"
+        uses: actions/upload-artifact@v2
+        with:
+          name: box64-${{ matrix.platform }}-${{ matrix.type }}
+          path: build/box64

.gitignore

@@ -59,3 +59,8 @@ build*/
 src/git_head.h
 backup/
 
+# LLVMprivateGenerator
+/LLVMprivateGenerator/*
+!/LLVMprivateGenerator/Makefile
+!/LLVMprivateGenerator/main.cpp
+!/LLVMprivateGenerator/registered_structs.cpp

.travis.yml

@@ -0,0 +1,24 @@
+language: c
+arch:
+  - amd64
+  - arm64-graviton2
+os: linux
+dist: focal
+
+compiler:
+    - gcc
+
+addons:
+  apt:
+    packages:
+      - python3
+
+      #Build steps
+before_script:
+    - mkdir build
+    - cd build
+    - if [ "$TRAVIS_CPU_ARCH" = "arm64" ]; then cmake .. -DRK3399=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo ; else cmake .. -DLD80BITS=1 -DNOALIGN=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo ; fi
+
+script:
+    - make
+    - ctest --output-on-failure

CHANGELOG.md

@@ -1,27 +0,0 @@
-v0.0.6
-======
-* Added Dynarec for ARM64
-* Many general CPU opcode added to the Dynarec
-* Many SSEx opcodes added to the Dynarec
-* Added a few more symbols in libc
-* A few changes to the "thread once" handling
-* New Logo and Icon from @grayduck
-
-v0.0.4
-======
-* Added a lot of opcodes
-* Added SDL1 and SDL2 wrapping
-* OpenGL/GLU wrapping done
-* libasound / libpulse wrapping done
-* libopenal / libalure / libalut wrapping done
-* Many X11 libs wrapped
-* Added "install" with binfmt integration
-* A few games are actualy starting now (old WorldOfGoo, Into The Breach, VVVVVV and Thimbeweed Park)
-
-v0.0.2
-======
-* Using box86 as a base, implemented most planned box64 part except dynarec
-* Wrapped a few libs
-* ELF loader a bit crude, but seems working
-* Signal handling implemented
-* MMX and x87 are sharing their registers

CMakeLists.txt

@@ -1,20 +1,58 @@
-cmake_minimum_required(VERSION 3.0)
+cmake_minimum_required(VERSION 3.4)
+
+cmake_policy(SET CMP0065 NEW)
+
+SET(CMAKE_C_FLAGS_DEBUG  "-O0 -g")
+SET(CMAKE_CXX_FLAGS_DEBUG  "-O0 -g")
 
 option(RPI4ARM64 "Set to ON if targeting an RaspberryPI4 device with multiarch arm64 and armhf" ${RPI4ARM64})
 option(RK3326 "Set to ON if targeting an Rockchip RK3326 based device" ${RK3326})
 option(RK3399 "Set to ON if targeting an Rockchip RK3399 based device" ${RK3399})
+option(ODROIDN2 "Set to ON if targeting an Odroid-N2 device" ${ODROIDN2})
+option(TEGRAX1 "Set to ON if targeting an Tegra X1 based device" ${TEGRAX1})
+option(PHYTIUM "Set to ON if targeting an Phytium (D2000 or FT2000/4) based device" ${PHYTIUM})
+option(SD845 "Set to ON if targeting a Snapragon 845 based device" ${SD845})
+option(M1 "Set to ON if targeting a AppleM1 running on Asahi computer" ${M1})
+option(LARCH64 "Set to ON if targeting an Loongarch64 based device" ${LARCH64})
+option(RV64 "Set to ON if targeting an RISCV RV64G based device" ${RV64})
+option(PPC64LE "Set to ON if targeting an PowerPC 64 LE based device" ${PPC64LE})
+option(LX2160A "Set to ON if targeting an LX2160A based device" ${LX2160A})
 option(USE_CCACHE "Set to ON to use ccache if present in the system" ${USE_CCACHE})
 option(HAVE_TRACE "Set to ON to have Trace ability (needs ZydisInfo library)" ${HAVE_TRACE})
-option(NOLOADADDR "Set to ON to avoid fixing the load address of Box64" ${NO_LOADAADR})
+option(NOLOADADDR "Set to ON to avoid fixing the load address of Box64" OFF)
 option(NOGIT "Set to ON if not building from a git clone repo (like when building from a zip download from github)" ${NOGIT})
-if(RK3399 OR RPI4ARM64 OR RK3326)
+if(LARCH64)
+    set(LD80BITS OFF CACHE BOOL "")
+    set(NOALIGN OFF CACHE BOOL "")
+    set(ARM_DYNAREC OFF CACHE BOOL "")
+endif()
+if(RV64)
+    set(LD80BITS OFF CACHE BOOL "")
+    set(NOALIGN OFF CACHE BOOL "")
+    set(ARM_DYNAREC OFF CACHE BOOL "")  
+    set(PAGE16K OFF CACHE BOOL "")
+endif()
+if(PPC64LE)
+    set(LD80BITS OFF CACHE BOOL "")
+    set(NOALIGN OFF CACHE BOOL "")
+    set(ARM_DYNAREC OFF CACHE BOOL "")
+    set(PAGE16K OFF CACHE BOOL "")
+endif()
+if(RK3399 OR ODROIDN2 OR RPI4ARM64 OR RK3326 OR TEGRAX1 OR PHYTIUM OR SD845 OR LX2160A OR M1)
     set(LD80BITS OFF CACHE BOOL "")
     set(NOALIGN OFF CACHE BOOL "")
     set(ARM_DYNAREC ON CACHE BOOL "")
 endif()
+if(RK3399 OR ODROIDN2 OR RPI4ARM64 OR RK3326 OR TEGRAX1 OR PHYTIUM OR SD845 OR LX2160A)
+    set(PAGE16K OFF CACHE BOOL "")
+endif()
+if(M1 OR LARCH64)
+    set(PAGE16K ON CACHE BOOL "")
+endif()
 option(LD80BITS "Set to ON if host device have 80bits long double (i.e. i386)" ${LD80BITS})
 option(NOALIGN "Set to ON if host device doesn't need re-align (i.e. i386)" ${NOALIGN})
 option(ARM_DYNAREC "Set to ON to use ARM Dynamic Recompilation" ${ARM_DYNAREC})
+option(PAGE16K "Set to ON if host device have PageSize of 16K (instead of 4K)" ${PAGE16K})
 
 if(${CMAKE_VERSION} VERSION_LESS "3.12.2")
     find_package(PythonInterp 3)
@@ -36,7 +74,7 @@ project(box64 C ASM)
 
 enable_testing()
 
-set(default_build_type "RelwithDebInfo")
+set(default_build_type "RelWithDebInfo")
 if(NOT CMAKE_BUILD_TYPE AND NOT CMAKE_CONFIGURATION_TYPES)
   message(STATUS "Setting build type to '${default_build_type}' as none was specified.")
   set(CMAKE_BUILD_TYPE "${default_build_type}" CACHE STRING "Choose the type of build." FORCE)
@@ -46,20 +84,56 @@ endif()
 if(RPI4ARM64)
     add_definitions(-DRPI)
     add_definitions(-DRPI4ARM64)
-    add_definitions(-pipe -march=armv8-a+crc -mtune=cortex-a72 -mfpu=neon-fp-armv8)
-    set(CMAKE_ASM_FLAGS  "-pipe -march=armv8-a+crc -mtune=cortex-a72 -mfpu=neon-fp-armv8")
-endif()
-
-if(RK3326)
+    add_definitions(-pipe -march=armv8-a+crc -mtune=cortex-a72)
+    set(CMAKE_ASM_FLAGS  "-pipe -march=armv8-a+crc -mtune=cortex-a72")
+elseif(RK3326)
     add_definitions(-DRK3326)
     add_definitions(-pipe -march=armv8-a+crc+simd+crypto -mcpu=cortex-a35+crypto)
     set(CMAKE_ASM_FLAGS  "-pipe -march=armv8-a+crc+simd+crypto -mcpu=cortex-a35+crypto")
-endif()
-
-if(RK3399)
+elseif(RK3399)
     add_definitions(-DRK3399)
     add_definitions(-pipe -march=armv8-a+crc+simd+crypto -mcpu=cortex-a72+crypto)
     set(CMAKE_ASM_FLAGS  "-pipe -march=armv8-a+crc+simd+crypto -mcpu=cortex-a72+crypto")
+elseif(ODROIDN2)
+    add_definitions(-DODROIDN2)
+    add_definitions(-march=armv8-a+crc+simd+crypto -mcpu=cortex-a73.cortex-a53+crypto)
+    set(CMAKE_ASM_FLAGS  "-pipe -march=armv8-a+crc+simd+crypto -mcpu=cortex-a73.cortex-a53+crypto")
+elseif(TEGRAX1)
+    add_definitions(-DTEGRAX1)
+    add_definitions(-pipe -march=armv8-a+crc+simd+crypto -mcpu=cortex-a57+crypto)
+    set(CMAKE_ASM_FLAGS  "-pipe -march=armv8-a+crc+simd+crypto -mcpu=cortex-a57+crypto")
+elseif(PHYTIUM)
+    add_definitions(-DPHYSIUM)
+    add_definitions(-pipe -march=armv8.1-a+crc+simd+crypto)
+    set(CMAKE_ASM_FLAGS  "-pipe -march=armv8.1-a+crc+simd+crypto+aes")
+elseif(SD845)
+    add_definitions(-DSD845)
+    add_definitions(-pipe -march=armv8.2-a+simd+crypto -mtune=cortex-a75.cortex-a55)
+    set(CMAKE_ASM_FLAGS  "-pipe -march=armv8.2-a+simd+crypto -mtune=cortex-a75.cortex-a55")
+elseif(M1)
+    add_definitions(-DM1)
+    add_definitions(-pipe -march=armv8.5-a+simd+crypto)
+    set(CMAKE_ASM_FLAGS  "-pipe -march=armv8.5-a+simd+crypto")
+elseif(LARCH64)
+    add_definitions(-DLA464)
+    add_definitions(-pipe -march=loongarch64)
+    set(CMAKE_ASM_FLAGS  "-pipe -march=loongarch64")
+elseif(RV64)
+    add_definitions(-DRV64)
+    add_definitions(-pipe -march=rv64g)
+    set(CMAKE_ASM_FLAGS  "-pipe -march=rv64g")
+elseif(PPC64LE)
+    add_definitions(-DPPC64LE)
+elseif(LX2160A)
+    add_definitions(-DLX2160A)
+    add_definitions(-pipe -march=armv8-a+crypto+crc -mcpu=cortex-a72+crypto)
+    set(CMAKE_ASM_FLAGS  "-pipe -march=armv8-a+crypto+crc -mcpu=cortex-a72+crypto")
+elseif(ARM_DYNAREC)
+    set(CMAKE_ASM_FLAGS  "-pipe -march=armv8-a+crc+simd+crypto")
+endif()
+
+if(PAGE16K)
+    add_definitions(-DPAGE16K)
 endif()
 
 if(NOGIT)
@@ -67,12 +141,13 @@ if(NOGIT)
 endif()
 
 if(HAVE_TRACE)
-    set(BOX64 box64t)
+    set(BOX64 box64)
 else()
     set(BOX64 box64)
 endif()
 
-set(BOX64_ELF_ADDRESS "0x500062800000")  #random load address...
+#set(BOX64_ELF_ADDRESS "0x500062800000")  #random load address...
+set(BOX64_ELF_ADDRESS "0x64800000")  #low address
 
 if(LD80BITS)
     add_definitions(-DHAVE_LD80BITS)
@@ -90,6 +165,10 @@ if(ARM_DYNAREC)
     add_definitions(-DDYNAREC)
     add_definitions(-DARM64)
     enable_language(ASM)
+    include_directories("${BOX64_ROOT}/src/dynarec/arm64")
+    set(DYNAREC ON)
+else()
+    set(DYNAREC OFF)
 endif()
 
 set(BOX64_ROOT ${CMAKE_SOURCE_DIR})
@@ -101,6 +180,8 @@ if(USE_CCACHE)
     if(CCACHE_FOUND)
         set_property(GLOBAL PROPERTY RULE_LAUNCH_COMPILE ccache)
         set_property(GLOBAL PROPERTY RULE_LAUNCH_LINK ccache)
+    else()
+        message(SEND_ERROR "ccache not found!")
     endif()
 endif()
 
@@ -121,7 +202,9 @@ set(ELFLOADER_SRC
     "${BOX64_ROOT}/src/box64context.c"
     "${BOX64_ROOT}/src/build_info.c"
     "${BOX64_ROOT}/src/custommem.c"
+    "${BOX64_ROOT}/src/steam.c"
     "${BOX64_ROOT}/src/dynarec/dynarec.c"
+    "${BOX64_ROOT}/src/elfs/elfdwarf_private.c"
     "${BOX64_ROOT}/src/elfs/elfloader.c"
     "${BOX64_ROOT}/src/elfs/elfparser.c"
     "${BOX64_ROOT}/src/elfs/elfload_dump.c"
@@ -137,6 +220,7 @@ set(ELFLOADER_SRC
     "${BOX64_ROOT}/src/emu/x64run6664.c"
     "${BOX64_ROOT}/src/emu/x64run66d9.c"
     "${BOX64_ROOT}/src/emu/x64run66dd.c"
+    "${BOX64_ROOT}/src/emu/x64run66f0.c"
     "${BOX64_ROOT}/src/emu/x64run67.c"
     "${BOX64_ROOT}/src/emu/x64run670f.c"
     "${BOX64_ROOT}/src/emu/x64run6766.c"
@@ -158,7 +242,11 @@ set(ELFLOADER_SRC
     "${BOX64_ROOT}/src/emu/x64trace.c"
     "${BOX64_ROOT}/src/librarian/librarian.c"
     "${BOX64_ROOT}/src/librarian/library.c"
+    "${BOX64_ROOT}/src/librarian/dictionnary.c"
+    "${BOX64_ROOT}/src/librarian/globalsymbols.c"
+    "${BOX64_ROOT}/src/librarian/symbols.c"
     "${BOX64_ROOT}/src/libtools/auxval.c"
+    "${BOX64_ROOT}/src/libtools/obstack.c"
     "${BOX64_ROOT}/src/libtools/myalign.c"
     "${BOX64_ROOT}/src/libtools/sdl1rwops.c"
     "${BOX64_ROOT}/src/libtools/sdl2rwops.c"
@@ -168,6 +256,7 @@ set(ELFLOADER_SRC
     "${BOX64_ROOT}/src/tools/bridge.c"
     "${BOX64_ROOT}/src/tools/callback.c"
     "${BOX64_ROOT}/src/tools/my_cpuid.c"
+    "${BOX64_ROOT}/src/tools/gtkclass.c"
     "${BOX64_ROOT}/src/tools/pathcoll.c"
     "${BOX64_ROOT}/src/tools/fileutils.c"
     "${BOX64_ROOT}/src/tools/wine_tools.c"
@@ -177,42 +266,96 @@ set(ELFLOADER_SRC
 set(WRAPPEDS
     "${BOX64_ROOT}/src/wrapped/wrappedalure.c"
     "${BOX64_ROOT}/src/wrapped/wrappedalut.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedatk.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedatkbridge.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedatspi.c"
     "${BOX64_ROOT}/src/wrapped/wrappedbz2.c"
     "${BOX64_ROOT}/src/wrapped/wrappedcairo.c"
     "${BOX64_ROOT}/src/wrapped/wrappedcrashhandler.c"
     "${BOX64_ROOT}/src/wrapped/wrappedcrypto.c"
     "${BOX64_ROOT}/src/wrapped/wrappedcurl.c"
     "${BOX64_ROOT}/src/wrapped/wrappeddbus.c"
+    "${BOX64_ROOT}/src/wrapped/wrappeddbusglib1.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedexpat.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedfaudio.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedflac.c"
     "${BOX64_ROOT}/src/wrapped/wrappedfontconfig.c"
     "${BOX64_ROOT}/src/wrapped/wrappedfreetype.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgbm.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgconf2.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgdkpixbuf2.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgdkx112.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgio2.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedglib2.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgmodule2.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgmp.c"
     "${BOX64_ROOT}/src/wrapped/wrappedgnutls.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgobject2.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgssapi.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgssapikrb5.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgstapp.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgstaudio.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgstbase.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgstreamer.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgsttag.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgstvideo.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgthread2.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedgtkx112.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedkrb5.c"
     "${BOX64_ROOT}/src/wrapped/wrappedldlinux.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibasound.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibc.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibcrypt.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibcups.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibdl.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibdrm.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibform.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibformw.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibfuse.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibgl.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibglu.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibice.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibm.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibncurses.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibncurses6.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibncursesw.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibncursesw6.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibogg.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibpanel.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibpci.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibpcre.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibpthread.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibresolv.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibrt.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibsm.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibsndfile.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibssl.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibtinfo.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibtinfo6.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibusb1.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibuuid.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibvorbis.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibx11.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibx11xcb.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibxau.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibxcb.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibxcbdri2.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibxcbdri3.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibxcbglx.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibxcbkeysyms.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibxcbimage.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibxcbrandr.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibxcbshape.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibxcbshm.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibxcbxfixes.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibxcbxtest.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibxcomposite.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibxcursor.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibxdamage.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibxdmcp.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibxext.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibxfixes.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlibxft.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibxi.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibxmu.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibxpm.c"
@@ -224,28 +367,50 @@ set(WRAPPEDS
     "${BOX64_ROOT}/src/wrapped/wrappedlibxxf86vm.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlibz.c"
     "${BOX64_ROOT}/src/wrapped/wrappedlzma.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedmpg123.c"
+    "${BOX64_ROOT}/src/wrapped/wrappednsl.c"
+    "${BOX64_ROOT}/src/wrapped/wrappednspr4.c"
+    "${BOX64_ROOT}/src/wrapped/wrappednss3.c"
+    "${BOX64_ROOT}/src/wrapped/wrappednssutil3.c"
     "${BOX64_ROOT}/src/wrapped/wrappedopenal.c"
     "${BOX64_ROOT}/src/wrapped/wrappedpango.c"
     "${BOX64_ROOT}/src/wrapped/wrappedpangocairo.c"
     "${BOX64_ROOT}/src/wrapped/wrappedpangoft2.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedplc4.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedplds4.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedpng16.c"
     "${BOX64_ROOT}/src/wrapped/wrappedpulse.c"
     "${BOX64_ROOT}/src/wrapped/wrappedpulsesimple.c"
     "${BOX64_ROOT}/src/wrapped/wrappedsdl1.c"
     "${BOX64_ROOT}/src/wrapped/wrappedsdl1image.c"
     "${BOX64_ROOT}/src/wrapped/wrappedsdl1mixer.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedsdl1net.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedsdl1sound.c"
     "${BOX64_ROOT}/src/wrapped/wrappedsdl1ttf.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedsecret1.c"
     "${BOX64_ROOT}/src/wrapped/wrappedsmpeg.c"
     "${BOX64_ROOT}/src/wrapped/wrappedsdl2.c"
     "${BOX64_ROOT}/src/wrapped/wrappedsdl2image.c"
     "${BOX64_ROOT}/src/wrapped/wrappedsdl2mixer.c"
     "${BOX64_ROOT}/src/wrapped/wrappedsdl2net.c"
     "${BOX64_ROOT}/src/wrapped/wrappedsdl2ttf.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedselinux.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedsmime3.c"
     "${BOX64_ROOT}/src/wrapped/wrappedsmpeg2.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedssl3.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedtcmallocminimal.c"
     "${BOX64_ROOT}/src/wrapped/wrappedudev0.c"
     "${BOX64_ROOT}/src/wrapped/wrappedudev1.c"
     "${BOX64_ROOT}/src/wrapped/wrappedutil.c"
     "${BOX64_ROOT}/src/wrapped/wrappedvorbisfile.c"
     "${BOX64_ROOT}/src/wrapped/wrappedxinerama.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedxkbcommon.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedxkbcommonx11.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedxml2.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedxslt.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedldapr.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedlber.c"
+    "${BOX64_ROOT}/src/wrapped/wrappedvulkan.c"
 )
 
 #set(WRAPPEDS_HEAD "${BOX64_ROOT}/src/wrapped/wrappedd3dadapter9_gen.h")
@@ -259,9 +424,9 @@ set(WRAPPER "${BOX64_ROOT}/src/wrapped/generated/wrapper.c" "${BOX64_ROOT}/src/w
 
 add_custom_command(
     OUTPUT "${BOX64_ROOT}/src/wrapped/generated/functions_list.txt"
-    COMMAND "${PYTHON_EXECUTABLE}" "${BOX64_ROOT}/rebuild_wrappers.py" 
-    "${BOX64_ROOT}" 
-    "PANDORA" "HAVE_LD80BITS" "NOALIGN" "HAVE_TRACE" "--" 
+    COMMAND "${PYTHON_EXECUTABLE}" "${BOX64_ROOT}/rebuild_wrappers.py"
+    "${BOX64_ROOT}"
+    "PANDORA" "HAVE_LD80BITS" "NOALIGN" "HAVE_TRACE" "--"
     ${WRAPPEDS_HEAD}
     MAIN_DEPENDENCY "${BOX64_ROOT}/rebuild_wrappers.py"
     DEPENDS ${WRAPPEDS} ${WRAPPEDS_HEAD}
@@ -279,77 +444,87 @@ add_custom_command(
 add_custom_target(WRAPPERS DEPENDS "${BOX64_ROOT}/src/wrapped/generated/functions_list.txt")
 #add_custom_target(PRINTER DEPENDS "${BOX64_ROOT}/src/dynarec/last_run.txt")
 
-if(ARM_DYNAREC)
+if(DYNAREC)
     set(DYNAREC_SRC
         "${BOX64_ROOT}/src/dynarec/dynablock.c"
+        "${BOX64_ROOT}/src/dynarec/dynarec_native.c"
+    )
+endif()
 
-        "${BOX64_ROOT}/src/dynarec/dynarec_arm64.c"
-        "${BOX64_ROOT}/src/dynarec/dynarec_arm64_functions.c"
-        "${BOX64_ROOT}/src/dynarec/arm64_printer.c"
+if(ARM_DYNAREC)
+    set(DYNAREC_SRC
+        ${DYNAREC_SRC}
 
-        "${BOX64_ROOT}/src/dynarec/arm64_prolog.S"
-        "${BOX64_ROOT}/src/dynarec/arm64_epilog.S"
-        "${BOX64_ROOT}/src/dynarec/arm64_next.S"
-        "${BOX64_ROOT}/src/dynarec/arm64_lock.S"
+        "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_functions.c"
+        "${BOX64_ROOT}/src/dynarec/arm64/arm64_printer.c"
+
+        "${BOX64_ROOT}/src/dynarec/arm64/arm64_prolog.S"
+        "${BOX64_ROOT}/src/dynarec/arm64/arm64_epilog.S"
+        "${BOX64_ROOT}/src/dynarec/arm64/arm64_next.S"
+        "${BOX64_ROOT}/src/dynarec/arm64/arm64_lock.S"
     )
 
     set(DYNAREC_PASS
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_helper.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_emit_tests.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_emit_math.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_emit_logic.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_emit_shift.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_pass.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_00.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_0f.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_64.c"
-    #"${BOX64_ROOT}/src/dynarec/dynarec_arm64_65.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_66.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_67.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_d8.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_d9.c"
-    #"${BOX64_ROOT}/src/dynarec/dynarec_arm64_da.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_db.c"
-    #"${BOX64_ROOT}/src/dynarec/dynarec_arm64_dc.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_dd.c"
-    #"${BOX64_ROOT}/src/dynarec/dynarec_arm64_de.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_df.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_f0.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_660f.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_6664.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_f20f.c"
-    "${BOX64_ROOT}/src/dynarec/dynarec_arm64_f30f.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_helper.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_emit_tests.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_emit_math.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_emit_logic.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_emit_shift.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_00.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_0f.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_64.c"
+    #"${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_65.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_66.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_67.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_d8.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_d9.c"
+    #"${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_da.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_db.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_dc.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_dd.c"
+    #"${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_de.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_df.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_f0.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_660f.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_6664.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_f20f.c"
+    "${BOX64_ROOT}/src/dynarec/arm64/dynarec_arm64_f30f.c"
+    )
+endif()
+
+if(DYNAREC)
+    set(DYNAREC_PASS 
+        "${BOX64_ROOT}/src/wrapped/generated/wrapper.h" 
+        ${DYNAREC_PASS}
+        "${BOX64_ROOT}/src/dynarec/dynarec_native_pass.c"
     )
 
-    set(DYNAREC_PASS "${BOX64_ROOT}/src/wrapped/generated/wrapper.h" ${DYNAREC_PASS})
+    add_library(dynarec_native OBJECT ${DYNAREC_SRC})
 
-    add_library(dynarec_arm OBJECT ${DYNAREC_SRC})
+    add_library(native_pass0 OBJECT ${DYNAREC_PASS})
+    set_target_properties(native_pass0 PROPERTIES COMPILE_FLAGS "-DSTEP=0")
+    add_library(native_pass1 OBJECT ${DYNAREC_PASS})
+    set_target_properties(native_pass1 PROPERTIES COMPILE_FLAGS "-DSTEP=1")
+    add_library(native_pass2 OBJECT ${DYNAREC_PASS})
+    set_target_properties(native_pass2 PROPERTIES COMPILE_FLAGS "-DSTEP=2")
+    add_library(native_pass3 OBJECT ${DYNAREC_PASS})
+    set_target_properties(native_pass3 PROPERTIES COMPILE_FLAGS "-DSTEP=3")
+    add_dependencies(native_pass0 WRAPPERS)
+    add_dependencies(native_pass1 WRAPPERS)
+    add_dependencies(native_pass2 WRAPPERS)
+    add_dependencies(native_pass3 WRAPPERS)
 
-    add_library(arm64_pass0 OBJECT ${DYNAREC_PASS})
-    set_target_properties(arm64_pass0 PROPERTIES COMPILE_FLAGS "-DSTEP=0")
-    add_library(arm64_pass1 OBJECT ${DYNAREC_PASS})
-    set_target_properties(arm64_pass1 PROPERTIES COMPILE_FLAGS "-DSTEP=1")
-    add_library(arm64_pass2 OBJECT ${DYNAREC_PASS})
-    set_target_properties(arm64_pass2 PROPERTIES COMPILE_FLAGS "-DSTEP=2")
-    add_library(arm64_pass3 OBJECT ${DYNAREC_PASS})
-    set_target_properties(arm64_pass3 PROPERTIES COMPILE_FLAGS "-DSTEP=3")
-    add_dependencies(arm64_pass0 WRAPPERS)
-    add_dependencies(arm64_pass1 WRAPPERS)
-    add_dependencies(arm64_pass2 WRAPPERS)
-    add_dependencies(arm64_pass3 WRAPPERS)
-
-    add_library(dynarec STATIC 
-        $<TARGET_OBJECTS:dynarec_arm> 
-        $<TARGET_OBJECTS:arm64_pass0> 
-        $<TARGET_OBJECTS:arm64_pass1>
-        $<TARGET_OBJECTS:arm64_pass2>
-        $<TARGET_OBJECTS:arm64_pass3>
+    add_library(dynarec STATIC
+        $<TARGET_OBJECTS:dynarec_native>
+        $<TARGET_OBJECTS:native_pass0>
+        $<TARGET_OBJECTS:native_pass1>
+        $<TARGET_OBJECTS:native_pass2>
+        $<TARGET_OBJECTS:native_pass3>
     )
-
 endif()
 
 # creates git_head.h
-if(ARM_DYNAREC)
+if(DYNAREC)
     add_custom_command(
         OUTPUT "${BOX64_ROOT}/src/git_head.h"
         COMMAND bash -c "echo \\\#define GITREV \\\"$(git rev-parse --short HEAD)\\\">\"${BOX64_ROOT}/src/git_head.h\""
@@ -364,28 +539,41 @@ else()
 endif()
 
 add_executable(${BOX64} ${ELFLOADER_SRC} ${WRAPPEDS} "${BOX64_ROOT}/src/git_head.h")
+set_target_properties(${BOX64} PROPERTIES ENABLE_EXPORTS ON)
 add_dependencies(${BOX64} WRAPPERS)
 #add_dependencies(${BOX64} PRINTER)
-target_link_libraries(${BOX64} m dl rt pthread)
-if(ARM_DYNAREC)
+#target_link_libraries(${BOX64} c m dl rt pthread resolv)
+set_target_properties(${BOX64} PROPERTIES LINK_FLAGS "-Wl,--no-as-needed -lc -lm -ldl -lrt -lpthread -lresolv -Wl,--as-needed -pthread")
+if(DYNAREC)
     target_link_libraries(${BOX64} dynarec)
 endif()
 
 if(${CMAKE_VERSION} VERSION_LESS "3.13")
     if(NOT NOLOADADDR)
-        set_target_properties(${BOX64} PROPERTIES LINK_FLAGS "-rdynamic -Wl,-Ttext-segment,${BOX64_ELF_ADDRESS}")
-    else()
-        set_target_properties(${BOX64} PROPERTIES LINK_FLAGS "-rdynamic")
+        if(CMAKE_C_COMPILER_ID STREQUAL "Clang")
+            set_target_properties(${BOX64} PROPERTIES LINK_FLAGS "-Wl,--image-base=${BOX64_ELF_ADDRESS}")
+        else()
+            set_target_properties(${BOX64} PROPERTIES LINK_FLAGS "-Wl,-Ttext-segment,${BOX64_ELF_ADDRESS}")
+        endif()
     endif()
 else()
-    target_link_options(${BOX64} PUBLIC -rdynamic)
+    # If symbols are missing, try this: target_link_options(${BOX64} PUBLIC -rdynamic)
     if(NOT NOLOADADDR)
-        target_link_options(${BOX64} PUBLIC -Wl,-Ttext-segment,${BOX64_ELF_ADDRESS})
+        if(CMAKE_C_COMPILER_ID STREQUAL "Clang")
+            target_link_options(${BOX64} PUBLIC LINKER:--image-base=${BOX64_ELF_ADDRESS})
+        else()
+            target_link_options(${BOX64} PUBLIC LINKER:-Ttext-segment,${BOX64_ELF_ADDRESS})
+        endif()
     endif()
 endif()
 
 string(COMPARE EQUAL "${CMAKE_HOST_SYSTEM_PROCESSOR}" "i686"  _x86)
 string(COMPARE EQUAL "${CMAKE_HOST_SYSTEM_PROCESSOR}" "x86_64"  _x86_64)
+string(COMPARE EQUAL "${CMAKE_HOST_SYSTEM_PROCESSOR}" "aarch64"  _aarch64)
+
+if(_x86_64 OR _aarch64)
+  add_definitions(-DCONFIG_64BIT)
+endif()
 
 if(NOT _x86 AND NOT _x86_64)
   install(TARGETS ${BOX64}
@@ -394,6 +582,7 @@ if(NOT _x86 AND NOT _x86_64)
   install(FILES ${CMAKE_BINARY_DIR}/system/box64.conf DESTINATION /etc/binfmt.d/)
   install(FILES ${CMAKE_SOURCE_DIR}/x64lib/libstdc++.so.6 DESTINATION /usr/lib/x86_64-linux-gnu/)
   install(FILES ${CMAKE_SOURCE_DIR}/x64lib/libgcc_s.so.1 DESTINATION /usr/lib/x86_64-linux-gnu/)
+  install(FILES ${CMAKE_SOURCE_DIR}/x64lib/libpng12.so.0 DESTINATION /usr/lib/x86_64-linux-gnu/)
 endif()
 
 if(NOT TARGET uninstall)
@@ -406,86 +595,138 @@ if(NOT TARGET uninstall)
         COMMAND ${CMAKE_COMMAND} -P ${CMAKE_CURRENT_BINARY_DIR}/cmake_uninstall.cmake)
 endif()
 
-add_test(test01 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64} 
-    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test01 -D TEST_OUTPUT=tmpfile.txt 
+set(CPACK_GENERATOR "DEB")
+set(CPACK_DEBIAN_PACKAGE_MAINTAINER "ptitSeb")
+set(CPACK_PACKAGE_CONTACT "[email protected]")
+set(CPACK_PACKAGE_DESCRIPTION "Box64 - Linux Userspace x86_64 Emulator with a twist")
+set(CPACK_DEBIAN_PACKAGE_DEPENDS "libc6")
+set(CPACK_PACKAGE_HOMEPAGE_URL, "https://box86.org")
+file(STRINGS "${BOX64_ROOT}/src/box64version.h" TEMP_STRING REGEX "BOX64_MAJOR\\s*")
+string(REGEX REPLACE "BOX64_MAJOR" "" TEMP_STRING ${TEMP_STRING})
+string(REGEX MATCH "[0-9]" BOX64_MAJOR ${TEMP_STRING})
+file(STRINGS "${BOX64_ROOT}/src/box64version.h" TEMP_STRING REGEX "BOX64_MINOR\\s*")
+string(REGEX REPLACE "BOX64_MINOR" "" TEMP_STRING ${TEMP_STRING})
+string(REGEX MATCH "[0-9]" BOX64_MINOR ${TEMP_STRING})
+file(STRINGS "${BOX64_ROOT}/src/box64version.h" TEMP_STRING REGEX "BOX64_REVISION\\s*")
+string(REGEX REPLACE "BOX64_REVISION" "" TEMP_STRING ${TEMP_STRING})
+string(REGEX MATCH "[0-9]" BOX64_REVISION ${TEMP_STRING})
+set(CPACK_PACKAGE_VERSION_MAJOR ${BOX64_MAJOR})
+set(CPACK_PACKAGE_VERSION_MINOR ${BOX64_MINOR})
+set(CPACK_PACKAGE_VERSION_PATCH ${BOX64_REVISION})
+set(CPACK_DEBIAN_PACKAGE_CONTROL_EXTRA "${CMAKE_CURRENT_SOURCE_DIR}/postinst")
+if(_aarch64)
+    set(CPACK_DEBIAN_PACKAGE_ARCHITECTURE "arm64")
+elseif(_x86_64)
+    set(CPACK_DEBIAN_PACKAGE_ARCHITECTURE "x86_64")
+else()
+    #probably wrong...
+    execute_process(COMMAND "dpkg --print-architecture" OUTPUT_VARIABLE CPACK_DEBIAN_PACKAGE_ARCHITECTURE)
+endif()
+set(CPACK_DEBIAN_FILE_NAME "${BOX64}-${BOX64_MAJOR}.${BOX64_MINOR}.${BOX64_REVISION}_Linux-${CPACK_DEBIAN_PACKAGE_ARCHITECTURE}.deb")
+INCLUDE(CPack)
+
+add_test(test01 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test01 -D TEST_OUTPUT=tmpfile01.txt
     -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref01.txt
     -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
 
-add_test(test02 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64} 
-    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test02 -D TEST_OUTPUT=tmpfile.txt 
+add_test(test02 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test02 -D TEST_OUTPUT=tmpfile02.txt
     -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref02.txt
     -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
 
-add_test(test03 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64} 
-    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test03 -D TEST_OUTPUT=tmpfile.txt 
+add_test(test03 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test03 -D TEST_OUTPUT=tmpfile03.txt
     -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref03.txt
     -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
 
-add_test(test04 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64} 
-    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test04 -D TEST_ARGS2=yeah -D TEST_OUTPUT=tmpfile.txt 
+add_test(test04 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test04 -D TEST_ARGS2=yeah -D TEST_OUTPUT=tmpfile04.txt
     -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref04.txt
     -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
 
-add_test(test05 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64} 
-    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test05 -D TEST_ARGS2=7 -D TEST_OUTPUT=tmpfile.txt 
+add_test(test05 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test05 -D TEST_ARGS2=7 -D TEST_OUTPUT=tmpfile05.txt
     -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref05.txt
     -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
 
-add_test(test06 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64} 
-    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test06 -D TEST_OUTPUT=tmpfile.txt 
+add_test(test06 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test06 -D TEST_OUTPUT=tmpfile06.txt
     -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref06.txt
     -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
 
-add_test(test07 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64} 
-    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test07 -D TEST_OUTPUT=tmpfile.txt 
+add_test(test07 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test07 -D TEST_OUTPUT=tmpfile07.txt
     -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref07.txt
     -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
 
-add_test(test08 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64} 
-    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test08 -D TEST_OUTPUT=tmpfile.txt 
+add_test(test08 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test08 -D TEST_OUTPUT=tmpfile08.txt
     -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref08.txt
     -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
 
-add_test(test09 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64} 
-    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test09 -D TEST_OUTPUT=tmpfile.txt 
+add_test(test09 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test09 -D TEST_OUTPUT=tmpfile09.txt
     -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref09.txt
     -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
 
-add_test(test10 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64} 
-    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test10 -D TEST_OUTPUT=tmpfile.txt 
+add_test(test10 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test10 -D TEST_OUTPUT=tmpfile10.txt
     -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref10.txt
     -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
 
-add_test(test11 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64} 
-    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test11 -D TEST_OUTPUT=tmpfile.txt 
+add_test(test11 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test11 -D TEST_OUTPUT=tmpfile11.txt
     -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref11.txt
     -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
 
-add_test(test12 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64} 
-    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test12 -D TEST_OUTPUT=tmpfile.txt 
+add_test(test12 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test12 -D TEST_OUTPUT=tmpfile12.txt
     -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref12.txt
     -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
 
-add_test(test13 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64} 
-    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test13 -D TEST_OUTPUT=tmpfile.txt 
+add_test(test13 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test13 -D TEST_OUTPUT=tmpfile13.txt
     -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref13.txt
     -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
 
-#add_test(test14 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64} 
-#    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test14 -D TEST_OUTPUT=tmpfile.txt 
+#add_test(test14 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+#    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test14 -D TEST_OUTPUT=tmpfile14.txt
 #    -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref14.txt
 #    -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
 
-add_test(test15 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64} 
-    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test15 -D TEST_OUTPUT=tmpfile.txt 
+add_test(test15 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test15 -D TEST_OUTPUT=tmpfile15.txt
     -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref15.txt
     -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
 
+add_test(test16 ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test16 -D TEST_OUTPUT=tmpfile16.txt
+    -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref16.txt
+    -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
+
+add_test(sse ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test17 -D TEST_OUTPUT=tmpfile17.txt
+    -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref17.txt
+    -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
+
+set_tests_properties(sse PROPERTIES ENVIRONMENT "BOX64_DYNAREC_FASTNAN=0")
+    
+add_test(aes ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test18 -D TEST_OUTPUT=tmpfile18.txt
+    -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref18.txt
+    -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
+
+add_test(backtrace ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
+    -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/test19 -D TEST_OUTPUT=tmpfile19.txt
+    -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/ref19.txt
+    -P ${CMAKE_SOURCE_DIR}/runTest.cmake )
+
 file(GLOB extension_tests "${CMAKE_SOURCE_DIR}/tests/extensions/*.c")
 foreach(file ${extension_tests})
     get_filename_component(testname "${file}" NAME_WE)
     add_test(NAME "${testname}" COMMAND ${CMAKE_COMMAND} -D TEST_PROGRAM=${CMAKE_BINARY_DIR}/${BOX64}
-        -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/extensions/${testname} -D TEST_OUTPUT=tmpfile.txt
+        -D TEST_ARGS=${CMAKE_SOURCE_DIR}/tests/extensions/${testname} -D TEST_OUTPUT=tmpfile-${testname}.txt
         -D TEST_REFERENCE=${CMAKE_SOURCE_DIR}/tests/extensions/${testname}.txt
         -P ${CMAKE_SOURCE_DIR}/runTest.cmake)
 endforeach()

COMPILE.md

@@ -1,75 +0,0 @@
-Compiling
-----
-#### for RK3399
-
-Using a 64bits OS:
-```
-git clone https://github.com/ptitSeb/box64
-cd box64
-mkdir build; cd build; cmake .. -DRK3399=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
-make -j4
-sudo make install
-```
-If it's the first install, you also need:
-```
-sudo systemctl restart systemd-binfmt
-```
-
-#### for PI4
-
-Warning, you need a 64bits OS:
-
-```
-git clone https://github.com/ptitSeb/box64
-cd box64
-mkdir build; cd build; cmake .. -DRPI4ARM64=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
-make -j4
-sudo make install
-```
-If it's the first install, you also need:
-```
-sudo systemctl restart systemd-binfmt
-```
-
-#### for Other ARM64 Linux platforms
-
- `mkdir build; cd build; cmake .. -DARM_DYNAREC=ON -DCMAKE_BUILD_TYPE=RelWithDebInfo; make -j$(nproc)`
-
-#### for x86_64 Linux
-
- `mkdir build; cd build; cmake .. -DLD80BITS=1 -DNOALIGN=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo; make -j$(nproc)`
-
-#### use ccmake
-
-Alternatively, you can use the curses-bases ccmake (or any other gui frontend for cmake) to select wich platform to use interactively.
-
-#### Customize your build
-
-*use ccache if you have it* 
-
-Add `-DUSE_CCACHE=1` if you have ccache (it's better if you plan to touch the sources)
-
-*have some debug info* 
-
-The `-DCMAKE_BUILD_TYPE=RelWithDebInfo` argument makes a build that is both optimized for speed, and has debug information embedded. That way, if you have a crash or try to analyse performance, you'll have some symbols.
-
-*to have a Trace Enabled build* 
-
-To have a trace enabled build ( ***it will be slower***), add `-DHAVE_TRACE=1` but you will need, at runtime, to have the [Zydis library](https://github.com/zyantific/zydis) library in your `LD_LIBRARY_PATH` or in the system library folders.
-
-*to have ARM Dynarec*
-
-The Dynarec is only available on the ARM architecture(Right now, anyways.). Notes also that VFPv3 and NEON are required for the Dynarec. Activate it by using `-DARM_DYNAREC=1`. Also, be sure to use `-marm` in compilation flags (because many compileur use Thumb as default, and the dynarec will not work in this mode).
-
-*not building from a git clone*
-
-If you are not building from a git clone (for example, downloading a release source zipped from github), you need to activate `-DNOGIT=1` from cmake to be able to build (normal process include git sha1 of HEAD in the version that box64 print).
-
-----
-
-Testing
-----
-A few tests are included.
-They can be launched with `ctest`
-They are very basic and don't test much for now.
-

LLVMprivateGenerator/Makefile

@@ -0,0 +1,12 @@
+all: dumpSigs
+
+dumpSigs: main.o registered_structs.o
+	g++ -g3 -std=gnu++17 -fno-rtti main.o registered_structs.o -o dumpSigs "-L$(LLVM_install_dir)/lib" -lclang-cpp -lclangTooling -Wl,-rpath "-Wl,$(LLVM_install_dir)/lib"
+
+main.o: main.cpp
+	g++ -g3 -std=gnu++17 -fno-rtti -c main.cpp -Wfatal-errors "-I$(LLVM_install_dir)/include" -o main.o
+registered_structs.o: registered_structs.cpp
+	g++ -g3 -std=gnu++17 -fno-rtti -c registered_structs.cpp -Wfatal-errors -o registered_structs.o
+
+clean:
+	$(RM) dumpSigs main.o registered_structs.o

LLVMprivateGenerator/main.cpp

@@ -0,0 +1,458 @@
+#include <algorithm>
+#include <fstream>
+#include <iostream>
+#include <numeric>
+#include <unordered_map>
+#include <utility>
+#include <vector>
+
+#include <llvm/Support/raw_ostream.h>
+#include <clang/AST/ASTConsumer.h>
+#include <clang/AST/Decl.h>
+#include <clang/AST/Mangle.h>
+#include <clang/AST/PrettyPrinter.h>
+#include <clang/AST/RecursiveASTVisitor.h>
+#include <clang/Frontend/CompilerInstance.h>
+#include <clang/Frontend/FrontendActions.h>
+#include <clang/Tooling/CommonOptionsParser.h>
+#include <clang/Tooling/Tooling.h>
+
+clang::MangleContext *mangler = nullptr;
+
+std::unordered_map<std::string, std::pair<std::string, bool>> funMap;
+std::vector<std::string> funList;
+
+bool isTypeTrivial(const clang::QualType &q, const clang::QualType *qorig);
+clang::QualType getPointedType(const clang::QualType q) {
+	if (const clang::PointerType *p = q->getAs<clang::PointerType>())
+		return getPointedType(p->getPointeeType());
+	else if (const clang::ReferenceType *r = q->getAs<clang::ReferenceType>())
+		return getPointedType(r->getPointeeType());
+	else
+		return q;
+}
+
+std::string record2name(const clang::RecordDecl &q, const clang::QualType *qorig) {
+	std::string s = q.getNameAsString();
+	if (s == "") {
+		if (!qorig) return "????.!";
+		if (const clang::TypedefType *tt = (*qorig)->getAs<clang::TypedefType>()) {
+			// Typedef
+			if (clang::TypedefNameDecl *td = tt->getDecl()) {
+				return td->getNameAsString();
+			} else {
+				return "<typedef with no declaration>";
+			}
+		} else {
+			return std::string("<unknown type ") + (*qorig)->getTypeClassName() + ">";
+		}
+	} else {
+		return s;
+	}
+}
+
+char ptr2char(const std::string &str) __attribute__((const));
+const char *ptr2str(const std::string &str) __attribute__((const));
+char type2char(const clang::QualType &qual /* Canonical */, const clang::QualType *qorig) {
+	if (qual->isBuiltinType()) {
+		switch (static_cast<const clang::BuiltinType&>(*qual).getKind()) {
+		case clang::BuiltinType::Kind::Void:
+			return 'v';
+		case clang::BuiltinType::Kind::Bool:
+			return 'i';
+		case clang::BuiltinType::Kind::Char_U:
+			return 'C';
+		case clang::BuiltinType::Kind::Char_S:
+			return 'c';
+		case clang::BuiltinType::Kind::Char8:
+			return 'c';
+		case clang::BuiltinType::Kind::UChar:
+			return 'C';
+		case clang::BuiltinType::Kind::SChar:
+			return 'c';
+		case clang::BuiltinType::Kind::WChar_U:
+			return 'W';
+		case clang::BuiltinType::Kind::UShort:
+			return 'W';
+		case clang::BuiltinType::Kind::WChar_S:
+			return 'w';
+		case clang::BuiltinType::Kind::Char16:
+			return 'w';
+		case clang::BuiltinType::Kind::Short:
+			return 'w';
+		case clang::BuiltinType::Kind::UInt:
+			return 'u';
+		case clang::BuiltinType::Kind::Char32:
+			return 'i';
+		case clang::BuiltinType::Kind::Int:
+			return 'i';
+		case clang::BuiltinType::Kind::ULong:
+			return 'L';
+		case clang::BuiltinType::Kind::Long:
+			return 'l';
+		case clang::BuiltinType::Kind::ULongLong:
+			return 'U';
+		case clang::BuiltinType::Kind::LongLong:
+			return 'I';
+		case clang::BuiltinType::Kind::UInt128:
+			return 'H';
+		case clang::BuiltinType::Kind::Int128:
+			return 'H';
+		case clang::BuiltinType::Kind::Float:
+			return 'f';
+		case clang::BuiltinType::Kind::Double:
+			return 'd';
+		case clang::BuiltinType::Kind::LongDouble:
+			return 'D';
+		case clang::BuiltinType::Kind::NullPtr:
+			return 'p'; // nullptr_t
+		
+		case clang::BuiltinType::Kind::Half:
+		case clang::BuiltinType::Kind::BFloat16:
+		case clang::BuiltinType::Kind::ShortAccum:
+		case clang::BuiltinType::Kind::Accum:
+		case clang::BuiltinType::Kind::LongAccum:
+		case clang::BuiltinType::Kind::UShortAccum:
+		case clang::BuiltinType::Kind::UAccum:
+		case clang::BuiltinType::Kind::ULongAccum:
+		case clang::BuiltinType::Kind::ShortFract:
+		case clang::BuiltinType::Kind::Fract:
+		case clang::BuiltinType::Kind::LongFract:
+		case clang::BuiltinType::Kind::UShortFract:
+		case clang::BuiltinType::Kind::UFract:
+		case clang::BuiltinType::Kind::ULongFract:
+		case clang::BuiltinType::Kind::SatShortAccum:
+		case clang::BuiltinType::Kind::SatAccum:
+		case clang::BuiltinType::Kind::SatLongAccum:
+		case clang::BuiltinType::Kind::SatUShortAccum:
+		case clang::BuiltinType::Kind::SatUAccum:
+		case clang::BuiltinType::Kind::SatULongAccum:
+		case clang::BuiltinType::Kind::SatShortFract:
+		case clang::BuiltinType::Kind::SatFract:
+		case clang::BuiltinType::Kind::SatLongFract:
+		case clang::BuiltinType::Kind::SatUShortFract:
+		case clang::BuiltinType::Kind::SatUFract:
+		case clang::BuiltinType::Kind::SatULongFract:
+		case clang::BuiltinType::Kind::Float16:
+		case clang::BuiltinType::Kind::Float128:
+		case clang::BuiltinType::Kind::Overload:
+		case clang::BuiltinType::Kind::BoundMember:
+		case clang::BuiltinType::Kind::PseudoObject:
+		case clang::BuiltinType::Kind::Dependent:
+		case clang::BuiltinType::Kind::UnknownAny:
+		case clang::BuiltinType::Kind::ARCUnbridgedCast:
+		case clang::BuiltinType::Kind::BuiltinFn:
+		case clang::BuiltinType::Kind::ObjCId:
+		case clang::BuiltinType::Kind::ObjCClass:
+		case clang::BuiltinType::Kind::ObjCSel:
+#define IMAGE_TYPE(it, id, si, a, s) case clang::BuiltinType::Kind::id:
+#include <clang/Basic/OpenCLImageTypes.def>
+#undef IMAGE_TYPE
+		case clang::BuiltinType::Kind::OCLSampler:
+		case clang::BuiltinType::Kind::OCLEvent:
+		case clang::BuiltinType::Kind::OCLClkEvent:
+		case clang::BuiltinType::Kind::OCLQueue:
+		case clang::BuiltinType::Kind::OCLReserveID:
+		case clang::BuiltinType::Kind::IncompleteMatrixIdx:
+		case clang::BuiltinType::Kind::OMPArraySection:
+		case clang::BuiltinType::Kind::OMPArrayShaping:
+		case clang::BuiltinType::Kind::OMPIterator:
+#define EXT_OPAQUE_TYPE(et, id, e) case clang::BuiltinType::Kind::id:
+#include <clang/Basic/OpenCLExtensionTypes.def>
+#define SVE_TYPE(n, id, si) case clang::BuiltinType::Kind::id:
+#include <clang/Basic/AArch64SVEACLETypes.def>
+#define PPC_VECTOR_TYPE(n, id, s) case clang::BuiltinType::Kind::id:
+#include <clang/Basic/PPCTypes.def>
+#undef EXT_OPAQUE_TYPE
+#undef SVE_TYPE
+#undef PPC_VECTOR_TYPE
+			return '!';
+		default:
+			return ':';
+		}
+	} else if (qual->isEnumeralType()) {
+		const clang::EnumDecl *ed = qual->getAs<clang::EnumType>()->getDecl();
+		if (!ed) {
+			return 'i';
+		} else {
+			return type2char(ed->getIntegerType().getCanonicalType(), qorig);
+		}
+	} else if (qual->isFunctionPointerType()) {
+		return '@';
+	} else if (qual->isAnyPointerType() || qual->isReferenceType()) {
+		const clang::QualType &pointed = getPointedType(qual);
+		if (isTypeTrivial(pointed, qorig)) {
+			return 'p';
+		} else if (const clang::RecordType *rct = pointed->getAs<clang::RecordType>()) {
+			clang::RecordDecl *rc = rct->getDecl();
+			if (!rc) {
+				return '!';
+			} else if (!rc->isCompleteDefinition()) {
+				return 'p';
+			} else {
+				std::string str;
+				if (qorig) {
+					const clang::QualType qpted = getPointedType(*qorig);
+					str = record2name(*rc, &qpted);
+				} else {
+					str = record2name(*rc, nullptr);
+				}
+				char ret = ptr2char(str);
+				if (ret) return ret;
+				else {
+					return '!';
+				}
+			}
+		} else {
+			return '!';
+		}
+	} else if (const clang::RecordType *rct = qual->getAs<clang::RecordType>()) {
+		clang::RecordDecl *rc = rct->getDecl();
+		if (!rc) {
+			return '?';
+		} else if (rc->getNameAsString() == "__builtin_va_list") {
+			// va_list
+			return 'A';
+		} else {
+			return '?';
+		}
+	} else {
+		return '?';
+	}
+}
+bool isTypeTrivial(const clang::QualType &q, const clang::QualType *qorig) {
+	const char c = type2char(q, qorig);
+#define GO(chr) || (c == chr)
+	return (c == 'v')
+		GO('i') GO('u')
+		GO('I') GO('U')
+		GO('l') GO('L')
+		GO('f') GO('d')
+		GO('D') GO('K')
+		GO('0') GO('1')
+		GO('C') GO('c')
+		GO('W') GO('w')
+		GO('H')
+		GO('p');
+#undef GO
+}
+bool isTypeValid(const clang::QualType &q, const clang::QualType *qorig) {
+	const char c = type2char(q, qorig);
+	if (c == 'A') return false;
+	if (c == 'V') return false;
+	return ((c >= '0') && (c <= '9')) || ((c >= 'A') && (c <= 'Z')) || ((c >= 'a') && (c <= 'z'));
+}
+
+const std::string type2string(const clang::QualType &qual, const clang::QualType *qorig) {
+	if (qual->isBuiltinType()) {
+		return std::string("(builtin) ") + static_cast<const clang::BuiltinType&>(*qual).getName(clang::PrintingPolicy{{}}).data();
+	} else if (qual->isFunctionPointerType()) {
+		return "Callback (function pointer)";
+	} else if (qual->isAnyPointerType() || qual->isReferenceType()) {
+		std::string prefix = qual->isAnyPointerType() ? "Pointer to " : "Reference to ";
+		const clang::QualType &pointed = getPointedType(qual);
+		if (isTypeTrivial(pointed, qorig)) {
+			return prefix + "trivial object " + type2string(pointed, qorig) + " (" + type2char(pointed, qorig) + ")";
+		} else if (const clang::RecordType *rct = pointed->getAs<clang::RecordType>()) {
+			clang::RecordDecl *rc = rct->getDecl();
+			if (!rc) {
+				return prefix + "unknown record";
+			} else if (!rc->isCompleteDefinition()) {
+				return prefix + "incomplete record " + rc->getNameAsString();
+			} else {
+				std::string str;
+				if (qorig) {
+					const clang::QualType qpted = getPointedType(*qorig);
+					str = record2name(*rc, &qpted);
+				} else {
+					str = record2name(*rc, nullptr);
+				}
+				const char *ret = ptr2str(str);
+				if (ret[0] != '\0') {
+					return prefix + ret;
+				} else {
+					if (mangler && mangler->shouldMangleDeclName(rc)) {
+						std::string mangled;
+						{
+							llvm::raw_string_ostream strstr{mangled};
+							mangler->mangleName(rc, strstr);
+						}
+						return prefix + "unknown record " + str + " (=== " + mangled + ")";
+					} else {
+						return prefix + "unknown record " + str;
+					}
+				}
+			}
+		} else {
+			return prefix + "non-trivial or typedef'ed object " + type2string(pointed, qorig) + " (" + type2char(pointed, qorig) + ")";
+			//return "Pointer (maybe to callback)";
+		}
+	} else if (qual->isEnumeralType()) {
+		const clang::EnumDecl *ed = qual->getAs<clang::EnumType>()->getDecl();
+		if (!ed) {
+			return "Enumeration with unknown underlying integer type (assuming int)";
+		} else {
+			return "Enumeration with underlying type " + type2string(ed->getIntegerType().getCanonicalType(), nullptr);
+		}
+	} else if (const clang::RecordType *rct = qual->getAs<clang::RecordType>()) {
+		clang::RecordDecl *rc = rct->getDecl();
+		if (!rc) {
+			return "Unknown record";
+		} else if (rc->getNameAsString() == "__builtin_va_list") {
+			return "va_list";
+		} else {
+			return "Unknown record " + std::string(rc->getName().data());
+		}
+	} else {
+		return std::string("??? ") + qual->getTypeClassName();
+	}
+}
+
+class Visitor : public clang::RecursiveASTVisitor<Visitor> {
+public:
+	clang::ASTContext &context;
+	
+	bool shouldVisitTemplateInstantiations() const /* override */ { return true; }
+	
+	Visitor(clang::CompilerInstance &ci) : context(ci.getASTContext()) {
+		if (!mangler) {
+			mangler = clang::ItaniumMangleContext::create(context, ci.getDiagnostics());
+		}
+	}
+	
+	~Visitor() {
+		if (mangler) {
+			delete mangler;
+			mangler = nullptr;
+		}
+	}
+	
+	bool VisitDecl(clang::Decl *decl) /* override */ {
+		std::cerr << std::flush;
+		if (!decl) return true;
+		
+		if ((decl->getKind() >= clang::Decl::Kind::firstFunction) && (decl->getKind() <= clang::Decl::Kind::lastFunction)) {
+			clang::DeclaratorDecl *ddecl = static_cast<clang::DeclaratorDecl*>(decl);
+			std::cout << "Function detected!\n";
+			
+			std::string funName{ddecl->getName()};
+			
+			auto niceprint = [](const std::string &infotype, const auto &dat){ std::cout << "    " << infotype << ": " << dat << "\n"; };
+			niceprint("Function name", funName);
+			if (mangler && mangler->shouldMangleDeclName(ddecl)) {
+				std::string mangled;
+				{
+					llvm::raw_string_ostream strstr{mangled};
+					mangler->mangleName(ddecl, strstr);
+				}
+				niceprint("Function mangled name", mangled);
+				funName = std::move(mangled);
+			}
+			
+			bool valid;
+			std::string funTypeStr{""};
+			if (ddecl->getFunctionType()->isFunctionNoProtoType()) {
+				const clang::FunctionNoProtoType *funType = static_cast<const clang::FunctionNoProtoType*>(ddecl->getFunctionType());
+				const auto &retType = funType->getReturnType();
+				
+				niceprint("Function return type", type2string(retType, &retType));
+				niceprint("Canonical function return type",
+					type2string(retType.getCanonicalType(), &retType) +
+					" (" + type2char(retType.getCanonicalType(), &retType) + ")");
+				niceprint("Is sugared", funType->isSugared());
+				if (funType->isSugared()) {
+					clang::QualType qft{funType, 0};
+					niceprint("Desugared", type2string(funType->desugar(), &qft));
+				}
+				
+				funTypeStr = type2char(retType.getCanonicalType(), &retType) + std::string("Fv");
+				valid = isTypeValid(retType.getCanonicalType(), &retType);
+			} else {
+				const clang::FunctionProtoType *funType = static_cast<const clang::FunctionProtoType*>(ddecl->getFunctionType());
+				const auto &retType = funType->getReturnType();
+				
+				niceprint("Function return type", type2string(retType, &retType));
+				niceprint("Canonical function return type",
+					type2string(retType.getCanonicalType(), &retType)
+					+ " (" + type2char(retType.getCanonicalType(), &retType) + ")");
+				niceprint("Parameter count", funType->getNumParams());
+				for (const clang::QualType &type : funType->getParamTypes()) {
+					niceprint("  " + type2string(type, &type),
+						type2string(type.getCanonicalType(), &type) + " (" + type2char(type.getCanonicalType(), &type) + ")");
+				}
+				niceprint("Variadic function", funType->isVariadic() ? "yes" : "no");
+				
+				funTypeStr =
+					type2char(retType.getCanonicalType(), &retType) +
+					((funType->getNumParams() == 0)
+					 ? std::string("Fv") : std::accumulate(funType->getParamTypes().begin(), funType->getParamTypes().end(), std::string("F"),
+											[](const std::string &acc, const clang::QualType &qual){ return acc + type2char(qual.getCanonicalType(), &qual); }));
+				if (funType->isVariadic()) funTypeStr += "V";
+				valid = !funType->isVariadic() &&
+					std::accumulate(funType->getParamTypes().begin(), funType->getParamTypes().end(), isTypeValid(retType.getCanonicalType(), &retType),
+						[](bool acc, const clang::QualType &qual){ return acc && isTypeValid(qual.getCanonicalType(), &qual); });
+			}
+			
+			niceprint("Conclusion", "");
+			niceprint("Function final name", funName);
+			niceprint("Function type", funTypeStr);
+			niceprint("Valid function type", valid ? "yes" : "no");
+			std::cout << "\n";
+			
+			funMap[funName] = std::make_pair(funTypeStr, valid);
+			funList.push_back(funName);
+		}
+		
+		return true;
+	}
+};
+
+class Consumer : public clang::ASTConsumer {
+public:
+	Visitor visitor;
+	
+	Consumer(clang::CompilerInstance &ci) : visitor(ci) {
+	}
+	
+	void HandleTranslationUnit(clang::ASTContext &context) override {
+		visitor.TraverseDecl(context.getTranslationUnitDecl());
+	}
+};
+
+class Action : public clang::ASTFrontendAction {
+public:
+	virtual std::unique_ptr<clang::ASTConsumer> CreateASTConsumer(clang::CompilerInstance &ci, llvm::StringRef inFile) override {
+		return std::make_unique<Consumer>(ci);
+	}
+};
+
+int main(int argc, const char **argv) {
+	if (argc < 2) {
+		std::cerr << "Usage: " << argv[0] << " (filenames) -- [-I...]" << std::endl;
+		return 2;
+	}
+	
+	/*int fakeargc = argc + 1;
+	const char **fakeargv = new const char*[fakeargc];
+	memcpy(fakeargv, argv, argc * sizeof(char*));
+	fakeargv[fakeargc - 1] = "--";*/
+	llvm::cl::OptionCategory opcat{""};
+	clang::tooling::CommonOptionsParser op{argc, argv, opcat};
+	std::vector<std::string> paths; for (int i = 1; i < argc; ++i) paths.push_back(argv[i]);
+	
+	clang::tooling::ClangTool tool{op.getCompilations(), paths};
+	
+	tool.run(clang::tooling::newFrontendActionFactory<Action>().get());
+	
+	std::cout << "Done, outputing output.h" << std::endl;
+	std::sort(funList.begin(), funList.end());
+	std::fstream file{"output.h", std::ios_base::out};
+	for (const std::string &funName : funList) {
+		if (!funMap[funName].second) {
+			file << "//";
+		}
+		file << "GO(" << funName << ", " << funMap[funName].first << ")\n";
+	}
+	
+	return 0;
+}

LLVMprivateGenerator/registered_structs.cpp

@@ -0,0 +1,267 @@
+#include <string>
+
+#define ALL START() \
+	/* libc */ \
+	STRUCT("_IO_FILE", "a FILE") \
+	STRUCT("_G_fpos_t", "a file position") \
+	STRUCT("sockaddr", "a socket address") \
+	STRUCT("itimerspec", "an itimerspec") \
+	STRUCT("timespec", "a timespec") \
+	STRUCT("itimerval", "an itimerval") \
+	STRUCT("timeval", "a timeval") \
+	STRUCT("timex", "a timex") \
+	STRUCT("timezone", "a timezone") \
+	STRUCT("dirent", "a dirent") \
+	STRUCT("dirent64", "a dirent64") \
+	STRUCT("__dirstream", "a dir stream") \
+	STRUCT("tm", "a time structure (tm)") \
+	STRUCT("cmsghdr", "a cmsghdr") \
+	STRUCT("msghdr", "a msghdr") \
+	STRUCT("rpcent", "an rpcent") \
+	STRUCT("random_data", "a random_data structure") \
+	STRUCT("drand48_data", "a drand48_data structure") \
+	STRUCT("termios", "a termios") \
+	STRUCT("iovec", "an iovec") \
+	STRUCT("file_handle", "a file handle") \
+	STRUCT("lconv", "an lconv") \
+	STRUCT("__locale_struct", "a locale structure") \
+	STRUCT("aliasent", "an alias") \
+	STRUCT("fstab", "an fstab") \
+	STRUCT("group", "a group") \
+	STRUCT("hostent", "a hostent") \
+	STRUCT("protoent", "a protoent") \
+	STRUCT("passwd", "a password") \
+	STRUCT("spwd", "an spwd") \
+	STRUCT("ttyent", "a ttyent") \
+	STRUCT("utmp", "an utmp structure") \
+	STRUCT("utmpx", "an utmpx structure") \
+	STRUCT("ifaddrs", "an ifaddrs structure") \
+	STRUCT("statfs", "a statfs structure") \
+	STRUCT("statfs64", "a statfs64 structure") \
+	STRUCT("statvfs", "a statvfs structure") \
+	STRUCT("statvfs64", "a statvfs64 structure") \
+	STRUCT("timeb", "a timeb structure") \
+	STRUCT("_ftsent", "an _ftsent structure") \
+	STRUCT("sysinfo", "a sysinfo structure") \
+	STRUCT("rlimit", "an rlimit structure") \
+	STRUCT("rlimit64", "an rlimit64 structure") \
+	STRUCT("rusage", "an rusage structure") \
+	STRUCT("entry", "an entry structure") \
+	STRUCT("pollfd", "a pollfd structure") \
+	STRUCT("re_pattern_buffer", "a re_pattern_buffer structure") \
+	STRUCT("sembuf", "a sembuf structure") \
+	STRUCT("tms", "a tms structure") \
+	STRUCT("utsname", "an utsname structure") \
+	STRUCT("utimbuf", "an utimbuf structure") \
+	STRUCT2("__va_list_tag", "__va_list_tag (aka, a va_list)", 'A') \
+	/* ncurses */ \
+	STRUCT("_win_st", "a _win_st structure") \
+	STRUCT("MEVENT", "an MEVENT structure") \
+	TYPEDEF("cchar_t", "a cchar_t") \
+	/* zlib */ \
+	STRUCT("gz_header_s", "a gz_header_s structure") \
+	STRUCT("gzFile_s", "a gzFile_s structure") \
+	STRUCT("z_stream_s", "a z_stream_s structure") \
+	\
+	END()
+
+#define START()
+#define STRUCT(s, ret) if (str == s) { return 'p'; } else
+#define STRUCT2(s, ret, c) if (str == s) { return c; } else
+#define TYPEDEF(s, ret) if (str == s) { return 'p'; } else
+#define END() { return 0; }
+char ptr2char(const std::string &str) {
+	/*if ((str == "_IO_FILE")
+	 || (str == "_G_fpos_t")
+	 || (str == "sockaddr")
+	 || (str == "itimerspec")
+	 || (str == "timespec")
+	 || (str == "itimerval")
+	 || (str == "timeval")
+	 || (str == "timex")
+	 || (str == "timezone")
+	 || (str == "dirent")
+	 || (str == "dirent64")
+	 || (str == "__dirstream")
+	 || (str == "tm")
+	 || (str == "cmsghdr")
+	 || (str == "msghdr")
+	 || (str == "rpcent")
+	 || (str == "random_data")
+	 || (str == "drand48_data")
+	 || (str == "termios")
+	 || (str == "iovec")
+	 || (str == "file_handle")
+	 || (str == "lconv")
+	 || (str == "__locale_struct")
+	 || (str == "aliasent")
+	 || (str == "fstab")
+	 || (str == "group")
+	 || (str == "hostent")
+	 || (str == "protoent")
+	 || (str == "passwd")
+	 || (str == "spwd")
+	 || (str == "ttyent")
+	 || (str == "utmp")
+	 || (str == "utmpx")
+	 || (str == "ifaddrs")
+	 || (str == "statfs")
+	 || (str == "statfs64")
+	 || (str == "statvfs")
+	 || (str == "timeb")
+	 || (str == "_ftsent")
+	 || (str == "sysinfo")
+	 || (str == "rlimit")
+	 || (str == "rlimit64")
+	 || (str == "rusage")
+	 || (str == "entry")
+	 || (str == "pollfd")
+	 || (str == "re_pattern_buffer")
+	 || (str == "sembuf")
+	 || (str == "tms")
+	 || (str == "utsname")
+	 || (str == "utimbuf")
+	// ncurses
+	 || (str == "_win_st")
+	 
+	 || (str == "cchar_t")
+	) {
+		// FILE*, fpos_t*, ...
+		return 'p';
+	} else if (str == "__va_list_tag") {
+		return 'A';
+	} else {
+		return 0;
+	}*/
+	ALL
+}
+#undef END
+#undef TYPEDEF
+#undef STRUCT2
+#undef STRUCT
+#undef START
+
+#define START()
+#define STRUCT(s, ret) if (str == s) { return ret; } else
+#define STRUCT2(s, ret, c) if (str == s) { return ret; } else
+#define TYPEDEF(s, ret) if (str == s) { return ret; } else
+#define END() return "";
+const char *ptr2str(const std::string &str) {
+	/*if (str == "_IO_FILE") {
+		return "a FILE";
+	} else if (str == "_G_fpos_t") {
+		return "a file position";
+	} else if (str == "sockaddr") {
+		return "a socket address";
+	} else if (str == "itimerspec") {
+		return "an itimerspec";
+	} else if (str == "timespec") {
+		return "a timespec";
+	} else if (str == "itimerval") {
+		return "an itimerval";
+	} else if (str == "timeval") {
+		return "a timeval";
+	} else if (str == "timex") {
+		return "a timex";
+	} else if (str == "timezone") {
+		return "a timezone";
+	} else if (str == "dirent") {
+		return "a dirent";
+	} else if (str == "dirent64") {
+		return "a dirent64";
+	} else if (str == "__dirstream") {
+		return "a dir stream";
+	} else if (str == "tm") {
+		return "a time structure (tm)";
+	} else if (str == "cmsghdr") {
+		return "a cmsghdr";
+	} else if (str == "msghdr") {
+		return "a msghdr";
+	} else if (str == "rpcent") {
+		return "an rpcent";
+	} else if (str == "random_data") {
+		return "a random_data structure";
+	} else if (str == "drand48_data") {
+		return "a drand48_data structure";
+	} else if (str == "termios") {
+		return "a termios";
+	} else if (str == "iovec") {
+		return "an iovec";
+	} else if (str == "file_handle") {
+		return "a file handle";
+	} else if (str == "lconv") {
+		return "an lconv";
+	} else if (str == "__locale_struct") {
+		return "a locale structure";
+	} else if (str == "aliasent") {
+		return "an alias";
+	} else if (str == "fstab") {
+		return "an fstab";
+	} else if (str == "group") {
+		return "a group";
+	} else if (str == "hostent") {
+		return "a hostent";
+	} else if (str == "protoent") {
+		return "a protoent";
+	} else if (str == "passwd") {
+		return "a password";
+	} else if (str == "spwd") {
+		return "an spwd";
+	} else if (str == "ttyent") {
+		return "a ttyent";
+	} else if (str == "utmp") {
+		return "an utmp structure";
+	} else if (str == "utmpx") {
+		return "an utmpx structure";
+	} else if (str == "ifaddrs") {
+		return "an ifaddrs structure";
+	} else if (str == "statfs") {
+		return "a statfs structure";
+	} else if (str == "statfs64") {
+		return "a statfs64 structure";
+	} else if (str == "statvfs") {
+		return "a statvfs structure";
+	} else if (str == "statvfs64") {
+		return "a statvfs64 structure";
+	} else if (str == "timeb") {
+		return "a timeb structure";
+	} else if (str == "_ftsent") {
+		return "an _ftsent structure";
+	} else if (str == "sysinfo") {
+		return "a sysinfo structure";
+	} else if (str == "rlimit") {
+		return "an rlimit structure";
+	} else if (str == "rlimit64") {
+		return "an rlimit64 structure";
+	} else if (str == "rusage") {
+		return "an rusage structure";
+	} else if (str == "entry") {
+		return "an entry structure";
+	} else if (str == "pollfd") {
+		return "a pollfd structure";
+	} else if (str == "re_pattern_buffer") {
+		return "a re_pattern_buffer structure";
+	} else if (str == "sembuf") {
+		return "a sembuf structure";
+	} else if (str == "tms") {
+		return "a tms structure";
+	} else if (str == "utsname") {
+		return "an utsname structure";
+	} else if (str == "utimbuf") {
+		return "an utimbuf structure";
+	} else if (str == "__va_list_tag") {
+		return "__va_list_tag (aka, a va_list)";
+	// ncurses
+	} else if (str == "_win_st") {
+		return "a _win_st structure";
+		
+	} else if (str == "cchar_t") {
+		return "a cchar_t";
+	} else return "";*/
+	ALL
+}
+#undef END
+#undef TYPEDEF
+#undef STRUCT2
+#undef STRUCT
+#undef START

README.md

@@ -1,49 +0,0 @@
-# box64
-
-![Official logo](Box64Logo.png "Official Logo")
-Linux Userspace x86_64 Emulator with a twist
-
-----
-
-Box64 lets you run x86_64 Linux programs (such as games) on non-x86_64 Linux systems, like ARM (host system needs to be 64bit little-endian).
-
-Because Box64 uses the native versions of some "system" libraries, like libc, libm, SDL, and OpenGL, it's easy to integrate and use with most applications, and performance can be surprisingly high in some cases.
-
-Box64 integrates a DynaRec (dynamic recompiler) for the ARM64 platform, providing a speed boost between 5 to 10 times faster than only using the interpreter.
-
-Some x86 internal opcodes use parts of "Realmode X86 Emulator Library", see [x86primop.c](src/emu/x86primop.c) for copyright details
-
-<img src="Box64Icon.png" width="96" height="96">
-
-Logo and Icon made by @grayduck, thanks!
-
-----
-
-Usage
-----
-
-There are a few environment variables to control the behaviour of Box64.
-
-See [here](USAGE.md) for all environment variables and what they do.
-
-Note: Box64's Dynarec uses a mechanism with Memory Protection and a SegFault signal handler to handle JIT code. In simpler terms, if you want to use GDB to debug a running program that use JIT'd code (like mono/Unity3D), you will still have many "normal" segfaults triggering. It is suggested to use something like `handle SIGSEGV nostop` in GDB to not stop at each segfault, and maybe put a breakpoint inside `my_memprotectionhandler` in `signals.c` if you want to trap SegFaults.
-
-----
-
-Compiling/Installation
-----
-> Compilation instructions can be found [here](COMPILE.md)  
-
-----
-
-Version history
-----
-
-The change log is available [here](CHANGELOG.md)
-
-----
-
-Final words
-----
-
-(If you use Box64 in your project, please don't forget to mention Box64!)

debian/changelog

@@ -0,0 +1,29 @@
+box64 (0.1.8) unstable; urgency=low
+
+  * Added an option to get generated -NAN on SSE2 operation
+  * Many small fixes and improvement to get SteamPlay (i.e. proton) working (along with box86)
+  * Added some workaround for program calling uname to mimic x86_64 system
+  * Added some granularity to mmap, and generic memory protection tracking improvment, to mimic x86 system (for wine stagging and proton)
+  * Better clone syscall and libc implementation
+  * Improved wrapping of GTK libs
+  * More wrapped libs (more gtk libs, like gstreamer-1.0 among other non-gtk libs too)
+  * More wrapped functions(with some tricky one, like dladdr1)
+  * Some fixes and improvment to some wrapped functions
+  * Refactor Dynarec:
+  *   - better handling of SSE/x87 registers
+  *   - optimisation to limit float/double conversion
+  *   - better handling of "internal" jump inside a dynablock
+  *   - make adding new architecture easier, by sharing as much infrastructure as possible
+  * Improved elfloader
+  * Improved some tests
+  * Improved a bit the "Hotpage" handling and messages
+  * Added more dynarec opcodes
+  * A few fixes in some Dynarec opcodes
+  * A bit more optimisation in some Dynarec opcodes
+  * Don't quit on unsupported syscall, return -1 / ENOSYS error
+  * Added some more Syscall
+  * Wrapped Vulkan library. Vulkan and dxvk now supported!
+  * Support building on PPC64LE (interpretor only)
+  * Added support for Risc-V (interpretor only)
+
+ -- Sebastien Chevalier <[email protected]>  Tue, 18 Jan 2022 11:20:33 -0500

debian/compat

@@ -0,0 +1 @@
+11

debian/control

@@ -0,0 +1,14 @@
+Source: box64
+Section: utils
+Priority: optional
+Maintainer: Ryan Fortner <[email protected]>
+Build-Depends: cmake, debhelper (>=11~), python3
+Standards-Version: 4.1.4
+Homepage: https://github.com/ptitSeb/box64
+
+Package: box64
+Architecture: any
+Multi-Arch: foreign
+Depends: ${misc:Depends}, ${shlibs:Depends}
+Description: Linux Userspace x86_64 Emulator with a twist, targeted at ARM Linux devices 
+ Box86 lets you run x86_64 Linux programs (such as games) on non-x86 Linux systems, like ARM (host system needs to be 64bit little-endian).

debian/copyright

@@ -0,0 +1,26 @@
+Format-Specification: http://dep.debian.net/deps/dep5/
+
+Files: *
+Copyright: © 2022 Sebastien Chevalier
+License: MIT
+
+License: MIT
+ Copyright (c) 2018-2021 Sebastien Chevalier ("ptitSeb")
+ .
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+ .
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+ .
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE.

debian/lintian-override

@@ -0,0 +1 @@
+box64: no-manual-page

debian/rules

@@ -0,0 +1,12 @@
+#!/usr/bin/make -f
+
+%:
+	dh $@  
+
+override_dh_auto_configure:
+	dh_auto_configure -- \
+	      -DCMAKE_BUILD_TYPE=RelWithDebInfo \
+	      -DARM_DYNAREC=1
+
+override_dh_shlibdeps:
+	dh_shlibdeps --exclude=libgcc_s.so.1 --exclude=libpng12.so.0 --exclude=libstdc++.so.6 

debian/source/format

@@ -0,0 +1 @@
+3.0 (quilt)

debian/upstream/metadata

@@ -0,0 +1,5 @@
+Bug-Database: https://github.com/ptitSeb/box64/issues
+Bug-Submit: https://github.com/ptitSeb/box64/issues/new
+Repository: https://github.com/ptitSeb/box64.git
+Repository-Browse: https://github.com/ptitSeb/box64
+Security-Contact: [email protected]

debian/watch

@@ -0,0 +1 @@
+version=3

docs/CHANGELOG.md

@@ -0,0 +1,114 @@
+v0.1.8
+======
+* Added an option to get generated -NAN on SSE2 operation
+* Many small fixes and improvement to get SteamPlay (i.e. proton) working (along with box86)
+* Added some workaround for program calling uname to mimic x86_64 system
+* Added some granularity to mmap, and generic memory protection tracking improvment, to mimic x86 system (for wine stagging and proton)
+* Better clone syscall and libc implementation
+* Improved wrapping of GTK libs
+* More wrapped libs (more gtk libs, like gstreamer-1.0 among other non-gtk libs too)
+* More wrapped functions(with some tricky one, like dladdr1)
+* Some fixes and improvment to some wrapped functions
+* Refactor Dynarec:
+    * better handling of SSE/x87 registers
+    * optimisation to limit float/double conversion
+    * better handling of "internal" jump inside a dynablock
+    * make adding new architecture easier, by sharing as much infrastructure as possible
+* Improved elfloader
+* Improved some tests
+* Improved a bit the "Hotpage" handling and messages
+* Added more dynarec opcodes
+* A few fixes in some Dynarec opcodes
+* A bit more optimisation in some Dynarec opcodes
+* Don't quit on unsupported syscall, return -1 / ENOSYS error
+* Added some more Syscall
+* Wrapped Vulkan library. Vulkan and dxvk now supported!
+* Support building on PPC64LE (interpretor only)
+* Added support for Risc-V (interpretor only)
+
+v0.1.6
+======
+* Introduce "HotPage", to temporarily disable Dynarec on a page were writing is also occuring (can help speed up C# code)
+* Some work on Dynarec to limit the number of mutex use, and also allow smaller block to be built (for JIT'd programs)
+* Introduce BOX64_DYNAREC_STRONGMEM for the (Arm) dynarec to emulate StrngMemory Model (needed by some games, like RimWorld)
+* More functions wrapped
+* Improve speed of the custom allocator used by dynarec and Hash (speedup loading)
+* Added a workaround for streamwebhelper to not load it
+* More opcodes added
+* More wrapped libraries, including gtk2
+* Added a fix for linking box64 on system using glibc 2.34+
+* Some residual fixes on thread attribute handling
+* Better handling of app that want 32bits jumps, like unity3d/mono (thanks mogery)
+* More ARM hardware option in CMake (Phytium, NX...)
+* Added loongarch64 support (interpretor only)
+* Some fixes to elfloader
+* Added a mecanism to cancel a Dynarec block construction if it triggers a segfault (instead of a crash)
+
+v0.1.4
+======
+* Reworked README a bit
+* Added some more wrapped libs
+* Added some SSE4x opcodes
+* Preliminary support for VSyscall (still missing VDSO)
+* Added support for AES-NI cpu extension, also in Dynarec (and using ARM extension if present)
+* Added some syscall
+* Added some more wrapped functions
+* Improvment to the handling of longjmp inside signal handlers
+* Improved wrapper helpers (from rajdakin)
+* Some fixes to opcodes (especially C2 flags for some x87 opcodes)
+* Handling of some specific opcode as privileged instruction (instead of NOP)
+* Fixed ELF signature detection
+* Some fixes to a few env. var. handling
+
+v0.1.2
+======
+* OpenSource!
+* A few more opcode added to the Interpretor and the Dynarec
+* Improved Native Function calling
+* Added some function to limit allocated memory to 47bits space (for Wine)
+* Improved and Fixed the functions to limit allocated memory to 32bits space
+* Wine is starting now, but not everything and every version works
+
+v0.1.0
+======
+* Improvement to ElfLoader
+* More opcode added to the Dynarec
+* More lib wrapping
+* Some fixes to a few function signature
+* Improvement to Signal handling, and internal mutex handling
+* A few fixes to some dynarec opcodes
+* A few fixes to some interpretor opcodes
+
+v0.0.8
+======
+* Improvement to SSE/x87 handling
+* More opcode added to the Dynarec
+* More lib wrapping
+
+v0.0.6
+======
+* Added Dynarec for ARM64
+* Many general CPU opcode added to the Dynarec
+* Many SSEx opcodes added to the Dynarec
+* Added a few more symbols in libc
+* A few changes to the "thread once" handling
+* New Logo and Icon from @grayduck
+
+v0.0.4
+======
+* Added a lot of opcodes
+* Added SDL1 and SDL2 wrapping
+* OpenGL/GLU wrapping done
+* libasound / libpulse wrapping done
+* libopenal / libalure / libalut wrapping done
+* Many X11 libs wrapped
+* Added "install" with binfmt integration
+* A few games are actualy starting now (old WorldOfGoo, Into The Breach, VVVVVV and Thimbeweed Park)
+
+v0.0.2
+======
+* Using box86 as a base, implemented most planned box64 part except dynarec
+* Wrapped a few libs
+* ELF loader a bit crude, but seems working
+* Signal handling implemented
+* MMX and x87 are sharing their registers

docs/COMPILE.md

@@ -0,0 +1,215 @@
+Compiling
+----
+#### for RK3399
+
+Using a 64bit OS:
+```
+git clone https://github.com/ptitSeb/box64
+cd box64
+mkdir build; cd build; cmake .. -DRK3399=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+make -j4
+sudo make install
+```
+If it's the first install, you also need:
+```
+sudo systemctl restart systemd-binfmt
+```
+
+#### for PI4
+
+Warning, you need a 64bit OS:
+
+```
+git clone https://github.com/ptitSeb/box64
+cd box64
+mkdir build; cd build; cmake .. -DRPI4ARM64=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+make -j4
+sudo make install
+```
+If it's the first install, you also need:
+```
+sudo systemctl restart systemd-binfmt
+```
+
+#### for TEGRA X1
+
+Using a 64bit OS:
+
+```
+git clone https://github.com/ptitSeb/box64
+cd box64
+mkdir build; cd build; cmake .. -DTEGRAX1=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+make -j4
+sudo make install
+```
+If it's the first install, you also need:
+```
+sudo systemctl restart systemd-binfmt
+```
+
+#### for Snapdragon 845
+
+Using a 64bit OS:
+
+```
+git clone https://github.com/ptitSeb/box64
+cd box64
+mkdir build; cd build; cmake .. -DSD845=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+make -j4
+sudo make install
+```
+If it's the first install, you also need:
+```
+sudo systemctl restart systemd-binfmt
+```
+
+
+----
+#### for Phytium
+
+Using a 64bit OS:
+```
+git clone https://github.com/ptitSeb/box64
+cd box64
+mkdir build; cd build; cmake .. -DPHYTIUM=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+make -j4
+sudo make install
+```
+If it's the first install, you also need:
+```
+sudo systemctl restart systemd-binfmt
+```
+
+#### for M1
+
+Only test on Asahi for now, using the default "16K page" kernel
+
+```
+git clone https://github.com/ptitSeb/box64
+cd box64
+mkdir build; cd build; cmake .. -DM1=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+make -j4
+sudo make install
+```
+If it's the first install, you also need:
+```
+sudo systemctl restart systemd-binfmt
+```
+
+
+#### for Other ARM64 Linux platforms
+
+ `mkdir build; cd build; cmake .. -DARM_DYNAREC=ON -DCMAKE_BUILD_TYPE=RelWithDebInfo; make -j$(nproc)`
+
+#### for LoongArch
+
+Using a 64bit OS:
+
+```
+git clone https://github.com/ptitSeb/box64
+cd box64
+mkdir build; cd build; cmake .. -DLARCH64=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+make -j4
+sudo make install
+```
+If it's the first install, you also need:
+```
+sudo systemctl restart systemd-binfmt
+```
+
+#### for RISCV
+
+Using a 64bit OS:
+
+```
+git clone https://github.com/ptitSeb/box64
+cd box64
+mkdir build; cd build; cmake .. -DRV64=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+make -j4
+sudo make install
+```
+If it's the first install, you also need:
+```
+sudo systemctl restart systemd-binfmt
+```
+
+#### for PowerPC 64 LE
+
+Using a 64bit OS:
+
+```
+git clone https://github.com/ptitSeb/box64
+cd box64
+mkdir build; cd build; cmake .. -DPPC64LE=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+make -j4
+sudo make install
+```
+If it's the first install, you also need:
+```
+sudo systemctl restart systemd-binfmt
+```
+
+#### for LX2160A
+
+Using a 64bit OS:
+
+```
+git clone https://github.com/ptitSeb/box64
+cd box64
+mkdir build; cd build; cmake .. -DLX2160A=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+make -j$(nproc)
+sudo make install
+```
+If it's the first install, you also need:
+```
+sudo systemctl restart systemd-binfmt
+```
+
+#### for x86_64 Linux
+
+ `mkdir build; cd build; cmake .. -DLD80BITS=1 -DNOALIGN=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo; make -j$(nproc)`
+
+If you encounter some linking errors, try using `NOLOADADDR=ON` (`cmake -DNOLOADADDR=ON; make -j$(nproc)`).
+
+### use ccmake
+
+Alternatively, you can **use the curses-bases ccmake (or any other gui frontend for cmake)** to select wich platform to use interactively.
+
+### Customize your build
+
+#### Use ccache if you have it
+
+Add `-DUSE_CCACHE=1` if you have ccache (it's better if you plan to touch the sources)
+
+#### To have some debug info
+
+The `-DCMAKE_BUILD_TYPE=RelWithDebInfo` argument makes a build that is both optimized for speed, and has debug information embedded. That way, if you have a crash or try to analyse performance, you'll have some symbols.
+
+#### To have a Trace Enabled build 
+
+To have a trace enabled build (***the interpreter will be slightly slower***), add `-DHAVE_TRACE=1`. But you will need to have the [Zydis library](https://github.com/zyantific/zydis) in your `LD_LIBRARY_PATH` or in the system library folders at runtime.
+
+#### To have ARM Dynarec
+
+Dynarec is only available on ARM (for the meantime), Activate it by using `-DARM_DYNAREC=1`.
+###### *Note: VFPv3 and NEON are required for Dynarec.*
+
+#### Not building from a git clone
+
+If you are not building from a git clone (for example, downloading a release source code zip from github), you need to use `-DNOGIT=1` from cmake to be able to build (box64 uses git SHA1 to show last commit in version number).
+
+----
+
+Testing
+----
+A few tests are included with box64.
+
+They can be launched using the `ctest` command.
+
+The tests are very basic and only tests some functionality for now.
+
+----
+
+Debian Packaging
+----
+Box64 can also be packaged into a .deb file with `DEB_BUILD_OPTIONS=nostrip dpkg-buildpackage -us -uc -nc`.

docs/README.md

@@ -0,0 +1,114 @@
+![Official logo](img/Box64Logo.png "Official Logo")
+
+Linux Userspace x86_64 Emulator with a twist
+
+[View changelog](https://github.com/ptitSeb/box64/blob/main/docs/CHANGELOG.md) | [中文](https://github.com/ptitSeb/box64/blob/main/docs/README_CN.md) | [Report an error](https://github.com/ptitSeb/box64/issues/new)
+
+![build](https://app.travis-ci.com/ptitSeb/box64.svg?branch=main) ![stars](https://img.shields.io/github/stars/ptitSeb/box64) ![forks](https://img.shields.io/github/forks/ptitSeb/box64) ![contributors](https://img.shields.io/github/contributors/ptitSeb/box64) ![prs](https://img.shields.io/github/issues-pr/ptitSeb/box64) ![issues](https://img.shields.io/github/issues/ptitSeb/box64)
+
+----
+
+Box64 lets you run x86_64 Linux programs (such as games) on non-x86_64 Linux systems, like ARM (host system needs to be 64-bit little-endian).
+
+You can find many Box64 videos on the [MicroLinux](https://www.youtube.com/channel/UCwFQAEj1lp3out4n7BeBatQ), [Pi Labs](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g) or [The Byteman](https://www.youtube.com/channel/UCEr8lpIJ3B5Ctc5BvcOHSnA) YouTube channels.
+
+Since Box64 uses the native versions of some "system" libraries, like libc, libm, SDL, and OpenGL, it's easy to integrate and use with most applications, and performance can be surprisingly high in many cases. Take a look at thoses bench analysis for an example [here](https://box86.org/index.php/2021/06/game-performances/).
+
+Box64 integrates with DynaRec (dynamic recompiler) for the ARM64 platform, providing a speed boost between 5 to 10 times faster than using only the interpreter. Some high level information on how DynaRec works can be found [here](https://box86.org/2021/07/inner-workings-a-high%e2%80%91level-view-of-box86-and-a-low%e2%80%91level-view-of-the-dynarec/).
+
+Some x64 internal opcodes use parts of "Realmode X86 Emulator Library", see [x64primop.c](../src/emu/x64primop.c) for copyright details
+
+<img src="img/Box64Icon.png" width="96" height="96">
+
+Logo and Icon made by @grayduck, thanks!
+
+----
+
+Usage
+----
+
+There are a few environment variables to control the behaviour of Box64.
+
+See [here](USAGE.md) for all the environment variables and what they do.
+
+Note: Box64's Dynarec uses a mechanism with Memory Protection and a SegFault signal handler to handle JIT code. In simpler terms, if you want to use GDB to debug a running program that use JIT'd code (like mono/Unity3D), you will still have many "normal" segfaults triggering. It is suggested to use something like `handle SIGSEGV nostop` in GDB to not stop at each segfault, and maybe put a breakpoint inside `my_memprotectionhandler` in `signals.c` if you want to trap SegFaults.
+
+----
+
+Compiling/Installation
+----
+> Compilation instructions can be found [here](COMPILE.md).
+
+----
+
+Version history/Change log
+----
+
+The change log is available [here](CHANGELOG.md).
+
+----
+
+Notes about 32-bit platforms
+----
+
+Because Box64 works by directly translating function calls from x86_64 to host system, the host system (the one Box64 is running on) needs to have 64-bit libraries. Box64 doesn't include any 64-bit <-> 32-bit translation. 
+
+So understand that box64 will only runs 64-bit linux binaries. For 32-bit binaries, you need box86 (with all the multiarch or proot trickery it imply on 64-bit OS).
+Note that many installer (mojo setup based) will fall back to "x86" when detecting ARM64 OS, and so will try to use box86 for the setup, even if an x86_64 version exist. You can hack your way around with a fake "uname" that return "x86_64" when the argument is "-m"
+
+----
+
+Notes about Unity game emulation
+----
+
+Running Unity games is a hit or miss for now. Unity uses Mono (which uses signals that are not always emulated in a 100% accurate way).
+You should also note that some Unity3D games require OpenGL 3+ which can be tricky to provide on ARM SBC (single-board computers).
+So, not all Unity games work and can require a high OpenGL profile, but many actualy work now.
+Hint: on Pi4, use `MESA_GL_VERSION_OVERRIDE=3.2` and with Panfrost use `PAN_MESA_DEBUG=gl3` to use higher profile if the game starts then quits before showing anything.
+
+----
+
+Notes about GTK programs
+----
+
+GTK libraries are now wrapped on box64, bu only gtk2, not gtk3 (contrary to box86).
+
+----
+
+Notes about Steam
+----
+
+Note that Steam is a hybrid 32-bit / 64-bit. You NEED box86 to run Steam, as the client app is a 32-bit binary. It also uses a 64-bit local server binaries, but like most stuff using libcef/chromium, it's not working correctly on box64 for now.
+So, no Steam for now on box64.
+
+----
+
+Notes about Wine
+----
+
+Wine64 is supported on box64. Proton should also work. Be aware that 64-bit Wine also includes 32-bit components, to be able to run 32-bit Windows programs. The 32-bit apps will need box86 and will not run without it. On a system where both box64 and box86 are present and working, a wine 64-bit setup can run both 32-bit and 64-bit Windows programs (just use `wine` and `wine64` respectively)
+
+----
+
+Notes about Vulkan
+----
+
+Box64 wraps Vulkan libraries, but note that it as only been tested with a RX550 card, some extensions may be missing depending on your graphics card.
+
+----
+
+Final word
+----
+
+I want to thank everyone who has contributed to box64 development.
+There are many ways to contribute: code contribution, financial, hardware and advertisement!
+So, in no particular order, I want to thank:
+ * For their major code contribution: rajdakin, mogery
+ * For their major financial contribution: FlyingFathead, stormchaser3000
+ * For hardware contribution and LoongArch migration: [xiaoji](https://www.linuxgame.cn/), Deepin Beijing Develop Team
+ * For their hardware contribution: [Radxa](https://rockpi.org/), [Pine64](https://www.pine64.org/), [StarFive](https://rvspace.org/)
+ * For their continous advertisement of box64 project: salva ([microLinux](https://www.youtube.com/channel/UCwFQAEj1lp3out4n7BeBatQ)), [PILab](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g)/[TwisterOS](https://twisteros.com/) team, [The Byteman](https://www.youtube.com/channel/UCEr8lpIJ3B5Ctc5BvcOHSnA), [NicoD](https://www.youtube.com/channel/UCpv7NFr0-9AB5xoklh3Snhg), ekianjo ([Boilingsteam](https://boilingsteam.com/))
+
+And I also thank the many other people who participated even once in this project.
+
+(If you use Box64 in your project, please don't forget to mention it!)

docs/README_CN.md

@@ -0,0 +1,119 @@
+# box64
+
+![Official logo](img/Box64Logo.png "Official Logo")
+Linux上用户空间的x86_64应用模拟器 
+
+----
+![box64 build status](https://app.travis-ci.com/ptitSeb/box64.svg?branch=main)
+
+[English](README.md)
+
+在ARM或其他非X86_64架构的Linux操作系统上，使用Box64可以运行x86_64 Linux程序（例如游戏），请注意，主机系统需要**64位小端**。
+
+您可以在Youtube的[MicroLinux](https://www.youtube.com/channel/UCwFQAEj1lp3out4n7BeBatQ)、[Pi Labs](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g)或[The Byteman](https://www.youtube.com/channel/UCEr8lpIJ3B5Ctc5BvcOHSnA)频道找到更多Box64视频。
+
+Box64使用了一些“系统”库的原生版本，例如libc、libm、SDL和OpenGL，所以它很容易与大多数应用程序集成和使用，并且在很多情况下性能会出奇的高。点击[此处](https://box86.org/index.php/2021/06/game-performances/)查看示例的基准测试分析。
+
+Box64为ARM64平台集成了DynaRec（动态重编译器），比仅使用解释器提升5到10倍性能。关于Dynarec如何工作的更多信息，可以在[这里](https://box86.org/2021/07/inner-workings-a-high%e2%80%91level-view-of-box86-and-a-low%e2%80%91level-view-of-the-dynarec/)找到。
+
+注：DynaRec需要针对不同平台编写一部分汇编代码，目前仅支持ARM64。
+
+一些x64内部操作码使用“Realmode X86 Emulator Library”的部分内容，请参阅[x64primop.c](../src/emu/x64primop.c)了解版权详情 
+
+<img src="img/Box64Icon.png" width="96" height="96">
+
+Logo和图标由grayduck制作，感谢!
+
+----
+
+使用方法
+----
+
+若干环境变量可以设置Box64的行为。
+
+点击[这里](USAGE.md)了解所有的环境变量和它们的作用。
+
+请注意：Box64的Dynarec提供了一种机制来处理JIT代码，包含内存保护和段错误信号处理程序。简单地说，如果您想用GDB来调试一个使用JIT代码的运行程序（比如mono/Unity3D），您仍然会触发很多“正常”的段错误。建议在GDB中使用类似于`handle SIGSEGV nostop`的东西，不要在每个段错误时都停止，如果您想捕获段错误，可以在`signals.c`中的`my_memprotectionhandler`中放置一个断点。
+
+----
+
+编译/安装
+----
+> 编译说明可以在[这里](COMPILE.md)查看。  
+
+----
+
+版本历史
+----
+
+版本日志在[这里](CHANGELOG.md)。
+
+----
+
+32位平台的注意事项
+----
+
+Box64的工作原理是直接将函数调用从x86_64转换到主机系统，主机系统（Box64运行的系统）需要有64位的库。Box64并不包括任何64位<->32位的转换。
+
+所以请理解，Box64只能运行64位的Linux二进制文件。对于32位的二进制文件，需要Box86（在64位的操作系统上需要所有的multiarch库或一些proot技巧）。
+
+请注意，许多(基于mojo的)安装程序，即使存在x86_64版本，但在检测到架构为ARM64时会退回到"x86"，这时会尝试使用（如果有）box86进行安装。这时你可以使用一个假的"uname"，当它的参数为"-m"时返回"x86_64"。
+
+----
+
+关于Unity游戏模拟的注意事项
+----
+
+当前Unity游戏模拟是一件碰运气的事情。Unity使用Mono（它的信号表示，并不总能100%成功模拟）。
+
+您还应该注意，一些Unity3D游戏需要OpenGL 3+，目前在ARM SBC（单板计算机）上提供OpenGL 3+是很棘手的。
+
+所以，并不是所有的Unity游戏都能工作，而且可能需要很高的OpenGL配置，但现在很多游戏都能工作。
+
+提示：如果游戏开始后在显示任何东西之前退出，在Pi4上使用`MESA_GL_VERSION_OVERRIDE=3.2`，在Panfrost上使用`PAN_MESA_DEBUG=gl3`来使用更高的配置文件。
+
+----
+
+关于GTK程序的注意事项
+----
+
+GTK 庫現在包裝在 box64 上，但只有 gtk2，而不是 gtk3（與 box86 相反）。
+
+----
+
+关于Steam的注意事项
+----
+
+Steam并不是32位/64位混合的，而是32位的，因此您需要Box86才能运行Steam。Steam也使用64位的本地服务器程序，但像大多数使用libcef/chromium的程序一样，在box64上暂时无法正常工作。
+所以：目前在box64上无法运行Steam。
+----
+
+关于Wine的注意事项
+----
+
+box64支持64位Wine，但请注意，64位的Wine还包含32位的组件，以便能够运行32位的Windws程序。32位程序需要Box86，没有它就不能运行。在Box64和Box86共存的系统上，设置64位Wine可以同时运行32位和64位windows程序（只需分别使用 `wine` 和 `wine64`）。
+
+----
+
+关于Vulkan注意事项
+----
+
+Box64 包裝 Vulkan 庫。但請注意，它僅使用 RX550 卡進行了測試，根據您的圖形卡，可能會缺少某些擴展。
+
+----
+
+结语
+----
+
+我要感谢所有为 box64 开发做出贡献的人。
+贡献方式有很多种：代码贡献、财务帮助、捐赠捐赠和广告合作！
+以下感谢不分先后： 
+ * 代码贡献：rajdakin, mogery
+ * 财务帮助：FlyingFathead, stormchaser3000
+ * 硬件捐赠：[Radxa](https://rockpi.org/), [Pine64](https://www.pine64.org/), [StarFive](https://rvspace.org/)
+ * 硬件捐赠和LoongArch迁移：[xiaoji](https://www.linuxgame.cn)
+ * 为本项目持续的宣传：salva ([microLinux](https://www.youtube.com/channel/UCwFQAEj1lp3out4n7BeBatQ)), [PILab](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g)/[TwisterOS](https://twisteros.com/) team, [The Byteman](https://www.youtube.com/channel/UCEr8lpIJ3B5Ctc5BvcOHSnA), [NicoD](https://www.youtube.com/channel/UCpv7NFr0-9AB5xoklh3Snhg), ekianjo ([Boilingsteam](https://boilingsteam.com/))
+
+我还要感谢很多人，即使他们只参与了一次本项目。
+
+(如果你的项目中使用了Box64，请不要忘记提及！)

docs/USAGE.md

@@ -31,6 +31,7 @@ Enables/Disables the logging of `dlsym` errors.
 #### BOX64_TRACE_FILE
 Send all log and trace to a file instead of `stdout`
 Also, if name contains `%pid` then this is replaced by the actual PID of box64 instance
+Use `stderr` to use this instead of default `stdout` 
 
 #### BOX64_TRACE
 Only on build with trace enabled. Trace allow the logging of all instruction executed, along with register dump
@@ -77,6 +78,11 @@ Disable handling of SigILL (to ease debugging mainly).
  * 0 : Let x86 program set sighandler for Illegal Instruction
  * 1 : Disables the handling of SigILL 
 
+#### BOX64_SHOWSEGV
+Show Segfault signal even if a signal handler is present
+ * 0 : Don"t force show the SIGSEGV analysis (Default.)
+ * 1 : Show SIGSEGV detail, even if a signal handler is present
+
 #### BOX64_X11THREADS
 Call XInitThreads when loading X11. (This is mostly for old Loki games with the Loki_Compat library.)
  * 0 : Don't force call XInitThreads. (Default.)
@@ -114,6 +120,27 @@ Enables/Disables trace for generated code.
 Forbid dynablock creation in the interval specified (helpfull for debugging behaviour difference between Dynarec and Interpretor)
  * 0xXXXXXXXX-0xYYYYYYYY : define the interval where dynablock cannot start (inclusive-exclusive)
 
+#### BOX64_DYNAREC_BIGBLOCK
+Enables/Disables Box64's Dynarec building BigBlock.
+ * 0 : Don't try to build block as big as possible (can help program using lots of thread and a JIT, like C#/Unity) (Default when libmonobdwgc-2.0.so is loaded)
+ * 1 : Build Dynarec block as big as possible (Default.)
+
+#### BOX64_DYNAREC_STRONGMEM
+Enable/Disable simulation of Strong Memory model
+* 0 : Don't try anything special (Default.)
+* 1 : Enable some Memory Barrier when reading from memory (on some MOV opcode) to simulate Strong Memory Model while trying to limit performance impact (Default when libmonobdwgc-2.0.so is loaded)
+* 2 : Enable some Memory Barrier when reading from memory (on some MOV opcode) to simulate Strong Memory Model
+
+#### BOX64_DYNAREC_X87DOUBLE
+Force the use of Double for x87 emulation
+* 0 : Try to use float when possible for x87 emulation (faster)
+* 1 : Only use Double for x87 emulation (slower, may be needed for some specific games, like Crysis)
+
+#### BOX64_DYNAREC_FASTNAN
+Enable/Disable generation of -NAN
+* 0 : Generate -NAN like on x86 (Default.)
+* 1 : Don't do anything special with NAN, to go as fast as possible (was default before this option exsted)
+
 #### BOX64_LIBGL
  * libXXXX set the name for libGL (defaults to libGL.so.1).
  * /PATH/TO/libGLXXX : Sets the name and path for libGL
@@ -133,8 +160,32 @@ Allow Box64 to continue even if a library is missing.
  * 0 : Box64 will stop if a library cannot be loaded. (Default.)
  * 1 : Continue even if a needed library cannot be loaded. Unadvised, this will, in most cases, crash later on.
 
-#### BOX64_JITGDB
+#### BOX64_PREFER_WRAPPED
+Box64 will use wrapped libs even if the lib is specified with absolute path
+ * 0 : Try to use emulated libs when they are defined with absolute path  (Default.)
+ * 1 : Use Wrapped native libs even if path is absolute
 
+#### BOX64_PREFER_EMULATED
+Box64 will prefer emulated libs first (execpt for glibc, alsa, pulse, GL, vulkan and X11
+ * 0 : Native libs are prefered (Default.)
+ * 1 : Emulated libs are prefered (Default for program running inside pressure-vessel)
+
+#### BOX64_NOPULSE
+Disables the load of pulseaudio libraries.
+ * 0 : Load pulseaudio libraries if found. (Default.)
+ * 1 : Disables the load of pulse audio libraries (libpulse and libpulse-simple), both the native library and the x86 library
+
+#### BOX64_NOGTK
+Disables the loading of wrapped GTK libraries.
+ * 0 : Load wrapped GTK libraries if found. (Default.)
+ * 1 : Disables loading wrapped GTK libraries.
+
+#### BOX64_NOVULKAN
+Disables the load of vulkan libraries.
+ * 0 : Load vulkan libraries if found.
+ * 1 : Disables the load of vulkan libraries, both the native and the i386 version (can be useful on Pi4, where the vulkan driver is not quite there yet.)
+
+#### BOX64_JITGDB
  * 0 : Just print the Segfault message on segfault (default)
  * 1 : Launch `gdb` when a segfault, bus error or illegal instruction signal is trapped, attached to the offending process and go in an endless loop, waiting.
  When in gdb, you need to find the correct thread yourself (the one with `my_box64signalhandler` in is stack)

pkgbuilds/PKGBUILD-arm64

@@ -0,0 +1,44 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-arm64-git
+pkgver=r1495.e6e9fae
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-arm64-git}-git" "${pkgname%-arm64-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-arm64-git}-git" "${pkgname%-arm64-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-arm64-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-arm64-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DARM_DYNAREC=ON -DCMAKE_BUILD_TYPE=RelWithDebInfo
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-arm64-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-arm64-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}

pkgbuilds/PKGBUILD-arm64-DEBUG

@@ -0,0 +1,44 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-arm64-git
+pkgver=r1495.e6e9fae
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-arm64-git}-git" "${pkgname%-arm64-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-arm64-git}-git" "${pkgname%-arm64-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-arm64-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-arm64-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DARM_DYNAREC=ON -DCMAKE_BUILD_TYPE=Debug
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-arm64-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-arm64-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}

pkgbuilds/PKGBUILD-lx2160a

@@ -0,0 +1,44 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-lx2160a-git
+pkgver=r1495.e6e9fae
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-lx2160a-git}-git" "${pkgname%-lx2160a-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-lx2160a-git}-git" "${pkgname%-lx2160a-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-lx2160a-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-lx2160a-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DLX2160A=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-lx2160a-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-lx2160a-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}

pkgbuilds/PKGBUILD-lx2160a-DEBUG

@@ -0,0 +1,44 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-lx2160a-git
+pkgver=r1495.e6e9fae
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-lx2160a-git}-git" "${pkgname%-lx2160a-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-lx2160a-git}-git" "${pkgname%-lx2160a-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-lx2160a-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-lx2160a-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DLX2160A=1 -DCMAKE_BUILD_TYPE=Debug
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-lx2160a-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-lx2160a-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}

pkgbuilds/PKGBUILD-rk3399

@@ -0,0 +1,44 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box86-rk3399-git
+pkgver=r1495.e6e9fae
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-rk3399-git}-git" "${pkgname%-rk3399-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-rk3399-git}-git" "${pkgname%-rk3399-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-rk3399-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-rk3399-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+                cmake .. -DRK3399=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-rk3399-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-rk3399-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}

pkgbuilds/PKGBUILD-rk3399-DEBUG

@@ -0,0 +1,44 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box86-rk3399-git
+pkgver=r1495.e6e9fae
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-rk3399-git}-git" "${pkgname%-rk3399-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-rk3399-git}-git" "${pkgname%-rk3399-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-rk3399-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-rk3399-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+                cmake .. -DRK3399=1 -DCMAKE_BUILD_TYPE=Debug
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-rk3399-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-rk3399-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}

pkgbuilds/PKGBUILD-rpi4

@@ -0,0 +1,44 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-rpi-git
+pkgver=r1495.e6e9fae
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-rpi-git}-git" "${pkgname%-rpi-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-rpi-git}-git" "${pkgname%-rpi-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-rpi-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-rpi-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DRPI4ARM64=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-rpi-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-rpi-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}

pkgbuilds/PKGBUILD-rpi4-DEBUG

@@ -0,0 +1,44 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-rpi-git
+pkgver=r1495.e6e9fae
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-rpi-git}-git" "${pkgname%-rpi-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-rpi-git}-git" "${pkgname%-rpi-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-rpi-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-rpi-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DRPI4ARM64=1 -DCMAKE_BUILD_TYPE=Debug
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-rpi-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-rpi-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}

pkgbuilds/PKGBUILD-tegra

@@ -0,0 +1,44 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-tegra-git
+pkgver=r1495.e6e9fae
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-tegra-git}-git" "${pkgname%-tegra-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-tegra-git}-git" "${pkgname%-tegra-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-tegra-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-tegra-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DTEGRAX1=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-tegra-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-tegra-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}

pkgbuilds/PKGBUILD-tegra-DEBUG

@@ -0,0 +1,44 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-tegra-git
+pkgver=r1495.e6e9fae
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-tegra-git}-git" "${pkgname%-tegra-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-tegra-git}-git" "${pkgname%-tegra-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-tegra-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-tegra-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DTEGRAX1=1 -DCMAKE_BUILD_TYPE=Debug
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-tegra-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-tegra-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}

pkgbuilds/PKGBUILD-x86_64

@@ -0,0 +1,43 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-x64-git
+pkgver=r1495.e6e9fae
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-x64-git}-git" "${pkgname%-x64-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-x64-git}-git" "${pkgname%-x64-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-x64-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-x64-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DLD80BITS=1 -DNOALIGN=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-x64-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-x64-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}

pkgbuilds/PKGBUILD-x86_64-DEBUG

@@ -0,0 +1,43 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-x64-git
+pkgver=r1495.e6e9fae
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-x64-git}-git" "${pkgname%-x64-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-x64-git}-git" "${pkgname%-x64-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "$srcdir/${pkgname%-x64-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-x64-git}"
+	if [[ ! -d ./build ]]; then
+		mkdir build && cd build
+		cmake .. -DLD80BITS=1 -DNOALIGN=1 -DCMAKE_BUILD_TYPE=Debug
+	fi
+}
+
+build() {
+	cd "$srcdir/${pkgname%-x64-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "$srcdir/${pkgname%-x64-git}/build"
+	make DESTDIR="${pkgdir}/" install
+	# /usr/local/bin isn't in PATH by the default,
+	# we should move it to /usr/bin
+	cd ${pkgdir}
+	mv usr/local/bin/ usr/bin/
+	# cleanup when dir is empty
+	rmdir usr/local || exit 0
+}

pkgbuilds/README.md

@@ -0,0 +1,24 @@
+# The directory containing all PKGBUILDs for BOX64
+## FAQ
+### 1. How to use it?
+Just download the `PKGBUILD-<your-platform>` (no need to download the whole repository), go to directory where you downloaded and type:
+```sh
+mv ./PKGBUILD-<your-platform> ./PKGBUILD
+cd ..
+makepkg -si
+```
+This will copy the PKGBUILD for your platform (where you type your platform name instead of `<your-platform>`), build it and install the PKGBUILD on 64-bit Archlinux ARM.
+
+In the future, I might try to do an unified PKGBUILD for all platforms that will recognize your platform automatically.
+
+### 2. What platforms are currently supported.
+All specified in [COMPILE.md](../docs/COMPILE.md).
+
+### 3. Any advantages with this solution?
+This might give you some advantages like:
+- automatic updates (with some AUR frontends like [`pamac-aur`](https://aur.archlinux.org/packages/pamac-aur/) or [`yay`](https://aur.archlinux.org/packages/yay));
+- easily uninstall with `pacman -R` when no needed (no need other scripts nor Makefile to do this);
+- your `box64` installation is recognized as a package (where it wasn't when installing with `make install`).
+
+
+### Note: You can use [makedeb](https://github.com/makedeb/makedeb) (or) [pkgbuild2spec](https://github.com/prozum/pkgbuild2spec) to compile box64 to .deb or .rpm installer files.

postinst

@@ -0,0 +1,2 @@
+#!/bin/sh
+systemctl restart systemd-binfmt

runTest.cmake

@@ -32,6 +32,9 @@ execute_process(
 
 # if the return value is !=0 bail out
 if( TEST_RESULT )
+  get_filename_component(TESTNAME "${TEST_ARGS}" NAME)
+  file(RENAME "${TEST_OUTPUT}" "${CMAKE_BINARY_DIR}/${TESTNAME}.out")
+  file(WRITE  "${CMAKE_BINARY_DIR}/${TESTNAME}.err" ${TEST_ERROR})
   message( FATAL_ERROR "Failed: Test program ${TEST_PROGRAM} exited != 0.\n${TEST_ERROR}" )
 endif( TEST_RESULT )
 
@@ -43,8 +46,16 @@ execute_process(
 
 # again, if return value is !=0 scream and shout
 if( TEST_RESULT )
+  get_filename_component(TESTNAME "${TEST_ARGS}" NAME)
+  file(RENAME "${TEST_OUTPUT}" "${CMAKE_BINARY_DIR}/${TESTNAME}.out")
+  file(WRITE  "${CMAKE_BINARY_DIR}/${TESTNAME}.err" ${TEST_ERROR})
   message( FATAL_ERROR "Failed: The output of ${TEST_PROGRAM} did not match ${TEST_REFERENCE}")
 endif( TEST_RESULT )
 
+# remove the temporary files if they exist
+if( EXISTS ${TEST_OUTPUT} )
+  file(REMOVE "${TEST_OUTPUT}")
+endif()
+
 # everything went fine...
 message( "Passed: The output of ${TEST_PROGRAM} matches ${TEST_REFERENCE}" )

src/box64context.c

@@ -5,6 +5,7 @@
 #include <dlfcn.h>
 #include <signal.h>
 #include <sys/mman.h>
+#include <pthread.h>
 
 #include "box64context.h"
 #include "debug.h"
@@ -73,9 +74,8 @@ int unlockMutex()
     int ret = unlockCustommemMutex();
     int i;
     #define GO(A, B)                    \
-        i = checkMutex(&A);             \
+        i = checkUnlockMutex(&A);       \
         if(i) {                         \
-            pthread_mutex_unlock(&A);   \
             ret|=(1<<B);                \
         }
 
@@ -89,6 +89,7 @@ int unlockMutex()
     #endif
     GO(my_context->mutex_tls, 9)
     GO(my_context->mutex_thread, 10)
+    GO(my_context->mutex_bridge, 11)
     #undef GO
 
     return ret;
@@ -111,6 +112,7 @@ void relockMutex(int locks)
     #endif
     GO(my_context->mutex_tls, 9)
     GO(my_context->mutex_thread, 10)
+    GO(my_context->mutex_bridge, 11)
     #undef GO
 }
 
@@ -129,6 +131,7 @@ static void init_mutexes(box64context_t* context)
 #endif
     pthread_mutex_init(&context->mutex_tls, &attr);
     pthread_mutex_init(&context->mutex_thread, &attr);
+    pthread_mutex_init(&context->mutex_bridge, &attr);
 
     pthread_mutexattr_destroy(&attr);
 }
@@ -158,9 +161,19 @@ box64context_t *NewBox64Context(int argc)
 
     context->maplib = NewLibrarian(context, 1);
     context->local_maplib = NewLibrarian(context, 1);
+    context->versym = NewDictionnary();
     context->system = NewBridge();
     // create vsyscall
-    context->vsyscall = AddBridge(context->system, vFv, x64Syscall, 0, NULL);
+    context->vsyscall = AddBridge(context->system, vFEv, x64Syscall, 0, NULL);
+    // create the vsyscalls
+    context->vsyscalls[0] = AddVSyscall(context->system, 96);
+    context->vsyscalls[1] = AddVSyscall(context->system, 201);
+    context->vsyscalls[2] = AddVSyscall(context->system, 309);
+    // create the alternate to map at address
+    addAlternate((void*)0xffffffffff600000, (void*)context->vsyscalls[0]);
+    addAlternate((void*)0xffffffffff600400, (void*)context->vsyscalls[1]);
+    addAlternate((void*)0xffffffffff600800, (void*)context->vsyscalls[2]);
+    // get handle to box64 itself
     context->box64lib = dlopen(NULL, RTLD_NOW|RTLD_GLOBAL);
     context->dlprivate = NewDLPrivate();
 
@@ -175,7 +188,7 @@ box64context_t *NewBox64Context(int argc)
 
     for (int i=0; i<8; ++i) context->canary[i] = 1 +  getrand(255);
     context->canary[getrand(4)] = 0;
-    printf_log(LOG_DEBUG, "Setting up canary (for Stack protector) at FS:0x14, value:%08X\n", *(uint32_t*)context->canary);
+    printf_log(LOG_DEBUG, "Setting up canary (for Stack protector) at FS:0x28, value:%08X\n", *(uint32_t*)context->canary);
 
     initAllHelpers(context);
 
@@ -197,6 +210,7 @@ void FreeBox64Context(box64context_t** context)
         FreeLibrarian(&ctx->local_maplib, NULL);
     if(ctx->maplib)
         FreeLibrarian(&ctx->maplib, NULL);
+    FreeDictionnary(&ctx->versym);
 
     for(int i=0; i<ctx->elfsize; ++i) {
         FreeElfHeader(&ctx->elfs[i]);
@@ -246,6 +260,9 @@ void FreeBox64Context(box64context_t** context)
     freeGLProcWrapper(ctx);
     freeALProcWrapper(ctx);
 
+    if(ctx->stack_clone)
+        free(ctx->stack_clone);
+
 
     void* ptr;
     if ((ptr = pthread_getspecific(ctx->tlskey)) != NULL) {
@@ -257,6 +274,13 @@ void FreeBox64Context(box64context_t** context)
     if(ctx->tlsdata)
         free(ctx->tlsdata);
 
+    free_neededlib(&ctx->neededlibs);
+
+    if(ctx->emu_sig)
+        FreeX64Emu(&ctx->emu_sig);
+
+    finiAllHelpers(ctx);
+
     pthread_mutex_destroy(&ctx->mutex_once);
     pthread_mutex_destroy(&ctx->mutex_once2);
     pthread_mutex_destroy(&ctx->mutex_trace);
@@ -267,13 +291,7 @@ void FreeBox64Context(box64context_t** context)
 #endif
     pthread_mutex_destroy(&ctx->mutex_tls);
     pthread_mutex_destroy(&ctx->mutex_thread);
-
-    free_neededlib(&ctx->neededlibs);
-
-    if(ctx->emu_sig)
-        FreeX64Emu(&ctx->emu_sig);
-
-    finiAllHelpers(ctx);
+    pthread_mutex_destroy(&ctx->mutex_bridge);
 
     free(ctx);
 }
@@ -311,6 +329,9 @@ void add_neededlib(needed_libs_t* needed, library_t* lib)
 {
     if(!needed)
         return;
+    for(int i=0; i<needed->size; ++i)
+        if(needed->libs[i] == lib)
+            return;
     if(needed->size == needed->cap) {
         needed->cap += 8;
         needed->libs = (library_t**)realloc(needed->libs, needed->cap*sizeof(library_t*));
@@ -333,6 +354,9 @@ void add_dependedlib(needed_libs_t* depended, library_t* lib)
 {
     if(!depended)
         return;
+    for(int i=0; i<depended->size; ++i)
+        if(depended->libs[i] == lib)
+            return;
     if(depended->size == depended->cap) {
         depended->cap += 8;
         depended->libs = (library_t**)realloc(depended->libs, depended->cap*sizeof(library_t*));

src/box64version.h

@@ -2,7 +2,7 @@
 #define __BOX64_VERSION_H_
 
 #define BOX64_MAJOR 0
-#define BOX64_MINOR 0
+#define BOX64_MINOR 1
 #define BOX64_REVISION 8
 
 #endif //__BOX64_VERSION_H_

src/dynarec/arm64/arm64_emitter.h

@@ -110,8 +110,9 @@
 #define MOVKw(Rd, imm16)                    EMIT(MOVK_gen(0, 0, ((uint16_t)imm16)&0xffff, Rd))
 #define MOVKw_LSL(Rd, imm16, shift)         EMIT(MOVK_gen(0, (shift)/16, ((uint16_t)imm16)&0xffff, Rd))
 
+// This macro will give a -Wsign-compare warning, probably bug #38341
 #define MOV32w(Rd, imm32) \
-    if(~((uint32_t)(imm32))<0xffff) {                                       \
+    if(~((uint32_t)(imm32))<0xffffu) {                                      \
         MOVNw(Rd, (~(uint32_t)(imm32))&0xffff);                             \
     } else {                                                                \
         MOVZw(Rd, (imm32)&0xffff);                                          \
@@ -193,6 +194,10 @@
 #define SBCSw_REG(Rd, Rn, Rm)       EMIT(ADDSUBC_gen(0, 1, 1, Rm, Rn, Rd))
 #define SBCSxw_REG(Rd, Rn, Rm)      EMIT(ADDSUBC_gen(rex.w, 1, 1, Rm, Rn, Rd))
 
+// ADR
+#define ADR_gen(immlo, immhi, Rd)   ((immlo)<<29 | 0b10000<<24 | (immhi)<<5 | (Rd))
+#define ADR_S20(Rd, imm)            EMIT(ADR_gen((imm)&3, ((imm)>>2)&0x7ffff, (Rd))
+
 // LDR
 #define LDR_gen(size, op1, imm9, op2, Rn, Rt)    ((size)<<30 | 0b111<<27 | (op1)<<24 | 0b01<<22 | (imm9)<<12 | (op2)<<10 | (Rn)<<5 | (Rt))
 #define LDRx_S9_postindex(Rt, Rn, imm9)   EMIT(LDR_gen(0b11, 0b00, (imm9)&0x1ff, 0b01, Rn, Rt))
@@ -210,14 +215,14 @@
 #define LDRSW_S9_preindex(Rt, Rn, imm9)   EMIT(LDRS_gen(0b10, 0b00, (imm9)&0x1ff, 0b11, Rn, Rt))
 
 #define LD_gen(size, op1, imm12, Rn, Rt)        ((size)<<30 | 0b111<<27 | (op1)<<24 | 0b01<<22 | (imm12)<<10 | (Rn)<<5 | (Rt))
-#define LDRx_U12(Rt, Rn, imm12)           EMIT(LD_gen(0b11, 0b01, ((uint32_t)(imm12>>3))&0xfff, Rn, Rt))
-#define LDRw_U12(Rt, Rn, imm12)           EMIT(LD_gen(0b10, 0b01, ((uint32_t)(imm12>>2))&0xfff, Rn, Rt))
-#define LDRB_U12(Rt, Rn, imm12)           EMIT(LD_gen(0b00, 0b01, ((uint32_t)(imm12))&0xfff, Rn, Rt))
-#define LDRH_U12(Rt, Rn, imm12)           EMIT(LD_gen(0b01, 0b01, ((uint32_t)(imm12>>1))&0xfff, Rn, Rt))
-#define LDRxw_U12(Rt, Rn, imm12)          EMIT(LD_gen((rex.w)?0b11:0b10, 0b01, ((uint32_t)(imm12>>(2+rex.w)))&0xfff, Rn, Rt))
+#define LDRx_U12(Rt, Rn, imm12)           EMIT(LD_gen(0b11, 0b01, ((uint32_t)((imm12)>>3))&0xfff, Rn, Rt))
+#define LDRw_U12(Rt, Rn, imm12)           EMIT(LD_gen(0b10, 0b01, ((uint32_t)((imm12)>>2))&0xfff, Rn, Rt))
+#define LDRB_U12(Rt, Rn, imm12)           EMIT(LD_gen(0b00, 0b01, ((uint32_t)((imm12)))&0xfff, Rn, Rt))
+#define LDRH_U12(Rt, Rn, imm12)           EMIT(LD_gen(0b01, 0b01, ((uint32_t)((imm12)>>1))&0xfff, Rn, Rt))
+#define LDRxw_U12(Rt, Rn, imm12)          EMIT(LD_gen((rex.w)?0b11:0b10, 0b01, ((uint32_t)((imm12)>>(2+rex.w)))&0xfff, Rn, Rt))
 
 #define LDS_gen(size, op1, imm12, Rn, Rt)       ((size)<<30 | 0b111<<27 | (op1)<<24 | 0b10<<22 | (imm12)<<10 | (Rn)<<5 | (Rt))
-#define LDRSW_U12(Rt, Rn, imm12)          EMIT(LDS_gen(0b10, 0b01, ((uint32_t)(imm12>>2))&0xfff, Rn, Rt))
+#define LDRSW_U12(Rt, Rn, imm12)          EMIT(LDS_gen(0b10, 0b01, ((uint32_t)((imm12)>>2))&0xfff, Rn, Rt))
 
 #define LDR_REG_gen(size, Rm, option, S, Rn, Rt)    ((size)<<30 | 0b111<<27 | 0b01<<22 | 1<<21 | (Rm)<<16 | (option)<<13 | (S)<<12 | (0b10)<<10 | (Rn)<<5 | (Rt))
 #define LDRx_REG(Rt, Rn, Rm)            EMIT(LDR_REG_gen(0b11, Rm, 0b011, 0, Rn, Rt))
@@ -229,13 +234,16 @@
 #define LDRB_REG(Rt, Rn, Rm)            EMIT(LDR_REG_gen(0b00, Rm, 0b011, 0, Rn, Rt))
 #define LDRH_REG(Rt, Rn, Rm)            EMIT(LDR_REG_gen(0b01, Rm, 0b011, 0, Rn, Rt))
 
-#define LDRSH_gen(size, op1, opc, imm12, Rn, Rt)    ((size)<<30 | 0b111<<27 | (op1)<<24 | (opc)<<22 | (imm12)<<10 | (Rn)<<5 | (Rt))
-#define LDRSHx_U12(Rt, Rn, imm12)           EMIT(LDRSH_gen(0b01, 0b01, 0b10, ((uint32_t)(imm12>>1))&0xfff, Rn, Rt))
-#define LDRSHw_U12(Rt, Rn, imm12)           EMIT(LDRSH_gen(0b01, 0b01, 0b11, ((uint32_t)(imm12>>1))&0xfff, Rn, Rt))
-#define LDRSHxw_U12(Rt, Rn, imm12)          EMIT(LDRSH_gen(0b01, 0b01, rex.w?0b10:0b11, ((uint32_t)(imm12>>1))&0xfff, Rn, Rt))
-#define LDRSBx_U12(Rt, Rn, imm12)           EMIT(LDRSH_gen(0b00, 0b01, 0b10, ((uint32_t)(imm12>>0))&0xfff, Rn, Rt))
-#define LDRSBw_U12(Rt, Rn, imm12)           EMIT(LDRSH_gen(0b00, 0b01, 0b11, ((uint32_t)(imm12>>0))&0xfff, Rn, Rt))
-#define LDRSBxw_U12(Rt, Rn, imm12)          EMIT(LDRSH_gen(0b00, 0b01, rex.w?0b10:0b11, ((uint32_t)(imm12>>0))&0xfff, Rn, Rt))
+#define LDRS_U12_gen(size, op1, opc, imm12, Rn, Rt)    ((size)<<30 | 0b111<<27 | (op1)<<24 | (opc)<<22 | (imm12)<<10 | (Rn)<<5 | (Rt))
+#define LDRSHx_U12(Rt, Rn, imm12)           EMIT(LDRS_U12_gen(0b01, 0b01, 0b10, ((uint32_t)(imm12>>1))&0xfff, Rn, Rt))
+#define LDRSHw_U12(Rt, Rn, imm12)           EMIT(LDRS_U12_gen(0b01, 0b01, 0b11, ((uint32_t)(imm12>>1))&0xfff, Rn, Rt))
+#define LDRSHxw_U12(Rt, Rn, imm12)          EMIT(LDRS_U12_gen(0b01, 0b01, rex.w?0b10:0b11, ((uint32_t)(imm12>>1))&0xfff, Rn, Rt))
+#define LDRSBx_U12(Rt, Rn, imm12)           EMIT(LDRS_U12_gen(0b00, 0b01, 0b10, ((uint32_t)(imm12>>0))&0xfff, Rn, Rt))
+#define LDRSBw_U12(Rt, Rn, imm12)           EMIT(LDRS_U12_gen(0b00, 0b01, 0b11, ((uint32_t)(imm12>>0))&0xfff, Rn, Rt))
+#define LDRSBxw_U12(Rt, Rn, imm12)          EMIT(LDRS_U12_gen(0b00, 0b01, rex.w?0b10:0b11, ((uint32_t)(imm12>>0))&0xfff, Rn, Rt))
+
+#define LDRS_REG_gen(size, Rm, option, S, Rn, Rt)    ((size)<<30 | 0b111<<27 | 0b10<<22 | 1<<21 | (Rm)<<16 | (option)<<13 | (S)<<12 | (0b10)<<10 | (Rn)<<5 | (Rt))
+#define LDRSW_REG(Rt, Rn, Rm)           EMIT(LDRS_REG_gen(0b10, Rm, 0b011, 0, Rn, Rt))
 
 #define LDR_PC_gen(opc, imm19, Rt)      ((opc)<<30 | 0b011<<27 | (imm19)<<5 | (Rt))
 #define LDRx_literal(Rt, imm19)         EMIT(LDR_PC_gen(0b01, ((imm19)>>2)&0x7FFFF, Rt))
@@ -251,10 +259,10 @@
 #define STRH_S9_postindex(Rt, Rn, imm9)   EMIT(STR_gen(0b01, 0b00, (imm9)&0x1ff, 0b01, Rn, Rt))
 
 #define ST_gen(size, op1, imm12, Rn, Rt)        ((size)<<30 | 0b111<<27 | (op1)<<24 | 0b00<<22 | (imm12)<<10 | (Rn)<<5 | (Rt))
-#define STRx_U12(Rt, Rn, imm12)           EMIT(ST_gen(0b11, 0b01, ((uint32_t)(imm12>>3))&0xfff, Rn, Rt))
-#define STRw_U12(Rt, Rn, imm12)           EMIT(ST_gen(0b10, 0b01, ((uint32_t)(imm12>>2))&0xfff, Rn, Rt))
-#define STRB_U12(Rt, Rn, imm12)           EMIT(ST_gen(0b00, 0b01, ((uint32_t)(imm12))&0xfff, Rn, Rt))
-#define STRH_U12(Rt, Rn, imm12)           EMIT(ST_gen(0b01, 0b01, ((uint32_t)(imm12>>1))&0xfff, Rn, Rt))
+#define STRx_U12(Rt, Rn, imm12)           EMIT(ST_gen(0b11, 0b01, ((uint32_t)((imm12)>>3))&0xfff, Rn, Rt))
+#define STRw_U12(Rt, Rn, imm12)           EMIT(ST_gen(0b10, 0b01, ((uint32_t)((imm12)>>2))&0xfff, Rn, Rt))
+#define STRB_U12(Rt, Rn, imm12)           EMIT(ST_gen(0b00, 0b01, ((uint32_t)((imm12)))&0xfff, Rn, Rt))
+#define STRH_U12(Rt, Rn, imm12)           EMIT(ST_gen(0b01, 0b01, ((uint32_t)((imm12)>>1))&0xfff, Rn, Rt))
 #define STRxw_U12(Rt, Rn, imm12)          EMIT(ST_gen((rex.w)?0b11:0b10, 0b01, ((uint32_t)((imm12)>>(2+rex.w)))&0xfff, Rn, Rt))
 
 #define STR_REG_gen(size, Rm, option, S, Rn, Rt)    ((size)<<30 | 0b111<<27 | 0b00<<22 | 1<<21 | (Rm)<<16 | (option)<<13 | (S)<<12 | (0b10)<<10 | (Rn)<<5 | (Rt))
@@ -345,6 +353,11 @@
 #define PLD_L2_STREAM_U12(Rn, imm12)    EMIT(PRFM_imm(((imm12)>>3)&0xfff, Rn, 0b00011))
 #define PLD_L3_STREAM_U12(Rn, imm12)    EMIT(PRFM_imm(((imm12)>>3)&0xfff, Rn, 0b00101))
 
+#define PST_L1_STREAM_U12(Rn, imm12)    EMIT(PRFM_imm(((imm12)>>3)&0xfff, Rn, 0b01001))
+
+// Data Memory Barrier
+#define DMB_gen(CRm)                    (0b1101010100<<22 | 0b011<<16 | 0b0011<<12 | (CRm)<<8 | 1<<7 | 0b01<<5 | 0b11111)
+#define DMB_ISH()                       EMIT(DMB_gen(0b1011))
 
 // BR and Branches
 #define BR_gen(Z, op, A, M, Rn, Rm)       (0b1101011<<25 | (Z)<<24 | (op)<<21 | 0b11111<<16 | (A)<<11 | (M)<<10 | (Rn)<<5 | (Rm))
@@ -430,11 +443,16 @@
 #define ORRx_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(1, 0b01, 0b00, 0, Rm, 0, Rn, Rd))
 #define ORRx_REG_LSL(Rd, Rn, Rm, lsl)   EMIT(LOGIC_REG_gen(1, 0b01, 0b00, 0, Rm, lsl, Rn, Rd))
 #define ORRw_REG_LSL(Rd, Rn, Rm, lsl)   EMIT(LOGIC_REG_gen(0, 0b01, 0b00, 0, Rm, lsl, Rn, Rd))
+#define ORRxw_REG_LSL(Rd, Rn, Rm, lsl)  EMIT(LOGIC_REG_gen(rex.w, 0b01, 0b00, 0, Rm, lsl, Rn, Rd))
+#define ORRx_REG_LSR(Rd, Rn, Rm, lsr)   EMIT(LOGIC_REG_gen(1, 0b01, 0b01, 0, Rm, lsr, Rn, Rd))
+#define ORRw_REG_LSR(Rd, Rn, Rm, lsr)   EMIT(LOGIC_REG_gen(0, 0b01, 0b01, 0, Rm, lsr, Rn, Rd))
+#define ORRxw_REG_LSR(Rd, Rn, Rm, lsr)  EMIT(LOGIC_REG_gen(rex.w, 0b01, 0b01, 0, Rm, lsr, Rn, Rd))
 #define ORRxw_REG(Rd, Rn, Rm)           EMIT(LOGIC_REG_gen(rex.w, 0b01, 0b00, 0, Rm, 0, Rn, Rd))
 #define ORRw_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(0, 0b01, 0b00, 0, Rm, 0, Rn, Rd))
 #define ORNx_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(1, 0b01, 0b00, 1, Rm, 0, Rn, Rd))
 #define ORNw_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(0, 0b01, 0b00, 1, Rm, 0, Rn, Rd))
 #define ORNxw_REG(Rd, Rn, Rm)           EMIT(LOGIC_REG_gen(rex.w, 0b01, 0b00, 1, Rm, 0, Rn, Rd))
+#define ORNx_REG_LSL(Rd, Rn, Rm, lsl)   EMIT(LOGIC_REG_gen(1, 0b01, 0b00, 1, Rm, lsl, Rn, Rd))
 #define EORx_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(1, 0b10, 0b00, 0, Rm, 0, Rn, Rd))
 #define EORw_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(0, 0b10, 0b00, 0, Rm, 0, Rn, Rd))
 #define EORxw_REG(Rd, Rn, Rm)           EMIT(LOGIC_REG_gen(rex.w, 0b10, 0b00, 0, Rm, 0, Rn, Rd))
@@ -447,6 +465,12 @@
 #define MOVx_REG(Rd, Rm)                ORRx_REG(Rd, xZR, Rm)
 #define MOVw_REG(Rd, Rm)                ORRw_REG(Rd, xZR, Rm)
 #define MOVxw_REG(Rd, Rm)               ORRxw_REG(Rd, xZR, Rm)
+#define LSLw_IMM(Rd, Rm, lsl)           ORRw_REG_LSL(Rd, xZR, Rm, lsl)
+#define LSLx_IMM(Rd, Rm, lsl)           ORRx_REG_LSL(Rd, xZR, Rm, lsl)
+#define LSLxw_IMM(Rd, Rm, lsl)          ORRxw_REG_LSL(Rd, xZR, Rm, lsl)
+#define LSRw_IMM(Rd, Rm, lsr)           ORRw_REG_LSR(Rd, xZR, Rm, lsr)
+#define LSRx_IMM(Rd, Rm, lsr)           ORRx_REG_LSR(Rd, xZR, Rm, lsr)
+#define LSRxw_IMM(Rd, Rm, lsr)          ORRxw_REG_LSR(Rd, xZR, Rm, lsr)
 #define MVNx_REG(Rd, Rm)                ORNx_REG(Rd, xZR, Rm)
 #define MVNx_REG_LSL(Rd, Rm, lsl)       ORNx_REG_LSL(Rd, xZR, Rm, lsl)
 #define MVNw_REG(Rd, Rm)                ORNw_REG(Rd, xZR, Rm)
@@ -575,13 +599,27 @@
 #define UMULH(Xd, Xn, Xm)               EMIT(MULH_gen(1, Xm, Xn, Xd))
 #define SMULH(Xd, Xn, Xm)               EMIT(MULH_gen(0, Xm, Xn, Xd))
 
-#define MADD_gen(sf, Rm, Ra, Rn, Rd)    ((sf)<<31 | 0b11011<<24 | (Rm)<<16 | (Ra)<<10 | (Rn)<<5 | (Rd))
-#define MADDx(Rd, Rn, Rm, Ra)           EMIT(MADD_gen(1, Rm, Ra, Rn, Rd))
-#define MADDw(Rd, Rn, Rm, Ra)           EMIT(MADD_gen(0, Rm, Ra, Rn, Rd))
-#define MADDxw(Rd, Rn, Rm, Ra)          EMIT(MADD_gen(rex.w, Rm, Ra, Rn, Rd))
+#define MADD_gen(sf, Rm, o0, Ra, Rn, Rd)    ((sf)<<31 | 0b11011<<24 | (Rm)<<16 | (o0)<<15 | (Ra)<<10 | (Rn)<<5 | (Rd))
+#define MADDx(Rd, Rn, Rm, Ra)           EMIT(MADD_gen(1, Rm, 0, Ra, Rn, Rd))
+#define MADDw(Rd, Rn, Rm, Ra)           EMIT(MADD_gen(0, Rm, 0, Ra, Rn, Rd))
+#define MADDxw(Rd, Rn, Rm, Ra)          EMIT(MADD_gen(rex.w, Rm, 0, Ra, Rn, Rd))
 #define MULx(Rd, Rn, Rm)                MADDx(Rd, Rn, Rm, xZR)
 #define MULw(Rd, Rn, Rm)                MADDw(Rd, Rn, Rm, xZR)
 #define MULxw(Rd, Rn, Rm)               MADDxw(Rd, Rn, Rm, xZR)
+#define MSUBx(Rd, Rn, Rm, Ra)           EMIT(MADD_gen(1, Rm, 1, Ra, Rn, Rd))
+#define MSUBw(Rd, Rn, Rm, Ra)           EMIT(MADD_gen(0, Rm, 1, Ra, Rn, Rd))
+#define MSUBxw(Rd, Rn, Rm, Ra)          EMIT(MADD_gen(rex.w, Rm, 1, Ra, Rn, Rd))
+#define MNEGx(Rd, Rn, Rm)               EMIT(MADD_gen(1, Rm, 1, xZR, Rn, Rd))
+#define MNEGw(Rd, Rn, Rm)               EMIT(MADD_gen(0, Rm, 1, xZR, Rn, Rd))
+#define MNEGxw(Rd, Rn, Rm)              EMIT(MADD_gen(rex.w, Rm, 1, xZR, Rn, Rd))
+
+
+// DIV
+#define DIV_gen(sf, Rm, o1, Rn, Rd)     ((sf)<<31 | 0b11010110<<21 | (Rm)<<16 | 0b00001<<11 | (o1)<<10 | (Rn)<<5 | (Rd))
+#define UDIVw(Wd, Wn, Wm)               EMIT(DIV_gen(0, Wm, 0, Wn, Wd))
+#define UDIVx(Xd, Xn, Xm)               EMIT(DIV_gen(1, Xm, 0, Xn, Xd))
+#define SDIVw(Wd, Wn, Wm)               EMIT(DIV_gen(0, Wm, 1, Wn, Wd))
+#define SDIVx(Xd, Xn, Xm)               EMIT(DIV_gen(1, Xm, 1, Xn, Xd))
 
 // CLZ
 #define CL_gen(sf, op, Rn, Rd)          ((sf)<<31 | 1<<30 | 0b11010110<<21 | 0b00010<<11 | (op)<<10 | (Rn)<<5 | (Rd))
@@ -600,9 +638,11 @@
 
 // REV
 #define REV_gen(sf, opc, Rn, Rd)        ((sf)<<31 | 1<<30 | 0b11010110<<21 | (opc)<<10 | (Rn)<<5 | (Rd))
-#define REVx(Rd, Rn)                    EMIT(REV_gen(1, 0b11, Rn, Rd))
-#define REVw(Rd, Rn)                    EMIT(REV_gen(0, 0b10, Rn, Rd))
+#define REV64x(Rd, Rn)                  EMIT(REV_gen(1, 0b11, Rn, Rd))
+#define REV32w(Rd, Rn)                  EMIT(REV_gen(0, 0b10, Rn, Rd))
 #define REVxw(Rd, Rn)                   EMIT(REV_gen(rex.w, 0b10|rex.w, Rn, Rd))
+#define REV16w(Rd, Rn)                  EMIT(REV_gen(0, 0b01, Rn, Rd))
+#define REV16x(Rd, Rn)                  EMIT(REV_gen(1, 0b01, Rn, Rd))
 
 // MRS
 #define MRS_gen(L, o0, op1, CRn, CRm, op2, Rt)  (0b1101010100<<22 | (L)<<21 | 1<<20 | (o0)<<19 | (op1)<<16 | (CRn)<<12 | (CRm)<<8 | (op2)<<5 | (Rt))
@@ -740,6 +780,7 @@
 
 #define SHL_scalar(U, size, Rm, R, S, Rn, Rd)   (0b01<<30 | (U)<<29 | 0b11110<<24 | (size)<<22 | 1<<21 | (Rm)<<16 | 0b010<<13 | (R)<<12 | (S)<<11 | 1<<10 | (Rn)<<5 | (Rd))
 #define SSHL_R_64(Vd, Vn, Vm)               EMIT(SHL_scalar(0, 0b11, Vm, 0, 0, Vn, Vd))
+#define USHL_R_64(Vd, Vn, Vm)               EMIT(SHL_scalar(1, 0b11, Vm, 0, 0, Vn, Vd))
 
 #define SHL_scalar_imm(U, immh, immb, Rn, Rd)   (0b01<<30 | 0b111110<<23 | (immh)<<19 | (immb)<<16 | 0b01010<<11 | 1<<10 | (Rn)<<5 | (Rd))
 #define SHL_64(Vd, Vn, shift)               EMIT(SHL_scalar_imm(0, 0b1000 | (((shift)>>3)&7), (shift)&7, Vn, Vd))
@@ -752,6 +793,13 @@
 #define SSHLQ_16(Vd, Vn, Vm)                EMIT(SHL_vector_vector(1, 0, 0b01, Vm, 0, 0, Vn, Vd))
 #define SSHLQ_32(Vd, Vn, Vm)                EMIT(SHL_vector_vector(1, 0, 0b10, Vm, 0, 0, Vn, Vd))
 #define SSHLQ_64(Vd, Vn, Vm)                EMIT(SHL_vector_vector(1, 0, 0b11, Vm, 0, 0, Vn, Vd))
+#define USHL_8(Vd, Vn, Vm)                  EMIT(SHL_vector_vector(0, 1, 0b00, Vm, 0, 0, Vn, Vd))
+#define USHL_16(Vd, Vn, Vm)                 EMIT(SHL_vector_vector(0, 1, 0b01, Vm, 0, 0, Vn, Vd))
+#define USHL_32(Vd, Vn, Vm)                 EMIT(SHL_vector_vector(0, 1, 0b10, Vm, 0, 0, Vn, Vd))
+#define USHLQ_8(Vd, Vn, Vm)                 EMIT(SHL_vector_vector(1, 1, 0b00, Vm, 0, 0, Vn, Vd))
+#define USHLQ_16(Vd, Vn, Vm)                EMIT(SHL_vector_vector(1, 1, 0b01, Vm, 0, 0, Vn, Vd))
+#define USHLQ_32(Vd, Vn, Vm)                EMIT(SHL_vector_vector(1, 1, 0b10, Vm, 0, 0, Vn, Vd))
+#define USHLQ_64(Vd, Vn, Vm)                EMIT(SHL_vector_vector(1, 1, 0b11, Vm, 0, 0, Vn, Vd))
 
 #define SHR_vector(Q, U, immh, immb, Rn, Rd)  ((Q)<<30 | (U)<<29 | 0b011110<<23 | (immh)<<19 | (immb)<<16 | 0b00000<<11 | 1<<10 | (Rn)<<5 | (Rd))
 #define VSHRQ_8(Vd, Vn, shift)              EMIT(SHR_vector(1, 1, 0b0001, (8-(shift))&7, Vn, Vd))
@@ -830,6 +878,10 @@
 #define ABSQ_32(Vd, Vn)                     EMIT(NEGABS_vector(1, 0, 0b10, Vn, Vd))
 #define ABSQ_64(Vd, Vn)                     EMIT(NEGABS_vector(1, 0, 0b11, Vn, Vd))
 
+#define NEGABS_vector_scalar(U, size, Rn, Rd)   (0b01<<30 | (U)<<29 | 0b11110<<24 | (size)<<22 | 0b10000<<17 | 0b01011<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define NEG_64(Vd, Vn)                     EMIT(NEGABS_vector_scalar(1, 0b11, Vn, Vd))
+#define ABS_64(Vd, Vn)                     EMIT(NEGABS_vector_scalar(0, 0b11, Vn, Vd))
+
 // FMOV
 #define FMOV_general(sf, type, mode, opcode, Rn, Rd)    ((sf)<<31 | 0b11110<<24 | (type)<<22 | 1<<21 | (mode)<<19 | (opcode)<<16 | (Rn)<<5 | (Rd))
 // 32-bit to single-precision
@@ -952,6 +1004,11 @@
 #define FMULS(Sd, Sn, Sm)           EMIT(FMUL_scalar(0b00, Sm, Sn, Sd))
 #define FMULD(Dd, Dn, Dm)           EMIT(FMUL_scalar(0b01, Dm, Dn, Dd))
 
+#define FMLA_vector(Q, op, sz, Rm, Rn, Rd)	((Q)<<30 | 0b01110<<24 | (op)<<23 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b11001<<11 | 1<<10 | (Rn)<<5 | (Rd))
+#define VFMLAS(Sd, Sn, Sm)	        EMIT(FMLA_vector(0, 0, 0, Sm, Sn, Sd))
+#define VFMLAQS(Sd, Sn, Sm)	        EMIT(FMLA_vector(1, 0, 0, Sm, Sn, Sd))
+#define CFMLAQD(Dd, Dn, Dm)	        EMIT(FMLA_vector(1, 0, 1, Dm, Dn, Dd))
+
 // DIV
 #define FDIV_vector(Q, sz, Rm, Rn, Rd)  ((Q)<<30 | 1<<29 | 0b01110<<24 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b11111<<11 | 1<<10 | (Rn)<<5 | (Rd))
 #define VFDIVS(Sd, Sn, Sm)          EMIT(FDIV_vector(0, 0, Sm, Sn, Sd))
@@ -962,6 +1019,16 @@
 #define FDIVS(Sd, Sn, Sm)           EMIT(FDIV_scalar(0b00, Sm, Sn, Sd))
 #define FDIVD(Dd, Dn, Dm)           EMIT(FDIV_scalar(0b01, Dm, Dn, Dd))
 
+#define FRECPE_vector(Q, sz, Rn, Rd)   ((Q)<<30 | 0<<29 | 0b01110<<24 | 1<<23 | (sz)<<22 | 0b10000<<17 | 0b11101<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define VFRECPES(Vd, Vn)           EMIT(FRECPE_vector(0, 0, Vn, Vd))
+#define VFRECPEQS(Vd, Vn)          EMIT(FRECPE_vector(1, 0, Vn, Vd))
+#define VFRECPEQD(Vd, Vn)          EMIT(FRECPE_vector(1, 0, Vn, Vd))
+
+#define FRECPS_vector(Q, sz, Rm, Rn, Rd)   ((Q)<<30 | 0<<29 | 0b01110<<24 | 0<<23 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b11111<<11 | 1<<10 | (Rn)<<5 | (Rd))
+#define VFRECPSS(Vd, Vn, Vm)       EMIT(FRECPS_vector(0, 0, Vm, Vn, Vd))
+#define VFRECPSQS(Vd, Vn, Vm)      EMIT(FRECPS_vector(1, 0, Vm, Vn, Vd))
+#define VFRECPSQD(Vd, Vn, Vm)      EMIT(FRECPS_vector(1, 0, Vm, Vn, Vd))
+
 // SQRT
 #define FSQRT_vector(Q, sz, Rn, Rd)     ((Q)<<30 | 1<<29 | 0b01110<<24 | 1<<23 | (sz)<<22 | 0b10000<<17 | 0b11111<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
 #define VFSQRTS(Sd, Sn)             EMIT(FSQRT_vector(0, 0, Sn, Sd))
@@ -972,6 +1039,16 @@
 #define FSQRTS(Sd, Sn)              EMIT(FSQRT_scalar(0b00, Sn, Sd))
 #define FSQRTD(Dd, Dn)              EMIT(FSQRT_scalar(0b01, Dn, Dd))
 
+#define FRSQRTE_vector(Q, sz, Rn, Rd)   ((Q)<<30 | 1<<29 | 0b01110<<24 | 1<<23 | (sz)<<22 | 0b10000<<17 | 0b11101<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define VFRSQRTES(Vd, Vn)           EMIT(FRSQRTE_vector(0, 0, Vn, Vd))
+#define VFRSQRTEQS(Vd, Vn)          EMIT(FRSQRTE_vector(1, 0, Vn, Vd))
+#define VFRSQRTEQD(Vd, Vn)          EMIT(FRSQRTE_vector(1, 0, Vn, Vd))
+
+#define FRSQRTS_vector(Q, sz, Rm, Rn, Rd)   ((Q)<<30 | 0<<29 | 0b01110<<24 | 1<<23 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b11111<<11 | 1<<10 | (Rn)<<5 | (Rd))
+#define VFRSQRTSS(Vd, Vn, Vm)       EMIT(FRSQRTS_vector(0, 0, Vm, Vn, Vd))
+#define VFRSQRTSQS(Vd, Vn, Vm)      EMIT(FRSQRTS_vector(1, 0, Vm, Vn, Vd))
+#define VFRSQRTSQD(Vd, Vn, Vm)      EMIT(FRSQRTS_vector(1, 0, Vm, Vn, Vd))
+
 // CMP
 #define FCMP_scalar(type, Rn, Rm, opc)  (0b11110<<24 | (type)<<22 | 1<<21 | (Rm)<<16 | 0b1000<<10 | (Rn)<<5 | (opc)<<3)
 #define FCMPS(Sn, Sm)               EMIT(FCMP_scalar(0b00, Sn, Sm, 0b00))
@@ -1173,10 +1250,18 @@
 #define FRINT64XD(Dd, Dn)           EMIT(FRINTxx_scalar(0b01, 0b11, Dn, Dd))
 
 #define FRINT_scalar(type, rmode, Rn, Rd)   (0b11110<<24 | (type)<<22 | 1<<21 | 0b001<<18 | (rmode)<<15 | 0b10000<<10 | (Rn)<<5 | (Rd))
+// round toward 0 (truncate)
 #define FRINTZS(Sd, Sn)             EMIT(FRINT_scalar(0b00, 0b011, Sn, Sd))
+// round toward 0 (truncate)
 #define FRINTZD(Sd, Sn)             EMIT(FRINT_scalar(0b01, 0b011, Sn, Sd))
+// round with current FPCR mode
 #define FRINTXS(Sd, Sn)             EMIT(FRINT_scalar(0b00, 0b110, Sn, Sd))
+// round with current FPCR mode
 #define FRINTXD(Sd, Sn)             EMIT(FRINT_scalar(0b01, 0b110, Sn, Sd))
+// round with mode, mode is 0 = TieEven, 1=+inf, 2=-inf, 3=zero
+#define FRINTRRS(Sd, Sn, mode)      EMIT(FRINT_scalar(0b00, ((mode)&3), Sn, Sd))
+// round with mode, mode is 0 = TieEven, 1=+inf, 2=-inf, 3=zero
+#define FRINTRRD(Dd, Dn, mode)      EMIT(FRINT_scalar(0b01, ((mode)&3), Dn, Dd))
 
 // FMAX / FMIN
 #define FMINMAX_vector(Q, U, o1, sz, Rm, Rn, Rd)    ((Q)<<30 | (U)<<29 | 0b01110<<24 | (o1)<<23 | (sz)<<22 | 0b1<<21 | (Rm)<<16 | 0b11110<<11 | 1<<10 | (Rn)<<5 | (Rd))
@@ -1234,6 +1319,15 @@
 #define VUZP1Q_64(Rt, Rn, Rm)       EMIT(UZP_gen(1, 0b11, Rm, 0, Rn, Rt))
 #define VUZP2Q_64(Rt, Rn, Rm)       EMIT(UZP_gen(1, 0b11, Rm, 1, Rn, Rt))
 
+#define DUP_gen(Q, imm5, Rn, Rd)    ((Q)<<30 | 0b01110000<<21 | (imm5)<<16 | 1<<10 | (Rn)<<5 | (Rd))
+#define VDUP_8(Vd, Vn, idx)         EMIT(DUP_gen(0, ((idx)<<1|1), Vn, Vd))
+#define VDUPQ_8(Vd, Vn, idx)        EMIT(DUP_gen(1, ((idx)<<1|1), Vn, Vd))
+#define VDUP_16(Vd, Vn, idx)        EMIT(DUP_gen(0, ((idx)<<2|0b10), Vn, Vd))
+#define VDUPQ_16(Vd, Vn, idx)       EMIT(DUP_gen(1, ((idx)<<2|0b10), Vn, Vd))
+#define VDUP_32(Vd, Vn, idx)        EMIT(DUP_gen(0, ((idx)<<3|0b100), Vn, Vd))
+#define VDUPQ_32(Vd, Vn, idx)       EMIT(DUP_gen(1, ((idx)<<3|0b100), Vn, Vd))
+#define VDUPQ_64(Vd, Vn, idx)       EMIT(DUP_gen(1, ((idx)<<4|0b1000), Vn, Vd))
+
 // TBL
 #define TBL_gen(Q, Rm, len, op, Rn, Rd) ((Q)<<30 | 0b001110<<24 | (Rm)<<16 | (len)<<13 | (op)<<12 | (Rn)<<5 | (Rd))
 //Use Rm[] to pick from Rn element and store in Rd. Out-of-range element gets 0
@@ -1342,27 +1436,66 @@
 #define VCMGTQ_16(Rd, Rn, Rm)       EMIT(CMG_vector(1, 0, 0b01, 0, Rm, Rn, Rd))
 #define VCMGTQ_32(Rd, Rn, Rm)       EMIT(CMG_vector(1, 0, 0b10, 0, Rm, Rn, Rd))
 #define VCMGTQ_64(Rd, Rn, Rm)       EMIT(CMG_vector(1, 0, 0b11, 0, Rm, Rn, Rd))
+#define VCMGT_8(Rd, Rn, Rm)         EMIT(CMG_vector(0, 0, 0b00, 0, Rm, Rn, Rd))
+#define VCMGT_16(Rd, Rn, Rm)        EMIT(CMG_vector(0, 0, 0b01, 0, Rm, Rn, Rd))
+#define VCMGT_32(Rd, Rn, Rm)        EMIT(CMG_vector(0, 0, 0b10, 0, Rm, Rn, Rd))
 // Unsigned Higher
 #define VCHIQQ_8(Rd, Rn, Rm)        EMIT(CMG_vector(1, 1, 0b00, 0, Rm, Rn, Rd))
 #define VCHIQQ_16(Rd, Rn, Rm)       EMIT(CMG_vector(1, 1, 0b01, 0, Rm, Rn, Rd))
 #define VCHIQQ_32(Rd, Rn, Rm)       EMIT(CMG_vector(1, 1, 0b10, 0, Rm, Rn, Rd))
 #define VCHIQQ_64(Rd, Rn, Rm)       EMIT(CMG_vector(1, 1, 0b11, 0, Rm, Rn, Rd))
 
+// Less Than 0
+#define CMLT_0_vector(Q, size, Rn, Rd)		((Q)<<30 | 0b01110<<24 | (size)<<22 | 0b10000<<17 | 0b01010<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define CMLT_0_8(Rd, Rn)		    EMIT(CMLT_0_vector(0, 0b00, Rn, Rd))
+#define CMLT_0_16(Rd, Rn)           EMIT(CMLT_0_vector(0, 0b01, Rn, Rd))
+#define CMLT_0_32(Rd, Rn)           EMIT(CMLT_0_vector(0, 0b10, Rn, Rd))
+#define CMLTQ_0_8(Rd, Rn)           EMIT(CMLT_0_vector(1, 0b00, Rn, Rd))
+#define CMLTQ_0_16(Rd, Rn)          EMIT(CMLT_0_vector(1, 0b01, Rn, Rd))
+#define CMLTQ_0_32(Rd, Rn)          EMIT(CMLT_0_vector(1, 0b10, Rn, Rd))
+#define CMLTQ_0_64(Rd, Rn)          EMIT(CMLT_0_vector(1, 0b11, Rn, Rd))
+// Equal 0
+#define CMEQ_0_vector(Q, size, Rn, Rd)          ((Q)<<30 | 0b01110<<24 | (size)<<22 | 0b10000<<17 | 0b0100<<13 | 1<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define CMEQ_0_8(Rd, Rn)            EMIT(CMEQ_0_vector(0, 0b00, Rn, Rd))
+#define CMEQ_0_16(Rd, Rn)           EMIT(CMEQ_0_vector(0, 0b01, Rn, Rd))
+#define CMEQ_0_32(Rd, Rn)           EMIT(CMEQ_0_vector(0, 0b10, Rn, Rd))
+#define CMEQQ_0_8(Rd, Rn)           EMIT(CMEQ_0_vector(1, 0b00, Rn, Rd))
+#define CMEQQ_0_16(Rd, Rn)          EMIT(CMEQ_0_vector(1, 0b01, Rn, Rd))
+#define CMEQQ_0_32(Rd, Rn)          EMIT(CMEQ_0_vector(1, 0b10, Rn, Rd))
+#define CMEQQ_0_64(Rd, Rn)          EMIT(CMEQ_0_vector(1, 0b11, Rn, Rd))
+
 // Vector Float CMP
 // EQual
 #define FCMP_vector(Q, U, E, sz, Rm, ac, Rn, Rd)    ((Q)<<30 | (U)<<29 | 0b01110<<24 | (E)<<23 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b1110<<12 | (ac)<<11 | 1<<10 | (Rn)<<5 | (Rd))
-#define FCMEQQD(Rd, Rn, Rm)          EMIT(FCMP_vector(1, 0, 0, 1, Rm, 0, Rn, Rd))
-#define FCMEQQS(Rd, Rn, Rm)          EMIT(FCMP_vector(1, 0, 0, 0, Rm, 0, Rn, Rd))
+#define VFCMEQQD(Rd, Rn, Rm)         EMIT(FCMP_vector(1, 0, 0, 1, Rm, 0, Rn, Rd))
+#define VFCMEQQS(Rd, Rn, Rm)         EMIT(FCMP_vector(1, 0, 0, 0, Rm, 0, Rn, Rd))
 // Greater or Equal
-#define FCMGEQD(Rd, Rn, Rm)          EMIT(FCMP_vector(1, 1, 0, 1, Rm, 0, Rn, Rd))
-#define FCMGEQS(Rd, Rn, Rm)          EMIT(FCMP_vector(1, 1, 0, 0, Rm, 0, Rn, Rd))
-#define FCMGEQD_ABS(Rd, Rn, Rm)      EMIT(FCMP_vector(1, 1, 0, 1, Rm, 1, Rn, Rd))
-#define FCMGEQS_ABS(Rd, Rn, Rm)      EMIT(FCMP_vector(1, 1, 0, 0, Rm, 1, Rn, Rd))
+#define VFCMGEQD(Rd, Rn, Rm)         EMIT(FCMP_vector(1, 1, 0, 1, Rm, 0, Rn, Rd))
+#define VFCMGEQS(Rd, Rn, Rm)         EMIT(FCMP_vector(1, 1, 0, 0, Rm, 0, Rn, Rd))
+#define VFCMGEQD_ABS(Rd, Rn, Rm)     EMIT(FCMP_vector(1, 1, 0, 1, Rm, 1, Rn, Rd))
+#define VFCMGEQS_ABS(Rd, Rn, Rm)     EMIT(FCMP_vector(1, 1, 0, 0, Rm, 1, Rn, Rd))
 // Greater Than
-#define FCMGTQD(Rd, Rn, Rm)          EMIT(FCMP_vector(1, 1, 1, 1, Rm, 0, Rn, Rd))
-#define FCMGTQS(Rd, Rn, Rm)          EMIT(FCMP_vector(1, 1, 1, 0, Rm, 0, Rn, Rd))
-#define FCMGTQD_ABS(Rd, Rn, Rm)      EMIT(FCMP_vector(1, 1, 1, 1, Rm, 1, Rn, Rd))
-#define FCMGTQS_ABS(Rd, Rn, Rm)      EMIT(FCMP_vector(1, 1, 1, 0, Rm, 1, Rn, Rd))
+#define VFCMGTQD(Rd, Rn, Rm)         EMIT(FCMP_vector(1, 1, 1, 1, Rm, 0, Rn, Rd))
+#define VFCMGTQS(Rd, Rn, Rm)         EMIT(FCMP_vector(1, 1, 1, 0, Rm, 0, Rn, Rd))
+#define VFCMGTQD_ABS(Rd, Rn, Rm)     EMIT(FCMP_vector(1, 1, 1, 1, Rm, 1, Rn, Rd))
+#define VFCMGTQS_ABS(Rd, Rn, Rm)     EMIT(FCMP_vector(1, 1, 1, 0, Rm, 1, Rn, Rd))
+
+// Scalar Float CMP to 0
+#define FCMP_0_scalar(U, sz, op, Rn, Rd) (0b01<<30 | (U)<<29| 0b11110<<24 | 1<<23 | (sz)<<22 | 0b10000<<17 | 0b011<<14 | (op)<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+// Less or equal to 0
+#define FCMLES_0(Rd, Rn)             EMIT(FCMP_0_scalar(1, 0, 0b01, (Rn), (Rd)))
+#define FCMLED_0(Rd, Rn)             EMIT(FCMP_0_scalar(1, 1, 0b01, (Rn), (Rd)))
+// Greater than 0
+#define FCMGTS_0(Rd, Rn)             EMIT(FCMP_0_scalar(0, 0, 0b00, (Rn), (Rd)))
+#define FCMGTD_0(Rd, Rn)             EMIT(FCMP_0_scalar(0, 1, 0b00, (Rn), (Rd)))
+// Less than 0
+#define FCMLTS_0(Rd, Rn)             EMIT(FCMP_0_scalar(0, 0, 0b10, (Rn), (Rd)))
+#define FCMLTD_0(Rd, Rn)             EMIT(FCMP_0_scalar(0, 1, 0b10, (Rn), (Rd)))
+
+// Scalar Float CMP
+#define FCMP_op_scalar(U, E, sz, Rm, ac, Rn, Rd)    (0b01<<30 | (U)<<29 | 0b11110<<24 | (E)<<23 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b1110<<12 | (ac)<<11 | 1<<10 | (Rn)<<5 | (Rd))
+#define FCMEQS(Rd, Rn, Rm)          EMIT(FCMP_op_scalar(0, 0, 0, (Rm), 0, (Rn), (Rd)))
+#define FCMEQD(Rd, Rn, Rm)          EMIT(FCMP_op_scalar(0, 0, 1, (Rm), 0, (Rn), (Rd)))
 
 // UMULL / SMULL
 #define MULL_vector(Q, U, size, Rm, Rn, Rd) ((Q)<<30 | (U)<<29 | 0b01110<<24 | (size)<<22 | 1<<21 | (Rm)<<16 | 0b1100<<12 |(Rn)<<5 |(Rd))
@@ -1627,4 +1760,13 @@
 #define SQDMULHQ_16(Vd, Vn, Vm)     EMIT(QDMULH_vector(1, 0, 0b01, Vm, Vn, Vd))
 #define SQDMULHQ_32(Vd, Vn, Vm)     EMIT(QDMULH_vector(1, 0, 0b10, Vm, Vn, Vd))
 
+// AES extensions
+#define AES_gen(D, Rn, Rd)      (0b01001110<<24 | 0b00<<22 | 0b10100<<17 | 0b0010<<13 | (D)<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define AESD(Vd, Vn)    EMIT(AES_gen(1, Vn, Vd))
+#define AESE(Vd, Vn)    EMIT(AES_gen(0, Vn, Vd))
+
+#define AESMC_gen(D, Rn, Rd)    (0b01001110<<24 | 0b00<<22 | 0b10100<<17 | 0b0011<<13 | (D)<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define AESIMC(Vd, Vn)  EMIT(AESMC_gen(1, Vn, Vd))
+#define AESMC(Vd, Vn)   EMIT(AESMC_gen(0, Vn, Vd))
+
 #endif  //__ARM64_EMITTER_H__

src/dynarec/arm64/arm64_lock.S

@@ -21,6 +21,7 @@
 
 
 arm64_lock_read_b:
+    dmb     ish
     // address is x0, return is x0
     ldaxrb  w0, [x0]
     ret
@@ -29,9 +30,11 @@ arm64_lock_write_b:
     // address is x0, value is x1, return is x0
     mov     x2, x0
     stlxrb  w0, w1, [x2]
+    dmb     ish
     ret
 
 arm64_lock_read_h:
+    dmb     ish
     // address is x0, return is x0
     ldaxrh  w0, [x0]
     ret
@@ -40,23 +43,24 @@ arm64_lock_write_h:
     // address is x0, value is x1, return is x0
     mov     x2, x0
     stlxrh  w0, w1, [x2]
+    dmb     ish
     ret
 
 arm64_lock_read_d:
+    dmb     ish
     // address is x0, return is x0
     ldaxr    w0, [x0]
-    #ldx     w0,[x0]
     ret
 
 arm64_lock_write_d:
     // address is x0, value is w1, return is x0
     mov     x2, x0
     stlxr   w0, w1, [x2]
-    #str     w1, [x2]
-    mov     w0, 0
+    dmb     ish
     ret
 
 arm64_lock_read_dd:
+    dmb     ish
     // address is x0, return is x0
     ldaxr   x0, [x0]
     ret
@@ -65,9 +69,11 @@ arm64_lock_write_dd:
     // address is x0, value is x1, return is x0
     mov     x2, x0
     stlxr   w0, x1, [x2]
+    dmb     ish
     ret
 
 arm64_lock_read_dq:
+    dmb     ish
     // address is r2, return is r0, r1
     ldaxp   x4, x3, [x2]
     str     x4, [x0]
@@ -79,37 +85,47 @@ arm64_lock_write_dq:
     // r0 needs to be aligned
     stlxp   w3, x0, x1, [x2]
     mov     w0, w3
+    dmb     ish
     ret
 
 
 arm64_lock_xchg:
+    dmb     ish
+arm64_lock_xchg_0:
     // address is x0, value is x1, return old value in x0
     ldaxr   x2, [x0]
     stlxr   w3, x1, [x0]
-    cbnz    w3, arm64_lock_xchg
+    cbnz    w3, arm64_lock_xchg_0
+    dmb     ish
     mov     x0, x2
     ret
 
 arm64_lock_storeifnull:
+    dmb     ish
+arm64_lock_storeifnull_0:
     // address is x0, value is x1, x1 store to x0 only if [x0] is 0. return new [x0] value (so x1 or old value)
     ldaxr   x2, [x0]
     cbnz    x2, arm64_lock_storeifnull_exit
     mov     x2, x1
     stlxr   w3, x2, [x0]
-    cbnz    w3, arm64_lock_storeifnull
+    cbnz    w3, arm64_lock_storeifnull_0
 arm64_lock_storeifnull_exit:
+    dmb     ish
     mov     x0, x2
     ret
 
 arm64_lock_storeifref:
+    dmb     ish
+arm64_lock_storeifref_0:
     // address is x0, value is x1, x1 store to x0 only if [x0] is x3. return new [x0] value (so x1 or old value)
     ldaxr   x3, [x0]
     cmp     x2, x3
     bne     arm64_lock_storeifref_exit
     stlxr   w4, x1, [x0]
-    cbnz    w4, arm64_lock_storeifref
+    cbnz    w4, arm64_lock_storeifref_0
     mov     x0, x1
     ret
 arm64_lock_storeifref_exit:
+    dmb     ish
     mov     x0, x3
     ret

src/dynarec/arm64/arm64_next.S

@@ -18,8 +18,10 @@ arm64_next:
     stp     x12, x13, [sp, (8 *  4)]
     stp     x14, x15, [sp, (8 *  6)]
     stp     x16, x17, [sp, (8 *  8)]
-    str     x18, [sp, (8 * 10)]
+    stp     x18, x27, [sp, (8 * 10)]    // also save x27(rip) to allow change in LinkNext
+
     mov     x2, lr      // "from" is in lr, so put in x2
+    add     x3, sp, 8*11    // x3 is address to change rip
     // call the function
     bl      LinkNext
     // preserve return value
@@ -30,7 +32,7 @@ arm64_next:
     ldp     x12, x13, [sp, (8 *  4)]
     ldp     x14, x15, [sp, (8 *  6)]
     ldp     x16, x17, [sp, (8 *  8)]
-    ldr     x18, [sp, (8 * 10)]
+    ldp     x18, x27, [sp, (8 * 10)]
     add     sp,  sp, (8 * 12)
     // return offset is jump address
     br      x3

src/dynarec/arm64/arm64_printer.c

@@ -236,6 +236,15 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
             snprintf(buff, sizeof(buff), "STR %s, [%s, %s, %s %d]", (size==2)?Wt[Rt]:Xt[Rt], XtSp[Rn], ((option&1)==0)?Wt[Rm]:Xt[Rm], extend[option], amount);
         return buff;
     }
+    if(isMask(opcode, "00111000001mmmmmoooS10nnnnnttttt", &a)) {
+        const char* extend[] = {"?0", "?1", "UXTW", "LSL", "?4", "?5", "SXTW", "SXTX"};
+        int amount = a.S;
+        if(option==3 && !amount)
+            snprintf(buff, sizeof(buff), "STRB %s, [%s, %s]", Wt[Rt], XtSp[Rn], ((option&1)==0)?Wt[Rm]:Xt[Rm]);
+        else
+            snprintf(buff, sizeof(buff), "STRB %s, [%s, %s, %s %d]", Wt[Rt], XtSp[Rn], ((option&1)==0)?Wt[Rm]:Xt[Rm], extend[option], amount);
+        return buff;
+    }
     if(isMask(opcode, "0x111000010iiiiiiiii01nnnnnttttt", &a)) {
         int size = a.x;
         int offset = signExtend(imm, 9);
@@ -278,12 +287,12 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
             snprintf(buff, sizeof(buff), "STR%c %s, [%s]", size?'H':'B', Xt[Rt], XtSp[Rn]);
         return buff;
     }    
-    if(isMask(opcode, "101110011xiiiiiiiiiiiinnnnnttttt", &a)) {
+    if(isMask(opcode, "1011100110iiiiiiiiiiiinnnnnttttt", &a)) {
         int offset = imm<<2;
         if(!offset)
-            snprintf(buff, sizeof(buff), "LDRSW %s, [%s]", a.x?Xt[Rt]:Wt[Rt], XtSp[Rn]);
+            snprintf(buff, sizeof(buff), "LDRSW %s, [%s]", Xt[Rt], XtSp[Rn]);
         else
-            snprintf(buff, sizeof(buff), "LDRSW %s, [%s, #%d]", a.x?Xt[Rt]:Wt[Rt], XtSp[Rn], offset);
+            snprintf(buff, sizeof(buff), "LDRSW %s, [%s, #%d]", Xt[Rt], XtSp[Rn], offset);
         return buff;
     }
     if(isMask(opcode, "011110011xiiiiiiiiiiiinnnnnttttt", &a)) {
@@ -620,7 +629,7 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
         else if(immr==0 && imms==0b001111)
             snprintf(buff, sizeof(buff), "SXTH %s, %s", sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn]);
         else if(sf && immr==0 && imms==0b011111)
-            snprintf(buff, sizeof(buff), "SXTW %s, %s", Xt[Rd], Xt[Rn]);
+            snprintf(buff, sizeof(buff), "SXTW %s, %s", Xt[Rd], Wt[Rn]);
         else if(imms>=immr)
             snprintf(buff, sizeof(buff), "SBFX %s, %s, %d, %d", sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn], immr, imms-immr+1);
         else
@@ -777,6 +786,19 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
             snprintf(buff, sizeof(buff), "MADD %s, %s, %s, %s", sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn], sf?Xt[Rm]:Wt[Rm], sf?Xt[Ra]:Wt[Ra]);
         return buff;
     }
+    if(isMask(opcode, "f0011011000mmmmm1aaaaannnnnddddd", &a)) {
+        if(Ra==31)
+            snprintf(buff, sizeof(buff), "MNEG %s, %s, %s", sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn], sf?Xt[Rm]:Wt[Rm]);
+        else
+            snprintf(buff, sizeof(buff), "MSUB %s, %s, %s, %s", sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn], sf?Xt[Rm]:Wt[Rm], sf?Xt[Ra]:Wt[Ra]);
+        return buff;
+    }
+
+    // DIV
+    if(isMask(opcode, "f0011010110mmmmm00001onnnnnddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%cDIV %s, %s, %s", option?'S':'U', sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn], sf?Xt[Rm]:Wt[Rm]);
+        return buff;
+    }
 
     // MRS / MSR
     if(isMask(opcode, "110101010001opppnnnnmmmm222ttttt", &a)) {
@@ -917,6 +939,12 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
         return buff;
     }
 
+    // ADR
+    if(isMask(opcode, "0ss10000iiiiiiiiiiiiiiiiiiiddddd", &a)) {
+      snprintf(buff, sizeof(buff), "ADR, %s, %ld", Xt[Rd], signExtend((imm)<<2|(imms), 20));
+      return buff;
+    }
+
     // LDR / STR
     if(isMask(opcode, "ss111101cciiiiiiiiiiiinnnnnttttt", &a)) {
         char s = '?';
@@ -1023,7 +1051,7 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
     //FMIN/FMAX
     if(isMask(opcode, "00011110ff1mmmmm01oo10nnnnnddddd", &a)) {
         char s = (sf==0)?'S':((sf==1)?'D':'?');
-        snprintf(buff, sizeof(buff), "F%s %c%d, %c%d, %c%d", (option==3)?"MINNM":((option==2)?"MINNMP":((!option)?"MAXNM":"MAXNMP")), s, Rd, s, Rn, s, Rm);
+        snprintf(buff, sizeof(buff), "F%s %c%d, %c%d, %c%d", (option==3)?"MINNM":((option==2)?"MAXNM":((!option)?"MAX":"MIN")), s, Rd, s, Rn, s, Rm);
         return buff;
     }
     if(isMask(opcode, "0Q001110of1mmmmm110001nnnnnddddd", &a)) {
@@ -1298,9 +1326,37 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
             snprintf(buff, sizeof(buff), "%cSHLL%s V%d.%s, V%d.%s, #%d", a.U?'U':'S', a.Q?"2":"", Rd, Va, Rn, Vd, sh);
         return buff;
     }
+
+    // DUP
+    if(isMask(opcode, "0Q001110000iiiii000001nnnnnddddd", &a)) {
+        const char* Y[] = {"8B", "16B", "4H", "8H", "2S", "4S", "2D", "??"};
+        const char* Z[] = {"B", "H", "S", "D"};
+        int sz = 3;
+        if((imm&0b0001)==0b0001) sz=0;
+        else if((imm&0b0011)==0b0010) sz=1;
+        else if((imm&0b0111)==0b0100) sz=2;
+        int sh=imm - (1<<sz);
+        const char* Vd = Y[(sz<<1)|a.Q];
+        const char* Vn = Z[sz];
+        snprintf(buff, sizeof(buff), "DUP V%d.%s, V%d.%s[%d]", Rd, Vd, Rn, Vn, sh);
+        return buff;
+    }
     
+    // AES
+    if(isMask(opcode, "0100111000101000010f10nnnnnddddd", &a)) {
+        snprintf(buff, sizeof(buff), "AES%c V%d.16B, V%d.16B", sf?'D':'E', Rd, Rn);
+        return buff;
+    }
+    if(isMask(opcode, "0100111000101000011f10nnnnnddddd", &a)) {
+        snprintf(buff, sizeof(buff), "AES%sMC V%d.16B, V%d.16B", sf?"I":"", Rd, Rn);
+        return buff;
+    }
+    // DMB ISH
+    if(isMask(opcode, "11010101000000110011nnnn10111111", &a)) {
+        snprintf(buff, sizeof(buff), "DMB %s", (Rn==0b1011)?"ISH":"???");
+    }
 
 
     snprintf(buff, sizeof(buff), "%08X ???", __builtin_bswap32(opcode));
     return buff;
-}
+}

src/dynarec/arm64/dynarec_arm64_64.c

@@ -0,0 +1,980 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <pthread.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_helper.h"
+#include "dynarec_arm64_functions.h"
+
+#define GETG        gd = ((nextop&0x38)>>3)+(rex.r<<3)
+
+uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int seg, int* ok, int* need_epilog)
+{
+    (void)ip; (void)rep; (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop;
+    uint8_t u8;
+    uint8_t gd, ed, eb1, eb2, gb1, gb2;
+    uint8_t wback, wb1, wb2, wb;
+    int64_t i64, j64;
+    int v0, v1;
+    int q0;
+    int d0;
+    int64_t fixedaddress;
+    MAYUSE(eb1);
+    MAYUSE(eb2);
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(j64);
+    MAYUSE(d0);
+    MAYUSE(q0);
+    MAYUSE(v0);
+    MAYUSE(v1);
+
+    while((opcode==0xF2) || (opcode==0xF3)) {
+        rep = opcode-0xF1;
+        opcode = F8;
+    }
+    // REX prefix before the F0 are ignored
+    rex.rex = 0;
+    while(opcode>=0x40 && opcode<=0x4f) {
+        rex.rex = opcode;
+        opcode = F8;
+    }
+
+    switch(opcode) {
+
+        case 0x03:
+            INST_NAME("ADD Gd, Seg:Ed");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            grab_segdata(dyn, addr, ninst, x4, seg);
+            nextop = F8;
+            GETGD;
+            GETEDO(x4, 0);
+            emit_add32(dyn, ninst, rex, gd, ed, x3, x4);
+            break;
+
+        case 0x0F:
+            opcode = F8;
+            switch(opcode) {
+
+                case 0x10:
+                    switch(rep) {
+                        case 1:
+                            INST_NAME("MOVSD Gx, Ex");
+                            nextop = F8;
+                            GETG;
+                            if(MODREG) {
+                                ed = (nextop&7)+ (rex.b<<3);
+                                v0 = sse_get_reg(dyn, ninst, x1, gd, 1);
+                                d0 = sse_get_reg(dyn, ninst, x1, ed, 0);
+                                VMOVeD(v0, 0, d0, 0);
+                            } else {
+                                grab_segdata(dyn, addr, ninst, x4, seg);
+                                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<3, 7, rex, 0, 0);
+                                ADDx_REG(x4, x4, ed);
+                                VLDR64_U12(v0, x4, fixedaddress); // upper part reseted
+                            }
+                            break;
+                        case 2:
+                            INST_NAME("MOVSS Gx, Ex");
+                            nextop = F8;
+                            GETG;
+                            if(MODREG) {
+                                v0 = sse_get_reg(dyn, ninst, x1, gd, 1);
+                                q0 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3), 0);
+                                VMOVeS(v0, 0, q0, 0);
+                            } else {
+                                grab_segdata(dyn, addr, ninst, x4, seg);
+                                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
+                                ADDx_REG(x4, x4, ed);
+                                VLDR32_U12(v0, x4, fixedaddress);
+                            }
+                            break;
+                        default:
+                            DEFAULT;
+                    }
+                    break;
+                case 0x11:
+                    switch(rep) {
+                        case 0:
+                            INST_NAME("MOVUPS Ex,Gx");
+                            nextop = F8;
+                            GETG;
+                            v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
+                            if(MODREG) {
+                                ed = (nextop&7)+(rex.b<<3);
+                                v1 = sse_get_reg_empty(dyn, ninst, x1, ed);
+                                VMOVQ(v1, v0);
+                            } else {
+                                grab_segdata(dyn, addr, ninst, x4, seg);
+                                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<4, 15, rex, 0, 0);
+                                ADDx_REG(x4, x4, ed);
+                                VSTR128_U12(v0, x4, fixedaddress);
+                            }
+                            break;
+                        case 1:
+                            INST_NAME("MOVSD Ex, Gx");
+                            nextop = F8;
+                            GETG;
+                            v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
+                            if(MODREG) {
+                                ed = (nextop&7)+ (rex.b<<3);
+                                d0 = sse_get_reg(dyn, ninst, x1, ed, 1);
+                                VMOVeD(d0, 0, v0, 0);
+                            } else {
+                                grab_segdata(dyn, addr, ninst, x4, seg);
+                                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<3, 7, rex, 0, 0);
+                                ADDx_REG(x4, x4, ed);
+                                VSTR64_U12(v0, x4, fixedaddress);
+                            }
+                            break;
+                        case 2:
+                            INST_NAME("MOVSS Ex, Gx");
+                            nextop = F8;
+                            GETG;
+                            v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
+                            if(MODREG) {
+                                q0 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3), 1);
+                                VMOVeS(q0, 0, v0, 0);
+                            } else {
+                                grab_segdata(dyn, addr, ninst, x4, seg);
+                                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
+                                ADDx_REG(x4, x4, ed);
+                                VSTR32_U12(v0, x4, fixedaddress);
+                            }
+                            break;
+                        default:
+                            DEFAULT;
+                    }
+                    break;
+
+                case 0x6F:
+                    switch(rep) {
+                        case 2:
+                            INST_NAME("MOVDQU Gx,Ex");// no alignment constraint on NEON here, so same as MOVDQA
+                            nextop = F8;
+                            GETG;
+                            v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                            if(MODREG) {
+                                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
+                                VMOVQ(v0, v1);
+                            } else {
+                                grab_segdata(dyn, addr, ninst, x4, seg);
+                                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<4, 15, rex, 0, 0);
+                                ADDx_REG(x4, x4, ed);
+                                VLDR128_U12(v0, ed, fixedaddress);
+                            }
+                            break;
+                        default:
+                            DEFAULT;
+                    }
+                    break;
+
+
+                case 0xAF:
+                    INST_NAME("IMUL Gd, Ed");
+                    SETFLAGS(X_ALL, SF_PENDING);
+                    nextop = F8;
+                    grab_segdata(dyn, addr, ninst, x4, seg);
+                    GETGD;
+                    GETEDO(x4, 0);
+                    if(rex.w) {
+                        // 64bits imul
+                        UFLAG_IF {
+                            SMULH(x3, gd, ed);
+                            MULx(gd, gd, ed);
+                            UFLAG_OP1(x3);
+                            UFLAG_RES(gd);
+                            UFLAG_DF(x3, d_imul64);
+                        } else {
+                            MULxw(gd, gd, ed);
+                        }
+                    } else {
+                        // 32bits imul
+                        UFLAG_IF {
+                            SMULL(gd, gd, ed);
+                            UFLAG_RES(gd);
+                            LSRx(x3, gd, 32);
+                            UFLAG_OP1(x3);
+                            UFLAG_DF(x3, d_imul32);
+                            MOVw_REG(gd, gd);
+                        } else {
+                            MULxw(gd, gd, ed);
+                        }
+                    }
+                    break;
+
+                case 0xB6:
+                    INST_NAME("MOVZX Gd, Eb");
+                    nextop = F8;
+                    grab_segdata(dyn, addr, ninst, x4, seg);
+                    GETGD;
+                    if(MODREG) {
+                        if(rex.rex) {
+                            eb1 = xRAX+(nextop&7)+(rex.b<<3);
+                            eb2 = 0;                \
+                        } else {
+                            ed = (nextop&7);
+                            eb1 = xRAX+(ed&3);  // Ax, Cx, Dx or Bx
+                            eb2 = (ed&4)>>2;    // L or H
+                        }
+                        UBFXxw(gd, eb1, eb2*8, 8);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0, rex, 0, 0);
+                        LDRB_REG(gd, ed, x4);
+                    }
+                    break;
+
+                default:
+                    DEFAULT;
+            }
+            break;
+
+        case 0x33:
+            INST_NAME("XOR Gd, Seg:Ed");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            grab_segdata(dyn, addr, ninst, x4, seg);
+            nextop = F8;
+            GETGD;
+            GETEDO(x4, 0);
+            emit_xor32(dyn, ninst, rex, gd, ed, x3, x4);
+            break;
+                    
+        case 0x39:
+            INST_NAME("CMP Seg:Ed, Gd");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            grab_segdata(dyn, addr, ninst, x4, seg);
+            nextop = F8;
+            GETGD;
+            GETEDO(x4, 0);
+            emit_cmp32(dyn, ninst, rex, ed, gd, x3, x4, x5);
+            break;
+
+        case 0x3B:
+            INST_NAME("CMP Gd, Seg:Ed");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            grab_segdata(dyn, addr, ninst, x4, seg);
+            nextop = F8;
+            GETGD;
+            GETEDO(x4, 0);
+            emit_cmp32(dyn, ninst, rex, gd, ed, x3, x4, x5);
+            break;
+
+        case 0x63:
+            INST_NAME("MOVSXD Gd, Ed");
+            nextop = F8;
+            GETGD;
+            if(rex.w) {
+                if(MODREG) {   // reg <= reg
+                    SXTWx(gd, xRAX+(nextop&7)+(rex.b<<3));
+                } else {                    // mem <= reg
+                    grab_segdata(dyn, addr, ninst, x4, seg);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0, rex, 0, 0);
+                    LDRSW_REG(gd, ed, x4);
+                }
+            } else {
+                if(MODREG) {   // reg <= reg
+                    MOVw_REG(gd, xRAX+(nextop&7)+(rex.b<<3));
+                } else {                    // mem <= reg
+                    grab_segdata(dyn, addr, ninst, x4, seg);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0, rex, 0, 0);
+                    LDRw_REG(gd, ed, x4);
+                }
+            }
+            break;
+
+        case 0x66:
+            addr = dynarec64_6664(dyn, addr, ip, ninst, rex, rep, ok, need_epilog);
+            break;
+
+        case 0x80:
+            nextop = F8;
+            switch((nextop>>3)&7) {
+                case 0: //ADD
+                    INST_NAME("ADD Eb, Ib");
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEBO(x1, 1);
+                    u8 = F8;
+                    emit_add8c(dyn, ninst, x1, u8, x2, x4);
+                    EBBACK;
+                    break;
+                case 1: //OR
+                    INST_NAME("OR Eb, Ib");
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEBO(x1, 1);
+                    u8 = F8;
+                    emit_or8c(dyn, ninst, x1, u8, x2, x4);
+                    EBBACK;
+                    break;
+                case 2: //ADC
+                    INST_NAME("ADC Eb, Ib");
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEBO(x1, 1);
+                    u8 = F8;
+                    emit_adc8c(dyn, ninst, x1, u8, x2, x4, x5);
+                    EBBACK;
+                    break;
+                case 3: //SBB
+                    INST_NAME("SBB Eb, Ib");
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEBO(x1, 1);
+                    u8 = F8;
+                    emit_sbb8c(dyn, ninst, x1, u8, x2, x4, x5);
+                    EBBACK;
+                    break;
+                case 4: //AND
+                    INST_NAME("AND Eb, Ib");
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEBO(x1, 1);
+                    u8 = F8;
+                    emit_and8c(dyn, ninst, x1, u8, x2, x4);
+                    EBBACK;
+                    break;
+                case 5: //SUB
+                    INST_NAME("SUB Eb, Ib");
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEBO(x1, 1);
+                    u8 = F8;
+                    emit_sub8c(dyn, ninst, x1, u8, x2, x4, x5);
+                    EBBACK;
+                    break;
+                case 6: //XOR
+                    INST_NAME("XOR Eb, Ib");
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEBO(x1, 1);
+                    u8 = F8;
+                    emit_xor8c(dyn, ninst, x1, u8, x2, x4);
+                    EBBACK;
+                    break;
+                case 7: //CMP
+                    INST_NAME("CMP Eb, Ib");
+                    grab_segdata(dyn, addr, ninst, x1, seg);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEBO(x1, 1);
+                    u8 = F8;
+                    if(u8) {
+                        MOV32w(x2, u8);
+                        emit_cmp8(dyn, ninst, x1, x2, x3, x4, x5);
+                    } else {
+                        emit_cmp8_0(dyn, ninst, x1, x3, x4);
+                    }
+                    break;
+                default:
+                    DEFAULT;
+            }
+            break;
+        case 0x81:
+        case 0x83:
+            nextop = F8;
+            grab_segdata(dyn, addr, ninst, x6, seg);
+            switch((nextop>>3)&7) {
+                case 0: //ADD
+                    if(opcode==0x81) {INST_NAME("ADD Ed, Id");} else {INST_NAME("ADD Ed, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, (opcode==0x81)?4:1);
+                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                    emit_add32c(dyn, ninst, rex, ed, i64, x3, x4, x5);
+                    WBACKO(x6);
+                    break;
+                case 1: //OR
+                    if(opcode==0x81) {INST_NAME("OR Ed, Id");} else {INST_NAME("OR Ed, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, (opcode==0x81)?4:1);
+                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                    emit_or32c(dyn, ninst, rex, ed, i64, x3, x4);
+                    WBACKO(x6);
+                    break;
+                case 2: //ADC
+                    if(opcode==0x81) {INST_NAME("ADC Ed, Id");} else {INST_NAME("ADC Ed, Ib");}
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, (opcode==0x81)?4:1);
+                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                    MOV64xw(x5, i64);
+                    emit_adc32(dyn, ninst, rex, ed, x5, x3, x4);
+                    WBACKO(x6);
+                    break;
+                case 3: //SBB
+                    if(opcode==0x81) {INST_NAME("SBB Ed, Id");} else {INST_NAME("SBB Ed, Ib");}
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, (opcode==0x81)?4:1);
+                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                    MOV64xw(x5, i64);
+                    emit_sbb32(dyn, ninst, rex, ed, x5, x3, x4);
+                    WBACKO(x6);
+                    break;
+                case 4: //AND
+                    if(opcode==0x81) {INST_NAME("AND Ed, Id");} else {INST_NAME("AND Ed, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, (opcode==0x81)?4:1);
+                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                    emit_and32c(dyn, ninst, rex, ed, i64, x3, x4);
+                    WBACKO(x6);
+                    break;
+                case 5: //SUB
+                    if(opcode==0x81) {INST_NAME("SUB Ed, Id");} else {INST_NAME("SUB Ed, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, (opcode==0x81)?4:1);
+                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                    emit_sub32c(dyn, ninst, rex, ed, i64, x3, x4, x5);
+                    WBACKO(x6);
+                    break;
+                case 6: //XOR
+                    if(opcode==0x81) {INST_NAME("XOR Ed, Id");} else {INST_NAME("XOR Ed, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, (opcode==0x81)?4:1);
+                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                    emit_xor32c(dyn, ninst, rex, ed, i64, x3, x4);
+                    WBACKO(x6);
+                    break;
+                case 7: //CMP
+                    if(opcode==0x81) {INST_NAME("CMP Ed, Id");} else {INST_NAME("CMP Ed, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, (opcode==0x81)?4:1);
+                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                    if(i64) {
+                        MOV64xw(x2, i64);
+                        emit_cmp32(dyn, ninst, rex, ed, x2, x3, x4, x5);
+                    } else
+                        emit_cmp32_0(dyn, ninst, rex, ed, x3, x4);
+                    break;
+            }
+            break;
+        case 0x8A:
+            INST_NAME("MOV Gb, Eb");
+            nextop = F8;
+            if(rex.rex) {
+                gb1 = gd = xRAX+((nextop&0x38)>>3)+(rex.r<<3);
+                gb2=0;
+            } else {
+                gd = (nextop&0x38)>>3;
+                gb1 = xRAX+(gd&3);
+                gb2 = ((gd&4)>>2);
+            }
+            if(MODREG) {
+                if(rex.rex) {
+                    wback = xRAX+(nextop&7)+(rex.b<<3);
+                    wb2 = 0;
+                } else {
+                    wback = (nextop&7);
+                    wb2 = (wback>>2);
+                    wback = xRAX+(wback&3);
+                }
+                if(wb2) {
+                    UBFXw(x4, wback, wb2*8, 8);
+                    ed = x4;
+                } else {
+                    ed = wback;
+                }
+            } else {
+                grab_segdata(dyn, addr, ninst, x4, seg);
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0, rex, 0, 0);
+                LDRB_REG(x4, wback, x4);
+                ed = x4;
+            }
+            BFIx(gb1, ed, gb2*8, 8);
+            break;
+        case 0x89:
+            INST_NAME("MOV Seg:Ed, Gd");
+            grab_segdata(dyn, addr, ninst, x4, seg);
+            nextop=F8;
+            GETGD;
+            if(MODREG) {   // reg <= reg
+                MOVxw_REG(xRAX+(nextop&7)+(rex.b<<3), gd);
+            } else {                    // mem <= reg
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0, rex, 0, 0);
+                STRxw_REG(gd, ed, x4);
+            }
+            break;
+
+        case 0x8B:
+            INST_NAME("MOV Gd, Seg:Ed");
+            grab_segdata(dyn, addr, ninst, x4, seg);
+            nextop=F8;
+            GETGD;
+            if(MODREG) {   // reg <= reg
+                MOVxw_REG(gd, xRAX+(nextop&7)+(rex.b<<3));
+            } else {                    // mem <= reg
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0, rex, 0, 0);
+                LDRxw_REG(gd, ed, x4);
+            }
+            break;
+
+        case 0xC6:
+            INST_NAME("MOV Seg:Eb, Ib");
+            grab_segdata(dyn, addr, ninst, x4, seg);
+            nextop=F8;
+            if(MODREG) {   // reg <= u8
+                u8 = F8;
+                if(!rex.rex) {
+                    ed = (nextop&7);
+                    eb1 = xRAX+(ed&3);  // Ax, Cx, Dx or Bx
+                    eb2 = (ed&4)>>2;    // L or H
+                } else {
+                    eb1 = xRAX+(nextop&7)+(rex.b<<3);
+                    eb2 = 0;            
+                }
+                MOV32w(x3, u8);
+                BFIx(eb1, x3, eb2*8, 8);
+            } else {                    // mem <= u8
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 1);
+                u8 = F8;
+                MOV32w(x3, u8);
+                STRB_REG(x3, ed, x4);
+            }
+            break;
+        case 0xC7:
+            INST_NAME("MOV Seg:Ed, Id");
+            grab_segdata(dyn, addr, ninst, x4, seg);
+            nextop=F8;
+            if(MODREG) {   // reg <= i32
+                i64 = F32S;
+                ed = xRAX+(nextop&7)+(rex.b<<3);
+                MOV64xw(ed, i64);
+            } else {                    // mem <= i32
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0, rex, 0, 4);
+                i64 = F32S;
+                MOV64xw(x3, i64);
+                STRxw_REG(x3, ed, x4);
+            }
+            break;
+
+        case 0xD1:
+            nextop = F8;
+            grab_segdata(dyn, addr, ninst, x6, seg);
+            switch((nextop>>3)&7) {
+                case 0:
+                    INST_NAME("ROL Ed, 1");
+                    SETFLAGS(X_OF|X_CF, SF_SUBSET_PENDING);
+                    GETEDO(x6, 0);
+                    emit_rol32c(dyn, ninst, rex, ed, 1, x3, x4);
+                    WBACKO(x6);
+                    break;
+                case 1:
+                    INST_NAME("ROR Ed, 1");
+                    SETFLAGS(X_OF|X_CF, SF_SUBSET_PENDING);
+                    GETEDO(x6, 0);
+                    emit_ror32c(dyn, ninst, rex, ed, 1, x3, x4);
+                    WBACKO(x6);
+                    break;
+                case 2:
+                    INST_NAME("RCL Ed, 1");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_OF|X_CF, SF_SET);
+                    MOV32w(x2, 1);
+                    GETEDO(x6, 0);
+                    if(wback) {ADDx_REG(x6, x6, wback); wback=x6;}
+                    if(ed!=x1) {MOVxw_REG(x1, ed);}
+                    CALL_(rcl32, ed, x6);
+                    WBACK;
+                    break;
+                case 3:
+                    INST_NAME("RCR Ed, 1");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_OF|X_CF, SF_SET);
+                    MOV32w(x2, 1);
+                    GETEDO(x6, 0);
+                    if(wback) {ADDx_REG(x6, x6, wback); wback=x6;}
+                    if(ed!=x1) {MOVxw_REG(x1, ed);}
+                    CALL_(rcr32, ed, x6);
+                    WBACK;
+                    break;
+                case 4:
+                case 6:
+                    INST_NAME("SHL Ed, 1");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);    // some flags are left undefined
+                    GETEDO(x6, 0);
+                    emit_shl32c(dyn, ninst, rex, ed, 1, x3, x4);
+                    WBACKO(x6);
+                    break;
+                case 5:
+                    INST_NAME("SHR Ed, 1");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);    // some flags are left undefined
+                    GETEDO(x6, 0);
+                    emit_shr32c(dyn, ninst, rex, ed, 1, x3, x4);
+                    WBACKO(x6);
+                    break;
+                case 7:
+                    INST_NAME("SAR Ed, 1");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);    // some flags are left undefined
+                    GETEDO(x6, 0);
+                    emit_sar32c(dyn, ninst, rex, ed, 1, x3, x4);
+                    WBACKO(x6);
+                    break;
+            }
+            break;
+        case 0xD3:
+            nextop = F8;
+            grab_segdata(dyn, addr, ninst, x6, seg);
+            switch((nextop>>3)&7) {
+                case 0:
+                    INST_NAME("ROL Ed, CL");
+                    SETFLAGS(X_OF|X_CF, SF_SUBSET);
+                    if(rex.w) {
+                        ANDSx_mask(x3, xRCX, 1, 0, 0b00101);  //mask=0x000000000000003f
+                    } else {
+                        ANDSw_mask(x3, xRCX, 0, 0b00100);  //mask=0x00000001f
+                    }
+                    MOV64xw(x4, (rex.w?64:32));
+                    SUBx_REG(x3, x4, x3);
+                    GETEDO(x6, 0);
+                    if(!rex.w && MODREG) {MOVw_REG(ed, ed);}
+                    B_NEXT(cEQ);
+                    RORxw_REG(ed, ed, x3);
+                    WBACKO(x6);
+                    UFLAG_IF {  // calculate flags directly
+                        CMPSw_U12(x3, rex.w?63:31);
+                        B_MARK(cNE);
+                            LSRxw(x4, ed, rex.w?63:31);
+                            ADDxw_REG(x4, x4, ed);
+                            BFIw(xFlags, x4, F_OF, 1);
+                        MARK;
+                        BFIw(xFlags, ed, F_CF, 1);
+                        UFLAG_DF(x2, d_none);
+                    }
+                    break;
+                case 1:
+                    INST_NAME("ROR Ed, CL");
+                    SETFLAGS(X_OF|X_CF, SF_SUBSET);
+                    if(rex.w) {
+                        ANDSx_mask(x3, xRCX, 1, 0, 0b00101);  //mask=0x000000000000003f
+                    } else {
+                        ANDSw_mask(x3, xRCX, 0, 0b00100);  //mask=0x00000001f
+                    }
+                    GETEDO(x6, 0);
+                    if(!rex.w && MODREG) {MOVw_REG(ed, ed);}
+                    B_NEXT(cEQ);
+                    RORxw_REG(ed, ed, x3);
+                    WBACKO(x6);
+                    UFLAG_IF {  // calculate flags directly
+                        CMPSw_U12(x3, 1);
+                        B_MARK(cNE);
+                            LSRxw(x2, ed, rex.w?62:30); // x2 = d>>30
+                            EORw_REG_LSR(x2, x2, x2, 1); // x2 = ((d>>30) ^ ((d>>30)>>1))
+                            BFIw(xFlags, x2, F_OF, 1);
+                        MARK;
+                        LSRxw(x2, ed, rex.w?63:31);
+                        BFIw(xFlags, x2, F_CF, 1);
+                        UFLAG_DF(x2, d_none);
+                    }
+                    break;
+                case 2:
+                    INST_NAME("RCL Ed, CL");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_OF|X_CF, SF_SET);
+                    if(rex.w) {
+                        ANDSx_mask(x2, xRCX, 1, 0, 0b00101);  //mask=0x000000000000003f
+                    } else {
+                        ANDSw_mask(x2, xRCX, 0, 0b00100);  //mask=0x00000001f
+                    }
+                    GETEDO(x6, 0);
+                    if(wback) {ADDx_REG(x6, x6, wback); wback=x6;}
+                    if(!rex.w && MODREG) {MOVw_REG(ed, ed);}
+                    B_NEXT(cEQ);
+                    CALL_(rex.w?((void*)rcl64):((void*)rcl32), ed, x6);
+                    WBACK;
+                    break;
+                case 3:
+                    INST_NAME("RCR Ed, CL");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_OF|X_CF, SF_SET);
+                    if(rex.w) {
+                        ANDSx_mask(x2, xRCX, 1, 0, 0b00101);  //mask=0x000000000000003f
+                    } else {
+                        ANDSw_mask(x2, xRCX, 0, 0b00100);  //mask=0x00000001f
+                    }
+                    GETEDO(x6, 0);
+                    if(wback) {ADDx_REG(x6, x6, wback); wback=x6;}
+                    if(!rex.w && MODREG) {MOVw_REG(ed, ed);}
+                    B_NEXT(cEQ);
+                    CALL_(rex.w?((void*)rcr64):((void*)rcr32), ed, x6);
+                    WBACK;
+                    break;
+                case 4:
+                case 6:
+                    INST_NAME("SHL Ed, CL");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);    // some flags are left undefined
+                    if(rex.w) {
+                        ANDSx_mask(x3, xRCX, 1, 0, 0b00101);  //mask=0x000000000000003f
+                    } else {
+                        ANDSw_mask(x3, xRCX, 0, 0b00100);  //mask=0x00000001f
+                    }
+                    GETEDO(x6, 0);
+                    if(!rex.w && MODREG) {MOVw_REG(ed, ed);}
+                    B_NEXT(cEQ);
+                    emit_shl32(dyn, ninst, rex, ed, x3, x5, x4);
+                    WBACKO(x6);
+                    break;
+                case 5:
+                    INST_NAME("SHR Ed, CL");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);    // some flags are left undefined
+                    if(rex.w) {
+                        ANDSx_mask(x3, xRCX, 1, 0, 0b00101);  //mask=0x000000000000003f
+                    } else {
+                        ANDSw_mask(x3, xRCX, 0, 0b00100);  //mask=0x00000001f
+                    }
+                    GETEDO(x6, 0);
+                    if(!rex.w && MODREG) {MOVw_REG(ed, ed);}
+                    B_NEXT(cEQ);
+                    emit_shr32(dyn, ninst, rex, ed, x3, x5, x4);
+                    WBACKO(x6);
+                    break;
+                case 7:
+                    INST_NAME("SAR Ed, CL");
+                    SETFLAGS(X_ALL, SF_PENDING);
+                    if(rex.w) {
+                        ANDSx_mask(x3, xRCX, 1, 0, 0b00101);  //mask=0x000000000000003f
+                    } else {
+                        ANDSw_mask(x3, xRCX, 0, 0b00100);  //mask=0x00000001f
+                    }
+                    GETEDO(x6, 0);
+                    if(!rex.w && MODREG) {MOVw_REG(ed, ed);}
+                    B_NEXT(cEQ);
+                    UFLAG_OP12(ed, x3);
+                    ASRxw_REG(ed, ed, x3);
+                    WBACKO(x6);
+                    UFLAG_RES(ed);
+                    UFLAG_DF(x3, rex.w?d_sar64:d_sar32);
+                    break;
+            }
+            break;
+            
+        case 0xF7:
+            nextop = F8;
+            switch((nextop>>3)&7) {
+                case 0:
+                case 1:
+                    INST_NAME("TEST Ed, Id");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, 4);
+                    i64 = F32S;
+                    MOV64xw(x2, i64);
+                    emit_test32(dyn, ninst, rex, ed, x2, x3, x4);
+                    break;
+                case 2:
+                    INST_NAME("NOT Ed");
+                    GETEDO(x6, 4);
+                    MVNxw_REG(ed, ed);
+                    WBACKO(x6);
+                    break;
+                case 3:
+                    INST_NAME("NEG Ed");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEDO(x6, 0);
+                    emit_neg32(dyn, ninst, rex, ed, x3, x4);
+                    WBACKO(x6);
+                    break;
+                case 4:
+                    INST_NAME("MUL EAX, Ed");
+                    SETFLAGS(X_ALL, SF_PENDING);
+                    UFLAG_DF(x2, rex.w?d_mul64:d_mul32);
+                    GETEDO(x6, 0);
+                    if(rex.w) {
+                        if(ed==xRDX) gd=x3; else gd=xRDX;
+                        UMULH(gd, xRAX, ed);
+                        MULx(xRAX, xRAX, ed);
+                        if(gd!=xRDX) {MOVx_REG(xRDX, gd);}
+                    } else {
+                        UMULL(xRDX, xRAX, ed);  //64 <- 32x32
+                        MOVw_REG(xRAX, xRDX);
+                        LSRx(xRDX, xRDX, 32);
+                    }
+                    UFLAG_RES(xRAX);
+                    UFLAG_OP1(xRDX);
+                    break;
+                case 5:
+                    INST_NAME("IMUL EAX, Ed");
+                    SETFLAGS(X_ALL, SF_PENDING);
+                    UFLAG_DF(x2, rex.w?d_imul64:d_imul32);
+                    GETEDO(x6, 0);
+                    if(rex.w) {
+                        if(ed==xRDX) gd=x3; else gd=xRDX;
+                        SMULH(gd, xRAX, ed);
+                        MULx(xRAX, xRAX, ed);
+                        if(gd!=xRDX) {MOVx_REG(xRDX, gd);}
+                    } else {
+                        SMULL(xRDX, xRAX, ed);  //64 <- 32x32
+                        MOVw_REG(xRAX, xRDX);
+                        LSRx(xRDX, xRDX, 32);
+                    }
+                    UFLAG_RES(xRAX);
+                    UFLAG_OP1(xRDX);
+                    break;
+                case 6:
+                    INST_NAME("DIV Ed");
+                    SETFLAGS(X_ALL, SF_SET);
+                    if(!rex.w) {
+                        SET_DFNONE(x2);
+                        GETEDO(x6, 0);
+                        MOVw_REG(x3, xRAX);
+                        ORRx_REG_LSL(x3, x3, xRDX, 32);
+                        if(MODREG) {
+                            MOVw_REG(x4, ed);
+                            ed = x4;
+                        }
+                        UDIVx(x2, x3, ed);
+                        MSUBx(x4, x2, ed, xRAX);
+                        MOVw_REG(xRAX, x2);
+                        MOVw_REG(xRDX, x4);
+                    } else {
+                        if(ninst
+                           && dyn->insts[ninst-1].x64.addr 
+                           && *(uint8_t*)(dyn->insts[ninst-1].x64.addr)==0x31 
+                           && *(uint8_t*)(dyn->insts[ninst-1].x64.addr+1)==0xD2) {
+                            SET_DFNONE(x2);
+                            GETEDO(x6, 0);
+                            UDIVx(x2, xRAX, ed);
+                            MSUBx(xRDX, x2, ed, xRAX);
+                            MOVx_REG(xRAX, x2);
+                        } else {
+                            GETEDO(x6, 0);
+                            CBZxw_MARK(xRDX);
+                            if(ed!=x1) {MOVx_REG(x1, ed);}
+                            CALL(div64, -1);
+                            B_NEXT_nocond;
+                            MARK;
+                            UDIVx(x2, xRAX, ed);
+                            MSUBx(xRDX, x2, ed, xRAX);
+                            MOVx_REG(xRAX, x2);
+                            SET_DFNONE(x2);
+                        }
+                    }
+                    break;
+                case 7:
+                    INST_NAME("IDIV Ed");
+                    SETFLAGS(X_ALL, SF_SET);
+                    if(!rex.w) {
+                        SET_DFNONE(x2)
+                        GETSEDOw(x6, 0);
+                        MOVw_REG(x3, xRAX);
+                        ORRx_REG_LSL(x3, x3, xRDX, 32);
+                        SDIVx(x2, x3, wb);
+                        MSUBx(x4, x2, wb, x3);
+                        MOVw_REG(xRAX, x2);
+                        MOVw_REG(xRDX, x4);
+                    } else {
+                        if(ninst && dyn->insts
+                           &&  dyn->insts[ninst-1].x64.addr 
+                           && *(uint8_t*)(dyn->insts[ninst-1].x64.addr)==0x48
+                           && *(uint8_t*)(dyn->insts[ninst-1].x64.addr+1)==0x99) {
+                            SET_DFNONE(x2)
+                            GETEDO(x6, 0);
+                            SDIVx(x2, xRAX, ed);
+                            MSUBx(xRDX, x2, ed, xRAX);
+                            MOVx_REG(xRAX, x2);
+                        } else {
+                            GETEDO(x6, 0);
+                            CBZxw_MARK(xRDX);
+                            MVNx_REG(x2, xRDX);
+                            CBZxw_MARK(x2);
+                            if(ed!=x1) {MOVx_REG(x1, ed);}
+                            CALL((void*)idiv64, -1);
+                            B_NEXT_nocond;
+                            MARK;
+                            SDIVx(x2, xRAX, ed);
+                            MSUBx(xRDX, x2, ed, xRAX);
+                            MOVx_REG(xRAX, x2);
+                            SET_DFNONE(x2)
+                        }
+                    }
+                    break;
+            }
+            break;
+            
+        case 0xFF:
+            nextop = F8;
+            grab_segdata(dyn, addr, ninst, x6, seg);
+            switch((nextop>>3)&7) {
+                case 0: // INC Ed
+                    INST_NAME("INC Ed");
+                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET_PENDING);
+                    GETEDO(x6, 0);
+                    emit_inc32(dyn, ninst, rex, ed, x3, x4);
+                    WBACKO(x6);
+                    break;
+                case 1: //DEC Ed
+                    INST_NAME("DEC Ed");
+                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET_PENDING);
+                    GETEDO(x6, 0);
+                    emit_dec32(dyn, ninst, rex, ed, x3, x4);
+                    WBACKO(x6);
+                    break;
+                case 2: // CALL Ed
+                    INST_NAME("CALL Ed");
+                    PASS2IF(((ninst && dyn->insts[ninst-1].x64.set_flags)
+                        || ((ninst>1) && dyn->insts[ninst-2].x64.set_flags)), 1)
+                    {
+                        READFLAGS(X_PEND);          // that's suspicious
+                    } else {
+                        SETFLAGS(X_ALL, SF_SET);    //Hack to put flag in "don't care" state
+                    }
+                    GETEDOx(x6, 0);
+                    BARRIER(BARRIER_FLOAT);
+                    if(!dyn->insts || ninst==dyn->size-1) {
+                        *need_epilog = 0;
+                        *ok = 0;
+                    }
+                    GETIP_(addr);
+                    PUSH1(xRIP);
+                    jump_to_next(dyn, 0, ed, ninst);
+                    break;
+                case 4: // JMP Ed
+                    INST_NAME("JMP Ed");
+                    BARRIER(1);
+                    GETEDOx(x6, 0);
+                    jump_to_next(dyn, 0, ed, ninst);
+                    *need_epilog = 0;
+                    *ok = 0;
+                    break;
+                case 6: // Push Ed
+                    INST_NAME("PUSH Ed");
+                    GETEDOx(x6, 0);
+                    PUSH1(ed);
+                    break;
+
+                default:
+                    DEFAULT;
+            }
+            break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}

src/dynarec/arm64/dynarec_arm64_66.c

@@ -15,10 +15,10 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
+#include "dynarec_native.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_helper.h"
 #include "dynarec_arm64_functions.h"
 
@@ -27,15 +27,18 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
 {
     uint8_t opcode = F8;
     uint8_t nextop, u8;
-    int32_t i32, j32;
     int16_t i16;
     uint16_t u16;
+    uint64_t u64;
+    int32_t i32;
+    int64_t j64;
     uint8_t gd, ed;
     uint8_t wback, wb1;
-    int fixedaddress;
-    MAYUSE(u16);
+    int64_t fixedaddress;
     MAYUSE(u8);
-    MAYUSE(j32);
+    MAYUSE(u16);
+    MAYUSE(u64);
+    MAYUSE(j64);
 
     while((opcode==0x2E) || (opcode==0x66))   // ignoring CS: or multiple 0x66
         opcode = F8;
@@ -52,12 +55,12 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
     }
 
     if(rex.w && opcode!=0x0f)   // rex.w cancels "66", but not for 66 0f type of prefix
-        return dynarec64_00(dyn, addr-2, ip, ninst, rex, rep, ok, need_epilog);
+        return dynarec64_00(dyn, addr-1, ip, ninst, rex, rep, ok, need_epilog); // addr-1, to "put back" opcode
 
     switch(opcode) {
         case 0x01:
             INST_NAME("ADD Ew, Gw");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             nextop = F8;
             GETGW(x2);
             GETEW(x1, 0);
@@ -66,7 +69,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             break;
         case 0x03:
             INST_NAME("ADD Gw, Ew");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             nextop = F8;
             GETGW(x1);
             GETEW(x2, 0);
@@ -75,7 +78,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             break;
         case 0x05:
             INST_NAME("ADD AX, Iw");
-            SETFLAGS(X_ALL, SF_PENDING);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             i32 = F16;
             UXTHw(x1, xRAX);
             MOV32w(x2, i32);
@@ -85,7 +88,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 
         case 0x09:
             INST_NAME("OR Ew, Gw");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             nextop = F8;
             GETGW(x2);
             GETEW(x1, 0);
@@ -94,7 +97,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             break;
         case 0x0B:
             INST_NAME("OR Gw, Ew");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             nextop = F8;
             GETGW(x1);
             GETEW(x2, 0);
@@ -103,7 +106,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             break;
         case 0x0D:
             INST_NAME("OR AX, Iw");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             i32 = F16;
             UXTHw(x1, xRAX);
             MOV32w(x2, i32);
@@ -117,7 +120,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0x11:
             INST_NAME("ADC Ew, Gw");
             READFLAGS(X_CF);
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             nextop = F8;
             GETGW(x2);
             GETEW(x1, 0);
@@ -127,7 +130,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0x13:
             INST_NAME("ADC Gw, Ew");
             READFLAGS(X_CF);
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             nextop = F8;
             GETGW(x1);
             GETEW(x2, 0);
@@ -137,7 +140,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0x15:
             INST_NAME("ADC AX, Iw");
             READFLAGS(X_CF);
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             i32 = F16;
             UXTHw(x1, xRAX);
             MOV32w(x2, i32);
@@ -148,7 +151,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0x19:
             INST_NAME("SBB Ew, Gw");
             READFLAGS(X_CF);
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             nextop = F8;
             GETGW(x2);
             GETEW(x1, 0);
@@ -158,7 +161,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0x1B:
             INST_NAME("SBB Gw, Ew");
             READFLAGS(X_CF);
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             nextop = F8;
             GETGW(x1);
             GETEW(x2, 0);
@@ -168,17 +171,17 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0x1D:
             INST_NAME("SBB AX, Iw");
             READFLAGS(X_CF);
-            SETFLAGS(X_ALL, SF_SET);
-            i16 = F16;
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            i16 = F16S;
             UXTHw(x1, xRAX);
-            MOV32w(x2, i16);
+            MOVZw(x2, i16);
             emit_sbb16(dyn, ninst, x1, x2, x3, x4);
             BFIx(xRAX, x1, 0, 16);
             break;
 
         case 0x21:
             INST_NAME("AND Ew, Gw");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             nextop = F8;
             GETGW(x2);
             GETEW(x1, 0);
@@ -187,7 +190,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             break;
         case 0x23:
             INST_NAME("AND Gw, Ew");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             nextop = F8;
             GETGW(x1);
             GETEW(x2, 0);
@@ -196,7 +199,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             break;
         case 0x25:
             INST_NAME("AND AX, Iw");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             i32 = F16;
             UXTHw(x1, xRAX);
             MOV32w(x2, i32);
@@ -206,7 +209,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
 
         case 0x29:
             INST_NAME("SUB Ew, Gw");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             nextop = F8;
             GETGW(x2);
             GETEW(x1, 0);
@@ -215,7 +218,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             break;
         case 0x2B:
             INST_NAME("SUB Gw, Ew");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             nextop = F8;
             GETGW(x1);
             GETEW(x2, 0);
@@ -224,7 +227,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             break;
         case 0x2D:
             INST_NAME("SUB AX, Iw");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             i32 = F16;
             UXTHw(x1, xRAX);
             MOV32w(x2, i32);
@@ -234,7 +237,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
 
         case 0x31:
             INST_NAME("XOR Ew, Gw");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             nextop = F8;
             GETGW(x2);
             GETEW(x1, 0);
@@ -243,7 +246,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             break;
         case 0x33:
             INST_NAME("XOR Gw, Ew");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             nextop = F8;
             GETGW(x1);
             GETEW(x2, 0);
@@ -252,7 +255,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             break;
         case 0x35:
             INST_NAME("XOR AX, Iw");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             i32 = F16;
             UXTHw(x1, xRAX);
             MOV32w(x2, i32);
@@ -262,7 +265,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
 
         case 0x39:
             INST_NAME("CMP Ew, Gw");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             nextop = F8;
             GETGW(x2);
             GETEW(x1, 0);
@@ -270,7 +273,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             break;
         case 0x3B:
             INST_NAME("CMP Gw, Ew");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             nextop = F8;
             GETGW(x1);
             GETEW(x2, 0);
@@ -278,7 +281,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             break;
         case 0x3D:
             INST_NAME("CMP AX, Iw");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             i32 = F16;
             UXTHw(x1, xRAX);
             if(i32) {
@@ -325,6 +328,25 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             GWBACK;
             break;
 
+        case 0x70:
+        case 0x71:
+        case 0x72:
+        case 0x73:
+        case 0x74:
+        case 0x75:
+        case 0x76:
+        case 0x77:
+        case 0x78:
+        case 0x79:
+        case 0x7a:
+        case 0x7b:
+        case 0x7c:
+        case 0x7d:
+        case 0x7e:
+        case 0x7f:
+            // just use regular conditional jump
+            return dynarec64_00(dyn, addr-1, ip, ninst, rex, rep, ok, need_epilog);
+
         case 0x81:
         case 0x83:
             nextop = F8;
@@ -335,76 +357,76 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     } else {
                         INST_NAME("ADD Ew, Ib");
                     }
-                    SETFLAGS(X_ALL, SF_SET);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
                     GETEW(x1, (opcode==0x81)?2:1);
                     if(opcode==0x81) i16 = F16S; else i16 = F8S;
-                    MOV32w(x5, i16);
+                    MOVZw(x5, i16);
                     emit_add16(dyn, ninst, ed, x5, x2, x4);
                     EWBACK;
                     break;
                 case 1: //OR
                     if(opcode==0x81) {INST_NAME("OR Ew, Iw");} else {INST_NAME("OR Ew, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
                     GETEW(x1, (opcode==0x81)?2:1);
                     if(opcode==0x81) i16 = F16S; else i16 = F8S;
-                    MOV32w(x5, i16);
+                    MOVZw(x5, i16);
                     emit_or16(dyn, ninst, x1, x5, x2, x4);
                     EWBACK;
                     break;
                 case 2: //ADC
                     if(opcode==0x81) {INST_NAME("ADC Ew, Iw");} else {INST_NAME("ADC Ew, Ib");}
                     READFLAGS(X_CF);
-                    SETFLAGS(X_ALL, SF_SET);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
                     GETEW(x1, (opcode==0x81)?2:1);
                     if(opcode==0x81) i16 = F16S; else i16 = F8S;
-                    MOV32w(x5, i16);
+                    MOVZw(x5, i16);
                     emit_adc16(dyn, ninst, x1, x5, x2, x4);
                     EWBACK;
                     break;
                 case 3: //SBB
                     if(opcode==0x81) {INST_NAME("SBB Ew, Iw");} else {INST_NAME("SBB Ew, Ib");}
                     READFLAGS(X_CF);
-                    SETFLAGS(X_ALL, SF_SET);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
                     GETEW(x1, (opcode==0x81)?2:1);
                     if(opcode==0x81) i16 = F16S; else i16 = F8S;
-                    MOV32w(x5, i16);
+                    MOVZw(x5, i16);
                     emit_sbb16(dyn, ninst, x1, x5, x2, x4);
                     EWBACK;
                     break;
                 case 4: //AND
                     if(opcode==0x81) {INST_NAME("AND Ew, Iw");} else {INST_NAME("AND Ew, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
                     GETEW(x1, (opcode==0x81)?2:1);
                     if(opcode==0x81) i16 = F16S; else i16 = F8S;
-                    MOV32w(x5, i16);
+                    MOVZw(x5, i16);
                     emit_and16(dyn, ninst, x1, x5, x2, x4);
                     EWBACK;
                     break;
                 case 5: //SUB
                     if(opcode==0x81) {INST_NAME("SUB Ew, Iw");} else {INST_NAME("SUB Ew, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
                     GETEW(x1, (opcode==0x81)?2:1);
                     if(opcode==0x81) i16 = F16S; else i16 = F8S;
-                    MOV32w(x5, i16);
+                    MOVZw(x5, i16);
                     emit_sub16(dyn, ninst, x1, x5, x2, x4);
                     EWBACK;
                     break;
                 case 6: //XOR
                     if(opcode==0x81) {INST_NAME("XOR Ew, Iw");} else {INST_NAME("XOR Ew, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
                     GETEW(x1, (opcode==0x81)?2:1);
                     if(opcode==0x81) i16 = F16S; else i16 = F8S;
-                    MOV32w(x5, i16);
+                    MOVZw(x5, i16);
                     emit_xor16(dyn, ninst, x1, x5, x2, x4);
                     EWBACK;
                     break;
                 case 7: //CMP
                     if(opcode==0x81) {INST_NAME("CMP Ew, Iw");} else {INST_NAME("CMP Ew, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
                     GETEW(x1, (opcode==0x81)?2:1);
                     if(opcode==0x81) i16 = F16S; else i16 = F8S;
                     if(i16) {
-                        MOV32w(x2, i16);
+                        MOVZw(x2, i16);
                         emit_cmp16(dyn, ninst, x1, x2, x3, x4, x5);
                     } else
                         emit_cmp16_0(dyn, ninst, x1, x3, x4);
@@ -414,7 +436,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             
         case 0x85:
             INST_NAME("TEST Ew, Gw");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             nextop = F8;
             GETEW(x1, 0);
             GETGW(x2);
@@ -451,8 +473,44 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             }
             break;
 
-        case 0x90:
-            INST_NAME("NOP");
+            case 0x90:
+            case 0x91:
+            case 0x92:
+            case 0x93:
+            case 0x94:
+            case 0x95:
+            case 0x96:
+            case 0x97:
+                gd = xRAX+(opcode&0x07)+(rex.b<<3);
+                if(gd==xRAX) {
+                    INST_NAME("NOP");
+                } else {
+                    INST_NAME("XCHG AX, Reg");
+                    MOVw_REG(x2, xRAX);
+                    BFIx(xRAX, gd, 0, 16);
+                    BFIx(gd, x2, 0, 16);
+                }
+            break;
+
+        case 0x98:
+            INST_NAME("CBW");
+            SXTBw(x1, xRAX);
+            BFIw(xRAX, x1, 0, 16);
+            break;
+
+        case 0xA1:
+            INST_NAME("MOV EAX,Od");
+            u64 = F64;
+            MOV64x(x1, u64);
+            LDRH_U12(x2, x1, 0);
+            BFIx(xRAX, x2, 0, 16);
+            break;
+
+        case 0xA3:
+            INST_NAME("MOV Od,EAX");
+            u64 = F64;
+            MOV64x(x1, u64);
+            STRH_U12(xRAX, x1, 0);
             break;
 
         case 0xA5:
@@ -484,7 +542,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
 
         case 0xA9:
             INST_NAME("TEST AX,Iw");
-            SETFLAGS(X_ALL, SF_SET);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
             u16 = F16;
             MOV32w(x2, u16);
             UBFXx(x1, xRAX, 0, 16);
@@ -534,6 +592,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             switch((nextop>>3)&7) {
                 case 0:
                     INST_NAME("ROL Ew, Ib");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
                     SETFLAGS(X_OF|X_CF, SF_SET);
                     GETEW(x1, 1);
                     u8 = F8;
@@ -543,6 +602,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     break;
                 case 1:
                     INST_NAME("ROR Ew, Ib");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
                     SETFLAGS(X_OF|X_CF, SF_SET);
                     GETEW(x1, 1);
                     u8 = F8;
@@ -552,6 +612,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     break;
                 case 2:
                     INST_NAME("RCL Ew, Ib");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
                     READFLAGS(X_CF);
                     SETFLAGS(X_OF|X_CF, SF_SET);
                     GETEW(x1, 1);
@@ -562,6 +623,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     break;
                 case 3:
                     INST_NAME("RCR Ew, Ib");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
                     READFLAGS(X_CF);
                     SETFLAGS(X_OF|X_CF, SF_SET);
                     GETEW(x1, 1);
@@ -573,24 +635,26 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 case 4:
                 case 6:
                     INST_NAME("SHL Ew, Ib");
+                    UFLAG_IF {MESSAGE(LOG_DUMP, "Need Optimization for flags\n");}
                     SETFLAGS(X_ALL, SF_PENDING);
                     GETEW(x1, 1);
                     u8 = F8;
                     MOV32w(x2, (u8&0x1f));
                     UFLAG_OP12(ed, x2)
-                    LSLw_REG(ed, ed, x2);
+                    LSLw_IMM(ed, ed, u8&0x1f);
                     EWBACK;
                     UFLAG_RES(ed);
                     UFLAG_DF(x3, d_shl16);
                     break;
                 case 5:
                     INST_NAME("SHR Ed, Ib");
+                    UFLAG_IF {MESSAGE(LOG_DUMP, "Need Optimization for flags\n");}
                     SETFLAGS(X_ALL, SF_PENDING);
                     GETEW(x1, 1);
                     u8 = F8;
                     MOV32w(x2, (u8&0x1f));
                     UFLAG_OP12(ed, x2)
-                    LSRw_REG(ed, ed, x2);
+                    LSRw_IMM(ed, ed, u8&0x1f);
                     EWBACK;
                     UFLAG_RES(ed);
                     UFLAG_DF(x3, d_shr16);
@@ -598,6 +662,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 case 7:
                     INST_NAME("SAR Ed, Ib");
                     SETFLAGS(X_ALL, SF_PENDING);
+                    UFLAG_IF {MESSAGE(LOG_DUMP, "Need Optimization for flags\n");}
                     GETSEW(x1, 0);
                     u8 = F8;
                     MOV32w(x2, (u8&0x1f));
@@ -638,6 +703,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         INST_NAME("ROL Ew, CL");
                         ANDSw_mask(x2, xRCX, 0, 0b00100);
                     }
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
                     SETFLAGS(X_OF|X_CF, SF_SET);
                     GETEW(x1, 0);
                     CALL_(rol16, x1, x3);
@@ -651,6 +717,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         INST_NAME("ROR Ew, CL");
                         ANDSw_mask(x2, xRCX, 0, 0b00100);
                     }
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
                     SETFLAGS(X_OF|X_CF, SF_SET);
                     GETEW(x1, 0);
                     CALL_(ror16, x1, x3);
@@ -658,6 +725,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     break;
                 case 2:
                     if(opcode==0xD1) {INST_NAME("RCL Ew, 1"); } else { INST_NAME("RCL Ew, CL");}
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
                     READFLAGS(X_CF);
                     SETFLAGS(X_OF|X_CF, SF_SET);
                     if(opcode==0xD1) {MOV32w(x2, 1);} else {ANDSw_mask(x2, xRCX, 0, 0b00100);}
@@ -667,6 +735,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     break;
                 case 3:
                     if(opcode==0xD1) {INST_NAME("RCR Ew, 1");} else {INST_NAME("RCR Ew, CL");}
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
                     READFLAGS(X_CF);
                     SETFLAGS(X_OF|X_CF, SF_SET);
                     if(opcode==0xD1) {MOV32w(x2, 1);} else {ANDSw_mask(x2, xRCX, 0, 0b00100);}
@@ -683,6 +752,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         INST_NAME("SHL Ew, CL");
                         ANDSw_mask(x4, xRCX, 0, 0b00100);
                     }
+                    UFLAG_IF {MESSAGE(LOG_DUMP, "Need Optimization for flags\n");}
                     SETFLAGS(X_ALL, SF_PENDING);
                     GETEW(x1, 0);
                     UFLAG_OP12(ed, x4)
@@ -699,6 +769,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         INST_NAME("SHR Ew, CL");
                         ANDSw_mask(x4, xRCX, 0, 0b00100);
                     }
+                    UFLAG_IF {MESSAGE(LOG_DUMP, "Need Optimization for flags\n");}
                     SETFLAGS(X_ALL, SF_PENDING);
                     GETEW(x1, 0);
                     UFLAG_OP12(ed, x4)
@@ -715,6 +786,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         INST_NAME("SAR Ew, CL");
                         ANDSw_mask(x4, xRCX, 0, 0b00100);
                     }
+                    UFLAG_IF {MESSAGE(LOG_DUMP, "Need Optimization for flags\n");}
                     SETFLAGS(X_ALL, SF_PENDING);
                     GETSEW(x1, 0);
                     UFLAG_OP12(ed, x4)
@@ -732,7 +804,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                 case 0:
                 case 1:
                     INST_NAME("TEST Ew, Iw");
-                    SETFLAGS(X_ALL, SF_SET);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
                     GETEW(x1, 2);
                     u16 = F16;
                     MOV32w(x2, u16);
@@ -746,7 +818,7 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     break;
                 case 3:
                     INST_NAME("NEG Ew");
-                    SETFLAGS(X_ALL, SF_SET);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
                     GETEW(x1, 0);
                     emit_neg16(dyn, ninst, ed, x2, x4);
                     EWBACK;
@@ -775,12 +847,14 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     break;
                 case 6:
                     INST_NAME("DIV Ew");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
                     SETFLAGS(X_ALL, SF_SET);
                     GETEW(x1, 0);
                     CALL(div16, -1);
                     break;
                 case 7:
                     INST_NAME("IDIV Ew");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
                     SETFLAGS(X_ALL, SF_SET);
                     GETEW(x1, 0);
                     CALL(idiv16, -1);
@@ -793,14 +867,14 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             switch((nextop>>3)&7) {
                 case 0:
                     INST_NAME("INC Ew");
-                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET);
+                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET_PENDING);
                     GETEW(x1, 0);
                     emit_inc16(dyn, ninst, x1, x2, x4);
                     EWBACK;
                     break;
                 case 1:
                     INST_NAME("DEC Ew");
-                    SETFLAGS(X_ALL&~X_CF, SF_SET);
+                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET_PENDING);
                     GETEW(x1, 0);
                     emit_dec16(dyn, ninst, x1, x2, x4);
                     EWBACK;
@@ -814,4 +888,3 @@ uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
     }
     return addr;
 }
-

src/dynarec/arm64/dynarec_arm64_6664.c

@@ -15,20 +15,24 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
+#include "dynarec_native.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_helper.h"
 #include "dynarec_arm64_functions.h"
 
+#define GETG        gd = ((nextop&0x38)>>3)+(rex.r<<3)
 
 uintptr_t dynarec64_6664(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
 {
+    (void)ip; (void)rep; (void)need_epilog;
+
     uint8_t opcode = F8;
     uint8_t nextop;
     uint8_t gd, ed;
-    int fixedaddress;
+    int v0, v1;
+    int64_t fixedaddress;
 
     // REX prefix before the 66 are ignored
     rex.rex = 0;
@@ -44,10 +48,56 @@ uintptr_t dynarec64_6664(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
 
     switch(opcode) {
 
+        case 0x0F:
+            opcode = F8;
+            switch(opcode) {
+
+            case 0xD6:
+                INST_NAME("MOVQ Ex, Gx");
+                nextop = F8;
+                GETG;
+                v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
+                if(MODREG) {
+                    v1 = sse_get_reg_empty(dyn, ninst, x1, (nextop&7) + (rex.b<<3));
+                    FMOVD(v1, v0);
+                } else {
+                    grab_segdata(dyn, addr, ninst, x4, _FS);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 0);
+                    VSTR64_REG(v0, ed, x4);
+                }
+                break;
+
+                default:
+                    DEFAULT;
+            }
+            break;
+
+        case 0x89:
+            INST_NAME("MOV FS:Ew, Gw");
+            nextop = F8;
+            GETGD;  // don't need GETGW here
+            if(MODREG) {
+                ed = xRAX+(nextop&7)+(rex.b<<3);
+                if(rex.w) {
+                    MOVx_REG(ed, gd);
+                } else {
+                    if(ed!=gd) {
+                        BFIx(ed, gd, 0, 16);
+                    }
+                }
+            } else {
+                grab_segdata(dyn, addr, ninst, x4, _FS);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0, rex, 0, 0);
+                if(rex.w) {
+                    STRx_REG(gd, ed, x4);
+                } else {
+                    STRH_REG(gd, ed, x4);
+                }
+            }
+            break;
 
         case 0x8B:
             INST_NAME("MOV Gd, FS:Ed");
-            grab_segdata(dyn, addr, ninst, x4, _FS);
             nextop=F8;
             GETGD;
             if(MODREG) {   // reg <= reg
@@ -60,6 +110,7 @@ uintptr_t dynarec64_6664(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
                     }
                 }
             } else {                    // mem <= reg
+                grab_segdata(dyn, addr, ninst, x4, _FS);
                 addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0, rex, 0, 0);
                 if(rex.w) {
                     LDRx_REG(gd, ed, x4);
@@ -76,4 +127,3 @@ uintptr_t dynarec64_6664(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
     }
     return addr;
 }
-

src/dynarec/arm64/dynarec_arm64_67.c

@@ -0,0 +1,437 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <pthread.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_helper.h"
+#include "dynarec_arm64_functions.h"
+
+#define GETGX(a, w)                     \
+    gd = ((nextop&0x38)>>3)+(rex.r<<3); \
+    a = sse_get_reg(dyn, ninst, x1, gd, w)
+
+#define GETGM(a)                        \
+    gd = ((nextop&0x38)>>3);            \
+    a = mmx_get_reg(dyn, ninst, x1, x2, x3, gd)
+
+#define GETGm   gd = ((nextop&0x38)>>3)
+
+uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
+{
+    (void)ip; (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop;
+    uint8_t gd, ed, wback, wb;
+    int64_t fixedaddress;
+    int8_t  i8;
+    uint8_t u8;
+    int32_t i32;
+    int64_t j64, i64;
+    int v0, v1, s0;
+    MAYUSE(i32);
+    MAYUSE(j64);
+    MAYUSE(v0);
+    MAYUSE(v1);
+    MAYUSE(s0);
+
+    // REX prefix before the 67 are ignored
+    rex.rex = 0;
+    while(opcode>=0x40 && opcode<=0x4f) {
+        rex.rex = opcode;
+        opcode = F8;
+    }
+    rep = 0;
+    while((opcode==0xF2) || (opcode==0xF3)) {
+        rep = opcode-0xF1;
+        opcode = F8;
+    }
+
+    switch(opcode) {
+
+        case 0x0F:
+            opcode=F8;
+            switch(opcode) {
+
+                case 0x2E:
+                    // no special check...
+                case 0x2F:
+                    if(rep) {
+                        DEFAULT;
+                    } else {
+                        if(opcode==0x2F) {INST_NAME("COMISS Gx, Ex");} else {INST_NAME("UCOMISS Gx, Ex");}
+                        SETFLAGS(X_ALL, SF_SET);
+                        nextop = F8;
+                        GETGX(v0, 0);
+                        if(MODREG) {
+                            s0 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3), 0);
+                        } else {
+                            s0 = fpu_get_scratch(dyn);
+                            addr = geted32(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
+                            VLDR32_U12(s0, ed, fixedaddress);
+                        }
+                        FCMPS(v0, s0);
+                        FCOMI(x1, x2);
+                    }
+                    break;
+
+                case 0x6F:
+                    INST_NAME("MOVQ Gm, Em");
+                    nextop = F8;
+                    GETGm;
+                    if(MODREG) {
+                        v1 = mmx_get_reg(dyn, ninst, x1, x2, x3, nextop&7); // no rex.b on MMX
+                        v0 = mmx_get_reg_empty(dyn, ninst, x1, x2, x3, gd);
+                        VMOVeD(v0, 0, v1, 0);
+                    } else {
+                        v0 = mmx_get_reg_empty(dyn, ninst, x1, x2, x3, gd);
+                        addr = geted32(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<3, 7, rex, 0, 0);
+                        VLDR64_U12(v0, ed, fixedaddress);
+                    }
+                    break;
+
+                case 0x7F:
+                    INST_NAME("MOVQ Em, Gm");
+                    nextop = F8;
+                    GETGM(v0);
+                    if(MODREG) {
+                        v1 = mmx_get_reg_empty(dyn, ninst, x1, x2, x3, nextop&7);
+                        VMOV(v1, v0);
+                    } else {
+                        addr = geted32(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<3, 7, rex, 0, 0);
+                        VSTR64_U12(v0, ed, fixedaddress);
+                    }
+                    break;
+
+                default:
+                    DEFAULT;
+            }
+            break;
+
+        case 0x89:
+            INST_NAME("MOV Ed, Gd");
+            nextop=F8;
+            GETGD;
+            if(MODREG) {   // reg <= reg
+                MOVxw_REG(xRAX+(nextop&7)+(rex.b<<3), gd);
+            } else {                    // mem <= reg
+                addr = geted32(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, 0, 0);
+                STRxw_U12(gd, ed, fixedaddress);
+            }
+            break;
+
+        case 0x8D:
+            INST_NAME("LEA Gd, Ed");
+            nextop=F8;
+            GETGD;
+            if(MODREG) {   // reg <= reg? that's an invalid operation
+                DEFAULT;
+            } else {                    // mem <= reg
+                // should a geted32 be created, to use 32bits regs instead of 64bits?
+                addr = geted32(dyn, addr, ninst, nextop, &ed, gd, &fixedaddress, 0, 0, rex, 0, 0);
+                if(ed!=gd) {
+                    MOVw_REG(gd, ed);
+                }
+            }
+            break;
+
+        case 0xC1:
+            nextop = F8;
+            switch((nextop>>3)&7) {
+                case 0:
+                    INST_NAME("ROL Ed, Ib");
+                    SETFLAGS(X_OF|X_CF, SF_SUBSET_PENDING);
+                    GETED32(1);
+                    u8 = (F8)&(rex.w?0x3f:0x1f);
+                    emit_rol32c(dyn, ninst, rex, ed, u8, x3, x4);
+                    if(u8) { WBACK; }
+                    break;
+                case 1:
+                    INST_NAME("ROR Ed, Ib");
+                    SETFLAGS(X_OF|X_CF, SF_SUBSET_PENDING);
+                    GETED32(1);
+                    u8 = (F8)&(rex.w?0x3f:0x1f);
+                    emit_ror32c(dyn, ninst, rex, ed, u8, x3, x4);
+                    if(u8) { WBACK; }
+                    break;
+                case 2:
+                    INST_NAME("RCL Ed, Ib");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_OF|X_CF, SF_SET);
+                    GETED32W(x4, x1, 1);
+                    u8 = F8;
+                    MOV32w(x2, u8);
+                    CALL_(rex.w?((void*)rcl64):((void*)rcl32), ed, x4);
+                    WBACK;
+                    break;
+                case 3:
+                    INST_NAME("RCR Ed, Ib");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_OF|X_CF, SF_SET);
+                    GETED32W(x4, x1, 1);
+                    u8 = F8;
+                    MOV32w(x2, u8);
+                    CALL_(rex.w?((void*)rcr64):((void*)rcr32), ed, x4);
+                    WBACK;
+                    break;
+                case 4:
+                case 6:
+                    INST_NAME("SHL Ed, Ib");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);    // some flags are left undefined
+                    GETED32(1);
+                    u8 = (F8)&(rex.w?0x3f:0x1f);
+                    emit_shl32c(dyn, ninst, rex, ed, u8, x3, x4);
+                    WBACK;
+                    break;
+                case 5:
+                    INST_NAME("SHR Ed, Ib");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);    // some flags are left undefined
+                    GETED32(1);
+                    u8 = (F8)&(rex.w?0x3f:0x1f);
+                    emit_shr32c(dyn, ninst, rex, ed, u8, x3, x4);
+                    if(u8) {
+                        WBACK;
+                    }
+                    break;
+                case 7:
+                    INST_NAME("SAR Ed, Ib");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);    // some flags are left undefined
+                    GETED32(1);
+                    u8 = (F8)&(rex.w?0x3f:0x1f);
+                    emit_sar32c(dyn, ninst, rex, ed, u8, x3, x4);
+                    if(u8) {
+                        WBACK;
+                    }
+                    break;
+            }
+            break;
+            
+        #define GO(NO, YES)                                             \
+            BARRIER(BARRIER_MAYBE);                                     \
+            JUMP(addr+i8, 1);                                           \
+            if(dyn->insts[ninst].x64.jmp_insts==-1 ||                   \
+                CHECK_CACHE()) {                                        \
+                /* out of the block */                                  \
+                i32 = dyn->insts[ninst].epilog-(dyn->native_size);      \
+                Bcond(NO, i32);                                         \
+                if(dyn->insts[ninst].x64.jmp_insts==-1) {               \
+                    if(!dyn->insts[ninst].x64.barrier)                  \
+                        fpu_purgecache(dyn, ninst, 1, x1, x2, x3);      \
+                    jump_to_next(dyn, addr+i8, 0, ninst);               \
+                } else {                                                \
+                    fpuCacheTransform(dyn, ninst, x1, x2, x3);          \
+                    i32 = dyn->insts[dyn->insts[ninst].x64.jmp_insts].address-(dyn->native_size);\
+                    B(i32);                                             \
+                }                                                       \
+            } else {    \
+                /* inside the block */  \
+                i32 = dyn->insts[dyn->insts[ninst].x64.jmp_insts].address-(dyn->native_size);    \
+                Bcond(YES, i32);    \
+            }
+        case 0xE0:
+            INST_NAME("LOOPNZ (32bits)");
+            READFLAGS(X_ZF);
+            i8 = F8S;
+            MOVw_REG(x1, xRCX);
+            SUBSw_U12(x1, x1, 1);
+            BFIx(xRCX, x1, 0, 32);
+            B_NEXT(cEQ);    // ECX is 0, no LOOP
+            TSTw_mask(xFlags, 0b011010, 0); //mask=0x40
+            GO(cNE, cEQ);
+            break;
+        case 0xE1:
+            INST_NAME("LOOPZ (32bits)");
+            READFLAGS(X_ZF);
+            i8 = F8S;
+            MOVw_REG(x1, xRCX);
+            SUBSw_U12(x1, x1, 1);
+            BFIx(xRCX, x1, 0, 32);
+            B_NEXT(cEQ);    // ECX is 0, no LOOP
+            TSTw_mask(xFlags, 0b011010, 0); //mask=0x40
+            GO(cEQ, cNE);
+            break;
+        case 0xE2:
+            INST_NAME("LOOP (32bits)");
+            i8 = F8S;
+            MOVw_REG(x1, xRCX);
+            SUBSw_U12(x1, x1, 1);
+            BFIx(xRCX, x1, 0, 32);
+            GO(cEQ, cNE);
+            break;
+        case 0xE3:
+            INST_NAME("JECXZ");
+            i8 = F8S;
+            MOVw_REG(x1, xRCX);
+            TSTw_REG(x1, x1);
+            GO(cNE, cEQ);
+            break;
+        #undef GO
+
+        case 0xE8:
+            return dynarec64_00(dyn, addr-1, ip, ninst, rex, rep, ok, need_epilog); // addr-1, to "put back" opcode)
+
+        case 0xF7:
+            nextop = F8;
+            switch((nextop>>3)&7) {
+                case 0:
+                case 1:
+                    INST_NAME("TEST Ed, Id");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETED32H(x1, 4);
+                    i64 = F32S;
+                    MOV64xw(x2, i64);
+                    emit_test32(dyn, ninst, rex, ed, x2, x3, x4);
+                    break;
+                case 2:
+                    INST_NAME("NOT Ed");
+                    GETED32(4);
+                    MVNxw_REG(ed, ed);
+                    WBACK;
+                    break;
+                case 3:
+                    INST_NAME("NEG Ed");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETED32(0);
+                    emit_neg32(dyn, ninst, rex, ed, x3, x4);
+                    WBACK;
+                    break;
+                case 4:
+                    INST_NAME("MUL EAX, Ed");
+                    SETFLAGS(X_ALL, SF_PENDING);
+                    UFLAG_DF(x2, rex.w?d_mul64:d_mul32);
+                    GETED32(0);
+                    if(rex.w) {
+                        if(ed==xRDX) gd=x3; else gd=xRDX;
+                        UMULH(gd, xRAX, ed);
+                        MULx(xRAX, xRAX, ed);
+                        if(gd!=xRDX) {MOVx_REG(xRDX, gd);}
+                    } else {
+                        UMULL(xRDX, xRAX, ed);  //64 <- 32x32
+                        MOVw_REG(xRAX, xRDX);
+                        LSRx(xRDX, xRDX, 32);
+                    }
+                    UFLAG_RES(xRAX);
+                    UFLAG_OP1(xRDX);
+                    break;
+                case 5:
+                    INST_NAME("IMUL EAX, Ed");
+                    SETFLAGS(X_ALL, SF_PENDING);
+                    UFLAG_DF(x2, rex.w?d_imul64:d_imul32);
+                    GETED32(0);
+                    if(rex.w) {
+                        if(ed==xRDX) gd=x3; else gd=xRDX;
+                        SMULH(gd, xRAX, ed);
+                        MULx(xRAX, xRAX, ed);
+                        if(gd!=xRDX) {MOVx_REG(xRDX, gd);}
+                    } else {
+                        SMULL(xRDX, xRAX, ed);  //64 <- 32x32
+                        MOVw_REG(xRAX, xRDX);
+                        LSRx(xRDX, xRDX, 32);
+                    }
+                    UFLAG_RES(xRAX);
+                    UFLAG_OP1(xRDX);
+                    break;
+                case 6:
+                    INST_NAME("DIV Ed");
+                    SETFLAGS(X_ALL, SF_SET);
+                    if(!rex.w) {
+                        SET_DFNONE(x2);
+                        GETED32(0);
+                        MOVw_REG(x3, xRAX);
+                        ORRx_REG_LSL(x3, x3, xRDX, 32);
+                        if(MODREG) {
+                            MOVw_REG(x4, ed);
+                            ed = x4;
+                        }
+                        UDIVx(x2, x3, ed);
+                        MSUBx(x4, x2, ed, xRAX);
+                        MOVw_REG(xRAX, x2);
+                        MOVw_REG(xRDX, x4);
+                    } else {
+                        if(ninst && dyn->insts 
+                           && dyn->insts[ninst-1].x64.addr 
+                           && *(uint8_t*)(dyn->insts[ninst-1].x64.addr)==0x31 
+                           && *(uint8_t*)(dyn->insts[ninst-1].x64.addr+1)==0xD2) {
+                            SET_DFNONE(x2);
+                            GETED32(0);
+                            UDIVx(x2, xRAX, ed);
+                            MSUBx(xRDX, x2, ed, xRAX);
+                            MOVx_REG(xRAX, x2);
+                        } else {
+                            GETED32H(x1, 0);  // get edd changed addr, so cannot be called 2 times for same op...
+                            CBZxw_MARK(xRDX);
+                            if(ed!=x1) {MOVx_REG(x1, ed);}
+                            CALL(div64, -1);
+                            B_NEXT_nocond;
+                            MARK;
+                            UDIVx(x2, xRAX, ed);
+                            MSUBx(xRDX, x2, ed, xRAX);
+                            MOVx_REG(xRAX, x2);
+                            SET_DFNONE(x2);
+                        }
+                    }
+                    break;
+                case 7:
+                    INST_NAME("IDIV Ed");
+                    SETFLAGS(X_ALL, SF_SET);
+                    if(!rex.w) {
+                        SET_DFNONE(x2)
+                        GETSED32w(0);
+                        MOVw_REG(x3, xRAX);
+                        ORRx_REG_LSL(x3, x3, xRDX, 32);
+                        SDIVx(x2, x3, wb);
+                        MSUBx(x4, x2, wb, x3);
+                        MOVw_REG(xRAX, x2);
+                        MOVw_REG(xRDX, x4);
+                    } else {
+                        if(ninst && dyn->insts
+                           &&  dyn->insts[ninst-1].x64.addr 
+                           && *(uint8_t*)(dyn->insts[ninst-1].x64.addr)==0x48
+                           && *(uint8_t*)(dyn->insts[ninst-1].x64.addr+1)==0x99) {
+                            SET_DFNONE(x2)
+                            GETED32(0);
+                            SDIVx(x2, xRAX, ed);
+                            MSUBx(xRDX, x2, ed, xRAX);
+                            MOVx_REG(xRAX, x2);
+                        } else {
+                            GETED32H(x1, 0);  // get edd changed addr, so cannot be called 2 times for same op...
+                            CBZxw_MARK(xRDX);
+                            MVNx_REG(x2, xRDX);
+                            CBZxw_MARK(x2);
+                            if(ed!=x1) {MOVx_REG(x1, ed);}
+                            CALL((void*)idiv64, -1);
+                            B_NEXT_nocond;
+                            MARK;
+                            SDIVx(x2, xRAX, ed);
+                            MSUBx(xRDX, x2, ed, xRAX);
+                            MOVx_REG(xRAX, x2);
+                            SET_DFNONE(x2)
+                        }
+                    }
+                    break;
+            }
+            break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}

src/dynarec/arm64/dynarec_arm64_d8.c

@@ -15,20 +15,22 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
 #include "emu/x87emu_private.h"
+#include "dynarec_native.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_helper.h"
 #include "dynarec_arm64_functions.h"
 
 
 uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
 {
+    (void)ip; (void)rep; (void)need_epilog;
+
     uint8_t nextop = F8;
     uint8_t ed;
-    int fixedaddress;
+    int64_t fixedaddress;
     int v1, v2;
     int s0;
 
@@ -46,9 +48,13 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xC6:
         case 0xC7:
             INST_NAME("FADD ST0, STx");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            FADDD(v1, v1, v2);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FADDS(v1, v1, v2);
+            } else {
+                FADDD(v1, v1, v2);
+            }
             break;
         case 0xC8:
         case 0xC9:
@@ -59,9 +65,13 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xCE:
         case 0xCF:
             INST_NAME("FMUL ST0, STx");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            FMULD(v1, v1, v2);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FMULS(v1, v1, v2);
+            } else {
+                FMULD(v1, v1, v2);
+            }
             break;
         case 0xD0:
         case 0xD1:
@@ -72,9 +82,13 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xD6:
         case 0xD7:
             INST_NAME("FCOM ST0, STx");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            FCMPD(v1, v2);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
             FCOM(x1, x2, x3);
             break;
         case 0xD8:
@@ -86,11 +100,15 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xDE:
         case 0xDF:
             INST_NAME("FCOMP ST0, STx");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            FCMPD(v1, v2);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
             FCOM(x1, x2, x3);
-            x87_do_pop(dyn, ninst);
+            x87_do_pop(dyn, ninst, x3);
             break;
         case 0xE0:
         case 0xE1:
@@ -101,9 +119,13 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xE6:
         case 0xE7:
             INST_NAME("FSUB ST0, STx");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            FSUBD(v1, v1, v2);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FSUBS(v1, v1, v2);
+            } else {
+                FSUBD(v1, v1, v2);
+            }
             break;
         case 0xE8:
         case 0xE9:
@@ -114,9 +136,13 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xEE:
         case 0xEF:
             INST_NAME("FSUBR ST0, STx");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            FSUBD(v1, v2, v1);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FSUBS(v1, v2, v1);
+            } else {
+                FSUBD(v1, v2, v1);
+            }
             break;
         case 0xF0:
         case 0xF1:
@@ -127,9 +153,13 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xF6:
         case 0xF7:
             INST_NAME("FDIV ST0, STx");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            FDIVD(v1, v1, v2);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FDIVS(v1, v1, v2);
+            } else {
+                FDIVD(v1, v1, v2);
+            }
             break;
         case 0xF8:
         case 0xF9:
@@ -140,87 +170,123 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xFE:
         case 0xFF:
             INST_NAME("FDIVR ST0, STx");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            FDIVD(v1, v2, v1);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FDIVS(v1, v2, v1);
+            } else {
+                FDIVD(v1, v2, v1);
+            }
             break;
       
         default:
             switch((nextop>>3)&7) {
                 case 0:
                     INST_NAME("FADD ST0, float[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
                     s0 = fpu_get_scratch(dyn);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
                     VLDR32_U12(s0, ed, fixedaddress);
-                    FCVT_D_S(s0, s0);
-                    FADDD(v1, v1, s0);
+                    if(ST_IS_F(0)) {
+                        FADDS(v1, v1, s0);
+                    } else {
+                        FCVT_D_S(s0, s0);
+                        FADDD(v1, v1, s0);
+                    }
                     break;
                 case 1:
                     INST_NAME("FMUL ST0, float[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
                     s0 = fpu_get_scratch(dyn);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
                     VLDR32_U12(s0, ed, fixedaddress);
-                    FCVT_D_S(s0, s0);
-                    FMULD(v1, v1, s0);
+                    if(ST_IS_F(0)) {
+                        FMULS(v1, v1, s0);
+                    } else {
+                        FCVT_D_S(s0, s0);
+                        FMULD(v1, v1, s0);
+                    }
                     break;
                 case 2:
                     INST_NAME("FCOM ST0, float[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
                     s0 = fpu_get_scratch(dyn);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
                     VLDR32_U12(s0, ed, fixedaddress);
-                    FCVT_D_S(s0, s0);
-                    FCMPD(v1, s0);
+                    if(ST_IS_F(0)) {
+                        FCMPS(v1, s0);
+                    } else {
+                        FCVT_D_S(s0, s0);
+                        FCMPD(v1, s0);
+                    }
                     FCOM(x1, x2, x3);
                     break;
                 case 3:
                     INST_NAME("FCOMP ST0, float[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
                     s0 = fpu_get_scratch(dyn);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
                     VLDR32_U12(s0, ed, fixedaddress);
-                    FCVT_D_S(s0, s0);
-                    FCMPD(v1, s0);
+                    if(ST_IS_F(0)) {
+                        FCMPS(v1, s0);
+                    } else {
+                        FCVT_D_S(s0, s0);
+                        FCMPD(v1, s0);
+                    }
                     FCOM(x1, x2, x3);
-                    x87_do_pop(dyn, ninst);
+                    x87_do_pop(dyn, ninst, x3);
                     break;
                 case 4:
                     INST_NAME("FSUB ST0, float[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
                     s0 = fpu_get_scratch(dyn);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
                     VLDR32_U12(s0, ed, fixedaddress);
-                    FCVT_D_S(s0, s0);
-                    FSUBD(v1, v1, s0);
+                    if(ST_IS_F(0)) {
+                        FSUBS(v1, v1, s0);
+                    } else {
+                        FCVT_D_S(s0, s0);
+                        FSUBD(v1, v1, s0);
+                    }
                     break;
                 case 5:
                     INST_NAME("FSUBR ST0, float[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
                     s0 = fpu_get_scratch(dyn);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
                     VLDR32_U12(s0, ed, fixedaddress);
-                    FCVT_D_S(s0, s0);
-                    FSUBD(v1, s0, v1);
+                    if(ST_IS_F(0)) {
+                        FSUBS(v1, s0, v1);
+                    } else {
+                        FCVT_D_S(s0, s0);
+                        FSUBD(v1, s0, v1);
+                    }
                     break;
                 case 6:
                     INST_NAME("FDIV ST0, float[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
                     s0 = fpu_get_scratch(dyn);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
                     VLDR32_U12(s0, ed, fixedaddress);
-                    FCVT_D_S(s0, s0);
-                    FDIVD(v1, v1, s0);
+                    if(ST_IS_F(0)) {
+                        FDIVS(v1, v1, s0);
+                    } else {
+                        FCVT_D_S(s0, s0);
+                        FDIVD(v1, v1, s0);
+                    }
                     break;
                 case 7:
                     INST_NAME("FDIVR ST0, float[ED]");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
                     s0 = fpu_get_scratch(dyn);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
                     VLDR32_U12(s0, ed, fixedaddress);
-                    FCVT_D_S(s0, s0);
-                    FDIVD(v1, s0, v1);
+                    if(ST_IS_F(0)) {
+                        FDIVS(v1, s0, v1);
+                    } else {
+                        FCVT_D_S(s0, s0);
+                        FDIVD(v1, s0, v1);
+                    }
                     break;
                 default:
                     DEFAULT;
@@ -228,4 +294,3 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
     }
     return addr;
 }
-

src/dynarec/arm64/dynarec_arm64_d9.c

@@ -15,21 +15,23 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
 #include "emu/x87emu_private.h"
+#include "dynarec_native.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_helper.h"
 #include "dynarec_arm64_functions.h"
 
 
 uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
 {
+    (void)ip; (void)rep; (void)need_epilog;
+
     uint8_t nextop = F8;
     uint8_t ed;
     uint8_t wback, wb1;
-    int fixedaddress;
+    int64_t fixedaddress;
     int v1, v2;
     int s0;
     int i1, i2, i3;
@@ -48,12 +50,18 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xC6:
         case 0xC7:
             INST_NAME("FLD STx");
-            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            v2 = x87_do_push(dyn, ninst);
-            FMOVD(v2, v1);
+            v2 = x87_do_push(dyn, ninst, x1, X87_ST(nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, (nextop&7)+1, X87_COMBINE(0, (nextop&7)+1));
+            if(ST_IS_F(0)) {
+                FMOVS(v2, v1);
+            } else {
+                FMOVD(v2, v1);
+            }
             break;
 
         case 0xC8:
+            INST_NAME("FXCH ST0");
+            break;
         case 0xC9:
         case 0xCA:
         case 0xCB:
@@ -63,11 +71,8 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xCF:
             INST_NAME("FXCH STx");
             // swap the cache value, not the double value itself :p
-            i1 = x87_get_cache(dyn, ninst, x1, x2, nextop&7);
-            i2 = x87_get_cache(dyn, ninst, x1, x2, 0);
-            i3 = dyn->x87cache[i1];
-            dyn->x87cache[i1] = dyn->x87cache[i2];
-            dyn->x87cache[i2] = i3;
+            x87_swapreg(dyn, ninst, x1, x2, 0, nextop&7);
+            // should set C1 to 0
             break;
 
         case 0xD0:
@@ -76,71 +81,178 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
 
         case 0xE0:
             INST_NAME("FCHS");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            FNEGD(v1, v1);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+            if(ST_IS_F(0)) {
+                FNEGS(v1, v1);
+            } else {
+                FNEGD(v1, v1);
+            }
             break;
         case 0xE1:
             INST_NAME("FABS");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            FABSD(v1, v1);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+            if(ST_IS_F(0)) {
+                FABSS(v1, v1);
+            } else {
+                FABSD(v1, v1);
+            }
             break;
 
         case 0xE4:
             INST_NAME("FTST");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            FCMPD_0(v1);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+            if(ST_IS_F(0)) {
+                FCMPS_0(v1);
+            } else {
+                FCMPD_0(v1);
+            }
             FCOM(x1, x2, x3);   // same flags...
             break;
         case 0xE5:
             INST_NAME("FXAM");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             x87_refresh(dyn, ninst, x1, x2, 0);
             CALL(fpu_fxam, -1);  // should be possible inline, but is it worth it?
             break;
 
         case 0xE8:
             INST_NAME("FLD1");
-            v1 = x87_do_push(dyn, ninst);
-            FTABLE64(v1, 1.0);
+            v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_F);
+            if(ST_IS_F(0)) {
+                FMOVS_8(v1, 0b01110000);
+            } else {
+                FMOVD_8(v1, 0b01110000);
+            }
             break;
         case 0xE9:
             INST_NAME("FLDL2T");
-            v1 = x87_do_push(dyn, ninst);
+            v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_D);
             FTABLE64(v1, L2T);
             break;
         case 0xEA:     
             INST_NAME("FLDL2E");
-            v1 = x87_do_push(dyn, ninst);
+            v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_D);
             FTABLE64(v1, L2E);
             break;
         case 0xEB:
             INST_NAME("FLDPI");
-            v1 = x87_do_push(dyn, ninst);
+            v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_D);
             FTABLE64(v1, PI);
             break;
         case 0xEC:
             INST_NAME("FLDLG2");
-            v1 = x87_do_push(dyn, ninst);
+            v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_D);
             FTABLE64(v1, LG2);
             break;
         case 0xED:
             INST_NAME("FLDLN2");
-            v1 = x87_do_push(dyn, ninst);
+            v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_D);
             FTABLE64(v1, LN2);
             break;
         case 0xEE:
             INST_NAME("FLDZ");
-            v1 = x87_do_push(dyn, ninst);
-            FTABLE64(v1, 0.0);
+            v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_F);
+            VEOR(v1, v1, v1);
             break;
 
+        case 0xF0:
+            INST_NAME("F2XM1");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
+            x87_forget(dyn, ninst, x1, x2, 0);
+            CALL(arm_f2xm1, -1);
+            break;
+        case 0xF1:
+            INST_NAME("FYL2X");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
+            x87_forget(dyn, ninst, x1, x2, 0);
+            x87_forget(dyn, ninst, x1, x2, 1);
+            CALL(arm_fyl2x, -1);
+            x87_do_pop(dyn, ninst, x3);
+            break;
+        case 0xF2:
+            INST_NAME("FPTAN");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
+            x87_forget(dyn, ninst, x1, x2, 0);
+            CALL(arm_ftan, -1);
+            v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_F);
+            if(ST_IS_F(0)) {
+                FMOVS_8(v1, 0b01110000);
+            } else {
+                FMOVD_8(v1, 0b01110000);
+            }
+            break;
+        case 0xF3:
+            INST_NAME("FPATAN");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
+            x87_forget(dyn, ninst, x1, x2, 0);
+            x87_forget(dyn, ninst, x1, x2, 1);
+            CALL(arm_fpatan, -1);
+            x87_do_pop(dyn, ninst, x3);
+            break;
+        case 0xF4:
+            INST_NAME("FXTRACT");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
+            x87_do_push_empty(dyn, ninst, 0);
+            x87_forget(dyn, ninst, x1, x2, 1);
+            CALL(arm_fxtract, -1);
+            break;
+        case 0xF5:
+            INST_NAME("FPREM1");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
+            x87_forget(dyn, ninst, x1, x2, 0);
+            x87_forget(dyn, ninst, x1, x2, 1);
+            CALL(arm_fprem1, -1);
+            break;
+        case 0xF6:
+            INST_NAME("FDECSTP");
+            fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
+            LDRw_U12(x2, xEmu, offsetof(x64emu_t, top));
+            SUBw_U12(x2, x2, 1);
+            ANDw_mask(x2, x2, 0, 2);    //mask=7
+            STRw_U12(x2, xEmu, offsetof(x64emu_t, top));
+            break;
+        case 0xF7:
+            INST_NAME("FINCSTP");
+            fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
+            LDRw_U12(x2, xEmu, offsetof(x64emu_t, top));
+            ADDw_U12(x2, x2, 1);
+            ANDw_mask(x2, x2, 0, 2);    //mask=7
+            STRw_U12(x2, xEmu, offsetof(x64emu_t, top));
+            break;
+        case 0xF8:
+            INST_NAME("FPREM");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
+            x87_forget(dyn, ninst, x1, x2, 0);
+            x87_forget(dyn, ninst, x1, x2, 1);
+            CALL(arm_fprem, -1);
+            break;
+        case 0xF9:
+            INST_NAME("FYL2XP1");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
+            x87_forget(dyn, ninst, x1, x2, 0);
+            x87_forget(dyn, ninst, x1, x2, 1);
+            CALL(arm_fyl2xp1, -1);
+            x87_do_pop(dyn, ninst, x3);
+            break;
         case 0xFA:
             INST_NAME("FSQRT");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            FSQRTD(v1, v1);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+            if(ST_IS_F(0)) {
+                FSQRTS(v1, v1);
+            } else {
+                FSQRTD(v1, v1);
+            }
+            break;
+        case 0xFB:
+            INST_NAME("FSINCOS");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
+            x87_do_push_empty(dyn, ninst, 0);
+            x87_forget(dyn, ninst, x1, x2, 1);
+            CALL(arm_fsincos, -1);
             break;
-
         case 0xFC:
             INST_NAME("FRNDINT");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             // use C helper for now, nothing staightforward is available
             x87_forget(dyn, ninst, x1, x2, 0);
             CALL(arm_frndint, -1);
@@ -156,92 +268,22 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             x87_restoreround(dyn, ninst, u8);
             */
             break;
-        case 0xF0:
-            INST_NAME("F2XM1");
-            x87_forget(dyn, ninst, x1, x2, 0);
-            CALL(arm_f2xm1, -1);
-            break;
-        case 0xF1:
-            INST_NAME("FYL2X");
-            x87_forget(dyn, ninst, x1, x2, 0);
-            x87_forget(dyn, ninst, x1, x2, 1);
-            CALL(arm_fyl2x, -1);
-            x87_do_pop(dyn, ninst);
-            break;
-        case 0xF2:
-            INST_NAME("FTAN");
-            x87_forget(dyn, ninst, x1, x2, 0);
-            CALL(arm_ftan, -1);
-            v1 = x87_do_push(dyn, ninst);
-            FTABLE64(v1, 1.0);
-            break;
-        case 0xF3:
-            INST_NAME("FPATAN");
-            x87_forget(dyn, ninst, x1, x2, 0);
-            x87_forget(dyn, ninst, x1, x2, 1);
-            CALL(arm_fpatan, -1);
-            x87_do_pop(dyn, ninst);
-            break;
-        case 0xF4:
-            INST_NAME("FXTRACT");
-            x87_do_push_empty(dyn, ninst, 0);
-            x87_forget(dyn, ninst, x1, x2, 1);
-            CALL(arm_fxtract, -1);
-            break;
-        case 0xF5:
-            INST_NAME("FPREM1");
-            x87_forget(dyn, ninst, x1, x2, 0);
-            x87_forget(dyn, ninst, x1, x2, 1);
-            CALL(arm_fprem1, -1);
-            break;
-        case 0xF6:
-            INST_NAME("FDECSTP");
-            fpu_purgecache(dyn, ninst, x1, x2, x3);
-            LDRw_U12(x2, xEmu, offsetof(x64emu_t, top));
-            SUBw_U12(x2, x2, 1);
-            ANDw_mask(x2, x2, 0, 2);    //mask=7
-            STRw_U12(x2, xEmu, offsetof(x64emu_t, top));
-            break;
-        case 0xF7:
-            INST_NAME("FINCSTP");
-            fpu_purgecache(dyn, ninst, x1, x2, x3);
-            LDRw_U12(x2, xEmu, offsetof(x64emu_t, top));
-            ADDw_U12(x2, x2, 1);
-            ANDw_mask(x2, x2, 0, 2);    //mask=7
-            STRw_U12(x2, xEmu, offsetof(x64emu_t, top));
-            break;
-        case 0xF8:
-            INST_NAME("FPREM");
-            x87_forget(dyn, ninst, x1, x2, 0);
-            x87_forget(dyn, ninst, x1, x2, 1);
-            CALL(arm_fprem, -1);
-            break;
-        case 0xF9:
-            INST_NAME("FYL2XP1");
-            x87_forget(dyn, ninst, x1, x2, 0);
-            x87_forget(dyn, ninst, x1, x2, 1);
-            CALL(arm_fyl2xp1, -1);
-            x87_do_pop(dyn, ninst);
-            break;
-        case 0xFB:
-            INST_NAME("FSINCOS");
-            x87_do_push_empty(dyn, ninst, 0);
-            x87_forget(dyn, ninst, x1, x2, 1);
-            CALL(arm_fsincos, -1);
-            break;
         case 0xFD:
             INST_NAME("FSCALE");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             x87_forget(dyn, ninst, x1, x2, 0);
             x87_forget(dyn, ninst, x1, x2, 1);
             CALL(arm_fscale, -1);
             break;
         case 0xFE:
             INST_NAME("FSIN");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             x87_forget(dyn, ninst, x1, x2, 0);
             CALL(arm_fsin, -1);
             break;
         case 0xFF:
             INST_NAME("FCOS");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             x87_forget(dyn, ninst, x1, x2, 0);
             CALL(arm_fcos, -1);
             break;
@@ -272,32 +314,46 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             switch((nextop>>3)&7) {
                 case 0:
                     INST_NAME("FLD ST0, float[ED]");
-                    v1 = x87_do_push(dyn, ninst);
-                    s0 = fpu_get_scratch(dyn);
+                    v1 = x87_do_push(dyn, ninst, x1, box64_dynarec_x87double?NEON_CACHE_ST_D:NEON_CACHE_ST_F);
+                    if(ST_IS_F(0))
+                        s0 = v1;
+                    else
+                        s0 = fpu_get_scratch(dyn);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
                     VLDR32_U12(s0, ed, fixedaddress);
-                    FCVT_D_S(v1, s0);
+                    if(!ST_IS_F(0)) {
+                        FCVT_D_S(v1, s0);
+                    }
                     break;
                 case 2:
                     INST_NAME("FST float[ED], ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    s0 = fpu_get_scratch(dyn);
-                    FCVT_S_D(s0, v1);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
+                    if(ST_IS_F(0))
+                        s0 = v1;
+                    else {
+                        s0 = fpu_get_scratch(dyn);
+                        FCVT_S_D(s0, v1);
+                    }
                     addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
                     VSTR32_U12(s0, ed, fixedaddress);
                     break;
                 case 3:
                     INST_NAME("FSTP float[ED], ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    s0 = fpu_get_scratch(dyn);
-                    FCVT_S_D(s0, v1);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
+                    if(ST_IS_F(0))
+                        s0 = v1;
+                    else {
+                        s0 = fpu_get_scratch(dyn);
+                        FCVT_S_D(s0, v1);
+                    }
                     addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
                     VSTR32_U12(s0, ed, fixedaddress);
-                    x87_do_pop(dyn, ninst);
+                    x87_do_pop(dyn, ninst, x3);
                     break;
                 case 4:
                     INST_NAME("FLDENV Ed");
-                    fpu_purgecache(dyn, ninst, x1, x2, x3); // maybe only x87, not SSE?
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    fpu_purgecache(dyn, ninst, 0, x1, x2, x3); // maybe only x87, not SSE?
                     addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 0);
                     if(ed!=x1) {
                         MOVx_REG(x1, ed);
@@ -314,7 +370,8 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     break;
                 case 6:
                     INST_NAME("FNSTENV Ed");
-                    fpu_purgecache(dyn, ninst, x1, x2, x3); // maybe only x87, not SSE?
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    fpu_purgecache(dyn, ninst, 0, x1, x2, x3); // maybe only x87, not SSE?
                     addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 0);
                     if(ed!=x1) {
                         MOVx_REG(x1, ed);
@@ -336,4 +393,3 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
     }
     return addr;
 }
-

src/dynarec/arm64/dynarec_arm64_db.c

@@ -15,30 +15,32 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
 #include "emu/x87emu_private.h"
+#include "dynarec_native.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_helper.h"
 #include "dynarec_arm64_functions.h"
 
 
 uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
 {
+    (void)ip; (void)rep; (void)need_epilog;
+
     uint8_t nextop = F8;
     uint8_t ed;
     uint8_t wback;
     uint8_t u8;
-    int fixedaddress;
+    int64_t fixedaddress;
     int v1, v2;
     int s0;
-    int j32;
+    int64_t j64;
 
     MAYUSE(s0);
     MAYUSE(v2);
     MAYUSE(v1);
-    MAYUSE(j32);
+    MAYUSE(j64);
 
     switch(nextop) {
         case 0xC0:
@@ -51,10 +53,14 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xC7:
             INST_NAME("FCMOVNB ST0, STx");
             READFLAGS(X_CF);
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
             TSTw_mask(xFlags, 0, 0);    //mask=1<<F_CF
-            FCSELD(v1, v2, v1, cEQ);    // F_CF==0
+            if(ST_IS_F(0)) {
+                FCSELS(v1, v2, v1, cEQ);
+            } else {
+                FCSELD(v1, v2, v1, cEQ);    // F_CF==0
+            }
             break;
         case 0xC8:
         case 0xC9:
@@ -66,10 +72,14 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xCF:
             INST_NAME("FCMOVNE ST0, STx");
             READFLAGS(X_ZF);
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
             TSTw_mask(xFlags, 0b011010, 0); //mask=1<<F_ZF
-            FCSELD(v1, v2, v1, cEQ);        // F_ZF==0
+            if(ST_IS_F(0)) {
+                FCSELS(v1, v2, v1, cEQ);
+            } else {
+                FCSELD(v1, v2, v1, cEQ);        // F_ZF==0
+            }
             break;
         case 0xD0:
         case 0xD1:
@@ -81,11 +91,15 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xD7:
             INST_NAME("FCMOVNBE ST0, STx");
             READFLAGS(X_CF|X_ZF);
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
             MOV32w(x1, (1<<F_CF)|(1<<F_ZF));
             TSTw_REG(xFlags, x1);
-            FCSELD(v1, v2, v1, cEQ);   // F_CF==0 & F_ZF==0
+            if(ST_IS_F(0)) {
+                FCSELS(v1, v2, v1, cEQ);
+            } else {
+                FCSELD(v1, v2, v1, cEQ);   // F_CF==0 & F_ZF==0
+            }
             break;
         case 0xD8:
         case 0xD9:
@@ -97,10 +111,14 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xDF:
             INST_NAME("FCMOVNU ST0, STx");
             READFLAGS(X_PF);
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
             TSTw_mask(xFlags, 0b011110, 0); //mask=1<<F_PF
-            FCSELD(v1, v2, v1, cEQ);        // F_PF==0
+            if(ST_IS_F(0)) {
+                FCSELS(v1, v2, v1, cEQ);
+            } else {
+                FCSELD(v1, v2, v1, cEQ);        // F_PF==0
+            }
             break;
         case 0xE1:
             INST_NAME("FDISI8087_NOP"); // so.. NOP?
@@ -115,7 +133,8 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             break;
         case 0xE3:
             INST_NAME("FNINIT");
-            x87_purgecache(dyn, ninst, x1, x2, x3);
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
+            x87_purgecache(dyn, ninst, 0, x1, x2, x3);
             CALL(reset_fpu, -1);
             break;
         case 0xE8:
@@ -128,9 +147,13 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xEF:
             INST_NAME("FUCOMI ST0, STx");
             SETFLAGS(X_ALL, SF_SET);
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            FCMPD(v1, v2);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
             FCOMI(x1, x2);
             break;
         case 0xF0:  
@@ -143,9 +166,13 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xF7:
             INST_NAME("FCOMI ST0, STx");
             SETFLAGS(X_ALL, SF_SET);
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            FCMPD(v1, v2);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
             FCOMI(x1, x2);
             break;
 
@@ -161,7 +188,7 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             switch((nextop>>3)&7) {
                 case 0:
                     INST_NAME("FILD ST0, Ed");
-                    v1 = x87_do_push(dyn, ninst);
+                    v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_D);
                     s0 = fpu_get_scratch(dyn);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
                     VLDR32_U12(s0, ed, fixedaddress);
@@ -170,7 +197,7 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     break;
                 case 1:
                     INST_NAME("FISTTP Ed, ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
                     if(MODREG) {
                         ed = xRAX+(nextop&7)+(rex.b<<3);
                         wback = 0;
@@ -184,23 +211,24 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     FCVTZSwD(ed, s0);
                     WBACK;
                     #else
-                    MSR_fpsr(x5);
-                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
                     MRS_fpsr(x5);
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    MSR_fpsr(x5);
                     FRINTZD(s0, v1);
                     VFCVTZSd(s0, s0);
                     SQXTN_S_D(s0, s0);
                     VSTR32_U12(s0, wback, fixedaddress);
-                    MSR_fpsr(x5);   // get back FPSR to check the IOC bit
-                    TBZ_NEXT(x5, FPSR_IOC);
+                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                    TBZ_MARK3(x5, FPSR_IOC);
                     MOV32w(x5, 0x80000000);
                     STRw_U12(x5, wback, fixedaddress);
+                    MARK3;
                     #endif
-                    x87_do_pop(dyn, ninst);
+                    x87_do_pop(dyn, ninst, x3);
                     break;
                 case 2:
                     INST_NAME("FIST Ed, ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
                     u8 = x87_setround(dyn, ninst, x1, x2, x4); // x1 have the modified RPSCR reg
                     if(MODREG) {
                         ed = xRAX+(nextop&7)+(rex.b<<3);
@@ -215,23 +243,24 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     FCVTZSwD(ed, s0);
                     WBACK;
                     #else
-                    MSR_fpsr(x5);
-                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
                     MRS_fpsr(x5);
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    MSR_fpsr(x5);
                     FRINTXD(s0, v1);
                     VFCVTZSd(s0, s0);
                     SQXTN_S_D(s0, s0);
                     VSTR32_U12(s0, wback, fixedaddress);
-                    MSR_fpsr(x5);   // get back FPSR to check the IOC bit
-                    TBZ_NEXT(x5, FPSR_IOC);
+                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                    TBZ_MARK3(x5, FPSR_IOC);
                     MOV32w(x5, 0x80000000);
                     STRw_U12(x5, wback, fixedaddress);
+                    MARK3;
                     #endif
                     x87_restoreround(dyn, ninst, u8);
                     break;
                 case 3:
                     INST_NAME("FISTP Ed, ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
                     u8 = x87_setround(dyn, ninst, x1, x2, x4); // x1 have the modified RPSCR reg
                     if(MODREG) {
                         ed = xRAX+(nextop&7)+(rex.b<<3);
@@ -246,29 +275,43 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     FCVTZSwD(ed, s0);
                     WBACK;
                     #else
-                    MSR_fpsr(x5);
-                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
                     MRS_fpsr(x5);
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    MSR_fpsr(x5);
                     FRINTXD(s0, v1);
                     VFCVTZSd(s0, s0);
                     SQXTN_S_D(s0, s0);
                     VSTR32_U12(s0, wback, fixedaddress);
-                    MSR_fpsr(x5);   // get back FPSR to check the IOC bit
-                    TBZ_NEXT(x5, FPSR_IOC);
+                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                    TBZ_MARK3(x5, FPSR_IOC);
                     MOV32w(x5, 0x80000000);
                     STRw_U12(x5, wback, fixedaddress);
+                    MARK3;
                     #endif
                     x87_restoreround(dyn, ninst, u8);
-                    x87_do_pop(dyn, ninst);
+                    x87_do_pop(dyn, ninst, x3);
                     break;
                 case 5:
                     INST_NAME("FLD tbyte");
-                    x87_do_push_empty(dyn, ninst, x1);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 0);
-                    if(ed!=x1) {
-                        MOVx_REG(x1, ed);
+                    if(PK(0)==0xDB && ((PK(1)>>3)&7)==7) {
+                        // the FLD is immediatly followed by an FSTP
+                        LDRx_U12(x5, ed, 0);
+                        LDRH_U12(x6, ed, 8);
+                        // no persistant scratch register, so unrool both instruction here...
+                        MESSAGE(LOG_DUMP, "\tHack: FSTP tbyte\n");
+                        nextop = F8;    //0xDB
+                        nextop = F8;    //modrm
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 0);
+                        STRx_U12(x5, ed, 0);
+                        STRH_U12(x6, ed, 8);
+                    } else {
+                        if(ed!=x1) {
+                            MOVx_REG(x1, ed);
+                        }
+                        x87_do_push_empty(dyn, ninst, x3);
+                        CALL(arm_fld, -1);
                     }
-                    CALL(arm_fld, -1);
                     break;
                 case 7:
                     INST_NAME("FSTP tbyte");
@@ -278,7 +321,7 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                         MOVx_REG(x1, ed);
                     }
                     CALL(arm_fstp, -1);
-                    x87_do_pop(dyn, ninst);
+                    x87_do_pop(dyn, ninst, x3);
                     break;
                 default:
                     DEFAULT;
@@ -286,4 +329,3 @@ uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
     }
     return addr;
 }
-

src/dynarec/arm64/dynarec_arm64_dc.c

@@ -0,0 +1,251 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <pthread.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "emu/x87emu_private.h"
+#include "dynarec_native.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_helper.h"
+#include "dynarec_arm64_functions.h"
+
+
+uintptr_t dynarec64_DC(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
+{
+    (void)ip; (void)rep; (void)need_epilog;
+
+    uint8_t nextop = F8;
+    uint8_t wback;
+    int64_t fixedaddress;
+    int v1, v2;
+
+    MAYUSE(v2);
+    MAYUSE(v1);
+
+    switch(nextop) {
+        case 0xC0:
+        case 0xC1:
+        case 0xC2:
+        case 0xC3:
+        case 0xC4:
+        case 0xC5:
+        case 0xC6:
+        case 0xC7:
+            INST_NAME("FADD STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FADDS(v1, v1, v2);
+            } else {
+                FADDD(v1, v1, v2);
+            }
+            break;
+        case 0xC8:
+        case 0xC9:
+        case 0xCA:
+        case 0xCB:
+        case 0xCC:
+        case 0xCD:
+        case 0xCE:
+        case 0xCF:
+            INST_NAME("FMUL STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FMULS(v1, v1, v2);
+            } else {
+                FMULD(v1, v1, v2);
+            }
+            break;
+        case 0xD0:
+        case 0xD1:
+        case 0xD2:
+        case 0xD3:
+        case 0xD4:
+        case 0xD5:
+        case 0xD6:
+        case 0xD7:
+            INST_NAME("FCOM ST0, STx"); //yep
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
+            FCOM(x1, x2, x3);
+            break;
+        case 0xD8:
+        case 0xD9:
+        case 0xDA:
+        case 0xDB:
+        case 0xDC:
+        case 0xDD:
+        case 0xDE:
+        case 0xDF:
+            INST_NAME("FCOMP ST0, STx");
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
+            FCOM(x1, x2, x3);
+            x87_do_pop(dyn, ninst, x3);
+            break;
+        case 0xE0:
+        case 0xE1:
+        case 0xE2:
+        case 0xE3:
+        case 0xE4:
+        case 0xE5:
+        case 0xE6:
+        case 0xE7:
+            INST_NAME("FSUBR STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FSUBS(v1, v2, v1);
+            } else {
+                FSUBD(v1, v2, v1);
+            }
+            break;
+        case 0xE8:
+        case 0xE9:
+        case 0xEA:
+        case 0xEB:
+        case 0xEC:
+        case 0xED:
+        case 0xEE:
+        case 0xEF:
+            INST_NAME("FSUB STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FSUBS(v1, v1, v2);
+            } else {
+                FSUBD(v1, v1, v2);
+            }
+            break;
+        case 0xF0:
+        case 0xF1:
+        case 0xF2:
+        case 0xF3:
+        case 0xF4:
+        case 0xF5:
+        case 0xF6:
+        case 0xF7:
+            INST_NAME("FDIVR STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FDIVS(v1, v2, v1);
+            } else {
+                FDIVD(v1, v2, v1);
+            }
+            break;       
+        case 0xF8:
+        case 0xF9:
+        case 0xFA:
+        case 0xFB:
+        case 0xFC:
+        case 0xFD:
+        case 0xFE:
+        case 0xFF:
+            INST_NAME("FDIV STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FDIVS(v1, v1, v2);
+            } else {
+                FDIVD(v1, v1, v2);
+            }
+            break;
+        default:
+            switch((nextop>>3)&7) {
+                case 0:
+                    INST_NAME("FADD ST0, double[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0xfff<<3, 3, rex, 0, 0);
+                    VLDR64_U12(v2, wback, fixedaddress);
+                    FADDD(v1, v1, v2);
+                    break;
+                case 1:
+                    INST_NAME("FMUL ST0, double[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0xfff<<3, 3, rex, 0, 0);
+                    VLDR64_U12(v2, wback, fixedaddress);
+                    FMULD(v1, v1, v2);
+                    break;
+                case 2:
+                    INST_NAME("FCOM ST0, double[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0xfff<<3, 3, rex, 0, 0);
+                    VLDR64_U12(v2, wback, fixedaddress);
+                    FCMPD(v1, v2);
+                    FCOM(x1, x2, x3);
+                    break;
+                case 3:
+                    INST_NAME("FCOMP ST0, double[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0xfff<<3, 3, rex, 0, 0);
+                    VLDR64_U12(v2, wback, fixedaddress);
+                    FCMPD(v1, v2);
+                    FCOM(x1, x2, x3);
+                    x87_do_pop(dyn, ninst, x3);
+                    break;
+                case 4:
+                    INST_NAME("FSUB ST0, double[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0xfff<<3, 3, rex, 0, 0);
+                    VLDR64_U12(v2, wback, fixedaddress);
+                    FSUBD(v1, v1, v2);
+                    break;
+                case 5:
+                    INST_NAME("FSUBR ST0, double[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0xfff<<3, 3, rex, 0, 0);
+                    VLDR64_U12(v2, wback, fixedaddress);
+                    FSUBD(v1, v2, v1);
+                    break;
+                case 6:
+                    INST_NAME("FDIV ST0, double[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0xfff<<3, 3, rex, 0, 0);
+                    VLDR64_U12(v2, wback, fixedaddress);
+                    FDIVD(v1, v1, v2);
+                    break;
+                case 7:
+                    INST_NAME("FDIVR ST0, double[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0xfff<<3, 3, rex, 0, 0);
+                    VLDR64_U12(v2, wback, fixedaddress);
+                    FDIVD(v1, v2, v1);
+                    break;
+            }
+    }
+    return addr;
+}

src/dynarec/arm64/dynarec_arm64_dd.c

@@ -15,20 +15,22 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
 #include "emu/x87emu_private.h"
+#include "dynarec_native.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_helper.h"
 #include "dynarec_arm64_functions.h"
 
 
 uintptr_t dynarec64_DD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
 {
+    (void)ip; (void)rep; (void)need_epilog;
+
     uint8_t nextop = F8;
     uint8_t ed;
-    int fixedaddress;
+    int64_t fixedaddress;
     int v1, v2;
     int s0;
 
@@ -46,7 +48,11 @@ uintptr_t dynarec64_DD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xC6:
         case 0xC7:
             INST_NAME("FFREE STx");
-            break;  // not handling Tag...
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
+            x87_purgecache(dyn, ninst, 0, x1, x2, x3);
+            MOV32w(x1, nextop&7);
+            CALL(fpu_do_free, -1);
+            break;
         case 0xD0:
         case 0xD1:
         case 0xD2:
@@ -56,13 +62,17 @@ uintptr_t dynarec64_DD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xD6:
         case 0xD7:
             INST_NAME("FST ST0, STx");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            FMOVD(v2, v1);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FMOVS(v2, v1);
+            } else {
+                FMOVD(v2, v1);
+            }
             break;
         case 0xD8:
             INST_NAME("FSTP ST0, ST0");
-            x87_do_pop(dyn, ninst);
+            x87_do_pop(dyn, ninst, x3);
             break;
         case 0xD9:
         case 0xDA:
@@ -72,10 +82,9 @@ uintptr_t dynarec64_DD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xDE:
         case 0xDF:
             INST_NAME("FSTP ST0, STx");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            FMOVD(v2, v1);
-            x87_do_pop(dyn, ninst);
+            // copy the cache value for st0 to stx
+            x87_swapreg(dyn, ninst, x1, x2, 0, nextop&7);
+            x87_do_pop(dyn, ninst, x3);
             break;
 
         case 0xE0:
@@ -87,9 +96,13 @@ uintptr_t dynarec64_DD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xE6:
         case 0xE7:
             INST_NAME("FUCOM ST0, STx");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            FCMPD(v1, v2);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
             FCOM(x1, x2, x3);
             break;
         case 0xE8:
@@ -101,11 +114,15 @@ uintptr_t dynarec64_DD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xEE:
         case 0xEF:
             INST_NAME("FUCOMP ST0, STx");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            FCMPD(v1, v2);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
             FCOM(x1, x2, x3);
-            x87_do_pop(dyn, ninst);
+            x87_do_pop(dyn, ninst, x3);
             break;
 
         case 0xC8:
@@ -139,54 +156,65 @@ uintptr_t dynarec64_DD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             switch((nextop>>3)&7) {
                 case 0:
                     INST_NAME("FLD double");
-                    v1 = x87_do_push(dyn, ninst);
+                    v1 = x87_do_push(dyn, ninst, x3, NEON_CACHE_ST_D);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<3, 7, rex, 0, 0);
                     VLDR64_U12(v1, ed, fixedaddress);
                     break;
                 case 1:
                     INST_NAME("FISTTP i64, ST0");
-                    v1 = x87_do_push(dyn, ninst);
+                    v1 = x87_do_push(dyn, ninst, x3, NEON_CACHE_ST_D);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<3, 7, rex, 0, 0);
                     s0 = fpu_get_scratch(dyn);
                     FRINT64ZD(s0, v1);
                     FCVTZSxD(x2, s0);
                     STRx_U12(x2, ed, fixedaddress);
-                    x87_do_pop(dyn, ninst);
+                    x87_do_pop(dyn, ninst, x3);
                     break;
                 case 2:
                     INST_NAME("FST double");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<3, 7, rex, 0, 0);
                     VSTR64_U12(v1, ed, fixedaddress);
                     break;
                 case 3:
                     INST_NAME("FSTP double");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<3, 7, rex, 0, 0);
                     VSTR64_U12(v1, ed, fixedaddress);
-                    x87_do_pop(dyn, ninst);
+                    x87_do_pop(dyn, ninst, x3);
                     break;
                 case 4: 
                     INST_NAME("FRSTOR m108byte");
-                    fpu_purgecache(dyn, ninst, x1, x2, x3);
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 0);
                     if(ed!=x1) {MOVx_REG(x1, ed);}
                     CALL(arm_frstor, -1);
                     break;
                 case 6: 
                     INST_NAME("FSAVE m108byte");
-                    fpu_purgecache(dyn, ninst, x1, x2, x3);
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 0);
                     if(ed!=x1) {MOVx_REG(x1, ed);}
                     CALL(arm_fsave, -1);
                     break;
                 case 7:
                     INST_NAME("FNSTSW m2byte");
-                    fpu_purgecache(dyn, ninst, x1, x2, x3);
+                    fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
                     addr = geted(dyn, addr, ninst, nextop, &ed, x4, &fixedaddress, 0xfff<<1, 1, rex, 0, 0);
-                    LDRw_U12(x1, xEmu, offsetof(x64emu_t, top));
+                    LDRw_U12(x2, xEmu, offsetof(x64emu_t, top));
                     LDRH_U12(x3, xEmu, offsetof(x64emu_t, sw));
-                    BFIw(x3, x1, 11, 3); // inject TOP at bit 11 (3 bits)
+                    if(dyn->n.x87stack) {
+                        // update top
+                        if(dyn->n.x87stack>0) {
+                            SUBw_U12(x2, x2, dyn->n.x87stack);
+                        } else {
+                            ADDw_U12(x2, x2, -dyn->n.x87stack);
+                        }
+                        ANDw_mask(x2, x2, 0, 2);
+                    }
+                    BFIw(x3, x2, 11, 3); // inject TOP at bit 11 (3 bits)
                     STRH_U12(x3, ed, fixedaddress);   // store whole sw flags
                     break;
                 default:
@@ -195,4 +223,3 @@ uintptr_t dynarec64_DD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
     }
     return addr;
 }
-

src/dynarec/arm64/dynarec_arm64_df.c

@@ -15,28 +15,30 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
 #include "emu/x87emu_private.h"
+#include "dynarec_native.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_helper.h"
 #include "dynarec_arm64_functions.h"
 
 
 uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
 {
+    (void)ip; (void)rep; (void)need_epilog;
+
     uint8_t nextop = F8;
     uint8_t ed, wback, u8;
-    int fixedaddress;
     int v1, v2;
-    int j32;
     int s0;
+    int64_t j64;
+    int64_t fixedaddress;
 
     MAYUSE(s0);
     MAYUSE(v2);
     MAYUSE(v1);
-    MAYUSE(j32);
+    MAYUSE(j64);
 
     switch(nextop) {
         case 0xC0:
@@ -49,7 +51,7 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xC7:
             INST_NAME("FFREEP STx");
             // not handling Tag...
-            x87_do_pop(dyn, ninst);
+            x87_do_pop(dyn, ninst, x3);
             break;
 
         case 0xE0:
@@ -69,11 +71,16 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xEF:
             INST_NAME("FUCOMIP ST0, STx");
             SETFLAGS(X_ALL, SF_SET);
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            FCMPD(v1, v2);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0))
+            {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
             FCOMI(x1, x2);
-            x87_do_pop(dyn, ninst);
+            x87_do_pop(dyn, ninst, x3);
             break;
         case 0xF0:
         case 0xF1:
@@ -85,11 +92,16 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xF7:
             INST_NAME("FCOMIP ST0, STx");
             SETFLAGS(X_ALL, SF_SET);
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            FCMPD(v1, v2);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0))
+            {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
             FCOMI(x1, x2);
-            x87_do_pop(dyn, ninst);
+            x87_do_pop(dyn, ninst, x3);
             break;
 
         case 0xC8:
@@ -138,19 +150,23 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             switch((nextop>>3)&7) {
                 case 0:
                     INST_NAME("FILD ST0, Ew");
-                    v1 = x87_do_push(dyn, ninst);
+                    v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_F);
                     addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0xfff<<1, 1, rex, 0, 0);
                     LDRSHw_U12(x1, wback, fixedaddress);
-                    SCVTFDw(v1, x1);
+                    if(ST_IS_F(0)) {
+                        SCVTFSw(v1, x1);
+                    } else {
+                        SCVTFDw(v1, x1);
+                    }
                     break;
                 case 1:
                     INST_NAME("FISTTP Ew, ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
                     addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0xfff<<1, 1, rex, 0, 0);
                     ed = x1;
                     s0 = fpu_get_scratch(dyn);
                     #if 0
-                    // this version needs ARM v8.5, //TODO: add detection of this extensio to use it
+                    // this version needs ARM v8.5, //TODO: add detection of this extension to use it
                     FRINT32ZD(s0, v1);
                     // no saturation instruction on Arm, so using NEON
                     VFCVTZSd(s0, s0);
@@ -158,23 +174,28 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     SQXTN_H_S(s0, s0);
                     VSTR16_U12(s0, wback, fixedaddress);
                     #else
-                    MSR_fpsr(x5);
-                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
                     MRS_fpsr(x5);
-                    VFCVTZSd(s0, v1);
-                    SQXTN_S_D(s0, s0);
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    MSR_fpsr(x5);
+                    if(ST_IS_F(0)) {
+                        VFCVTZSs(s0, v1);
+                    } else {
+                        VFCVTZSd(s0, v1);
+                        SQXTN_S_D(s0, s0);
+                    }
                     SQXTN_H_S(s0, s0);
                     VSTR16_U12(s0, wback, fixedaddress);
-                    MSR_fpsr(x5);   // get back FPSR to check the IOC bit
-                    TBZ_NEXT(x5, FPSR_IOC);
+                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                    TBZ_MARK3(x5, FPSR_IOC);
                     MOV32w(x5, 0x8000);
                     STRH_U12(x5, wback, fixedaddress);
+                    MARK3;
                     #endif
-                    x87_do_pop(dyn, ninst);
+                    x87_do_pop(dyn, ninst, x3);
                     break;
                 case 2:
                     INST_NAME("FIST Ew, ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
                     u8 = x87_setround(dyn, ninst, x1, x2, x4);
                     addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0xfff<<1, 1, rex, 0, 0);
                     ed = x1;
@@ -187,24 +208,30 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     SQXTN_H_S(s0, s0);
                     VSTR16_U12(s0, wback, fixedaddress);
                     #else
-                    MSR_fpsr(x5);
-                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
                     MRS_fpsr(x5);
-                    FRINTXD(s0, v1);
-                    VFCVTZSd(s0, s0);
-                    SQXTN_S_D(s0, s0);
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    MSR_fpsr(x5);
+                    if(ST_IS_F(0)) {
+                        FRINTXS(s0, v1);
+                        VFCVTZSs(s0, s0);
+                    } else {
+                        FRINTXD(s0, v1);
+                        VFCVTZSd(s0, s0);
+                        SQXTN_S_D(s0, s0);
+                    }
                     SQXTN_H_S(s0, s0);
                     VSTR16_U12(s0, wback, fixedaddress);
-                    MSR_fpsr(x5);   // get back FPSR to check the IOC bit
-                    TBZ_NEXT(x5, FPSR_IOC);
+                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                    TBZ_MARK3(x5, FPSR_IOC);
                     MOV32w(x5, 0x8000);
                     STRH_U12(x5, wback, fixedaddress);
+                    MARK3;
                     #endif
                     x87_restoreround(dyn, ninst, u8);
                     break;
                 case 3:
                     INST_NAME("FISTP Ew, ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
                     u8 = x87_setround(dyn, ninst, x1, x2, x4);
                     addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0xfff<<1, 1, rex, 0, 0);
                     ed = x1;
@@ -217,20 +244,26 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     SQXTN_H_S(s0, s0);
                     VSTR16_U12(s0, wback, fixedaddress);
                     #else
-                    MSR_fpsr(x5);
-                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
                     MRS_fpsr(x5);
-                    FRINTXD(s0, v1);
-                    VFCVTZSd(s0, s0);
-                    SQXTN_S_D(s0, s0);
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    MSR_fpsr(x5);
+                    if(ST_IS_F(0)) {
+                        FRINTXS(s0, v1);
+                        VFCVTZSs(s0, s0);
+                    } else {
+                        FRINTXD(s0, v1);
+                        VFCVTZSd(s0, s0);
+                        SQXTN_S_D(s0, s0);
+                    }
                     SQXTN_H_S(s0, s0);
                     VSTR16_U12(s0, wback, fixedaddress);
-                    MSR_fpsr(x5);   // get back FPSR to check the IOC bit
-                    TBZ_NEXT(x5, FPSR_IOC);
+                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                    TBZ_MARK3(x5, FPSR_IOC);
                     MOV32w(x5, 0x8000);
                     STRH_U12(x5, wback, fixedaddress);
+                    MARK3;
                     #endif
-                    x87_do_pop(dyn, ninst);
+                    x87_do_pop(dyn, ninst, x3);
                     x87_restoreround(dyn, ninst, u8);
                     break;
                 case 4:
@@ -242,7 +275,7 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     break;
                 case 5:
                     INST_NAME("FILD ST0, i64");
-                    v1 = x87_do_push(dyn, ninst);
+                    v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_D);
                     addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0xfff<<3, 7, rex, 0, 0);
                     LDRx_U12(x1, wback, fixedaddress);
                     SCVTFDx(v1, x1);
@@ -253,11 +286,11 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 0);
                     if(ed!=x1) {MOVx_REG(x1, ed);}
                     CALL(fpu_fbst, -1);
-                    x87_do_pop(dyn, ninst);
+                    x87_do_pop(dyn, ninst, x3);
                     break;
                 case 7:
                     INST_NAME("FISTP i64, ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
                     u8 = x87_setround(dyn, ninst, x1, x2, x4);
                     addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0xfff<<3, 7, rex, 0, 0);
                     ed = x1;
@@ -267,18 +300,20 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     VFCVTZSd(s0, s0);
                     VSTR64_U12(s0, wback, fixedaddress);
                     #else
-                    MSR_fpsr(x5);
-                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
                     MRS_fpsr(x5);
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    MSR_fpsr(x5);
                     FRINTXD(s0, v1);
                     VFCVTZSd(s0, s0);
                     VSTR64_U12(s0, wback, fixedaddress);
-                    MSR_fpsr(x5);   // get back FPSR to check the IOC bit
-                    TBZ_NEXT(x5, FPSR_IOC);
+                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                    TBZ_MARK3(x5, FPSR_IOC);
                     MOV64x(x5, 0x8000000000000000LL);
                     STRx_U12(x5, wback, fixedaddress);
+                    MARK3;
                     #endif
                     x87_restoreround(dyn, ninst, u8);
+                    x87_do_pop(dyn, ninst, x3);
                     break;
                 default:
                     DEFAULT;
@@ -286,4 +321,3 @@ uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
     }
     return addr;
 }
-

src/dynarec/arm64/dynarec_arm64_emit_logic.c

@@ -15,17 +15,18 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
+#include "dynarec_native.h"
 #include "../tools/bridge_private.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_functions.h"
 #include "dynarec_arm64_helper.h"
 
-// emit OR32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+// emit OR32 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_or32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -89,9 +90,10 @@ void emit_or32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, int
     }
 }
 
-// emit XOR32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+// emit XOR32 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_xor32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -155,9 +157,10 @@ void emit_xor32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
     }
 }
 
-// emit AND32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+// emit AND32 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_and32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -227,9 +230,10 @@ void emit_and32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
     }
 }
 
-// emit OR8 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
+// emit OR8 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
 void emit_or8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -292,9 +296,10 @@ void emit_or8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
     }
 }
 
-// emit XOR8 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
+// emit XOR8 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
 void emit_xor8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -357,9 +362,10 @@ void emit_xor8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4
     }
 }
 
-// emit AND8 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
+// emit AND8 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
 void emit_and8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -429,9 +435,10 @@ void emit_and8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4
 }
 
 
-// emit OR16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
+// emit OR16 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
 void emit_or16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -507,9 +514,10 @@ void emit_or16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 //    }
 //}
 
-// emit XOR16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
+// emit XOR16 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
 void emit_xor16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -585,9 +593,10 @@ void emit_xor16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 //    }
 //}
 
-// emit AND16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
+// emit AND16 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
 void emit_and16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -667,4 +676,4 @@ void emit_and16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 //    IFX(X_PF) {
 //        emit_pf(dyn, ninst, s1, s3, s4);
 //    }
-//}
+//}

src/dynarec/arm64/dynarec_arm64_emit_math.c

@@ -15,17 +15,18 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
+#include "dynarec_native.h"
 #include "../tools/bridge_private.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_functions.h"
 #include "dynarec_arm64_helper.h"
 
-// emit ADD32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+// emit ADD32 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_add32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -51,21 +52,17 @@ void emit_add32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         LSRxw(s4, s3, 3);
         BFIxw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
     }
-    IFX(X_ZF|X_CF|X_OF) {
-        MOV32w(s3, (1<<F_ZF)|(1<<F_CF)|(1<<F_OF));
-        BICx(xFlags, xFlags, s3);
-    }
     IFX(X_ZF) {
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_CF) {
-        Bcond(cCC, +8);
-        ORRw_mask(xFlags, xFlags, 0, 0);    // mask=0x01
+        CSETw(s4, cCS);
+        BFIw(xFlags, s4, F_CF, 1);
     }
     IFX(X_OF) {
-        Bcond(cVC, +8);
-        ORRw_mask(xFlags, xFlags, 0b010101, 0);  // mask=0x800
+        CSETw(s4, cVS);
+        BFIw(xFlags, s4, F_OF, 1);
     }
     IFX(X_SF) {
         LSRxw(s3, s1, (rex.w)?63:31);
@@ -76,9 +73,10 @@ void emit_add32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     }
 }
 
-// emit ADD32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+// emit ADD32 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
 void emit_add32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, int s3, int s4, int s5)
 {
+    MAYUSE(s5);
     if(s1==xRSP && (!dyn->insts || dyn->insts[ninst].x64.need_flags==X_PEND))
     {
         // special case when doing math on ESP and only PEND is needed: ignoring it!
@@ -126,21 +124,17 @@ void emit_add32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
         LSRxw(s4, s3, 3);
         BFIxw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
     }
-    IFX(X_ZF|X_CF|X_OF) {
-        MOV32w(s3, (1<<F_ZF)|(1<<F_CF)|(1<<F_OF));
-        BICx(xFlags, xFlags, s3);
-    }
     IFX(X_ZF) {
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_CF) {
-        Bcond(cCC, +8);
-        ORRw_mask(xFlags, xFlags, 0, 0);    // mask=0x01
+        CSETw(s4, cCS);
+        BFIw(xFlags, s4, F_CF, 1);
     }
     IFX(X_OF) {
-        Bcond(cVC, +8);
-        ORRw_mask(xFlags, xFlags, 0b010101, 0);  // mask=0x800
+        CSETw(s4, cVS);
+        BFIw(xFlags, s4, F_OF, 1);
     }
     IFX(X_SF) {
         LSRxw(s3, s1, (rex.w)?63:31);
@@ -151,9 +145,10 @@ void emit_add32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
     }
 }
 
-// emit SUB32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+// emit SUB32 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_sub32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -180,22 +175,18 @@ void emit_sub32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         LSRxw(s4, s3, 3);
         BFIx(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
     }
-    IFX(X_ZF|X_CF|X_OF) {
-        MOV32w(s3, (1<<F_ZF)|(1<<F_CF)|(1<<F_OF));
-        BICx(xFlags, xFlags, s3);
-    }
     IFX(X_ZF) {
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_CF) {
         // inverted carry
-        Bcond(cCS, +8);
-        ORRw_mask(xFlags, xFlags, 0, 0);    // mask=0x01
+        CSETw(s4, cCC);
+        BFIw(xFlags, s4, F_CF, 1);
     }
     IFX(X_OF) {
-        Bcond(cVC, +8);
-        ORRw_mask(xFlags, xFlags, 0b010101, 0);  // mask=0x800
+        CSETw(s4, cVS);
+        BFIw(xFlags, s4, F_OF, 1);
     }
     IFX(X_SF) {
         LSRxw(s3, s1, (rex.w)?63:31);
@@ -206,9 +197,10 @@ void emit_sub32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     }
 }
 
-// emit SUB32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+// emit SUB32 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
 void emit_sub32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, int s3, int s4, int s5)
 {
+    MAYUSE(s5);
     if(s1==xRSP && (!dyn->insts || dyn->insts[ninst].x64.need_flags==X_PEND))
     {
         // special case when doing math on RSP and only PEND is needed: ignoring it!
@@ -256,22 +248,18 @@ void emit_sub32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
         LSRxw(s4, s3, 3);
         BFIw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
     }
-    IFX(X_ZF|X_CF|X_OF) {
-        MOV32w(s3, (1<<F_ZF)|(1<<F_CF)|(1<<F_OF));
-        BICx(xFlags, xFlags, s3);
-    }
     IFX(X_ZF) {
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_CF) {
         // inverted carry
-        Bcond(cCS, +8);
-        ORRw_mask(xFlags, xFlags, 0, 0);    // mask=0x01
+        CSETw(s4, cCC);
+        BFIw(xFlags, s4, F_CF, 1);
     }
     IFX(X_OF) {
-        Bcond(cVC, +8);
-        ORRw_mask(xFlags, xFlags, 0b010101, 0);  // mask=0x800
+        CSETw(s4, cVS);
+        BFIw(xFlags, s4, F_OF, 1);
     }
     IFX(X_SF) {
         LSRxw(s3, s1, (rex.w)?63:31);
@@ -282,9 +270,10 @@ void emit_sub32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
     }
 }
 
-// emit ADD8 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit ADD8 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_add8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -331,7 +320,7 @@ void emit_add8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     }
 }
 
-// emit ADD8 instruction, from s1 , const c, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit ADD8 instruction, from s1, const c, store result in s1 using s3 and s4 as scratch
 void emit_add8c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
 {
     IFX(X_PEND) {
@@ -383,9 +372,10 @@ void emit_add8c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
     }
 }
 
-// emit SUB8 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit SUB8 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_sub8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -434,9 +424,10 @@ void emit_sub8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     }
 }
 
-// emit SUB8 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+// emit SUB8 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
 void emit_sub8c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4, int s5)
 {
+    MAYUSE(s5);
     IFX(X_ALL|X_PEND) {
         MOV32w(s5, c&0xff);
     }
@@ -491,9 +482,10 @@ void emit_sub8c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4, in
     }
 }
 
-// emit ADD16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit ADD16 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_add16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -541,7 +533,7 @@ void emit_add16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     }
 }
 
-// emit ADD16 instruction, from s1 , const c, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit ADD16 instruction, from s1, const c, store result in s1 using s3 and s4 as scratch
 //void emit_add16c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
@@ -608,9 +600,10 @@ void emit_add16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 //    }
 //}
 
-// emit SUB16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit SUB16 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_sub16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -659,7 +652,7 @@ void emit_sub16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     }
 }
 
-// emit SUB16 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+// emit SUB16 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
 //void emit_sub16c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
@@ -756,17 +749,13 @@ void emit_inc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4
         LSRxw(s4, s3, 3);
         BFIxw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
     }
-    IFX(X_ZF|X_OF) {
-        MOV32w(s3, (1<<F_ZF)|(1<<F_OF));
-        BICx(xFlags, xFlags, s3);
-    }
     IFX(X_ZF) {
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_OF) {
-        Bcond(cVC, +8);
-        ORRw_mask(xFlags, xFlags, 0b010101, 0);  // mask=0x800
+        CSETw(s4, cVS);
+        BFIw(xFlags, s4, F_OF, 1);
     }
     IFX(X_SF) {
         LSRxw(s3, s1, rex.w?63:31);
@@ -777,7 +766,7 @@ void emit_inc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4
     }
 }
 
-// emit INC8 instruction, from s1, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit INC8 instruction, from s1, store result in s1 using s3 and s4 as scratch
 void emit_inc8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
 {
     IFX(X_PEND) {
@@ -822,7 +811,7 @@ void emit_inc8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
     }
 }
 
-// emit INC16 instruction, from s1 , store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit INC16 instruction, from s1, store result in s1 using s3 and s4 as scratch
 void emit_inc16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
 {
     IFX(X_PEND) {
@@ -900,17 +889,13 @@ void emit_dec32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4
         LSRxw(s4, s3, 3);
         BFIw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
     }
-    IFX(X_ZF|X_OF) {
-        MOV32w(s3, (1<<F_ZF)|(1<<F_OF));
-        BICx(xFlags, xFlags, s3);
-    }
     IFX(X_ZF) {
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_OF) {
-        Bcond(cVC, +8);
-        ORRw_mask(xFlags, xFlags, 0b010101, 0);  // mask=0x800
+        CSETw(s4, cVS);
+        BFIw(xFlags, s4, F_OF, 1);
     }
     IFX(X_SF) {
         LSRxw(s3, s1, rex.w?63:31);
@@ -1009,9 +994,10 @@ void emit_dec16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
     }
 }
 
-// emit ADC32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+// emit ADC32 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_adc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -1062,7 +1048,7 @@ void emit_adc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     }
 }
 
-// emit ADC32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+// emit ADC32 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
 //void emit_adc32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
@@ -1132,9 +1118,10 @@ void emit_adc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
 //    }
 //}
 
-// emit ADC8 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit ADC8 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_adc8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -1185,9 +1172,10 @@ void emit_adc8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     }
 }
 
-// emit ADC8 instruction, from s1 , const c, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit ADC8 instruction, from s1, const c, store result in s1 using s3 and s4 as scratch
 void emit_adc8c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4, int s5)
 {
+    MAYUSE(s5);
     MOV32w(s5, c&0xff);
     IFX(X_PEND) {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
@@ -1239,9 +1227,10 @@ void emit_adc8c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4, in
     }
 }
 
-// emit ADC16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit ADC16 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_adc16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -1292,7 +1281,7 @@ void emit_adc16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     }
 }
 
-// emit ADC16 instruction, from s1 , const c, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit ADC16 instruction, from s1, const c, store result in s1 using s3 and s4 as scratch
 //void emit_adc16c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
@@ -1359,9 +1348,10 @@ void emit_adc16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 //    }
 //}
 
-// emit SBB32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+// emit SBB32 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_sbb32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -1414,7 +1404,7 @@ void emit_sbb32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     }
 }
 
-// emit SBB32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+// emit SBB32 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
 //void emit_sbb32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
@@ -1486,9 +1476,10 @@ void emit_sbb32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
 //    }
 //}
 
-// emit SBB8 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit SBB8 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_sbb8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -1540,9 +1531,10 @@ void emit_sbb8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     }
 }
 
-// emit SBB8 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+// emit SBB8 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
 void emit_sbb8c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4, int s5)
 {
+    MAYUSE(s5);
     MOV32w(s5, c&0xff);
     IFX(X_PEND) {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
@@ -1595,9 +1587,10 @@ void emit_sbb8c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4, in
     }
 }
 
-// emit SBB16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit SBB16 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_sbb16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -1649,7 +1642,7 @@ void emit_sbb16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     }
 }
 
-// emit SBB16 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+// emit SBB16 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
 //void emit_sbb16c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
@@ -1853,4 +1846,4 @@ void emit_neg8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
     IFX(X_PF) {
         emit_pf(dyn, ninst, s1, s3, s4);
     }
-}
+}

src/dynarec/arm64/dynarec_arm64_emit_shift.c

@@ -15,19 +15,20 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
+#include "dynarec_native.h"
 #include "../tools/bridge_private.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_functions.h"
 #include "dynarec_arm64_helper.h"
 
 // emit SHL32 instruction, from s1 , shift s2, store result in s1 using s3 and s4 as scratch. s3 can be same as s2
 void emit_shl32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
-    int32_t j32;
-    MAYUSE(j32);
+    MAYUSE(s2);
+    int64_t j64;
+    MAYUSE(j64);
 
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
@@ -60,9 +61,8 @@ void emit_shl32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     }
     IFX(X_ZF) {
         TSTxw_REG(s1, s1);
-        BFCx(xFlags, F_ZF, 1);
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_SF) {
         LSRxw(s4, s1, (rex.w)?63:31);
@@ -71,9 +71,8 @@ void emit_shl32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     IFX(X_OF) {
         CMPSxw_U12(s2, 1);   // if s2==1
             IFX(X_SF) {} else {LSRxw(s4, s1, (rex.w)?63:31);}
-            Bcond(cNE, 4+3*4);
-            BFCw(xFlags, F_OF, 1);
             EORxw_REG(s4, s4, xFlags);  // CF is set if OF is asked
+            CSELw(s4, s4, wZR, cEQ);
             BFIw(xFlags, s4, F_OF, 1);
     }
     IFX(X_PF) {
@@ -101,7 +100,7 @@ void emit_shl32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
         }
         return;
     }
-    IFX(X_CF) {
+    IFX(X_CF|X_OF) {
         LSRxw(s3, s1, (rex.w?64:32)-c);
         BFIxw(xFlags, s3, F_CF, 1);
     }
@@ -112,9 +111,8 @@ void emit_shl32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
     }
     IFX(X_ZF) {
         TSTxw_REG(s1, s1);
-        BFCx(xFlags, F_ZF, 1);
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_SF) {
         LSRxw(s4, s1, (rex.w)?63:31);
@@ -123,7 +121,6 @@ void emit_shl32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
     IFX(X_OF) {
         if(c==1) {
             IFX(X_SF) {} else {LSRxw(s4, s1, (rex.w)?63:31);}
-            Bcond(cNE, +12);
             EORxw_REG(s4, s4, xFlags);  // CF is set if OF is asked
             BFIw(xFlags, s4, F_OF, 1);
         } else {
@@ -138,8 +135,9 @@ void emit_shl32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
 // emit SHR32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, s2 can be same as s3
 void emit_shr32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
-    int32_t j32;
-    MAYUSE(j32);
+    MAYUSE(s2);
+    int64_t j64;
+    MAYUSE(j64);
 
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
@@ -167,9 +165,8 @@ void emit_shr32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     }
     IFX(X_ZF) {
         TSTxw_REG(s1, s1);
-        BFCx(xFlags, F_ZF, 1);
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_SF) {
         LSRxw(s4, s1, (rex.w)?63:31);
@@ -209,8 +206,10 @@ void emit_shr32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
         return;
     }
     IFX(X_CF) {
-        LSRxw_REG(s3, s1, c-1);
-        BFIw(xFlags, s3, 0, 1);
+        if(c>1) {
+            LSRxw(s3, s1, c-1);
+        }
+        BFIw(xFlags, (c>1)?s3:s1, 0, 1);
     }
     LSRxw(s1, s1, c);
     IFX(X_PEND) {
@@ -218,9 +217,8 @@ void emit_shr32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
     }
     IFX(X_ZF) {
         TSTxw_REG(s1, s1);
-        BFCx(xFlags, F_ZF, 1);
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_SF) {
         LSRxw(s4, s1, (rex.w)?63:31);
@@ -255,19 +253,20 @@ void emit_sar32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
         }
         return;
     }
+    IFX(X_CF) {
+        if(c>1) {
+            ASRxw(s3, s1, c-1);
+        }
+        BFIw(xFlags, (c>1)?s3:s1, 0, 1);
+    }
     ASRxw(s1, s1, c);
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
     }
     IFX(X_ZF) {
         TSTw_REG(s1, s1);
-        BFCx(xFlags, F_ZF, 1);
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
-    }
-    IFX(X_CF) {
-        ASRxw(s3, s1, c-1);
-        BFIw(xFlags, s3, 0, 1);
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_SF) {
         LSRxw(s4, s1, (rex.w)?63:31);
@@ -281,6 +280,7 @@ void emit_sar32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
 // emit ROL32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
 void emit_rol32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, int s3, int s4)
 {
+    MAYUSE(rex); MAYUSE(s1); MAYUSE(s3); MAYUSE(s4);
     IFX(X_PEND) {
         MOV32w(s3, c);
         STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
@@ -312,6 +312,7 @@ void emit_rol32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
 // emit ROR32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
 void emit_ror32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, int s3, int s4)
 {
+    MAYUSE(s1); MAYUSE(s3); MAYUSE(s4);
     IFX(X_PEND) {
         MOV32w(s3, c);
         STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
@@ -343,119 +344,106 @@ void emit_ror32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
 }
 
 // emit SHRD32 instruction, from s1, fill s2 , constant c, store result in s1 using s3 and s4 as scratch
-//void emit_shrd32c(dynarec_arm_t* dyn, int ninst, int s1, int s2, int32_t c, int s3, int s4)
-//{
-//    c&=0x1f;
-//    IFX(X_PEND) {
-//        MOVW(s3, c);
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, op1));
-//        STR_IMM9(s3, xEmu, offsetof(x64emu_t, op2));
-//        // same flags calc as shr32
-//        SET_DF(s4, d_shr32);
-//    } else IFX(X_ALL) {
-//        SET_DFNONE(s4);
-//    }
-//    if(!c) {
-//        IFX(X_PEND) {
-//            STR_IMM9(s1, xEmu, offsetof(x64emu_t, res));
-//        }
-//        return;
-//    }
-//    IFX(X_CF) {
-//        MOVS_REG_LSR_IMM5(s1, s1, c);
-//    } else {
-//        MOV_REG_LSR_IMM5(s1, s1, c);
-//    }
-//    IFX(X_ZF|X_CF) {
-//        BIC_IMM8(xFlags, xFlags, (1<<F_ZF)|(1<<F_CF), 0);
-//    }
-//    IFX(X_CF) {
-//        ORR_IMM8_COND(cCS, xFlags, xFlags, 1<<F_CF, 0);
-//    }
-//    IFX(X_ZF) {
-//        ORRS_REG_LSL_IMM5(s1, s1, s2, 32-c);
-//    } else {
-//        ORR_REG_LSL_IMM5(s1, s1, s2, 32-c);
-//    }
-//    IFX(X_PEND) {
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, res));
-//    }
-//    IFX(X_ZF) {
-//        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
-//    }
-//    IFX(X_SF) {
-//        MOV_REG_LSR_IMM5(s3, s1, 31);
-//        BFI(xFlags, s3, F_SF, 1);
-//    }
-//    IFX(X_OF) {
-//        if(c==1) {
-//            MOV_REG_LSR_IMM5(s4, s1, 30);
-//            XOR_REG_LSR_IMM8(s4, s4, s4, 1);
-//            BFI(xFlags, s4, F_OF, 1);
-//        }
-//    }
-//    IFX(X_PF) {
-//        emit_pf(dyn, ninst, s1, s3, s4);
-//    }
-//}
+void emit_shrd32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int32_t c, int s3, int s4)
+{
+    c&=(rex.w?0x3f:0x1f);
+    IFX(X_PEND) {
+        MOV32w(s3, c);
+        STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
+        STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
+        // same flags computation as with shl64/shl32
+        SET_DF(s4, rex.w?d_shl64:d_shl32);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    if(!c) {
+        IFX(X_PEND) {
+            STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
+        }
+        return;
+    }
+    IFX(X_CF) {
+        if(c>1) {
+            LSRxw(s3, s1, c-1);
+        }
+        BFIw(xFlags, (c>1)?s3:s1, 0, 1);
+    }
+    LSRxw(s3, s1, c);
+    ORRxw_REG_LSL(s1, s3, s2, (rex.w?64:32)-c);
+    IFX(X_PEND) {
+        STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
+    }
+    IFX(X_ZF) {
+        TSTxw_REG(s1, s1);
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
+    }
+    IFX(X_SF) {
+        LSRxw(s4, s1, (rex.w)?63:31);
+        BFIx(xFlags, s4, F_SF, 1);
+    }
+    IFX(X_OF) {
+        if(c==1) {
+            LSRxw(s4, s1, rex.w?62:30);
+            EORw_REG_LSR(s4, s4, s4, 1);
+            BFIw(xFlags, s4, F_OF, 1);
+        }
+    }
+    IFX(X_PF) {
+        emit_pf(dyn, ninst, s1, s3, s4);
+    }
+}
 
-//void emit_shld32c(dynarec_arm_t* dyn, int ninst, int s1, int s2, int32_t c, int s3, int s4)
-//{
-//    c&=0x1f;
-//    IFX(X_PEND) {
-//        MOVW(s3, c);
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, op1));
-//        STR_IMM9(s3, xEmu, offsetof(x64emu_t, op2));
-//        // same flags computation as with shl32
-//        SET_DF(s4, d_shl32);
-//    } else IFX(X_ALL) {
-//        SET_DFNONE(s4);
-//    }
-//    if(c==0) {
-//        IFX(F_OF) {
-//            BFC(xFlags, F_OF, 1);
-//        }
-//        IFX(X_PEND) {
-//            STR_IMM9(s1, xEmu, offsetof(x64emu_t, res));
-//        }
-//        return;
-//    }
-//    IFX(X_CF) {
-//        MOV_REG_LSR_IMM5(s3, s1, 32-c);
-//        BFI(xFlags, s3, F_CF, 1);
-//    }
-//    IFX(X_OF) {
-//        MOVS_REG_LSL_IMM5(s1, s1, c);
-//    } else {
-//        MOV_REG_LSL_IMM5(s1, s1, c);
-//    }
-//    IFX(X_OF) {
-//        if(c==1) {
-//            UBFX(s3, s2, 0, 1);
-//            XOR_IMM8_COND(cCS, s3, s3, 1);
-//            BFI(xFlags, s3, F_OF, 1);
-//        } else {
-//            BFC(xFlags, F_OF, 1);
-//        }
-//    }
-//    IFX(X_ZF) {
-//        ORRS_REG_LSR_IMM5(s1, s1, s2, 32-c);
-//    } else {
-//        ORR_REG_LSR_IMM5(s1, s1, s2, 32-c);
-//    }
-//
-//    IFX(X_PEND) {
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, res));
-//    }
-//    IFX(X_ZF) {
-//        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
-//        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
-//    }
-//    IFX(X_SF) {
-//        MOV_REG_LSR_IMM5(s3, s1, 31);
-//        BFI(xFlags, s3, F_SF, 1);
-//    }
-//    IFX(X_PF) {
-//        emit_pf(dyn, ninst, s1, s3, s4);
-//    }
-//}
+void emit_shld32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int32_t c, int s3, int s4)
+{
+    c&=(rex.w?0x3f:0x1f);
+    IFX(X_PEND) {
+        MOV32w(s3, c);
+        STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
+        STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
+        // same flags computation as with shl64/shl32
+        SET_DF(s4, rex.w?d_shl64:d_shl32);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    if(c==0) {
+        IFX(F_OF) {
+            BFCx(xFlags, F_OF, 1);
+        }
+        IFX(X_PEND) {
+            STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
+        }
+        return;
+    }
+    IFX(X_CF|X_OF) {
+        LSRxw(s3, s1, (rex.w?64:32)-c);
+        BFIxw(xFlags, s3, F_CF, 1);
+    }
+    LSLxw(s3, s1, c);
+    ORRxw_REG_LSR(s1, s3, s2, (rex.w?64:32)-c);
+
+    IFX(X_PEND) {
+        STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
+    }
+    IFX(X_ZF) {
+        TSTxw_REG(s1, s1);
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
+    }
+    IFX(X_SF) {
+        LSRxw(s4, s1, (rex.w)?63:31);
+        BFIx(xFlags, s4, F_SF, 1);
+    }
+    IFX(X_OF) {
+        if(c==1) {
+            UBFXxw(s3, s1, rex.w?63:31, 1);
+            EORxw_REG(s3, s3, xFlags);  // CF is set if OF is asked
+            BFIw(xFlags, s3, F_OF, 1);
+        } else {
+            BFCw(xFlags, F_OF, 1);
+        }
+    }
+    IFX(X_PF) {
+        emit_pf(dyn, ninst, s1, s3, s4);
+    }
+}

src/dynarec/arm64/dynarec_arm64_emit_tests.c

@@ -15,17 +15,18 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
+#include "dynarec_native.h"
 #include "../tools/bridge_private.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_functions.h"
 #include "dynarec_arm64_helper.h"
 
-// emit CMP32 instruction, from cmp s1 , s2, using s3 and s4 as scratch
+// emit CMP32 instruction, from cmp s1, s2, using s3 and s4 as scratch
 void emit_cmp32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4, int s5)
 {
+    MAYUSE(s1); MAYUSE(s2);
     IFX_PENDOR0 {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -47,22 +48,18 @@ void emit_cmp32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         LSRxw(s4, s3, 3);
         BFIx(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
     }
-    IFX(X_ZF|X_CF|X_OF) {
-        MOV32w(s4, (1<<F_ZF)|(1<<F_CF)|(1<<F_OF));
-        BICx(xFlags, xFlags, s4);
-    }
     IFX(X_ZF) {
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_CF) {
         // inverted carry
-        Bcond(cCS, +8);
-        ORRw_mask(xFlags, xFlags, 0, 0);    // mask=0x01
+        CSETw(s4, cCC);
+        BFIw(xFlags, s4, F_CF, 1);
     }
     IFX(X_OF) {
-        Bcond(cVC, +8);
-        ORRw_mask(xFlags, xFlags, 0b010101, 0);  // mask=0x800
+        CSETw(s4, cVS);
+        BFIw(xFlags, s4, F_OF, 1);
     }
     IFX(X_SF) {
         LSRxw(s3, s5, (rex.w)?63:31);
@@ -88,18 +85,18 @@ void emit_cmp32_0(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int
     SUBSxw_U12(s3, s1, 0);   // res = s1 - 0
     // and now the tricky ones (and mostly unused), PF and AF
     // bc = (res & (~d | s)) | (~d & s) => is 0 here...
-    IFX(X_ZF|X_CF|X_OF|X_AF) {
-        MOV32w(s4, (1<<F_ZF)|(1<<F_CF)|(1<<F_OF)|(1<<F_AF));
+    IFX(X_OF|X_AF) {
+        MOV32w(s4, (1<<F_OF)|(1<<F_AF));
         BICw(xFlags, xFlags, s4);
     }
     IFX(X_ZF) {
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_CF) {
         // inverted carry
-        Bcond(cCS, +8);
-        ORRw_mask(xFlags, xFlags, 0, 0);    // mask=0x01
+        CSETw(s4, cCC);
+        BFIw(xFlags, s4, F_CF, 1);
     }
     IFX(X_SF) {
         LSRxw(s3, s1, (rex.w)?63:31);
@@ -110,9 +107,10 @@ void emit_cmp32_0(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int
     }
 }
 
-// emit CMP16 instruction, from cmp s1 , s2, using s3 and s4 as scratch
+// emit CMP16 instruction, from cmp s1, s2, using s3 and s4 as scratch
 void emit_cmp16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int s5)
 {
+    MAYUSE(s1); MAYUSE(s2);
     IFX_PENDOR0 {
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -189,9 +187,10 @@ void emit_cmp16_0(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
         emit_pf(dyn, ninst, s1, s3, s4);
     }
 }
-// emit CMP8 instruction, from cmp s1 , s2, using s3 and s4 as scratch
+// emit CMP8 instruction, from cmp s1, s2, using s3 and s4 as scratch
 void emit_cmp8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int s5)
 {
+    MAYUSE(s1); MAYUSE(s2);
     IFX_PENDOR0 {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -252,8 +251,8 @@ void emit_cmp8_0(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
         SET_DFNONE(s4);
     }
     // bc = (res & (~d | s)) | (~d & s) = 0
-    IFX(X_CF | X_AF | X_ZF | X_OF) {
-        MOV32w(s3, (1<<F_ZF)|(1<<F_CF)|(1<<F_AF)|(1<<F_OF));
+    IFX(X_CF | X_AF | X_OF) {
+        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
         BICw(xFlags, xFlags, s3);
     }
     IFX(X_ZF) {
@@ -270,9 +269,10 @@ void emit_cmp8_0(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
     }
 }
 
-// emit TEST32 instruction, from test s1 , s2, using s3 and s4 as scratch
+// emit TEST32 instruction, from test s1, s2, using s3 and s4 as scratch
 void emit_test32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s1); MAYUSE(s2); MAYUSE(s3); MAYUSE(s4);
     IFX_PENDOR0 {
         SET_DF(s3, rex.w?d_tst64:d_tst32);
     } else {
@@ -296,7 +296,7 @@ void emit_test32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s
     }
     // PF: (((emu->x64emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
     IFX(X_PF) {
-        ANDw_mask(s3, s3, 0b011011, 000010); // 0xE0
+        ANDw_mask(s3, s3, 0b011011, 0b000010); // 0xE0
         LSRw(s3, s3, 5);
         MOV64x(s4, (uintptr_t)GetParityTab());
         LDRw_REG_LSL2(s4, s4, s3);
@@ -307,9 +307,10 @@ void emit_test32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s
     }
 }
 
-// emit TEST16 instruction, from test s1 , s2, using s3 and s4 as scratch
+// emit TEST16 instruction, from test s1, s2, using s3 and s4 as scratch
 void emit_test16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int s5)
 {
+    MAYUSE(s1); MAYUSE(s2);
     IFX_PENDOR0 {
         SET_DF(s3, d_tst16);
     } else {
@@ -339,9 +340,10 @@ void emit_test16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4,
     }
 }
 
-// emit TEST8 instruction, from test s1 , s2, using s3 and s4 as scratch
+// emit TEST8 instruction, from test s1, s2, using s3 and s4 as scratch
 void emit_test8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int s5)
 {
+    MAYUSE(s1); MAYUSE(s2);
     IFX_PENDOR0 {
         SET_DF(s3, d_tst8);
     } else {

src/dynarec/arm64/dynarec_arm64_f0.c

@@ -0,0 +1,983 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <pthread.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_helper.h"
+#include "dynarec_arm64_functions.h"
+
+
+uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
+{
+    (void)ip; (void)rep; (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop;
+    uint8_t gd, ed, u8;
+    uint8_t wback, wb1, wb2, gb1, gb2;
+    int32_t i32;
+    int64_t i64, j64;
+    int64_t fixedaddress;
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(j64);
+
+    while((opcode==0xF2) || (opcode==0xF3)) {
+        rep = opcode-0xF1;
+        opcode = F8;
+    }
+    // REX prefix before the F0 are ignored
+    rex.rex = 0;
+    while(opcode>=0x40 && opcode<=0x4f) {
+        rex.rex = opcode;
+        opcode = F8;
+    }
+
+    switch(opcode) {
+        case 0x00:
+            INST_NAME("LOCK ADD Eb, Gb");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            DMB_ISH();
+            GETGB(x2);
+            if((nextop&0xC0)==0xC0) {
+                if(rex.rex) {
+                    wback = xRAX + (nextop&7) + (rex.b<<3);
+                    wb2 = 0;
+                } else {
+                    wback = (nextop&7);    
+                    wb2 = (wback>>2);      
+                    wback = xRAX+(wback&3);
+                }
+                UBFXw(x1, wback, wb2*8, 8);   
+                emit_add8(dyn, ninst, x1, x2, x4, x3);
+                BFIx(wback, x1, wb2*8, 8);
+            } else {                   
+                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0, rex, 0, 0);
+                MARKLOCK;
+                LDAXRB(x1, wback);
+                emit_add8(dyn, ninst, x1, x2, x4, x3);
+                STLXRB(x4, x1, wback);
+                CBNZx_MARKLOCK(x4);
+            }
+            DMB_ISH();
+            break;
+        case 0x01:
+            INST_NAME("LOCK ADD Ed, Gd");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGD;
+            DMB_ISH();
+            if((nextop&0xC0)==0xC0) {
+                ed = xRAX+(nextop&7)+(rex.b<<3);
+                emit_add32(dyn, ninst, rex, ed, gd, x3, x4);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, 0);
+                MARKLOCK;
+                LDAXRxw(x1, wback);
+                emit_add32(dyn, ninst, rex, x1, gd, x3, x4);
+                STLXRxw(x3, x1, wback);
+                CBNZx_MARKLOCK(x3);
+            }
+            DMB_ISH();
+            break;
+
+        case 0x09:
+            INST_NAME("LOCK OR Ed, Gd");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGD;
+            DMB_ISH();
+            if(MODREG) {
+                ed = xRAX+(nextop&7)+(rex.b<<3);
+                emit_or32(dyn, ninst, rex, ed, gd, x3, x4);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, 0);
+                MARKLOCK;
+                LDAXRxw(x1, wback);
+                emit_or32(dyn, ninst, rex, x1, gd, x3, x4);
+                STLXRxw(x3, x1, wback);
+                CBNZx_MARKLOCK(x3);
+            }
+            DMB_ISH();
+            break;
+
+        case 0x0F:
+            nextop = F8;
+            switch(nextop) {
+
+                case 0xB0:
+                    INST_NAME("LOCK CMPXCHG Eb, Gb");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    nextop = F8;
+                    GETGB(x1);
+                    UBFXx(x6, xRAX, 0, 8);
+                    DMB_ISH();
+                    if(MODREG) {
+                        if(rex.rex) {
+                            wback = xRAX+(nextop&7)+(rex.b<<3);
+                            wb2 = 0;
+                        } else { 
+                            wback = (nextop&7);
+                            wb2 = (wback>>2)*8;
+                            wback = xRAX+(wback&3);
+                        } 
+                        UBFXx(x2, wback, wb2, 8);
+                        wb1 = 0;
+                        ed = x2;
+                        UFLAG_IF {emit_cmp8(dyn, ninst, x6, ed, x3, x4, x5);}
+                        CMPSxw_REG(x6, x2);
+                        B_MARK2(cNE);
+                        BFIx(wback, x2, wb2, 8);
+                        MOVxw_REG(ed, gd);
+                        MARK2;
+                        BFIx(xRAX, x2, 0, 8);
+                        B_NEXT_nocond;
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0, rex, 0, 0);
+                        // Aligned version
+                        MARKLOCK;
+                        LDAXRB(x2, wback);
+                        CMPSxw_REG(x6, x2);
+                        B_MARK(cNE);
+                        // EAX == Ed
+                        STLXRB(x4, gd, wback);
+                        CBNZx_MARKLOCK(x4);
+                        // done
+                        MARK;
+                        UFLAG_IF {emit_cmp32(dyn, ninst, rex, x6, x2, x3, x4, x5);}
+                        BFIx(xRAX, x2, 0, 8);    // upper par of RAX will be erase on 32bits, no mater what
+                    }
+                    DMB_ISH();
+                    break;
+                case 0xB1:
+                    INST_NAME("LOCK CMPXCHG Ed, Gd");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    nextop = F8;
+                    GETGD;
+                    DMB_ISH();
+                    if(MODREG) {
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        wback = 0;
+                        UFLAG_IF {emit_cmp32(dyn, ninst, rex, xRAX, ed, x3, x4, x5);}
+                        MOVxw_REG(x1, ed);  // save value
+                        CMPSxw_REG(xRAX, x1);
+                        B_MARK2(cNE);
+                        MOVxw_REG(ed, gd);
+                        MARK2;
+                        MOVxw_REG(xRAX, x1);
+                        B_NEXT_nocond;
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, 0);
+                        TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
+                        B_MARK3(cNE);
+                        // Aligned version
+                        MARKLOCK;
+                        LDAXRxw(x1, wback);
+                        CMPSxw_REG(xRAX, x1);
+                        B_MARK(cNE);
+                        // EAX == Ed
+                        STLXRxw(x4, gd, wback);
+                        CBNZx_MARKLOCK(x4);
+                        // done
+                        B_MARK_nocond;
+                        // Unaligned version
+                        MARK3;
+                        LDRxw_U12(x1, wback, 0);
+                        LDAXRB(x3, wback); // dummy read, to arm the write...
+                        CMPSxw_REG(xRAX, x1);
+                        B_MARK(cNE);
+                        // EAX == Ed
+                        STLXRB(x4, gd, wback);
+                        CBNZx_MARK3(x4);
+                        STRxw_U12(gd, wback, 0);
+                        MARK;
+                        // Common part (and fallback for EAX != Ed)
+                        UFLAG_IF {emit_cmp32(dyn, ninst, rex, xRAX, x1, x3, x4, x5);}
+                        MOVxw_REG(xRAX, x1);    // upper par of RAX will be erase on 32bits, no mater what
+                    }
+                    DMB_ISH();
+                    break;
+
+                case 0xC1:
+                    INST_NAME("LOCK XADD Gd, Ed");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    nextop = F8;
+                    GETGD;
+                    DMB_ISH();
+                    if(MODREG) {
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        MOVxw_REG(x1, ed);
+                        MOVxw_REG(ed, gd);
+                        MOVxw_REG(gd, x1);
+                        emit_add32(dyn, ninst, rex, ed, gd, x3, x4);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, 0);
+                        TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
+                        B_MARK(cNE);    // unaligned
+                        MARKLOCK;
+                        LDAXRxw(x1, wback);
+                        ADDxw_REG(x4, x1, gd);
+                        STLXRxw(x3, x4, wback);
+                        CBNZx_MARKLOCK(x3);
+                        B_MARK2_nocond;
+                        MARK;
+                        LDRxw_U12(x1, wback, 0);
+                        LDAXRB(x4, wback);
+                        BFIxw(x1, x4, 0, 8);
+                        ADDxw_REG(x4, x1, gd);
+                        STLXRB(x3, x4, wback);
+                        CBNZx_MARK(x3);
+                        STRxw_U12(x4, wback, 0);
+                        MARK2;
+                        IFX(X_ALL|X_PEND) {
+                            MOVxw_REG(x2, x1);
+                            emit_add32(dyn, ninst, rex, x2, gd, x3, x4);
+                        }
+                        MOVxw_REG(gd, x1);
+                    }
+                    DMB_ISH();
+                    break;
+
+                case 0xC7:
+                    INST_NAME("LOCK CMPXCHG8B Gq, Eq");
+                    SETFLAGS(X_ZF, SF_SUBSET);
+                    nextop = F8;
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x1, &fixedaddress, 0, 0, rex, 0, 0);
+                    DMB_ISH();
+                    MARKLOCK;
+                    LDAXPxw(x2, x3, wback);
+                    CMPSxw_REG(xRAX, x2);
+                    B_MARK(cNE);    // EAX != Ed[0]
+                    CMPSxw_REG(xRDX, x3);
+                    B_MARK(cNE);    // EDX != Ed[1]
+                    STLXPxw(x4, xRBX, xRCX, wback);
+                    CBNZx_MARKLOCK(x4);
+                    MOV32w(x1, 1);
+                    B_MARK3_nocond;
+                    MARK;
+                    MOVxw_REG(xRAX, x2);
+                    MOVxw_REG(xRDX, x3);
+                    MOV32w(x1, 0);
+                    MARK3;
+                    DMB_ISH();
+                    BFIw(xFlags, x1, F_ZF, 1);
+                    break;
+
+                default:
+                    DEFAULT;
+            }
+            break;
+                    
+        case 0x29:
+            INST_NAME("LOCK SUB Ed, Gd");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGD;
+            DMB_ISH();
+            if(MODREG) {
+                ed = xRAX+(nextop&7)+(rex.b<<3);
+                emit_sub32(dyn, ninst, rex, ed, gd, x3, x4);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, 0);
+                MARKLOCK;
+                LDAXRxw(x1, wback);
+                emit_sub32(dyn, ninst, rex, x1, gd, x3, x4);
+                STLXRxw(x3, x1, wback);
+                CBNZx_MARKLOCK(x3);
+            }
+            DMB_ISH();
+            break;
+
+        case 0x66:
+            opcode = F8;
+            switch(opcode) {
+                case 0x09:
+                    INST_NAME("LOCK OR Ew, Gw");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    nextop = F8;
+                    GETGW(x5);
+                    DMB_ISH();
+                    if(MODREG) {
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        UXTHw(x6, ed);
+                        emit_or16(dyn, ninst, x6, x5, x3, x4);
+                        BFIx(ed, x6, 0, 16);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, 0);
+                        MARKLOCK;
+                        LDAXRH(x1, wback);
+                        emit_or16(dyn, ninst, x1, x5, x3, x4);
+                        STLXRH(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    DMB_ISH();
+                    break;
+
+                case 0x81:
+                case 0x83:
+                    nextop = F8;
+                    DMB_ISH();
+                    switch((nextop>>3)&7) {
+                        case 0: //ADD
+                            if(opcode==0x81) {
+                                INST_NAME("LOCK ADD Ew, Iw");
+                            } else {
+                                INST_NAME("LOCK ADD Ew, Iw");
+                            }
+                            SETFLAGS(X_ALL, SF_SET_PENDING);
+                            if(MODREG) {
+                                if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                                ed = xRAX+(nextop&7)+(rex.b<<3);
+                                MOV32w(x5, i32);
+                                UXTHw(x6, ed);
+                                emit_add16(dyn, ninst, x6, x5, x3, x4);
+                                BFIx(ed, x6, 0, 16);
+                            } else {
+                                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?2:1);
+                                if(opcode==0x81) i32 = F32S; else i32 = F8S;
+                                MOV32w(x5, i32);
+                                TSTx_mask(wback, 1, 0, 0);    // mask=1
+                                B_MARK(cNE);
+                                MARKLOCK;
+                                LDAXRH(x1, wback);
+                                emit_add16(dyn, ninst, x1, x5, x3, x4);
+                                STLXRH(x3, x1, wback);
+                                CBNZx_MARKLOCK(x3);
+                                B_NEXT_nocond;
+                                MARK;   // unaligned! also, not enough 
+                                LDRH_U12(x1, wback, 0);
+                                LDAXRB(x4, wback);
+                                BFIw(x1, x4, 0, 8); // re-inject
+                                emit_add16(dyn, ninst, x1, x5, x3, x4);
+                                STLXRB(x3, x1, wback);
+                                CBNZx_MARK(x3);
+                                STRH_U12(x1, wback, 0);    // put the whole value
+                            }
+                            break;
+                        case 1: //OR
+                            if(opcode==0x81) {INST_NAME("LOCK OR Ew, Iw");} else {INST_NAME("LOCK OR Ew, Iw");}
+                            SETFLAGS(X_ALL, SF_SET_PENDING);
+                            if(MODREG) {
+                                if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                                ed = xRAX+(nextop&7)+(rex.b<<3);
+                                MOV32w(x5, i32);
+                                UXTHw(x6, ed);
+                                emit_or16(dyn, ninst, x6, x5, x3, x4);
+                                BFIx(ed, x6, 0, 16);
+                            } else {
+                                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?2:1);
+                                if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                                MOV32w(x5, i32);
+                                MARKLOCK;
+                                LDAXRH(x1, wback);
+                                emit_or16(dyn, ninst, x1, x5, x3, x4);
+                                STLXRH(x3, x1, wback);
+                                CBNZx_MARKLOCK(x3);
+                            }
+                            break;
+                        case 2: //ADC
+                            if(opcode==0x81) {INST_NAME("LOCK ADC Ew, Iw");} else {INST_NAME("LOCK ADC Ew, Ib");}
+                            READFLAGS(X_CF);
+                            SETFLAGS(X_ALL, SF_SET_PENDING);
+                            if(MODREG) {
+                                if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                                ed = xRAX+(nextop&7)+(rex.b<<3);
+                                MOV32w(x5, i32);
+                                UXTHw(x6, ed);
+                                emit_adc16(dyn, ninst, x6, x5, x3, x4);
+                                BFIx(ed, x6, 0, 16);
+                            } else {
+                                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?2:1);
+                                if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                                MOV32w(x5, i32);
+                                MARKLOCK;
+                                LDAXRH(x1, wback);
+                                emit_adc16(dyn, ninst, x1, x5, x3, x4);
+                                STLXRH(x3, x1, wback);
+                                CBNZx_MARKLOCK(x3);
+                            }
+                            break;
+                        case 3: //SBB
+                            if(opcode==0x81) {INST_NAME("LOCK SBB Ew, Iw");} else {INST_NAME("LOCK SBB Ew, Ib");}
+                            READFLAGS(X_CF);
+                            SETFLAGS(X_ALL, SF_SET_PENDING);
+                            if(MODREG) {
+                                if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                                ed = xRAX+(nextop&7)+(rex.b<<3);
+                                MOV32w(x5, i32);
+                                UXTHw(x6, ed);
+                                emit_sbb16(dyn, ninst, x6, x5, x3, x4);
+                                BFIx(ed, x6, 0, 16);
+                            } else {
+                                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?2:1);
+                                if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                                MOV32w(x5, i32);
+                                MARKLOCK;
+                                LDAXRH(x1, wback);
+                                emit_sbb16(dyn, ninst, x1, x5, x3, x4);
+                                STLXRH(x3, x1, wback);
+                                CBNZx_MARKLOCK(x3);
+                            }
+                            break;
+                        case 4: //AND
+                            if(opcode==0x81) {INST_NAME("LOCK AND Ew, Iw");} else {INST_NAME("LOCK AND Ew, Ib");}
+                            SETFLAGS(X_ALL, SF_SET_PENDING);
+                            if(MODREG) {
+                                if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                                ed = xRAX+(nextop&7)+(rex.b<<3);
+                                MOV32w(x5, i32);
+                                UXTHw(x6, ed);
+                                emit_and16(dyn, ninst, x6, x5, x3, x4);
+                                BFIx(ed, x6, 0, 16);
+                            } else {
+                                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?2:1);
+                                if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                                MOV32w(x5, i32);
+                                MARKLOCK;
+                                LDAXRH(x1, wback);
+                                emit_and16(dyn, ninst, x1, x5, x3, x4);
+                                STLXRH(x3, x1, wback);
+                                CBNZx_MARKLOCK(x3);
+                            }
+                            break;
+                        case 5: //SUB
+                            if(opcode==0x81) {INST_NAME("LOCK SUB Ew, Iw");} else {INST_NAME("LOCK SUB Ew, Ib");}
+                            SETFLAGS(X_ALL, SF_SET_PENDING);
+                            if(MODREG) {
+                                if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                                ed = xRAX+(nextop&7)+(rex.b<<3);
+                                MOV32w(x5, i32);
+                                UXTHw(x6, ed);
+                                emit_sub16(dyn, ninst, x6, x5, x3, x4);
+                                BFIx(ed, x6, 0, 16);
+                            } else {
+                                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?2:1);
+                                if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                                MOV32w(x5, i32);
+                                TSTx_mask(wback, 1, 0, 0);    // mask=1
+                                B_MARK(cNE);
+                                MARKLOCK;
+                                LDAXRH(x1, wback);
+                                emit_sub16(dyn, ninst, x1, x5, x3, x4);
+                                STLXRH(x3, x1, wback);
+                                CBNZx_MARKLOCK(x3);
+                                B_NEXT_nocond;
+                                MARK;   // unaligned! also, not enough 
+                                LDRH_U12(x1, wback, 0);
+                                LDAXRB(x4, wback);
+                                BFIw(x1, x4, 0, 8); // re-inject
+                                emit_sub16(dyn, ninst, x1, x5, x3, x4);
+                                STLXRB(x3, x1, wback);
+                                CBNZx_MARK(x3);
+                                STRH_U12(x1, wback, 0);    // put the whole value
+                            }
+                            break;
+                        case 6: //XOR
+                            if(opcode==0x81) {INST_NAME("LOCK XOR Ew, Iw");} else {INST_NAME("LOCK XOR Ew, Ib");}
+                            SETFLAGS(X_ALL, SF_SET_PENDING);
+                            if(MODREG) {
+                                if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                                ed = xRAX+(nextop&7)+(rex.b<<3);
+                                MOV32w(x5, i32);
+                                UXTHw(x6, ed);
+                                emit_xor16(dyn, ninst, x6, x5, x3, x4);
+                                BFIx(ed, x6, 0, 16);
+                            } else {
+                                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?2:1);
+                                if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                                MOV32w(x5, i32);
+                                MARKLOCK;
+                                LDAXRH(x1, wback);
+                                emit_xor16(dyn, ninst, x1, x5, x3, x4);
+                                STLXRH(x3, x1, wback);
+                                CBNZx_MARKLOCK(x3);
+                            }
+                            break;
+                        case 7: //CMP
+                            if(opcode==0x81) {INST_NAME("(LOCK) CMP Ew, Iw");} else {INST_NAME("(LOCK) CMP Ew, Ib");}
+                            SETFLAGS(X_ALL, SF_SET_PENDING);
+                            GETEW(x6, (opcode==0x81)?2:1);
+                            (void)wb1;
+                            // No need to LOCK, this is readonly
+                            if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                            if(i32) {
+                                MOV32w(x5, i32);
+                                UXTHw(x6, ed);
+                                emit_cmp16(dyn, ninst, x6, x5, x3, x4, x6);
+                                BFIx(ed, x6, 0, 16);
+                            } else {
+                                emit_cmp16_0(dyn, ninst, ed, x3, x4);
+                            }
+                            break;
+                    }
+                    DMB_ISH();
+                    break;
+                default:
+                    DEFAULT;
+            }
+            break;
+
+        case 0x80:
+            nextop = F8;
+            DMB_ISH();
+            switch((nextop>>3)&7) {
+                case 0: //ADD
+                    INST_NAME("ADD Eb, Ib");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        GETEB(x1, 1);
+                        u8 = F8;
+                        emit_add8c(dyn, ninst, x1, u8, x2, x4);
+                        wb1 = 0;
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x5, &fixedaddress, 0, 0, rex, 0, 1);
+                        u8 = F8;
+                        wb1 = 1;
+                        MARKLOCK;
+                        LDAXRB(x1, wback);
+                        emit_add8c(dyn, ninst, x1, u8, x2, x4);
+                        STLXRB(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    EBBACK;
+                    break;
+                case 1: //OR
+                    INST_NAME("OR Eb, Ib");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        GETEB(x1, 1);
+                        u8 = F8;
+                        emit_or8c(dyn, ninst, x1, u8, x2, x4);
+                        wb1 = 0;
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x5, &fixedaddress, 0, 0, rex, 0, 1);
+                        u8 = F8;
+                        wb1 = 1;
+                        MARKLOCK;
+                        LDAXRB(x1, wback);
+                        emit_or8c(dyn, ninst, x1, u8, x2, x4);
+                        STLXRB(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    EBBACK;
+                    break;
+                case 2: //ADC
+                    INST_NAME("ADC Eb, Ib");
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        GETEB(x1, 1);
+                        u8 = F8;
+                        emit_adc8c(dyn, ninst, x1, u8, x2, x4, x5);
+                        wb1 = 0;
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x5, &fixedaddress, 0, 0, rex, 0, 1);
+                        u8 = F8;
+                        wb1 = 1;
+                        MARKLOCK;
+                        LDAXRB(x1, wback);
+                        emit_adc8c(dyn, ninst, x1, u8, x2, x4, x5);
+                        STLXRB(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    EBBACK;
+                    break;
+                case 3: //SBB
+                    INST_NAME("SBB Eb, Ib");
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        GETEB(x1, 1);
+                        u8 = F8;
+                        emit_sbb8c(dyn, ninst, x1, u8, x2, x4, x5);
+                        wb1 = 0;
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x5, &fixedaddress, 0, 0, rex, 0, 1);
+                        u8 = F8;
+                        wb1 = 1;
+                        MARKLOCK;
+                        LDAXRB(x1, wback);
+                        emit_sbb8c(dyn, ninst, x1, u8, x2, x4, x5);
+                        STLXRB(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    EBBACK;
+                    break;
+                case 4: //AND
+                    INST_NAME("AND Eb, Ib");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        GETEB(x1, 1);
+                        u8 = F8;
+                        emit_and8c(dyn, ninst, x1, u8, x2, x4);
+                        wb1 = 0;
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x5, &fixedaddress, 0, 0, rex, 0, 1);
+                        u8 = F8;
+                        wb1 = 1;
+                        MARKLOCK;
+                        LDAXRB(x1, wback);
+                        emit_and8c(dyn, ninst, x1, u8, x2, x4);
+                        STLXRB(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    EBBACK;
+                    break;
+                case 5: //SUB
+                    INST_NAME("SUB Eb, Ib");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        GETEB(x1, 1);
+                        u8 = F8;
+                        emit_sub8c(dyn, ninst, x1, u8, x2, x4, x5);
+                        wb1 = 0;
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x5, &fixedaddress, 0, 0, rex, 0, 1);
+                        u8 = F8;
+                        wb1 = 1;
+                        MARKLOCK;
+                        LDAXRB(x1, wback);
+                        emit_sub8c(dyn, ninst, x1, u8, x2, x4, x5);
+                        STLXRB(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    EBBACK;
+                    break;
+                case 6: //XOR
+                    INST_NAME("XOR Eb, Ib");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        GETEB(x1, 1);
+                        u8 = F8;
+                        emit_xor8c(dyn, ninst, x1, u8, x2, x4);
+                        wb1 = 0;
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x5, &fixedaddress, 0, 0, rex, 0, 1);
+                        u8 = F8;
+                        wb1 = 1;
+                        MARKLOCK;
+                        LDAXRB(x1, wback);
+                        emit_xor8c(dyn, ninst, x1, u8, x2, x4);
+                        STLXRB(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    EBBACK;
+                    break;
+                case 7: //CMP
+                    INST_NAME("CMP Eb, Ib");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEB(x1, 1);
+                    u8 = F8;
+                    if(u8) {
+                        MOV32w(x2, u8);
+                        emit_cmp8(dyn, ninst, x1, x2, x3, x4, x5);
+                    } else {
+                        emit_cmp8_0(dyn, ninst, x1, x3, x4);
+                    }
+                    break;
+                default:
+                    DEFAULT;
+            }
+            DMB_ISH();
+            break;
+        case 0x81:
+        case 0x83:
+            nextop = F8;
+            DMB_ISH();
+            switch((nextop>>3)&7) {
+                case 0: //ADD
+                    if(opcode==0x81) {
+                        INST_NAME("LOCK ADD Ed, Id");
+                    } else {
+                        INST_NAME("LOCK ADD Ed, Ib");
+                    }
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        MOV64xw(x5, i64);
+                        emit_add32(dyn, ninst, rex, ed, x5, x3, x4);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?4:1);
+                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                        TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
+                        B_MARK(cNE);
+                        MARKLOCK;
+                        LDAXRxw(x1, wback);
+                        emit_add32c(dyn, ninst, rex, x1, i64, x3, x4, x5);
+                        STLXRxw(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                        DMB_ISH();
+                        B_NEXT_nocond;
+                        MARK;   // unaligned! also, not enough 
+                        LDRxw_U12(x1, wback, 0);
+                        LDAXRB(x4, wback);
+                        BFIxw(x1, x4, 0, 8); // re-inject
+                        emit_add32c(dyn, ninst, rex, x1, i64, x3, x4, x5);
+                        STLXRB(x3, x1, wback);
+                        CBNZx_MARK(x3);
+                        STRxw_U12(x1, wback, 0);    // put the whole value
+                    }
+                    break;
+                case 1: //OR
+                    if(opcode==0x81) {INST_NAME("LOCK OR Ed, Id");} else {INST_NAME("LOCK OR Ed, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        MOV64xw(x5, i64);
+                        emit_or32(dyn, ninst, rex, ed, x5, x3, x4);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?4:1);
+                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                        MOV64xw(x5, i64);
+                        MARKLOCK;
+                        LDAXRxw(x1, wback);
+                        emit_or32(dyn, ninst, rex, x1, x5, x3, x4);
+                        STLXRxw(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    break;
+                case 2: //ADC
+                    if(opcode==0x81) {INST_NAME("LOCK ADC Ed, Id");} else {INST_NAME("LOCK ADC Ed, Ib");}
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        MOV64xw(x5, i64);
+                        emit_adc32(dyn, ninst, rex, ed, x5, x3, x4);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?4:1);
+                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                        MOV64xw(x5, i64);
+                        MARKLOCK;
+                        LDAXRxw(x1, wback);
+                        emit_adc32(dyn, ninst, rex, x1, x5, x3, x4);
+                        STLXRxw(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    break;
+                case 3: //SBB
+                    if(opcode==0x81) {INST_NAME("LOCK SBB Ed, Id");} else {INST_NAME("LOCK SBB Ed, Ib");}
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        MOV64xw(x5, i64);
+                        emit_sbb32(dyn, ninst, rex, ed, x5, x3, x4);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?4:1);
+                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                        MOV64xw(x5, i64);
+                        MARKLOCK;
+                        LDAXRxw(x1, wback);
+                        emit_sbb32(dyn, ninst, rex, x1, x5, x3, x4);
+                        STLXRxw(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    break;
+                case 4: //AND
+                    if(opcode==0x81) {INST_NAME("LOCK AND Ed, Id");} else {INST_NAME("LOCK AND Ed, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        MOV64xw(x5, i64);
+                        emit_and32(dyn, ninst, rex, ed, x5, x3, x4);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?4:1);
+                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                        MOV64xw(x5, i64);
+                        MARKLOCK;
+                        LDAXRxw(x1, wback);
+                        emit_and32(dyn, ninst, rex, x1, x5, x3, x4);
+                        STLXRxw(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    break;
+                case 5: //SUB
+                    if(opcode==0x81) {INST_NAME("LOCK SUB Ed, Id");} else {INST_NAME("LOCK SUB Ed, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        MOV64xw(x5, i64);
+                        emit_sub32(dyn, ninst, rex, ed, x5, x3, x4);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?4:1);
+                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                        TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
+                        B_MARK(cNE);
+                        MARKLOCK;
+                        LDAXRxw(x1, wback);
+                        emit_sub32c(dyn, ninst, rex, x1, i64, x3, x4, x5);
+                        STLXRxw(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                        DMB_ISH();
+                        B_NEXT_nocond;
+                        MARK;   // unaligned! also, not enough 
+                        LDRxw_U12(x1, wback, 0);
+                        LDAXRB(x4, wback);
+                        BFIxw(x1, x4, 0, 8); // re-inject
+                        emit_sub32c(dyn, ninst, rex, x1, i64, x3, x4, x5);
+                        STLXRB(x3, x1, wback);
+                        CBNZx_MARK(x3);
+                        STRxw_U12(x1, wback, 0);    // put the whole value
+                    }
+                    break;
+                case 6: //XOR
+                    if(opcode==0x81) {INST_NAME("LOCK XOR Ed, Id");} else {INST_NAME("LOCK XOR Ed, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        MOV64xw(x5, i64);
+                        emit_xor32(dyn, ninst, rex, ed, x5, x3, x4);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?4:1);
+                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                        MOV64xw(x5, i64);
+                        MARKLOCK;
+                        LDAXRxw(x1, wback);
+                        emit_xor32(dyn, ninst, rex, x1, x5, x3, x4);
+                        STLXRxw(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    break;
+                case 7: //CMP
+                    if(opcode==0x81) {INST_NAME("(LOCK) CMP Ed, Id");} else {INST_NAME("(LOCK) CMP Ed, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETED((opcode==0x81)?4:1);
+                    // No need to LOCK, this is readonly
+                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
+                    if(i64) {
+                        MOV64xw(x5, i64);
+                        emit_cmp32(dyn, ninst, rex, ed, x5, x3, x4, x6);
+                    } else {
+                        emit_cmp32_0(dyn, ninst, rex, ed, x3, x4);
+                    }
+                    break;
+            }
+            DMB_ISH();
+            break;
+            
+        case 0x87:
+            INST_NAME("LOCK XCHG Ed, Gd");
+            nextop = F8;
+            if(MODREG) {
+                GETGD;
+                GETED(0);
+                MOVxw_REG(x1, gd);
+                MOVxw_REG(gd, ed);
+                MOVxw_REG(ed, x1);
+            } else {
+                GETGD;
+                DMB_ISH();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0, rex, 0, 0);
+                TSTx_mask(ed, 1, 0, 1+rex.w);    // mask=3 or 7
+                B_MARK(cNE);
+                MARKLOCK;
+                LDAXRxw(x1, ed);
+                STLXRxw(x3, gd, ed);
+                CBNZx_MARKLOCK(x3);
+                B_MARK2_nocond;
+                MARK;
+                LDRxw_U12(x1, ed, 0);
+                STRxw_U12(gd, ed, 0);
+                MARK2;
+                DMB_ISH();
+                MOVxw_REG(gd, x1);
+            }
+            break;
+            
+        case 0xFF:
+            nextop = F8;
+            switch((nextop>>3)&7)
+            {
+                case 0: // INC Ed
+                    INST_NAME("LOCK INC Ed");
+                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET_PENDING);
+                    DMB_ISH();
+                    if(MODREG) {
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        emit_inc32(dyn, ninst, rex, ed, x3, x4);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, 0);
+                        TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
+                        B_MARK(cNE);    // unaligned
+                        MARKLOCK;
+                        LDAXRxw(x1, wback);
+                        emit_inc32(dyn, ninst, rex, x1, x3, x4);
+                        STLXRxw(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                        B_NEXT_nocond;
+                        MARK;
+                        LDRxw_U12(x1, wback, 0);
+                        LDAXRB(x4, wback);
+                        BFIxw(x1, x4, 0, 8); // re-inject
+                        emit_inc32(dyn, ninst, rex, x1, x3, x4);
+                        STLXRB(x3, x1, wback);
+                        CBNZw_MARK(x3);
+                        STRxw_U12(x1, wback, 0);
+                    }
+                    DMB_ISH();
+                    break;
+                case 1: //DEC Ed
+                    INST_NAME("LOCK DEC Ed");
+                    SETFLAGS(X_ALL&~X_CF, SF_SUBSET_PENDING);
+                    DMB_ISH();
+                    if(MODREG) {
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        emit_dec32(dyn, ninst, rex, ed, x3, x4);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, 0);
+                        TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
+                        B_MARK(cNE);    // unaligned
+                        MARKLOCK;
+                        LDAXRxw(x1, wback);
+                        emit_dec32(dyn, ninst, rex, x1, x3, x4);
+                        STLXRxw(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                        B_NEXT_nocond;
+                        MARK;
+                        LDRxw_U12(x1, wback, 0);
+                        LDAXRB(x4, wback);
+                        BFIxw(x1, x4, 0, 8); // re-inject
+                        emit_dec32(dyn, ninst, rex, x1, x3, x4);
+                        STLXRB(x3, x1, wback);
+                        CBNZw_MARK(x3);
+                        STRxw_U12(x1, wback, 0);
+                    }
+                    DMB_ISH();
+                    break;
+                default:
+                    DEFAULT;
+            }
+            break;
+            
+        default:
+            DEFAULT;
+    }
+    return addr;
+}

src/dynarec/arm64/dynarec_arm64_f20f.c

@@ -15,17 +15,17 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
+#include "dynarec_native.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_functions.h"
 #include "dynarec_arm64_helper.h"
 
 // Get Ex as a double, not a quad (warning, x2 get used)
-#define GETEX(a, D)                                                                                 \
+#define GETEX(a, w, D)                                                                              \
     if(MODREG) {                                                                                    \
-        a = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3));                                     \
+        a = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), w);                                  \
     } else {                                                                                        \
         a = fpu_get_scratch(dyn);                                                                   \
         addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<3, 7, rex, 0, D);     \
@@ -34,24 +34,30 @@
 
 #define GETG        gd = ((nextop&0x38)>>3)+(rex.r<<3)
 
-#define GETGX(a)    gd = ((nextop&0x38)>>3)+(rex.r<<3); \
-                    a = sse_get_reg(dyn, ninst, x1, gd)
+#define GETGX(a, w) gd = ((nextop&0x38)>>3)+(rex.r<<3); \
+                    a = sse_get_reg(dyn, ninst, x1, gd, w)
 
 #define GETGX_empty(a)  gd = ((nextop&0x38)>>3)+(rex.r<<3); \
                         a = sse_get_reg_empty(dyn, ninst, x1, gd)
 
+#define GETGM(a)                        \
+    gd = ((nextop&0x38)>>3);            \
+    a = mmx_get_reg(dyn, ninst, x1, x2, x3, gd)
+
 uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int* ok, int* need_epilog)
 {
+    (void)ip; (void)need_epilog;
+
     uint8_t opcode = F8;
     uint8_t nextop;
     uint8_t gd, ed;
     uint8_t wback;
     uint8_t u8;
-    uint64_t u64;
+    uint64_t u64, j64;
     int v0, v1;
     int q0;
     int d0, d1;
-    int fixedaddress;
+    int64_t fixedaddress;
 
 #ifdef PRECISE_CVT
     int j32;
@@ -71,9 +77,9 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             GETG;
             if(MODREG) {
                 ed = (nextop&7)+ (rex.b<<3);
-                v0 = sse_get_reg(dyn, ninst, x1, gd);
-                d0 = sse_get_reg(dyn, ninst, x1, ed);
-                VMOV(v0, d0);
+                v0 = sse_get_reg(dyn, ninst, x1, gd, 1);
+                d0 = sse_get_reg(dyn, ninst, x1, ed, 0);
+                VMOVeD(v0, 0, d0, 0);
             } else {
                 v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
                 addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<3, 7, rex, 0, 0);
@@ -84,11 +90,11 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             INST_NAME("MOVSD Ex, Gx");
             nextop = F8;
             GETG;
-            v0 = sse_get_reg(dyn, ninst, x1, gd);
+            v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
             if(MODREG) {
                 ed = (nextop&7)+ (rex.b<<3);
-                d0 = sse_get_reg(dyn, ninst, x1, ed);
-                VMOV(d0, v0);
+                d0 = sse_get_reg(dyn, ninst, x1, ed, 1);
+                VMOVeD(d0, 0, v0, 0);
             } else {
                 addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<3, 7, rex, 0, 0);
                 VSTR64_U12(v0, ed, fixedaddress);
@@ -99,7 +105,7 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             nextop = F8;
             GETG;
             if(MODREG) {
-                d0 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3));
+                d0 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
                 v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
                 VMOVeD(v0, 0, d0, 0);
             } else {
@@ -113,7 +119,7 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0x2A:
             INST_NAME("CVTSI2SD Gx, Ed");
             nextop = F8;
-            GETGX(v0);
+            GETGX(v0, 1);
             GETED(0);
             d1 = fpu_get_scratch(dyn);
             if(rex.w) {
@@ -128,23 +134,23 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             INST_NAME("CVTTSD2SI Gd, Ex");
             nextop = F8;
             GETGD;
-            GETEX(q0, 0);
+            GETEX(q0, 0, 0);
             FCVTZSxwD(gd, q0);
             break;
         case 0x2D:
             INST_NAME("CVTSD2SI Gd, Ex");
             nextop = F8;
             GETGD;
-            GETEX(q0, 0);
+            GETEX(q0, 0, 0);
             #ifdef PRECISE_CVT
             LDRH_U12(x1, xEmu, offsetof(x64emu_t, mxcsr));
             UBFXx(x1, x1, 13, 2);   // extract round requested
             LSLx_REG(x1, x1, 3);
-            ADDx_U12(x1, x1, 8);    // add the actual add+jump opcodes
             // Construct a "switch case", with each case 2 instructions, so 8 bytes
-            BL(+4); // Branch with Link to next, so LR gets next PC address
+            ADR(xLR, GETMARK);
             ADDx_REG(xLR, xLR, x1);
-            B(xLR); // could use RET, but it's not really one
+            B(xLR);
+            MARK;
             FCVTNSxwD(gd, q0);  // 0: Nearest (even)
             B_NEXT_nocond;
             FCVTMSxwD(gd, q0);  // 1: Toward -inf
@@ -161,36 +167,70 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0x51:
             INST_NAME("SQRTSD Gx, Ex");
             nextop = F8;
-            GETGX(v0);
+            GETGX(v0, 1);
             d1 = fpu_get_scratch(dyn);
-            GETEX(d0, 0);
+            GETEX(d0, 0, 0);
+            if(!box64_dynarec_fastnan) {
+                v1 = fpu_get_scratch(dyn);
+                FCMLTD_0(v1, d0);
+                SHL_64(v1, v1, 63);
+            }
             FSQRTD(d1, d0);
+            if(!box64_dynarec_fastnan) {
+                VORR(d1, d1, v1);
+            }
             VMOVeD(v0, 0, d1, 0);
             break;
 
         case 0x58:
             INST_NAME("ADDSD Gx, Ex");
             nextop = F8;
-            GETGX(v0);
-            d1 = fpu_get_scratch(dyn);
-            GETEX(d0, 0);
-            FADDD(d1, v0, d0);  // the high part of the vector is erased...
-            VMOVeD(v0, 0, d1, 0);
+            GETGX(d1, 1);
+            v1 = fpu_get_scratch(dyn);
+            GETEX(d0, 0, 0);
+            if(!box64_dynarec_fastnan) {
+                v0 = fpu_get_scratch(dyn);
+                q0 = fpu_get_scratch(dyn);
+                // check if any input value was NAN
+                FMAXD(v0, d0, d1);    // propagate NAN
+                FCMEQD(v0, v0, v0);    // 0 if NAN, 1 if not NAN
+            }
+            FADDD(v1, d1, d0);  // the high part of the vector is erased...
+            if(!box64_dynarec_fastnan) {
+                FCMEQD(q0, v1, v1);    // 0 => out is NAN
+                VBIC(q0, v0, q0);      // forget it in any input was a NAN already
+                SHL_64(q0, q0, 63);     // only keep the sign bit
+                VORR(v1, v1, q0);      // NAN -> -NAN
+            }
+            VMOVeD(d1, 0, v1, 0);
             break;
         case 0x59:
             INST_NAME("MULSD Gx, Ex");
             nextop = F8;
-            GETGX(v0);
-            d1 = fpu_get_scratch(dyn);
-            GETEX(d0, 0);
-            FMULD(d1, v0, d0);
-            VMOVeD(v0, 0, d1, 0);
+            GETGX(d1, 1);
+            v1 = fpu_get_scratch(dyn);
+            GETEX(d0, 0, 0);
+            if(!box64_dynarec_fastnan) {
+                v0 = fpu_get_scratch(dyn);
+                q0 = fpu_get_scratch(dyn);
+                // check if any input value was NAN
+                FMAXD(v0, d0, d1);    // propagate NAN
+                FCMEQD(v0, v0, v0);    // 0 if NAN, 1 if not NAN
+            }
+            FMULD(v1, d1, d0);
+            if(!box64_dynarec_fastnan) {
+                FCMEQD(q0, v1, v1);    // 0 => out is NAN
+                VBIC(q0, v0, q0);      // forget it in any input was a NAN already
+                SHL_64(q0, q0, 63);     // only keep the sign bit
+                VORR(v1, v1, q0);      // NAN -> -NAN
+            }
+            VMOVeD(d1, 0, v1, 0);
             break;
         case 0x5A:
             INST_NAME("CVTSD2SS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
-            GETEX(d0, 0);
+            GETGX(v0, 1);
+            GETEX(d0, 0, 0);
             d1 = fpu_get_scratch(dyn);
             FCVT_S_D(d1, d0);
             VMOVeS(v0, 0, d1, 0);
@@ -199,49 +239,85 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0x5C:
             INST_NAME("SUBSD Gx, Ex");
             nextop = F8;
-            GETGX(v0);
-            d1 = fpu_get_scratch(dyn);
-            GETEX(d0, 0);
-            FSUBD(d1, v0, d0);
-            VMOVeD(v0, 0, d1, 0);
+            GETGX(d1, 1);
+            v1 = fpu_get_scratch(dyn);
+            GETEX(d0, 0, 0);
+            if(!box64_dynarec_fastnan) {
+                v0 = fpu_get_scratch(dyn);
+                q0 = fpu_get_scratch(dyn);
+                // check if any input value was NAN
+                FMAXD(v0, d0, d1);    // propagate NAN
+                FCMEQD(v0, v0, v0);    // 0 if NAN, 1 if not NAN
+            }
+            FSUBD(v1, d1, d0);
+            if(!box64_dynarec_fastnan) {
+                FCMEQD(q0, v1, v1);    // 0 => out is NAN
+                VBIC(q0, v0, q0);      // forget it in any input was a NAN already
+                SHL_64(q0, q0, 63);     // only keep the sign bit
+                VORR(v1, v1, q0);      // NAN -> -NAN
+            }
+            VMOVeD(d1, 0, v1, 0);
             break;
         case 0x5D:
             INST_NAME("MINSD Gx, Ex");
             nextop = F8;
-            GETG;
-            v0 = sse_get_reg(dyn, ninst, x1, gd);
-            GETEX(v1, 0);
+            GETGX(v0, 1);
+            GETEX(v1, 0, 0);
             // MINSD: if any input is NaN, or Ex[0]<Gx[0], copy Ex[0] -> Gx[0]
+            #if 0
             d0 = fpu_get_scratch(dyn);
             FMINNMD(d0, v0, v1);    // NaN handling may be slightly different, is that a problem?
             VMOVeD(v0, 0, d0, 0);   // to not erase uper part
+            #else
+            FCMPD(v0, v1);
+            B_NEXT(cLS);    //Less than or equal
+            VMOVeD(v0, 0, v1, 0);   // to not erase uper part
+            #endif
             break;
         case 0x5E:
             INST_NAME("DIVSD Gx, Ex");
             nextop = F8;
-            GETGX(v0);
+            GETGX(v0, 1);
             d1 = fpu_get_scratch(dyn);
-            GETEX(d0, 0);
-            FDIVD(d1, v0, d0);
+            GETEX(v1, 0, 0);
+            if(!box64_dynarec_fastnan) {
+                d0 = fpu_get_scratch(dyn);
+                q0 = fpu_get_scratch(dyn);
+                // check if any input value was NAN
+                FMAXD(d0, v0, v1);      // propagate NAN
+                FCMEQD(d0, d0, d0);     // 0 if NAN, 1 if not NAN
+            }
+            FDIVD(d1, v0, v1);
+            if(!box64_dynarec_fastnan) {
+                FCMEQD(q0, d1, d1);     // 0 => out is NAN
+                VBIC(q0, d0, q0);       // forget it in any input was a NAN already
+                SHL_64(q0, q0, 63);     // only keep the sign bit
+                VORR(d1, d1, q0);       // NAN -> -NAN
+            }
             VMOVeD(v0, 0, d1, 0);
             break;
         case 0x5F:
             INST_NAME("MAXSD Gx, Ex");
             nextop = F8;
-            GETG;
-            v0 = sse_get_reg(dyn, ninst, x1, gd);
-            GETEX(v1, 0);
+            GETGX(v0, 1);
+            GETEX(v1, 0, 0);
             // MAXSD: if any input is NaN, or Ex[0]>Gx[0], copy Ex[0] -> Gx[0]
+            #if 0
             d0 = fpu_get_scratch(dyn);
             FMAXNMD(d0, v0, v1);    // NaN handling may be slightly different, is that a problem?
             VMOVeD(v0, 0, d0, 0);   // to not erase uper part
+            #else
+            FCMPD(v0, v1);
+            B_NEXT(cGE);    //Greater than or equal
+            VMOVeD(v0, 0, v1, 0);   // to not erase uper part
+            #endif
             break;
 
         case 0x70:
             INST_NAME("PSHUFLW Gx, Ex, Ib");
             nextop = F8;
-            GETEX(v1, 1);
-            GETGX(v0);
+            GETEX(v1, 0, 1);
+            GETGX(v0, 1);
 
             u8 = F8;
             // only low part need to be suffled. VTBL only handle 8bits value, so the 16bits suffles need to be changed in 8bits
@@ -255,14 +331,17 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             VMOVQDfrom(d0, 0, x2);
             VTBL1_8(d0, v1, d0);
             VMOVeD(v0, 0, d0, 0);
+            if(v0!=v1) {
+                VMOVeD(v0, 1, v1, 1);
+            }
             break;
 
         case 0x7C:
             INST_NAME("HADDPS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
+            GETGX(v0, 1);
             if(MODREG) {
-                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3));
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
             } else {
                 addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<4, 15, rex, 0, 0);
                 v1 = fpu_get_scratch(dyn);
@@ -274,34 +353,62 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0xC2:
             INST_NAME("CMPSD Gx, Ex, Ib");
             nextop = F8;
-            GETGX(v0);
-            GETEX(v1, 1);
+            GETGX(v0, 1);
+            GETEX(v1, 0, 1);
             u8 = F8;
-            if((u8&7)==6){
-                FCMPD(v1, v0);
-            } else {
-                FCMPD(v0, v1);
-            }
+            FCMPD(v0, v1);
             switch(u8&7) {
                 case 0: CSETMx(x2, cEQ); break;   // Equal
-                case 1: CSETMx(x2, cMI); break;   // Less than
-                case 2: //CSETMx(x2, cLE); break;   // Less or equal (or unordered on ARM64, not on x86...)
-                        CSETMx(x2, cPL); CSINVx(x2, xZR, x2, cEQ); break;   // so use a 2 step here, but 1st test inverted because 2nd step invert again
+                case 1: CSETMx(x2, cCC); break;   // Less than
+                case 2: CSETMx(x2, cLS); break;   // Less or equal
                 case 3: CSETMx(x2, cVS); break;   // NaN
-                case 4: CSETMx(x2, cNE); break;   // Not Equal (or unordered on ARM, not on X86...)
+                case 4: CSETMx(x2, cNE); break;   // Not Equal or unordered
                 case 5: CSETMx(x2, cCS); break;   // Greater or equal or unordered
-                case 6: CSETMx(x2, cLT); break;   // Greater or unordered, test inverted, N!=V so unordereded or less than (inverted)
+                case 6: CSETMx(x2, cHI); break;   // Greater or unordered, test inverted, N!=V so unordered or less than (inverted)
                 case 7: CSETMx(x2, cVC); break;   // not NaN
             }
             VMOVQDfrom(v0, 0, x2);
             break;
 
+        case 0xD0:
+            INST_NAME("ADDSUBPS Gx, Ex");
+            nextop = F8;
+            GETGX(v0, 1);
+            GETEX(v1, 0, 0);
+            q0 = fpu_get_scratch(dyn);
+            static float addsubps[4] = {-1.f, 1.f, -1.f, 1.f};
+            MAYUSE(addsubps);
+            TABLE64(x2, (uintptr_t)&addsubps);
+            VLDR128_U12(q0, x2, 0);
+            VFMLAQS(v0, v1, q0);
+            break;
+
+        case 0xD6:
+            INST_NAME("MOVDQ2Q Gm, Ex");
+            nextop = F8;
+            GETGM(v0);
+            GETEX(v1, 0, 0);
+            VMOV(v0, v1);
+            break;
+
+        case 0xE6:
+            INST_NAME("CVTPD2DQ Gx, Ex");
+            nextop = F8;
+            GETEX(v1, 0, 0);
+            GETGX_empty(v0);
+            u8 = sse_setround(dyn, ninst, x1, x2, x3);
+            VFRINTIDQ(v0, v1);
+            x87_restoreround(dyn, ninst, u8);
+            VFCVTNSQD(v0, v0);  // convert double -> int64
+            SQXTN_32(v0, v0);   // convert int64 -> int32 with saturation in lower part, RaZ high part
+            break;
+
         case 0xF0:
             INST_NAME("LDDQU Gx,Ex");
             nextop = F8;
             GETG;
             if(MODREG) {
-                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3));
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
                 v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
                 VMOVQ(v0, v1);
             } else {
@@ -316,4 +423,3 @@ uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
     }
     return addr;
 }
-

src/dynarec/arm64/dynarec_arm64_f30f.c

@@ -15,17 +15,17 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
+#include "dynarec_native.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_functions.h"
 #include "dynarec_arm64_helper.h"
 
 // Get Ex as a single, not a quad (warning, x2 get used)
-#define GETEX(a, D)                                                                                 \
+#define GETEX(a, w, D)                                                                              \
     if(MODREG) {                                                                                    \
-        a = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3));                                     \
+        a = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), w);                                  \
     } else {                                                                                        \
         a = fpu_get_scratch(dyn);                                                                   \
         addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<2, 3, rex, 0, D);     \
@@ -34,14 +34,16 @@
 
 #define GETG        gd = ((nextop&0x38)>>3)+(rex.r<<3)
 
-#define GETGX(a)    gd = ((nextop&0x38)>>3)+(rex.r<<3); \
-                    a = sse_get_reg(dyn, ninst, x1, gd)
+#define GETGX(a, w) gd = ((nextop&0x38)>>3)+(rex.r<<3); \
+                    a = sse_get_reg(dyn, ninst, x1, gd, w)
 
 #define GETGX_empty(a)  gd = ((nextop&0x38)>>3)+(rex.r<<3);         \
                         a = sse_get_reg_empty(dyn, ninst, x1, gd)
 
 uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int* ok, int* need_epilog)
 {
+    (void)ip; (void)need_epilog;
+
     uint8_t opcode = F8;
     uint8_t nextop, u8;
     uint8_t gd, ed;
@@ -50,8 +52,8 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
     int v0, v1;
     int q0, q1;
     int d0, d1;
-    int fixedaddress;
-    int j32;
+    int64_t fixedaddress;
+    int64_t j64;
 
     MAYUSE(d0);
     MAYUSE(d1);
@@ -59,7 +61,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
     MAYUSE(q1);
     MAYUSE(v0);
     MAYUSE(v1);
-    MAYUSE(j32);
+    MAYUSE(j64);
 
     switch(opcode) {
 
@@ -68,8 +70,8 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             nextop = F8;
             GETG;
             if(MODREG) {
-                v0 = sse_get_reg(dyn, ninst, x1, gd);
-                q0 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3));
+                v0 = sse_get_reg(dyn, ninst, x1, gd, 1);
+                q0 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3), 0);
                 VMOVeS(v0, 0, q0, 0);
             } else {
                 v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
@@ -81,9 +83,9 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             INST_NAME("MOVSS Ex, Gx");
             nextop = F8;
             GETG;
-            v0 = sse_get_reg(dyn, ninst, x1, gd);
+            v0 = sse_get_reg(dyn, ninst, x1, gd, 1);
             if(MODREG) {
-                q0 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3));
+                q0 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3), 0);
                 VMOVeS(q0, 0, v0, 0);
             } else {
                 addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
@@ -94,7 +96,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             INST_NAME("MOVSLDUP Gx, Ex");
             nextop = F8;
             if(MODREG) {
-                q1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3));
+                q1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
             } else {
                 addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<4, 15, rex, 0, 0);
                 q1 = fpu_get_scratch(dyn);
@@ -108,7 +110,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             INST_NAME("MOVSHDUP Gx, Ex");
             nextop = F8;
             if(MODREG) {
-                q1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3));
+                q1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
             } else {
                 addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<4, 15, rex, 0, 0);
                 q1 = fpu_get_scratch(dyn);
@@ -118,10 +120,16 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             VTRNQ2_32(q0, q1, q1);
             break;
 
+        case 0x1E:
+            INST_NAME("NOP / ENDBR32 / ENDBR64");
+            nextop = F8;
+            FAKEED;
+            break;
+
         case 0x2A:
             INST_NAME("CVTSI2SS Gx, Ed");
             nextop = F8;
-            GETGX(v0);
+            GETGX(v0, 1);
             GETED(0);
             d1 = fpu_get_scratch(dyn);
             if(rex.w) {
@@ -136,23 +144,22 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             INST_NAME("CVTTSS2SI Gd, Ex");
             nextop = F8;
             GETGD;
-            GETEX(d0, 0);
+            GETEX(d0, 0, 0);
             FCVTZSxwS(gd, d0);
             break;
         case 0x2D:
             INST_NAME("CVTSS2SI Gd, Ex");
             nextop = F8;
             GETGD;
-            GETEX(q0, 0);
+            GETEX(q0, 0, 0);
             #ifdef PRECISE_CVT
             LDRH_U12(x1, xEmu, offsetof(x64emu_t, mxcsr));
             UBFXx(x1, x1, 13, 2);   // extract round requested
             LSLx_REG(x1, x1, 3);
-            ADDx_U12(x1, x1, 8);    // add the actual add+jump opcodes
             // Construct a "switch case", with each case 2 instructions, so 8 bytes
-            BL(+4); // Branch with Link to next, so LR gets next PC address
+            ADR(xLR, GETMARK);
             ADDx_REG(xLR, xLR, x1);
-            B(xLR); // could use RET, but it's not really one
+            B(xLR);
             FCVTNSxwS(gd, q0);  // 0: Nearest (even)
             B_NEXT_nocond;
             FCVTMSxwS(gd, q0);  // 1: Toward -inf
@@ -167,52 +174,63 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0x51:
             INST_NAME("SQRTSS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
+            GETGX(v0, 1);
             d1 = fpu_get_scratch(dyn);
-            GETEX(d0, 0);
+            GETEX(d0, 0, 0);
             FSQRTS(d1, d0);
             VMOVeS(v0, 0, d1, 0);
             break;
         case 0x52:
             INST_NAME("RSQRTSS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
-            GETEX(v1, 0);
+            GETGX(v0, 1);
+            GETEX(v1, 0, 0);
             d0 = fpu_get_scratch(dyn);
+            d1 = fpu_get_scratch(dyn);
             // so here: F32: Imm8 = abcd efgh that gives => aBbbbbbc defgh000 00000000 00000000
             // and want 1.0f = 0x3f800000
             // so 00111111 10000000 00000000 00000000
             // a = 0, b = 1, c = 1, d = 1, efgh=0
             // 0b01110000
             FMOVS_8(d0, 0b01110000);
-            FSQRTS(v0, v1);
-            FDIVS(d0, d0, v0);
+            FSQRTS(d1, v1);
+            FDIVS(d0, d0, d1);
+            VMOVeS(v0, 0, d0, 0);
+            break;
+        case 0x53:
+            INST_NAME("RCPSS Gx, Ex");
+            nextop = F8;
+            GETGX(v0, 1);
+            GETEX(v1, 0, 0);
+            d0 = fpu_get_scratch(dyn);
+            FMOVS_8(d0, 0b01110000);    //1.0f
+            FDIVS(d0, d0, v1);
             VMOVeS(v0, 0, d0, 0);
             break;
 
         case 0x58:
             INST_NAME("ADDSS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
+            GETGX(v0, 1);
             d1 = fpu_get_scratch(dyn);
-            GETEX(d0, 0);
+            GETEX(d0, 0, 0);
             FADDS(d1, v0, d0);  // the high part of the vector is erased...
             VMOVeS(v0, 0, d1, 0);
             break;
         case 0x59:
             INST_NAME("MULSS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
+            GETGX(v0, 1);
             d1 = fpu_get_scratch(dyn);
-            GETEX(d0, 0);
+            GETEX(d0, 0, 0);
             FMULS(d1, v0, d0);
             VMOVeS(v0, 0, d1, 0);
             break;
         case 0x5A:
             INST_NAME("CVTSS2SD Gx, Ex");
             nextop = F8;
-            GETGX(v0);
-            GETEX(v1, 0);
+            GETGX(v0, 1);
+            GETEX(v1, 0, 0);
             d0 = fpu_get_scratch(dyn);
             FCVT_D_S(d0, v1);
             VMOVeD(v0, 0, d0, 0);
@@ -220,7 +238,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0x5B:
             INST_NAME("CVTPS2DQ Gx, Ex");
             nextop = F8;
-            GETEX(d0, 0);
+            GETEX(d0, 0, 0);
             GETGX_empty(v0);
             VFCVTZSQS(v0, d0);
             break;
@@ -228,51 +246,64 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0x5C:
             INST_NAME("SUBSS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
+            GETGX(v0, 1);
             d1 = fpu_get_scratch(dyn);
-            GETEX(d0, 0);
+            GETEX(d0, 0, 0);
             FSUBS(d1, v0, d0);
             VMOVeS(v0, 0, d1, 0);
             break;
         case 0x5D:
             INST_NAME("MINSS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
-            GETEX(v1, 0);
+            GETGX(v0, 1);
+            GETEX(v1, 0, 0);
             // MINSS: if any input is NaN, or Ex[0]<Gx[0], copy Ex[0] -> Gx[0]
+            #if 0
             d0 = fpu_get_scratch(dyn);
             FMINNMS(d0, v0, v1);    // NaN handling may be slightly different, is that a problem?
             VMOVeS(v0, 0, d0, 0);   // to not erase uper part
+            #else
+            FCMPS(v0, v1);
+            B_NEXT(cLS);    //Less than or equal
+            VMOVeS(v0, 0, v1, 0);   // to not erase uper part
+            #endif
             break;
         case 0x5E:
             INST_NAME("DIVSS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
+            GETGX(v0, 1);
             d1 = fpu_get_scratch(dyn);
-            GETEX(d0, 0);
+            GETEX(d0, 0, 0);
             FDIVS(d1, v0, d0);
             VMOVeS(v0, 0, d1, 0);
             break;
         case 0x5F:
             INST_NAME("MAXSS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
-            GETEX(v1, 0);
+            GETGX(v0, 1);
+            GETEX(v1, 0, 0);
             // MAXSS: if any input is NaN, or Ex[0]>Gx[0], copy Ex[0] -> Gx[0]
+            #if 0
             d0 = fpu_get_scratch(dyn);
             FMAXNMS(d0, v0, v1);    // NaN handling may be slightly different, is that a problem?
             VMOVeS(v0, 0, d0, 0);   // to not erase uper part
+            #else
+            FCMPS(v0, v1);
+            B_NEXT(cGE);    //Greater than or equal
+            VMOVeS(v0, 0, v1, 0);   // to not erase uper part
+            #endif
             break;
             
         case 0x6F:
             INST_NAME("MOVDQU Gx,Ex");// no alignment constraint on NEON here, so same as MOVDQA
             nextop = F8;
             GETG;
-            v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
             if(MODREG) {
-                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3));
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
+                GETGX_empty(v0);
                 VMOVQ(v0, v1);
             } else {
+                GETGX_empty(v0);
                 addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<4, 15, rex, 0, 0);
                 VLDR128_U12(v0, ed, fixedaddress);
             }
@@ -280,9 +311,8 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0x70:
             INST_NAME("PSHUFHW Gx, Ex, Ib");
             nextop = F8;
-            GETEX(v1, 1);
-            GETGX(v0);
-
+            GETEX(v1, 0, 1);
+            GETGX(v0, 1);
             u8 = F8;
             // only high part need to be suffled. VTBL only handle 8bits value, so the 16bits suffles need to be changed in 8bits
             u64 = 0;
@@ -295,18 +325,20 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             VMOVQDfrom(d0, 0, x2);
             VTBL1_8(d0, v1, d0);
             VMOVeD(v0, 1, d0, 0);
+            if(v0!=v1) {
+                VMOVeD(v0, 0, v1, 0);
+            }
             break;
 
         case 0x7E:
             INST_NAME("MOVQ Gx, Ex");
             nextop = F8;
-            GETG;
             if(MODREG) {
-                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3));
-                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3), 0);
+                GETGX_empty(v0);
                 FMOVD(v0, v1);
             } else {
-                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                GETGX_empty(v0);
                 addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<3, 7, rex, 0, 0);
                 VLDR64_U12(v0, ed, fixedaddress);
             }
@@ -314,13 +346,11 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0x7F:
             INST_NAME("MOVDQU Ex,Gx");
             nextop = F8;
-            GETG;
+            GETGX(v0, 0);
             if(MODREG) {
-                v0 = sse_get_reg(dyn, ninst, x1, gd);
                 v1 = sse_get_reg_empty(dyn, ninst, x1, (nextop&7) + (rex.b<<3));
                 VMOVQ(v1, v0);
             } else {
-                v0 = sse_get_reg(dyn, ninst, x1, gd);
                 addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<4, 15, rex, 0, 0);
                 VSTR128_U12(v0, ed, fixedaddress);
             }
@@ -328,11 +358,11 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
 
         case 0xBC:
             INST_NAME("TZCNT Gd, Ed");
-            SETFLAGS(X_CF|X_ZF, SF_SET);
+            SETFLAGS(X_CF|X_ZF, SF_SUBSET);
+            SET_DFNONE(x1);
             nextop = F8;
             GETED(0);
             GETGD;
-            SET_DFNONE(x1);
             TSTxw_REG(ed, ed);
             BFIw(xFlags, x1, F_CF, 1);  // CF = is source 0?
             RBITxw(x1, ed);   // reverse
@@ -341,27 +371,36 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             CSETw(x1, cEQ);
             BFIw(xFlags, x1, F_ZF, 1);  // ZF = is dest 0?
             break;
+        case 0xBD:
+            INST_NAME("LZCNT Gd, Ed");
+            SETFLAGS(X_CF|X_ZF, SF_SUBSET);
+            SET_DFNONE(x1);
+            nextop = F8;
+            GETED(0);
+            GETGD;
+            TSTxw_REG(ed, ed);
+            BFIw(xFlags, x1, F_CF, 1);  // CF = is source 0?
+            CLZxw(gd, x1);    // x2 gets leading 0 == LZCNT
+            TSTxw_REG(gd, gd);
+            CSETw(x1, cEQ);
+            BFIw(xFlags, x1, F_ZF, 1);  // ZF = is dest 0?
+            break;
 
         case 0xC2:
             INST_NAME("CMPSS Gx, Ex, Ib");
             nextop = F8;
-            GETGX(v0);
-            GETEX(v1, 1);
+            GETGX(v0, 1);
+            GETEX(v1, 0, 1);
             u8 = F8;
-            if((u8&7)==6){
-                FCMPS(v1, v0);
-            } else {
-                FCMPS(v0, v1);
-            }
+            FCMPS(v0, v1);
             switch(u8&7) {
                 case 0: CSETMw(x2, cEQ); break;   // Equal
-                case 1: CSETMw(x2, cMI); break;   // Less than
-                case 2: //CSETMw(x2, cLE); break;   // Less or equal (or unordered on ARM64, not on x86...)
-                        CSETMw(x2, cPL); CSINVw(x2, xZR, x2, cEQ); break;   // so use a 2 step here, but 1st test inverted because 2nd step invert again
+                case 1: CSETMw(x2, cCC); break;   // Less than
+                case 2: CSETMw(x2, cLS); break;   // Less or equal
                 case 3: CSETMw(x2, cVS); break;   // NaN
-                case 4: CSETMw(x2, cNE); break;   // Not Equal (or unordered on ARM, not on X86...)
+                case 4: CSETMw(x2, cNE); break;   // Not Equal or unordered
                 case 5: CSETMw(x2, cCS); break;   // Greater or equal or unordered
-                case 6: CSETMw(x2, cLT); break;   // Greater or unordered, test inverted, N!=V so unordereded or less than (inverted)
+                case 6: CSETMw(x2, cHI); break;   // Greater or unordered, test inverted, N!=V so unordered or less than (inverted)
                 case 7: CSETMw(x2, cVC); break;   // not NaN
             }
             VMOVQSfrom(v0, 0, x2);
@@ -372,7 +411,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             nextop = F8;
             GETGX_empty(v0);
             if(MODREG) {
-                v1 = mmx_get_reg(dyn, ninst, x1, (nextop&7));
+                v1 = mmx_get_reg(dyn, ninst, x1, x2, x3, (nextop&7));
                 VEORQ(v0, v0, v0);  // usefull?
                 VMOV(v0, v1);
             } else {
@@ -384,7 +423,14 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
         case 0xE6:
             INST_NAME("CVTDQ2PD Gx, Ex");
             nextop = F8;
-            GETEX(v1, 0);
+            // cannot use GETEX because we want 64bits not 32bits
+            if(MODREG) {
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
+            } else {
+                v1 = fpu_get_scratch(dyn);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<3, 7, rex, 0, 0);
+                VLDR64_U12(v1, ed, fixedaddress);
+            }
             GETGX_empty(v0);
             d0 = fpu_get_scratch(dyn);
             SXTL_32(v0, v1);
@@ -396,4 +442,3 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
     }
     return addr;
 }
-

src/dynarec/arm64/dynarec_arm64_functions.c

@@ -0,0 +1,858 @@
+#define _GNU_SOURCE
+#include <stdio.h>
+#include <stdlib.h>
+#include <pthread.h>
+#include <errno.h>
+#include <string.h>
+#include <math.h>
+#include <signal.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "tools/bridge_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "emu/x87emu_private.h"
+#include "x64trace.h"
+#include "signals.h"
+#include "dynarec_native.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_functions.h"
+#include "custommem.h"
+#include "bridge.h"
+
+void arm_fstp(x64emu_t* emu, void* p)
+{
+    if(ST0.q!=STld(0).uref)
+        D2LD(&ST0.d, p);
+    else
+        memcpy(p, &STld(0).ld, 10);
+}
+
+void arm_print_armreg(x64emu_t* emu, uintptr_t reg, uintptr_t n)
+{
+    (void)emu;
+    dynarec_log(LOG_DEBUG, "R%lu=0x%lx (%lu)\n", n, reg, reg);
+}
+
+void arm_f2xm1(x64emu_t* emu)
+{
+    ST0.d = exp2(ST0.d) - 1.0;
+}
+void arm_fyl2x(x64emu_t* emu)
+{
+    ST(1).d = log2(ST0.d)*ST(1).d;
+}
+void arm_ftan(x64emu_t* emu)
+{
+    ST0.d = tan(ST0.d);
+    emu->sw.f.F87_C2 = 0;
+}
+void arm_fpatan(x64emu_t* emu)
+{
+    ST1.d = atan2(ST1.d, ST0.d);
+}
+void arm_fxtract(x64emu_t* emu)
+{
+    int32_t tmp32s = (ST1.q&0x7ff0000000000000LL)>>52;
+    tmp32s -= 1023;
+    ST1.d /= exp2(tmp32s);
+    ST0.d = tmp32s;
+}
+void arm_fprem(x64emu_t* emu)
+{
+    int32_t tmp32s = ST0.d / ST1.d;
+    ST0.d -= ST1.d * tmp32s;
+    emu->sw.f.F87_C2 = 0;
+    emu->sw.f.F87_C0 = (tmp32s&1);
+    emu->sw.f.F87_C3 = ((tmp32s>>1)&1);
+    emu->sw.f.F87_C1 = ((tmp32s>>2)&1);
+}
+void arm_fyl2xp1(x64emu_t* emu)
+{
+    ST(1).d = log2(ST0.d + 1.0)*ST(1).d;
+}
+void arm_fsincos(x64emu_t* emu)
+{
+    sincos(ST1.d, &ST1.d, &ST0.d);
+    emu->sw.f.F87_C2 = 0;
+}
+void arm_frndint(x64emu_t* emu)
+{
+    ST0.d = fpu_round(emu, ST0.d);
+}
+void arm_fscale(x64emu_t* emu)
+{
+    if(ST0.d!=0.0)
+        ST0.d *= exp2(trunc(ST1.d));
+}
+void arm_fsin(x64emu_t* emu)
+{
+    ST0.d = sin(ST0.d);
+    emu->sw.f.F87_C2 = 0;
+}
+void arm_fcos(x64emu_t* emu)
+{
+    ST0.d = cos(ST0.d);
+    emu->sw.f.F87_C2 = 0;
+}
+
+void arm_fbld(x64emu_t* emu, uint8_t* ed)
+{
+    fpu_fbld(emu, ed);
+}
+
+void arm_fild64(x64emu_t* emu, int64_t* ed)
+{
+    int64_t tmp;
+    memcpy(&tmp, ed, sizeof(tmp));
+    ST0.d = tmp;
+    STll(0).sq = tmp;
+    STll(0).sref = ST0.sq;
+}
+
+void arm_fbstp(x64emu_t* emu, uint8_t* ed)
+{
+    fpu_fbst(emu, ed);
+}
+
+void arm_fistp64(x64emu_t* emu, int64_t* ed)
+{
+    // used of memcpy to avoid aligments issues
+    if(STll(0).sref==ST(0).sq) {
+        memcpy(ed, &STll(0).sq, sizeof(int64_t));
+    } else {
+        int64_t tmp;
+        if(isgreater(ST0.d, (double)(int64_t)0x7fffffffffffffffLL) || isless(ST0.d, (double)(int64_t)0x8000000000000000LL) || !isfinite(ST0.d))
+            tmp = 0x8000000000000000LL;
+        else
+            tmp = fpu_round(emu, ST0.d);
+        memcpy(ed, &tmp, sizeof(tmp));
+    }
+}
+
+void arm_fistt64(x64emu_t* emu, int64_t* ed)
+{
+    // used of memcpy to avoid aligments issues
+    int64_t tmp = ST0.d;
+    memcpy(ed, &tmp, sizeof(tmp));
+}
+
+void arm_fld(x64emu_t* emu, uint8_t* ed)
+{
+    memcpy(&STld(0).ld, ed, 10);
+    LD2D(&STld(0), &ST(0).d);
+    STld(0).uref = ST0.q;
+}
+
+void arm_ud(x64emu_t* emu)
+{
+    emit_signal(emu, SIGILL, (void*)R_RIP, 0);
+}
+
+void arm_fsave(x64emu_t* emu, uint8_t* ed)
+{
+    fpu_savenv(emu, (char*)ed, 0);
+
+    uint8_t* p = ed;
+    p += 28;
+    for (int i=0; i<8; ++i) {
+        LD2D(p, &ST(i).d);
+        p+=10;
+    }
+}
+void arm_frstor(x64emu_t* emu, uint8_t* ed)
+{
+    fpu_loadenv(emu, (char*)ed, 0);
+
+    uint8_t* p = ed;
+    p += 28;
+    for (int i=0; i<8; ++i) {
+        D2LD(&ST(i).d, p);
+        p+=10;
+    }
+
+}
+
+void arm_fprem1(x64emu_t* emu)
+{
+    // simplified version
+    int32_t tmp32s = round(ST0.d / ST1.d);
+    ST0.d -= ST1.d*tmp32s;
+    emu->sw.f.F87_C2 = 0;
+    emu->sw.f.F87_C0 = (tmp32s&1);
+    emu->sw.f.F87_C3 = ((tmp32s>>1)&1);
+    emu->sw.f.F87_C1 = ((tmp32s>>2)&1);
+}
+
+static uint8_t ff_mult(uint8_t a, uint8_t b)
+{
+	int retval = 0;
+
+	for(int i = 0; i < 8; i++) {
+		if((b & 1) == 1) 
+			retval ^= a;
+		
+		if((a & 0x80)) {
+			a <<= 1;
+			a  ^= 0x1b;
+		} else {
+			a <<= 1;
+		}
+		
+		b >>= 1;
+	}
+	
+	return retval;
+}
+
+void arm_aesimc(x64emu_t* emu, int xmm)
+{
+    sse_regs_t eax1 = emu->xmm[xmm];
+
+    for(int j=0; j<4; ++j) {
+        emu->xmm[xmm].ub[0+j*4] = ff_mult(0x0E, eax1.ub[0+j*4]) ^ ff_mult(0x0B, eax1.ub[1+j*4]) ^ ff_mult(0x0D, eax1.ub[2+j*4]) ^ ff_mult(0x09, eax1.ub[3+j*4]);
+        emu->xmm[xmm].ub[1+j*4] = ff_mult(0x09, eax1.ub[0+j*4]) ^ ff_mult(0x0E, eax1.ub[1+j*4]) ^ ff_mult(0x0B, eax1.ub[2+j*4]) ^ ff_mult(0x0D, eax1.ub[3+j*4]);
+        emu->xmm[xmm].ub[2+j*4] = ff_mult(0x0D, eax1.ub[0+j*4]) ^ ff_mult(0x09, eax1.ub[1+j*4]) ^ ff_mult(0x0E, eax1.ub[2+j*4]) ^ ff_mult(0x0B, eax1.ub[3+j*4]);
+        emu->xmm[xmm].ub[3+j*4] = ff_mult(0x0B, eax1.ub[0+j*4]) ^ ff_mult(0x0D, eax1.ub[1+j*4]) ^ ff_mult(0x09, eax1.ub[2+j*4]) ^ ff_mult(0x0E, eax1.ub[3+j*4]);
+    }
+}
+void arm_aesmc(x64emu_t* emu, int xmm)
+{
+    sse_regs_t eax1 = emu->xmm[xmm];
+
+    for(int j=0; j<4; ++j) {
+        emu->xmm[xmm].ub[0+j*4] = ff_mult(0x02, eax1.ub[0+j*4]) ^ ff_mult(0x03, eax1.ub[1+j*4]) ^               eax1.ub[2+j*4]  ^               eax1.ub[3+j*4] ;
+        emu->xmm[xmm].ub[1+j*4] =               eax1.ub[0+j*4]  ^ ff_mult(0x02, eax1.ub[1+j*4]) ^ ff_mult(0x03, eax1.ub[2+j*4]) ^               eax1.ub[3+j*4] ;
+        emu->xmm[xmm].ub[2+j*4] =               eax1.ub[0+j*4]  ^               eax1.ub[1+j*4]  ^ ff_mult(0x02, eax1.ub[2+j*4]) ^ ff_mult(0x03, eax1.ub[3+j*4]);
+        emu->xmm[xmm].ub[3+j*4] = ff_mult(0x03, eax1.ub[0+j*4]) ^               eax1.ub[1+j*4]  ^               eax1.ub[2+j*4]  ^ ff_mult(0x02, eax1.ub[3+j*4]);
+    }
+}
+void arm_aesdlast(x64emu_t* emu, int xmm)
+{
+                            //   A0 B1 C2 D3 E4 F5 G6 H7 I8 J9 Ka Lb Mc Nd Oe Pf
+                            //   A  N  K  H  E  B  O  L  I  F  C  P  M  J  G  D
+    const uint8_t invshiftrows[] = {0,13,10, 7, 4, 1,14,11, 8, 5, 2,15,12, 9, 6, 3};
+    const uint8_t invsubbytes[256] = {
+        0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, 0xf3, 0xd7, 0xfb,
+        0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb,
+        0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e,
+        0x08, 0x2e, 0xa1, 0x66, 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25,
+        0x72, 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, 0xb6, 0x92,
+        0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, 0x57, 0xa7, 0x8d, 0x9d, 0x84,
+        0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06,
+        0xd0, 0x2c, 0x1e, 0x8f, 0xca, 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b,
+        0x3a, 0x91, 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, 0x73,
+        0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, 0x1c, 0x75, 0xdf, 0x6e,
+        0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b,
+        0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4,
+        0x1f, 0xdd, 0xa8, 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f,
+        0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, 0xc9, 0x9c, 0xef,
+        0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61,
+        0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d,
+    };
+
+    sse_regs_t eax1;
+    for(int i=0; i<16; ++i)
+        eax1.ub[i] = emu->xmm[xmm].ub[invshiftrows[i]];
+    //STATE ← InvSubBytes( STATE );
+    for(int i=0; i<16; ++i)
+        emu->xmm[xmm].ub[i] = invsubbytes[eax1.ub[i]];
+
+}
+void arm_aeselast(x64emu_t* emu, int xmm)
+{
+                            //   A0 B1 C2 D3 E4 F5 G6 H7 I8 J9 Ka Lb Mc Nd Oe Pf
+                            //   A  F  K  P  E  J  O  D  I  N  C  H  M  B  G  L
+    const uint8_t shiftrows[] = {0, 5,10,15, 4, 9,14, 3, 8,13, 2, 7,12, 1, 6,11};
+    const uint8_t subbytes[256] = {
+        0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
+        0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
+        0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
+        0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
+        0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
+        0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
+        0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
+        0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
+        0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
+        0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
+        0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
+        0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
+        0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
+        0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
+        0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
+        0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16,
+    };
+
+    sse_regs_t eax1;
+    for(int i=0; i<16; ++i)
+        eax1.ub[i] = emu->xmm[xmm].ub[shiftrows[i]];
+    //STATE ← SubBytes( STATE );
+    for(int i=0; i<16; ++i)
+        emu->xmm[xmm].ub[i] = subbytes[eax1.ub[i]];
+}
+void arm_aesd(x64emu_t* emu, int xmm)
+{
+    arm_aesdlast(emu, xmm);
+    arm_aesimc(emu, xmm);
+}
+void arm_aese(x64emu_t* emu, int xmm)
+{
+    arm_aeselast(emu, xmm);
+    arm_aesmc(emu, xmm);
+}
+
+
+#define XMM0    0
+#define XMM8    16
+#define X870    8
+#define EMM0    8
+#define SCRATCH0    24
+
+// Get a FPU scratch reg
+int fpu_get_scratch(dynarec_arm_t* dyn)
+{
+    return SCRATCH0 + dyn->n.fpu_scratch++;  // return an Sx
+}
+// Reset scratch regs counter
+void fpu_reset_scratch(dynarec_arm_t* dyn)
+{
+    dyn->n.fpu_scratch = 0;
+}
+// Get a x87 double reg
+int fpu_get_reg_x87(dynarec_arm_t* dyn, int t, int n)
+{
+    int i=X870;
+    while (dyn->n.fpuused[i]) ++i;
+    dyn->n.fpuused[i] = 1;
+    dyn->n.neoncache[i].n = n;
+    dyn->n.neoncache[i].t = t;
+    dyn->n.news |= (1<<i);
+    return i; // return a Dx
+}
+// Free a FPU double reg
+void fpu_free_reg(dynarec_arm_t* dyn, int reg)
+{
+    // TODO: check upper limit?
+    dyn->n.fpuused[reg] = 0;
+    if(dyn->n.neoncache[reg].t!=NEON_CACHE_ST_F && dyn->n.neoncache[reg].t!=NEON_CACHE_ST_D)
+        dyn->n.neoncache[reg].v = 0;
+}
+// Get an MMX double reg
+int fpu_get_reg_emm(dynarec_arm_t* dyn, int emm)
+{
+    dyn->n.fpuused[EMM0 + emm] = 1;
+    dyn->n.neoncache[EMM0 + emm].t = NEON_CACHE_MM;
+    dyn->n.neoncache[EMM0 + emm].n = emm;
+    return EMM0 + emm;
+}
+// Get an XMM quad reg
+int fpu_get_reg_xmm(dynarec_arm_t* dyn, int t, int xmm)
+{
+    int i;
+    if(xmm>7) {
+        i = XMM8 + xmm - 8;
+    } else {
+        i = XMM0 + xmm;
+    }
+    dyn->n.fpuused[i] = 1;
+    dyn->n.neoncache[i].t = t;
+    dyn->n.neoncache[i].n = xmm;
+    return i;
+}
+// Reset fpu regs counter
+void fpu_reset_reg(dynarec_arm_t* dyn)
+{
+    dyn->n.fpu_reg = 0;
+    for (int i=0; i<24; ++i) {
+        dyn->n.fpuused[i]=0;
+        dyn->n.neoncache[i].v = 0;
+    }
+
+}
+
+int neoncache_get_st(dynarec_arm_t* dyn, int ninst, int a)
+{
+    if (dyn->insts[ninst].n.swapped) {
+        if(dyn->insts[ninst].n.combined1 == a)
+            a = dyn->insts[ninst].n.combined2;
+        else if(dyn->insts[ninst].n.combined2 == a)
+            a = dyn->insts[ninst].n.combined1;
+    }
+    for(int i=0; i<24; ++i)
+        if((dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F
+         || dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_D)
+         && dyn->insts[ninst].n.neoncache[i].n==a)
+            return dyn->insts[ninst].n.neoncache[i].t;
+    // not in the cache yet, so will be fetched...
+    return NEON_CACHE_ST_D;
+}
+
+int neoncache_get_current_st(dynarec_arm_t* dyn, int ninst, int a)
+{
+    (void)ninst;
+    if(!dyn->insts)
+        return NEON_CACHE_ST_D;
+    for(int i=0; i<24; ++i)
+        if((dyn->n.neoncache[i].t==NEON_CACHE_ST_F
+         || dyn->n.neoncache[i].t==NEON_CACHE_ST_D)
+         && dyn->n.neoncache[i].n==a)
+            return dyn->n.neoncache[i].t;
+    // not in the cache yet, so will be fetched...
+    return NEON_CACHE_ST_D;
+}
+
+int neoncache_get_st_f(dynarec_arm_t* dyn, int ninst, int a)
+{
+    /*if(a+dyn->insts[ninst].n.stack_next-st<0)
+        // The STx has been pushed at the end of instructon, so stop going back
+        return -1;*/
+    for(int i=0; i<24; ++i)
+        if(dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F
+         && dyn->insts[ninst].n.neoncache[i].n==a)
+            return i;
+    return -1;
+} 
+int neoncache_get_st_f_noback(dynarec_arm_t* dyn, int ninst, int a)
+{
+    for(int i=0; i<24; ++i)
+        if(dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F
+         && dyn->insts[ninst].n.neoncache[i].n==a)
+            return i;
+    return -1;
+} 
+int neoncache_get_current_st_f(dynarec_arm_t* dyn, int a)
+{
+    for(int i=0; i<24; ++i)
+        if(dyn->n.neoncache[i].t==NEON_CACHE_ST_F
+         && dyn->n.neoncache[i].n==a)
+            return i;
+    return -1;
+} 
+static void neoncache_promote_double_forward(dynarec_arm_t* dyn, int ninst, int maxinst, int a);
+static void neoncache_promote_double_internal(dynarec_arm_t* dyn, int ninst, int maxinst, int a);
+static void neoncache_promote_double_combined(dynarec_arm_t* dyn, int ninst, int maxinst, int a)
+{
+    if(a == dyn->insts[ninst].n.combined1 || a == dyn->insts[ninst].n.combined2) {
+        if(a == dyn->insts[ninst].n.combined1) {
+            a = dyn->insts[ninst].n.combined2;
+        } else 
+            a = dyn->insts[ninst].n.combined1;
+        int i = neoncache_get_st_f_noback(dyn, ninst, a);
+        //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double_combined, ninst=%d combined%c %d i=%d (stack:%d/%d)\n", ninst, (a == dyn->insts[ninst].n.combined2)?'2':'1', a ,i, dyn->insts[ninst].n.stack_push, -dyn->insts[ninst].n.stack_pop);
+        if(i>=0) {
+            dyn->insts[ninst].n.neoncache[i].t = NEON_CACHE_ST_D;
+            if(!dyn->insts[ninst].n.barrier)
+                neoncache_promote_double_internal(dyn, ninst-1, maxinst, a-dyn->insts[ninst].n.stack_push);
+            // go forward is combined is not pop'd
+            if(a-dyn->insts[ninst].n.stack_pop>=0)
+                if(!dyn->insts[ninst+1].n.barrier)
+                    neoncache_promote_double_forward(dyn, ninst+1, maxinst, a-dyn->insts[ninst].n.stack_pop);
+        }
+    }
+}
+static void neoncache_promote_double_internal(dynarec_arm_t* dyn, int ninst, int maxinst, int a)
+{
+    if(dyn->insts[ninst+1].n.barrier)
+        return;
+    while(ninst>=0) {
+        a+=dyn->insts[ninst].n.stack_pop;    // adjust Stack depth: add pop'd ST (going backward)
+        int i = neoncache_get_st_f(dyn, ninst, a);
+        //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double_internal, ninst=%d, a=%d st=%d:%d, i=%d\n", ninst, a, dyn->insts[ninst].n.stack, dyn->insts[ninst].n.stack_next, i);
+        if(i<0) return;
+        dyn->insts[ninst].n.neoncache[i].t = NEON_CACHE_ST_D;
+        // check combined propagation too
+        if(dyn->insts[ninst].n.combined1 || dyn->insts[ninst].n.combined2) {
+            if(dyn->insts[ninst].n.swapped) {
+                //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double_internal, ninst=%d swapped %d/%d vs %d with st %d\n", ninst, dyn->insts[ninst].n.combined1 ,dyn->insts[ninst].n.combined2, a, dyn->insts[ninst].n.stack);
+                if (a==dyn->insts[ninst].n.combined1)
+                    a = dyn->insts[ninst].n.combined2;
+                else if (a==dyn->insts[ninst].n.combined2)
+                    a = dyn->insts[ninst].n.combined1;
+            } else {
+                //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double_internal, ninst=%d combined %d/%d vs %d with st %d\n", ninst, dyn->insts[ninst].n.combined1 ,dyn->insts[ninst].n.combined2, a, dyn->insts[ninst].n.stack);
+                neoncache_promote_double_combined(dyn, ninst, maxinst, a);
+            }
+        }
+        a-=dyn->insts[ninst].n.stack_push;  // // adjust Stack depth: remove push'd ST (going backward)
+        --ninst;
+        if(ninst<0 || a<0 || dyn->insts[ninst].n.barrier)
+            return;
+    }
+}
+
+static void neoncache_promote_double_forward(dynarec_arm_t* dyn, int ninst, int maxinst, int a)
+{
+    while((ninst!=-1) && (ninst<maxinst) && (a>=0)) {
+        a+=dyn->insts[ninst].n.stack_push;  // // adjust Stack depth: add push'd ST (going forward)
+        if((dyn->insts[ninst].n.combined1 || dyn->insts[ninst].n.combined2) && dyn->insts[ninst].n.swapped) {
+            //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double_forward, ninst=%d swapped %d/%d vs %d with st %d\n", ninst, dyn->insts[ninst].n.combined1 ,dyn->insts[ninst].n.combined2, a, dyn->insts[ninst].n.stack);
+            if (a==dyn->insts[ninst].n.combined1)
+                a = dyn->insts[ninst].n.combined2;
+            else if (a==dyn->insts[ninst].n.combined2)
+                a = dyn->insts[ninst].n.combined1;
+        }
+        int i = neoncache_get_st_f_noback(dyn, ninst, a);
+        //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double_forward, ninst=%d, a=%d st=%d:%d(%d/%d), i=%d\n", ninst, a, dyn->insts[ninst].n.stack, dyn->insts[ninst].n.stack_next, dyn->insts[ninst].n.stack_push, -dyn->insts[ninst].n.stack_pop, i);
+        if(i<0) return;
+        dyn->insts[ninst].n.neoncache[i].t = NEON_CACHE_ST_D;
+        // check combined propagation too
+        if((dyn->insts[ninst].n.combined1 || dyn->insts[ninst].n.combined2) && !dyn->insts[ninst].n.swapped) {
+            //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double_forward, ninst=%d combined %d/%d vs %d with st %d\n", ninst, dyn->insts[ninst].n.combined1 ,dyn->insts[ninst].n.combined2, a, dyn->insts[ninst].n.stack);
+            neoncache_promote_double_combined(dyn, ninst, maxinst, a);
+        }
+        a-=dyn->insts[ninst].n.stack_pop;    // adjust Stack depth: remove pop'd ST (going forward)
+        if(dyn->insts[ninst].x64.has_next && !dyn->insts[ninst].n.barrier)
+            ++ninst;
+        else
+            ninst=-1;
+    }
+    if(ninst==maxinst)
+        neoncache_promote_double(dyn, ninst, a);
+}
+
+void neoncache_promote_double(dynarec_arm_t* dyn, int ninst, int a)
+{
+    int i = neoncache_get_current_st_f(dyn, a);
+    //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double, ninst=%d a=%d st=%d i=%d\n", ninst, a, dyn->n.stack, i);
+    if(i<0) return;
+    dyn->n.neoncache[i].t = NEON_CACHE_ST_D;
+    dyn->insts[ninst].n.neoncache[i].t = NEON_CACHE_ST_D;
+    // check combined propagation too
+    if(dyn->n.combined1 || dyn->n.combined2) {
+        if(dyn->n.swapped) {
+            //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double, ninst=%d swapped! %d/%d vs %d\n", ninst, dyn->n.combined1 ,dyn->n.combined2, a);
+            if(dyn->n.combined1 == a)
+                a = dyn->n.combined2;
+            else if(dyn->n.combined2 == a)
+                a = dyn->n.combined1;
+        } else {
+            //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double, ninst=%d combined! %d/%d vs %d\n", ninst, dyn->n.combined1 ,dyn->n.combined2, a);
+            if(dyn->n.combined1 == a)
+                neoncache_promote_double(dyn, ninst, dyn->n.combined2);
+            else if(dyn->n.combined2 == a)
+                neoncache_promote_double(dyn, ninst, dyn->n.combined1);
+        }
+    }
+    a-=dyn->insts[ninst].n.stack_push;  // // adjust Stack depth: remove push'd ST (going backward)
+    if(!ninst || a<0) return;
+    neoncache_promote_double_internal(dyn, ninst-1, ninst, a);
+}
+
+int neoncache_combine_st(dynarec_arm_t* dyn, int ninst, int a, int b)
+{
+    dyn->n.combined1=a;
+    dyn->n.combined2=b;
+    if( neoncache_get_current_st(dyn, ninst, a)==NEON_CACHE_ST_F
+     && neoncache_get_current_st(dyn, ninst, b)==NEON_CACHE_ST_F )
+        return NEON_CACHE_ST_F;
+    return NEON_CACHE_ST_D;
+}
+
+int isPred(dynarec_arm_t* dyn, int ninst, int pred) {
+    for(int i=0; i<dyn->insts[ninst].pred_sz; ++i)
+        if(dyn->insts[ninst].pred[i]==pred)
+            return pred;
+    return -1;
+}
+int getNominalPred(dynarec_arm_t* dyn, int ninst) {
+    if((ninst<=0) || !dyn->insts[ninst].pred_sz)
+        return -1;
+    if(isPred(dyn, ninst, ninst-1)!=-1)
+        return ninst-1;
+    return dyn->insts[ninst].pred[0];
+}
+
+int isCacheEmpty(dynarec_arm_t* dyn, int ninst) {
+    if(dyn->insts[ninst].n.stack_next) {
+        return 0;
+    }
+    for(int i=0; i<24; ++i)
+        if(dyn->insts[ninst].n.neoncache[i].v) {       // there is something at ninst for i
+            if(!(
+            (dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F || dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_D)
+            && dyn->insts[ninst].n.neoncache[i].n<dyn->insts[ninst].n.stack_pop))
+                return 0;
+        }
+    return 1;
+
+}
+
+int fpuCacheNeedsTransform(dynarec_arm_t* dyn, int ninst) {
+    int i2 = dyn->insts[ninst].x64.jmp_insts;
+    if(i2<0)
+        return 1;
+    if((dyn->insts[i2].x64.barrier&BARRIER_FLOAT))
+        // if the barrier as already been apply, no transform needed
+        return ((dyn->insts[ninst].x64.barrier&BARRIER_FLOAT))?0:(isCacheEmpty(dyn, ninst)?0:1);
+    int ret = 0;
+    if(!i2) { // just purge
+        if(dyn->insts[ninst].n.stack_next) {
+            return 1;
+        }
+        for(int i=0; i<24 && !ret; ++i)
+            if(dyn->insts[ninst].n.neoncache[i].v) {       // there is something at ninst for i
+                if(!(
+                (dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F || dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_D)
+                && dyn->insts[ninst].n.neoncache[i].n<dyn->insts[ninst].n.stack_pop))
+                    ret = 1;
+            }
+        return ret;
+    }
+    // Check if ninst can be compatible to i2
+    if(dyn->insts[ninst].n.stack_next != dyn->insts[i2].n.stack-dyn->insts[i2].n.stack_push) {
+        return 1;
+    }
+    neoncache_t cache_i2 = dyn->insts[i2].n;
+    neoncacheUnwind(&cache_i2);
+
+    for(int i=0; i<24; ++i) {
+        if(dyn->insts[ninst].n.neoncache[i].v) {       // there is something at ninst for i
+            if(!cache_i2.neoncache[i].v) {    // but there is nothing at i2 for i
+                ret = 1;
+            } else if(dyn->insts[ninst].n.neoncache[i].v!=cache_i2.neoncache[i].v) {  // there is something different
+                if(dyn->insts[ninst].n.neoncache[i].n!=cache_i2.neoncache[i].n) {   // not the same x64 reg
+                    ret = 1;
+                }
+                else if(dyn->insts[ninst].n.neoncache[i].t == NEON_CACHE_XMMR && cache_i2.neoncache[i].t == NEON_CACHE_XMMW)
+                    {/* nothing */ }
+                else
+                    ret = 1;
+            }
+        } else if(cache_i2.neoncache[i].v)
+            ret = 1;
+    }
+    return ret;
+}
+
+void neoncacheUnwind(neoncache_t* cache)
+{
+    if(cache->swapped) {
+        // unswap
+        int a = -1; 
+        int b = -1;
+        for(int j=0; j<24 && ((a==-1) || (b==-1)); ++j)
+            if((cache->neoncache[j].t == NEON_CACHE_ST_D || cache->neoncache[j].t == NEON_CACHE_ST_F)) {
+                if(cache->neoncache[j].n == cache->combined1)
+                    a = j;
+                else if(cache->neoncache[j].n == cache->combined2)
+                    b = j;
+            }
+        if(a!=-1 && b!=-1) {
+            int tmp = cache->neoncache[a].n;
+            cache->neoncache[a].n = cache->neoncache[b].n;
+            cache->neoncache[b].n = tmp;
+        }
+        cache->swapped = 0;
+        cache->combined1 = cache->combined2 = 0;
+    }
+    if(cache->news) {
+        // reove the newly created neoncache
+        for(int i=0; i<24; ++i)
+            if(cache->news&(1<<i))
+                cache->neoncache[i].v = 0;
+        cache->news = 0;
+    }
+    if(cache->stack_push) {
+        // unpush
+        for(int j=0; j<24; ++j) {
+            if((cache->neoncache[j].t == NEON_CACHE_ST_D || cache->neoncache[j].t == NEON_CACHE_ST_F)) {
+                if(cache->neoncache[j].n<cache->stack_push)
+                    cache->neoncache[j].v = 0;
+                else
+                    cache->neoncache[j].n-=cache->stack_push;
+            }
+        }
+        cache->x87stack-=cache->stack_push;
+        cache->stack-=cache->stack_push;
+        cache->stack_push = 0;
+    }
+    cache->x87stack+=cache->stack_pop;
+    cache->stack_next = cache->stack;
+    cache->stack_pop = 0;
+    cache->barrier = 0;
+    // And now, rebuild the x87cache info with neoncache
+    cache->mmxcount = 0;
+    cache->fpu_scratch = 0;
+    cache->fpu_extra_qscratch = 0;
+    cache->fpu_reg = 0;
+    for(int i=0; i<8; ++i) {
+        cache->x87cache[i] = -1;
+        cache->mmxcache[i] = -1;
+        cache->x87reg[i] = 0;
+        cache->ssecache[i*2].v = -1;
+        cache->ssecache[i*2+1].v = -1;
+    }
+    int x87reg = 0;
+    for(int i=0; i<24; ++i) {
+        if(cache->neoncache[i].v) {
+            cache->fpuused[i] = 1;
+            switch (cache->neoncache[i].t) {
+                case NEON_CACHE_MM:
+                    cache->mmxcache[cache->neoncache[i].n] = i;
+                    ++cache->mmxcount;
+                    ++cache->fpu_reg;
+                    break;
+                case NEON_CACHE_XMMR:
+                case NEON_CACHE_XMMW:
+                    cache->ssecache[cache->neoncache[i].n].reg = i;
+                    cache->ssecache[cache->neoncache[i].n].write = (cache->neoncache[i].t==NEON_CACHE_XMMW)?1:0;
+                    ++cache->fpu_reg;
+                    break;
+                case NEON_CACHE_ST_F:
+                case NEON_CACHE_ST_D:
+                    cache->x87cache[x87reg] = cache->neoncache[i].n;
+                    cache->x87reg[x87reg] = i;
+                    ++x87reg;
+                    ++cache->fpu_reg;
+                    break;
+                case NEON_CACHE_SCR:
+                    cache->fpuused[i] = 0;
+                    cache->neoncache[i].v = 0;
+                    break;
+            }
+        } else {
+            cache->fpuused[i] = 0;
+        }
+    }
+}
+
+#define F8      *(uint8_t*)(addr++)
+#define F32     *(uint32_t*)(addr+=4, addr-4)
+#define F32S64  (uint64_t)(int64_t)*(int32_t*)(addr+=4, addr-4)
+// Get if ED will have the correct parity. Not emiting anything. Parity is 2 for DWORD or 3 for QWORD
+int getedparity(dynarec_arm_t* dyn, int ninst, uintptr_t addr, uint8_t nextop, int parity, int delta)
+{
+    (void)dyn; (void)ninst;
+
+    uint32_t tested = (1<<parity)-1;
+    if((nextop&0xC0)==0xC0)
+        return 0;   // direct register, no parity...
+    if(!(nextop&0xC0)) {
+        if((nextop&7)==4) {
+            uint8_t sib = F8;
+            int sib_reg = (sib>>3)&7;
+            if((sib&0x7)==5) {
+                uint64_t tmp = F32S64;
+                if (sib_reg!=4) {
+                    // if XXXXXX+reg<<N then check parity of XXXXX and N should be enough
+                    return ((tmp&tested)==0 && (sib>>6)>=parity)?1:0;
+                } else {
+                    // just a constant...
+                    return (tmp&tested)?0:1;
+                }
+            } else {
+                if(sib_reg==4 && parity<3)
+                    return 0;   // simple [reg]
+                // don't try [reg1 + reg2<<N], unless reg1 is ESP
+                return ((sib&0x7)==4 && (sib>>6)>=parity)?1:0;
+            }
+        } else if((nextop&7)==5) {
+            uint64_t tmp = F32S64;
+            tmp+=addr+delta;
+            return (tmp&tested)?0:1;
+        } else {
+            return 0;
+        }
+    } else {
+        return 0; //Form [reg1 + reg2<<N + XXXXXX]
+    }
+}
+
+// Do the GETED, but don't emit anything...
+uintptr_t fakeed(dynarec_arm_t* dyn, uintptr_t addr, int ninst, uint8_t nextop) 
+{
+    (void)dyn; (void)addr; (void)ninst;
+
+    if((nextop&0xC0)==0xC0)
+        return addr;
+    if(!(nextop&0xC0)) {
+        if((nextop&7)==4) {
+            uint8_t sib = F8;
+            if((sib&0x7)==5) {
+                addr+=4;
+            }
+        } else if((nextop&7)==5) {
+            addr+=4;
+        }
+    } else {
+        if((nextop&7)==4) {
+            ++addr;
+        }
+        if(nextop&0x80) {
+            addr+=4;
+        } else {
+            ++addr;
+        }
+    }
+    return addr;
+}
+#undef F8
+#undef F32
+
+int isNativeCall(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t* calladdress, int* retn)
+{
+    (void)dyn;
+
+#define PK(a)       *(uint8_t*)(addr+a)
+#define PK32(a)     *(int32_t*)(addr+a)
+
+    if(!addr || !getProtection(addr))
+        return 0;
+    if(PK(0)==0xff && PK(1)==0x25) {            // "absolute" jump, maybe the GOT (well, RIP relative in fact)
+        uintptr_t a1 = addr + 6 + (PK32(2));    // need to add a check to see if the address is from the GOT !
+        addr = (uintptr_t)getAlternate(*(void**)a1);
+    }
+    if(!addr || !getProtection(addr))
+        return 0;
+    onebridge_t *b = (onebridge_t*)(addr);
+    if(b->CC==0xCC && b->S=='S' && b->C=='C' && b->w!=(wrapper_t)0 && b->f!=(uintptr_t)PltResolver) {
+        // found !
+        if(retn) *retn = (b->C3==0xC2)?b->N:0;
+        if(calladdress) *calladdress = addr+1;
+        return 1;
+    }
+    return 0;
+#undef PK32
+#undef PK
+}
+
+const char* getCacheName(int t, int n)
+{
+    static char buff[20];
+    switch(t) {
+        case NEON_CACHE_ST_D: sprintf(buff, "ST%d", n); break;
+        case NEON_CACHE_ST_F: sprintf(buff, "st%d", n); break;
+        case NEON_CACHE_MM: sprintf(buff, "MM%d", n); break;
+        case NEON_CACHE_XMMW: sprintf(buff, "XMM%d", n); break;
+        case NEON_CACHE_XMMR: sprintf(buff, "xmm%d", n); break;
+        case NEON_CACHE_SCR: sprintf(buff, "Scratch"); break;
+        case NEON_CACHE_NONE: buff[0]='\0'; break;
+    }
+    return buff;
+}
+
+// is inst clean for a son branch?
+int isInstClean(dynarec_arm_t* dyn, int ninst)
+{
+    // check flags cache
+    if(dyn->insts[ninst].f_entry.dfnone || dyn->insts[ninst].f_entry.pending)
+        return 0;
+    if(dyn->insts[ninst].x64.state_flags)
+        return 0;
+    // check neoncache
+    neoncache_t* n = &dyn->insts[ninst].n;
+    if(n->news || n->stack || n->stack_next)
+        return 0;
+    for(int i=0; i<24; ++i)
+        if(n->neoncache[i].v)
+            return 0;
+    return 1;
+}

src/dynarec/arm64/dynarec_arm64_functions.h

@@ -29,6 +29,13 @@ void arm_fsave(x64emu_t* emu, uint8_t* ed);
 void arm_frstor(x64emu_t* emu, uint8_t* ed);
 void arm_fprem1(x64emu_t* emu);
 
+void arm_aesd(x64emu_t* emu, int xmm);
+void arm_aese(x64emu_t* emu, int xmm);
+void arm_aesdlast(x64emu_t* emu, int xmm);
+void arm_aeselast(x64emu_t* emu, int xmm);
+void arm_aesimc(x64emu_t* emu, int xmm);
+
+
 void arm_ud(x64emu_t* emu);
 
 // Get an FPU scratch reg
@@ -36,16 +43,43 @@ int fpu_get_scratch(dynarec_arm_t* dyn);
 // Reset scratch regs counter
 void fpu_reset_scratch(dynarec_arm_t* dyn);
 // Get an x87 double reg
-int fpu_get_reg_x87(dynarec_arm_t* dyn);
+int fpu_get_reg_x87(dynarec_arm_t* dyn, int t, int n);
 // Get an MMX double reg
 int fpu_get_reg_emm(dynarec_arm_t* dyn, int emm);
 // Get an XMM quad reg
-int fpu_get_reg_xmm(dynarec_arm_t* dyn, int xmm);
+int fpu_get_reg_xmm(dynarec_arm_t* dyn, int t, int xmm);
 // Free a FPU/MMX/XMM reg
 void fpu_free_reg(dynarec_arm_t* dyn, int reg);
 // Reset fpu regs counter
 void fpu_reset_reg(dynarec_arm_t* dyn);
 
+// ---- Neon cache functions
+// Get type for STx
+int neoncache_get_st(dynarec_arm_t* dyn, int ninst, int a);
+// Get if STx is FLOAT or DOUBLE
+int neoncache_get_st_f(dynarec_arm_t* dyn, int ninst, int a);
+// Get actual type for STx
+int neoncache_get_current_st(dynarec_arm_t* dyn, int ninst, int a);
+// Get actual STx is FLOAT or DOUBLE
+int neoncache_get_current_st_f(dynarec_arm_t* dyn, int a);
+// Back-propagate a change float->double
+void neoncache_promote_double(dynarec_arm_t* dyn, int ninst, int a);
+// Combine and propagate if needed (pass 1 only)
+int neoncache_combine_st(dynarec_arm_t* dyn, int ninst, int a, int b);  // with stack current dyn->n_stack*
+
+// FPU Cache transformation (for loops)
+int fpuCacheNeedsTransform(dynarec_arm_t* dyn, int i1);
+
+// Undo the changes of a neoncache to get the status before the instruction
+void neoncacheUnwind(neoncache_t* cache);
+
+// is inst clean for a son branch?
+int isInstClean(dynarec_arm_t* dyn, int ninst);
+
+// predecessor access
+int isPred(dynarec_arm_t* dyn, int ninst, int pred);
+int getNominalPred(dynarec_arm_t* dyn, int ninst);
+
 // Get if ED will have the correct parity. Not emiting anything. Parity is 2 for DWORD or 3 for QWORD
 int getedparity(dynarec_arm_t* dyn, int ninst, uintptr_t addr, uint8_t nextop, int parity, int delta);
 // Do the GETED, but don't emit anything...
@@ -54,4 +88,6 @@ uintptr_t fakeed(dynarec_arm_t* dyn, uintptr_t addr, int ninst, uint8_t nextop);
 // Is what pointed at addr a native call? And if yes, to what function?
 int isNativeCall(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t* calladdress, int* retn);
 
+const char* getCacheName(int t, int n);
+
 #endif //__DYNAREC_ARM_FUNCTIONS_H__

src/dynarec/arm64/dynarec_arm64_helper.h

@@ -47,7 +47,7 @@
                     ed = xRAX+(nextop&7)+(rex.b<<3);    \
                     wback = 0;                          \
                 } else {                                \
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0xfff<<3, 3, rex, 0, D); \
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0xfff<<3, 7, rex, 0, D); \
                     LDRx_U12(x1, wback, fixedaddress);  \
                     ed = x1;                            \
                 }
@@ -55,10 +55,38 @@
                     ed = xEAX+(nextop&7)+(rex.b<<3);    \
                     wback = 0;                          \
                 } else {                                \
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0xfff<<2, 2, rex, 0, D); \
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, D); \
                     LDRw_U12(x1, wback, fixedaddress);  \
                     ed = x1;                            \
                 }
+#define GETSEDw(D)  if((nextop&0xC0)==0xC0) {           \
+                    ed = xRAX+(nextop&7)+(rex.b<<3);    \
+                    SXTWx(x1, ed);                      \
+                    wb = x1;                            \
+                    wback = 0;                          \
+                } else {                                \
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, D); \
+                    LDRSW_U12(x1, wback, fixedaddress); \
+                    wb = ed = x1;                       \
+                }
+#define GETED32(D)  if(MODREG) {                        \
+                    ed = xRAX+(nextop&7)+(rex.b<<3);    \
+                    wback = 0;                          \
+                } else {                                \
+                    addr = geted32(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, 0, D); \
+                    LDRxw_U12(x1, wback, fixedaddress); \
+                    ed = x1;                            \
+                }
+#define GETSED32w(D)  if((nextop&0xC0)==0xC0) {         \
+                    ed = xRAX+(nextop&7)+(rex.b<<3);    \
+                    SXTWx(x1, ed);                      \
+                    wb = x1;                            \
+                    wback = 0;                          \
+                } else {                                \
+                    addr = geted32(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, D); \
+                    LDRSW_U12(x1, wback, fixedaddress); \
+                    wb = ed = x1;                       \
+                }
 //GETEDH can use hint for ed, and r1 or r2 for wback (depending on hint). wback is 0 if ed is xEAX..xEDI
 #define GETEDH(hint, D) if(MODREG) {                    \
                     ed = xRAX+(nextop&7)+(rex.b<<3);    \
@@ -68,8 +96,16 @@
                     LDRxw_U12(hint, wback, fixedaddress); \
                     ed = hint;                            \
                 }
+#define GETED32H(hint, D) if(MODREG) {                  \
+                    ed = xRAX+(nextop&7)+(rex.b<<3);    \
+                    wback = 0;                          \
+                } else {                                \
+                    addr = geted32(dyn, addr, ninst, nextop, &wback, (hint==x2)?x1:x2, &fixedaddress, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, 0, D); \
+                    LDRxw_U12(hint, wback, fixedaddress); \
+                    ed = hint;                            \
+                }
 //GETEDW can use hint for wback and ret for ed. wback is 0 if ed is xEAX..xEDI
-#define GETEDW(hint, ret, D)   if(MODREG) {              \
+#define GETEDW(hint, ret, D)   if(MODREG) {             \
                     ed = xRAX+(nextop&7)+(rex.b<<3);    \
                     MOVxw_REG(ret, ed);                 \
                     wback = 0;                          \
@@ -78,6 +114,15 @@
                     ed = ret;                           \
                     LDRxw_U12(ed, wback, fixedaddress); \
                 }
+#define GETED32W(hint, ret, D)   if(MODREG) {           \
+                    ed = xRAX+(nextop&7)+(rex.b<<3);    \
+                    MOVxw_REG(ret, ed);                 \
+                    wback = 0;                          \
+                } else {                                \
+                    addr = geted32(dyn, addr, ninst, nextop, &wback, hint, &fixedaddress, 0xfff<<(2+rex.w), (1<<(2+rex.w))-1, rex, 0, D); \
+                    ed = ret;                           \
+                    LDRxw_U12(ed, wback, fixedaddress); \
+                }
 // Write back ed in wback (if wback not 0)
 #define WBACK       if(wback) {STRxw_U12(ed, wback, fixedaddress);}
 // Write back ed in wback (if wback not 0)
@@ -96,6 +141,25 @@
                     ed = x1;                            \
                 }
 #define WBACKO(O)   if(wback) {STRxw_REG(ed, wback, O);}
+//GETEDOx can use r1 for ed, and r2 for wback. wback is 0 if ed is xEAX..xEDI
+#define GETEDOx(O, D)  if(MODREG) {                     \
+                    ed = xRAX+(nextop&7)+(rex.b<<3);    \
+                    wback = 0;                          \
+                } else {                                \
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, D); \
+                    LDRx_REG(x1, wback, O);             \
+                    ed = x1;                            \
+                }
+#define GETSEDOw(O, D)  if((nextop&0xC0)==0xC0) {       \
+                    ed = xRAX+(nextop&7)+(rex.b<<3);    \
+                    SXTWx(x1, ed);                      \
+                    wb = x1;                            \
+                    wback = 0;                          \
+                } else {                                \
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, D); \
+                    LDRSW_REG(x1, wback, O);            \
+                    wb = ed = x1;                       \
+                }
 //FAKEELike GETED, but doesn't get anything
 #define FAKEED  if(!MODREG) {   \
                     addr = fakeed(dyn, addr, ninst, nextop); \
@@ -166,19 +230,25 @@
                     ed = i;                     \
                 }
 //GETEBO will use i for ed, i is also Offset, and can use r3 for wback.
-#define GETEBO(i) if((nextop&0xC0)==0xC0) {  \
-                    wback = (nextop&7);     \
-                    wb2 = (wback>>2);       \
-                    wback = xEAX+(wback&3); \
-                    UBFXx(i, wback, wb2, 8);\
-                    wb1 = 0;                \
-                    ed = i;                 \
-                } else {                    \
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0); \
-                    ADD_REG_LSL_IMM5(wback, wback, i, 0);   \
-                    LDRB_IMM9(i, wback, fixedaddress);      \
-                    wb1 = 1;                \
-                    ed = i;                 \
+#define GETEBO(i, D) if(MODREG) {               \
+                    if(rex.rex) {               \
+                        wback = xRAX+(nextop&7)+(rex.b<<3);     \
+                        wb2 = 0;                \
+                    } else {                    \
+                        wback = (nextop&7);     \
+                        wb2 = (wback>>2)*8;     \
+                        wback = xRAX+(wback&3); \
+                    }                           \
+                    UBFXx(i, wback, wb2, 8);    \
+                    wb1 = 0;                    \
+                    ed = i;                     \
+                } else {                        \
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0, rex, 0, D); \
+                    ADDx_REG(x3, wback, i);     \
+                    if(wback!=x3) wback = x3;   \
+                    LDRB_U12(i, wback, fixedaddress);      \
+                    wb1 = 1;                    \
+                    ed = i;                     \
                 }
 //GETSEB sign extend EB, will use i for ed, and can use r3 for wback.
 #define GETSEB(i, D) if(MODREG) {                \
@@ -243,121 +313,145 @@
 // R0 will not be pushed/popd if ret is -2. Flags are not save/restored
 #define CALL_S(F, ret) call_c(dyn, ninst, F, x7, ret, 0, 0)
 
-#define MARK    if(dyn->insts) {dyn->insts[ninst].mark = (uintptr_t)dyn->arm_size;}
-#define GETMARK ((dyn->insts)?dyn->insts[ninst].mark:(dyn->arm_size+4))
-#define MARK2   if(dyn->insts) {dyn->insts[ninst].mark2 = (uintptr_t)dyn->arm_size;}
-#define GETMARK2 ((dyn->insts)?dyn->insts[ninst].mark2:(dyn->arm_size+4))
-#define MARK3   if(dyn->insts) {dyn->insts[ninst].mark3 = (uintptr_t)dyn->arm_size;}
-#define GETMARK3 ((dyn->insts)?dyn->insts[ninst].mark3:(dyn->arm_size+4))
-#define MARKF   if(dyn->insts) {dyn->insts[ninst].markf = (uintptr_t)dyn->arm_size;}
-#define GETMARKF ((dyn->insts)?dyn->insts[ninst].markf:(dyn->arm_size+4))
-#define MARKSEG if(dyn->insts) {dyn->insts[ninst].markseg = (uintptr_t)dyn->arm_size;}
-#define GETMARKSEG ((dyn->insts)?dyn->insts[ninst].markseg:(dyn->arm_size+4))
-#define MARKLOCK if(dyn->insts) {dyn->insts[ninst].marklock = (uintptr_t)dyn->arm_size;}
-#define GETMARKLOCK ((dyn->insts)?dyn->insts[ninst].marklock:(dyn->arm_size+4))
+#define MARK    dyn->insts[ninst].mark = dyn->native_size
+#define GETMARK dyn->insts[ninst].mark
+#define MARK2   dyn->insts[ninst].mark2 = dyn->native_size
+#define GETMARK2 dyn->insts[ninst].mark2
+#define MARK3   dyn->insts[ninst].mark3 = dyn->native_size
+#define GETMARK3 dyn->insts[ninst].mark3
+#define MARKF   dyn->insts[ninst].markf = dyn->native_size
+#define GETMARKF dyn->insts[ninst].markf
+#define MARKSEG dyn->insts[ninst].markseg = dyn->native_size
+#define GETMARKSEG dyn->insts[ninst].markseg
+#define MARKLOCK dyn->insts[ninst].marklock = dyn->native_size
+#define GETMARKLOCK dyn->insts[ninst].marklock
 
-// Branch to MARK if cond (use j32)
+// Branch to MARK if cond (use j64)
 #define B_MARK(cond)                \
-    j32 = GETMARK-(dyn->arm_size);  \
-    Bcond(cond, j32)
-// Branch to MARK unconditionnal (use j32)
+    j64 = GETMARK-(dyn->native_size);  \
+    Bcond(cond, j64)
+// Branch to MARK unconditionnal (use j64)
 #define B_MARK_nocond               \
-    j32 = GETMARK-(dyn->arm_size);  \
-    B(j32)
-// Branch to MARK if reg is 0 (use j32)
+    j64 = GETMARK-(dyn->native_size);  \
+    B(j64)
+// Branch to MARK if reg is 0 (use j64)
 #define CBZxw_MARK(reg)             \
-    j32 = GETMARK-(dyn->arm_size);  \
-    CBZxw(reg, j32)
-// Branch to MARK if reg is not 0 (use j32)
+    j64 = GETMARK-(dyn->native_size);  \
+    CBZxw(reg, j64)
+// Branch to MARK if reg is not 0 (use j64)
 #define CBNZx_MARK(reg)             \
-    j32 = GETMARK-(dyn->arm_size);  \
-    CBNZx(reg, j32)
-// Branch to MARK if reg is not 0 (use j32)
+    j64 = GETMARK-(dyn->native_size);  \
+    CBNZx(reg, j64)
+// Branch to MARK if reg is not 0 (use j64)
 #define CBNZw_MARK(reg)             \
-    j32 = GETMARK-(dyn->arm_size);  \
-    CBNZw(reg, j32)
-// Branch to MARK2 if cond (use j32)
+    j64 = GETMARK-(dyn->native_size);  \
+    CBNZw(reg, j64)
+// Test bit N of A and branch to MARK if not set
+#define TBZ_MARK(A, N)              \
+    j64 = GETMARK-(dyn->native_size);  \
+    TBZ(A, N, j64)
+// Test bit N of A and branch to MARK if set
+#define TBNZ_MARK(A, N)             \
+    j64 = GETMARK-(dyn->native_size);  \
+    TBNZ(A, N, j64)
+// Branch to MARK2 if cond (use j64)
 #define B_MARK2(cond)               \
-    j32 = GETMARK2-(dyn->arm_size); \
-    Bcond(cond, j32)
-// Branch to MARK2 unconditionnal (use j32)
+    j64 = GETMARK2-(dyn->native_size); \
+    Bcond(cond, j64)
+// Branch to MARK2 unconditionnal (use j64)
 #define B_MARK2_nocond              \
-    j32 = GETMARK2-(dyn->arm_size); \
-    B(j32)
-// Branch to MARK2 if reg is not 0 (use j32)
+    j64 = GETMARK2-(dyn->native_size); \
+    B(j64)
+// Branch to MARK2 if reg is not 0 (use j64)
 #define CBNZx_MARK2(reg)            \
-    j32 = GETMARK2-(dyn->arm_size); \
-    CBNZx(reg, j32)
+    j64 = GETMARK2-(dyn->native_size); \
+    CBNZx(reg, j64)
 // Test bit N of A and branch to MARK2 if set
 #define TBNZ_MARK2(A, N)            \
-    j32 = GETMARK2-(dyn->arm_size); \
-    TBNZ(A, N, j32)
-// Branch to MARK3 if cond (use j32)
+    j64 = GETMARK2-(dyn->native_size); \
+    TBNZ(A, N, j64)
+// Branch to MARK3 if cond (use j64)
 #define B_MARK3(cond)               \
-    j32 = GETMARK3-(dyn->arm_size); \
-    Bcond(cond, j32)
-// Branch to MARK3 unconditionnal (use j32)
+    j64 = GETMARK3-(dyn->native_size); \
+    Bcond(cond, j64)
+// Test bit N of A and branch to MARK3 if not set
+#define TBZ_MARK2(A, N)            \
+    j64 = GETMARK2-(dyn->native_size); \
+    TBZ(A, N, j64)
+// Branch to MARK3 unconditionnal (use j64)
 #define B_MARK3_nocond              \
-    j32 = GETMARK3-(dyn->arm_size); \
-    B(j32)
-// Branch to MARK3 if reg is not 0 (use j32)
+    j64 = GETMARK3-(dyn->native_size); \
+    B(j64)
+// Branch to MARK3 if reg is not 0 (use j64)
 #define CBNZx_MARK3(reg)            \
-    j32 = GETMARK3-(dyn->arm_size); \
-    CBNZx(reg, j32)
-// Test bit N of A and branch to MARK3 if set
-#define TBNZ_MARK3(A, N)            \
-    j32 = GETMARK3-(dyn->arm_size); \
-    TBNZ(A, N, j32)
+    j64 = GETMARK3-(dyn->native_size); \
+    CBNZx(reg, j64)
+// Branch to MARK3 if reg is 0 (use j64)
+#define CBZx_MARK3(reg)             \
+    j64 = GETMARK3-(dyn->native_size); \
+    CBZx(reg, j64)
 // Test bit N of A and branch to MARK3 if not set
 #define TBZ_MARK3(A, N)             \
-    j32 = GETMARK3-(dyn->arm_size); \
-    TBZ(A, N, j32)
-// Branch to next instruction if cond (use j32)
+    j64 = GETMARK3-(dyn->native_size); \
+    TBZ(A, N, j64)
+// Test bit N of A and branch to MARK3 if set
+#define TBNZ_MARK3(A, N)            \
+    j64 = GETMARK3-(dyn->native_size); \
+    TBNZ(A, N, j64)
+// Branch to next instruction if cond (use j64)
 #define B_NEXT(cond)     \
-    j32 = (dyn->insts)?(dyn->insts[ninst].epilog-(dyn->arm_size)):0; \
-    Bcond(cond, j32)
-// Branch to next instruction unconditionnal (use j32)
+    j64 = (dyn->insts)?(dyn->insts[ninst].epilog-(dyn->native_size)):0; \
+    Bcond(cond, j64)
+// Branch to next instruction unconditionnal (use j64)
 #define B_NEXT_nocond                                               \
-    j32 = (dyn->insts)?(dyn->insts[ninst].epilog-(dyn->arm_size)):0;\
-    B(j32)
-// Branch to next instruction if reg is 0 (use j32)
+    j64 = (dyn->insts)?(dyn->insts[ninst].epilog-(dyn->native_size)):0;\
+    B(j64)
+// Branch to next instruction if reg is 0 (use j64)
 #define CBZw_NEXT(reg)    \
-    j32 =  (dyn->insts)?(dyn->insts[ninst].epilog-(dyn->arm_size)):0; \
-    CBZw(reg, j32)
-// Branch to next instruction if reg is 0 (use j32)
+    j64 =  (dyn->insts)?(dyn->insts[ninst].epilog-(dyn->native_size)):0; \
+    CBZw(reg, j64)
+// Branch to next instruction if reg is 0 (use j64)
 #define CBZx_NEXT(reg)    \
-    j32 =  (dyn->insts)?(dyn->insts[ninst].epilog-(dyn->arm_size)):0; \
-    CBZx(reg, j32)
+    j64 =  (dyn->insts)?(dyn->insts[ninst].epilog-(dyn->native_size)):0; \
+    CBZx(reg, j64)
+// Branch to next instruction if reg is not 0 (use j64)
+#define CBNZx_NEXT(reg)   \
+    j64 =  (dyn->insts)?(dyn->insts[ninst].epilog-(dyn->native_size)):0; \
+    CBNZx(reg, j64)
 // Test bit N of A and branch to next instruction if not set
 #define TBZ_NEXT(A, N)              \
-    j32 = (dyn->insts)?(dyn->insts[ninst].epilog-(dyn->arm_size)):0; \
-    TBZ(A, N, j32)
-// Branch to MARKSEG if cond (use j32)
+    j64 = (dyn->insts)?(dyn->insts[ninst].epilog-(dyn->native_size)):0; \
+    TBZ(A, N, j64)
+// Test bit N of A and branch to next instruction if set
+#define TBNZ_NEXT(A, N)             \
+    j64 = (dyn->insts)?(dyn->insts[ninst].epilog-(dyn->native_size)):0; \
+    TBNZ(A, N, j64)
+// Branch to MARKSEG if cond (use j64)
 #define B_MARKSEG(cond)    \
-    j32 = GETMARKSEG-(dyn->arm_size);   \
-    Bcond(cond, j32)
-// Branch to MARKSEG if reg is 0 (use j32)
+    j64 = GETMARKSEG-(dyn->native_size);   \
+    Bcond(cond, j64)
+// Branch to MARKSEG if reg is 0 (use j64)
 #define CBZw_MARKSEG(reg)    \
-    j32 = GETMARKSEG-(dyn->arm_size);   \
-    CBZw(reg, j32)
-// Branch to MARKSEG if reg is not 0 (use j32)
+    j64 = GETMARKSEG-(dyn->native_size);   \
+    CBZw(reg, j64)
+// Branch to MARKSEG if reg is not 0 (use j64)
 #define CBNZw_MARKSEG(reg)              \
-    j32 = GETMARKSEG-(dyn->arm_size);   \
-    CBNZw(reg, j32)
-// Branch to MARKLOCK if cond (use j32)
+    j64 = GETMARKSEG-(dyn->native_size);   \
+    CBNZw(reg, j64)
+// Branch to MARKLOCK if cond (use j64)
 #define B_MARKLOCK(cond)    \
-    j32 = GETMARKLOCK-(dyn->arm_size);   \
-    Bcond(cond, j32)
-// Branch to MARKLOCK if reg is not 0 (use j32)
+    j64 = GETMARKLOCK-(dyn->native_size);   \
+    Bcond(cond, j64)
+// Branch to MARKLOCK if reg is not 0 (use j64)
 #define CBNZx_MARKLOCK(reg)             \
-    j32 = GETMARKLOCK-(dyn->arm_size);  \
-    CBNZx(reg, j32)
+    j64 = GETMARKLOCK-(dyn->native_size);  \
+    CBNZx(reg, j64)
 
-#define IFX(A)  if(dyn->insts && (dyn->insts[ninst].x64.need_flags&(A)))
-#define IFX_PENDOR0  if(dyn->insts && (dyn->insts[ninst].x64.need_flags&(X_PEND) || !dyn->insts[ninst].x64.need_flags))
-#define IFXX(A) if(dyn->insts && (dyn->insts[ninst].x64.need_flags==(A)))
-#define IFX2X(A, B) if(dyn->insts && (dyn->insts[ninst].x64.need_flags==(A) || dyn->insts[ninst].x64.need_flags==(B) || dyn->insts[ninst].x64.need_flags==((A)|(B))))
-#define IFXN(A, B)  if(dyn->insts && (dyn->insts[ninst].x64.need_flags&(A) && !(dyn->insts[ninst].x64.need_flags&(B))))
+#define IFX(A)  if((dyn->insts[ninst].x64.need_flags&(A)))
+#define IFX_PENDOR0  if((dyn->insts[ninst].x64.need_flags&(X_PEND) || !dyn->insts[ninst].x64.need_flags))
+#define IFXX(A) if((dyn->insts[ninst].x64.need_flags==(A)))
+#define IFX2X(A, B) if((dyn->insts[ninst].x64.need_flags==(A) || dyn->insts[ninst].x64.need_flags==(B) || dyn->insts[ninst].x64.need_flags==((A)|(B))))
+#define IFXN(A, B)  if((dyn->insts[ninst].x64.need_flags&(A) && !(dyn->insts[ninst].x64.need_flags&(B))))
 
 // Generate FCOM with s1 and s2 scratch regs (the VCMP is already done)
 #define FCOM(s1, s2, s3)                                                    \
@@ -400,6 +494,7 @@
 
 #define STORE_REG(A)    STRx_U12(x##A, xEmu, offsetof(x64emu_t, regs[_##A]))
 #define STP_REGS(A, B)  STPx_S7_offset(x##A, x##B, xEmu, offsetof(x64emu_t, regs[_##A]))
+#define LDP_REGS(A, B)  LDPx_S7_offset(x##A, x##B, xEmu, offsetof(x64emu_t, regs[_##A]))
 #define STORE_XEMU_REGS(A)  \
     STORE_REG(RAX);         \
     STORE_REG(RCX);         \
@@ -465,38 +560,57 @@
     if(A) {STPx_S7_offset(xFlags, A, xEmu, offsetof(x64emu_t, eflags));}    \
     else {STRx_U12(xFlags, xEmu, offsetof(x64emu_t, eflags));}
 
-#define LOAD_XEMU_CALL(A)  \
+#define LOAD_XEMU_CALL(A)   \
     if(A) {LDPx_S7_offset(xFlags, A, xEmu, offsetof(x64emu_t, eflags));}    \
     else {LDRx_U12(xFlags, xEmu, offsetof(x64emu_t, eflags));};             \
     if(A==xRIP) dyn->last_ip = 0
 
-#define SET_DFNONE(S)    if(!dyn->dfnone) {MOVZw(S, d_none); STRw_U12(S, xEmu, offsetof(x64emu_t, df)); dyn->dfnone=1;}
-#define SET_DF(S, N)     if((N)!=d_none) {MOVZw(S, (N)); STRw_U12(S, xEmu, offsetof(x64emu_t, df)); dyn->dfnone=0;} else SET_DFNONE(S)
-#define SET_NODF()          dyn->dfnone = 0
-#define SET_DFOK()          dyn->dfnone = 1
+#define LOAD_XEMU_REM()     \
+    LDP_REGS(R10, R11);     \
+    LDP_REGS(R12, R13);     \
+    LDP_REGS(R14, R15)
+
+#define SET_DFNONE(S)    if(!dyn->f.dfnone) {MOVZw(S, d_none); STRw_U12(S, xEmu, offsetof(x64emu_t, df)); dyn->f.dfnone=1;}
+#define SET_DF(S, N)     if((N)!=d_none) {MOVZw(S, (N)); STRw_U12(S, xEmu, offsetof(x64emu_t, df)); dyn->f.dfnone=0;} else SET_DFNONE(S)
+#define SET_NODF()          dyn->f.dfnone = 0
+#define SET_DFOK()          dyn->f.dfnone = 1
 
 #ifndef READFLAGS
 #define READFLAGS(A) \
-    if(((A)!=X_PEND) && dyn->state_flags!=SF_SET) {     \
-        if(dyn->state_flags!=SF_PENDING) {              \
+    if(((A)!=X_PEND && dyn->f.pending!=SF_SET)          \
+    && (dyn->f.pending!=SF_SET_PENDING)) {              \
+        if(dyn->f.pending!=SF_PENDING) {                \
             LDRw_U12(x3, xEmu, offsetof(x64emu_t, df)); \
-            j32 = (GETMARKF)-(dyn->arm_size);           \
-            CBZw(x3, j32);                              \
+            j64 = (GETMARKF)-(dyn->native_size);        \
+            CBZw(x3, j64);                              \
         }                                               \
         CALL_(UpdateFlags, -1, 0);                      \
         MARKF;                                          \
-        dyn->state_flags = SF_SET;                      \
+        dyn->f.pending = SF_SET;                        \
         SET_DFOK();                                     \
     }
 #endif
+// SF_MAYSET doesn't change the flags status cache
+// it also doesn't consume any needed flags
 #ifndef SETFLAGS
-#define SETFLAGS(A, B)  \
-    if(dyn->state_flags!=SF_SET && B==SF_SUBSET && (dyn->insts[ninst].x64.need_flags&(~((A)|X_PEND)))) \
-        READFLAGS(dyn->insts[ninst].x64.need_flags&(~(A)));    \
-    dyn->state_flags = (B==SF_SUBSET)?SF_SET:B
+#define SETFLAGS(A, B)                                                                          \
+    if(dyn->f.pending!=SF_SET                                                                   \
+    && (B==SF_SUBSET || B==SF_SUBSET_PENDING)                                                   \
+    && (dyn->insts[ninst].x64.need_flags&(~((A)|((B==SF_SUBSET_PENDING)?X_PEND:0)))))           \
+        READFLAGS(dyn->insts[ninst].x64.need_flags&(~(A)|X_PEND));                              \
+    if(dyn->insts[ninst].x64.need_flags) switch(B) {                                            \
+        case SF_SUBSET:                                                                         \
+        case SF_SET: dyn->f.pending = SF_SET; break;                                            \
+        case SF_PENDING: dyn->f.pending = SF_PENDING; break;                                    \
+        case SF_SUBSET_PENDING:                                                                 \
+        case SF_SET_PENDING:                                                                    \
+            dyn->f.pending = (dyn->insts[ninst].x64.need_flags&X_PEND)?SF_SET_PENDING:SF_SET;   \
+            break;                                                                              \
+        case SF_MAYSET: break;                                                                  \
+    } else dyn->f.pending = SF_SET
 #endif
 #ifndef JUMP
-#define JUMP(A) 
+#define JUMP(A, C) 
 #endif
 #ifndef BARRIER
 #define BARRIER(A) 
@@ -504,12 +618,12 @@
 #ifndef BARRIER_NEXT
 #define BARRIER_NEXT(A)
 #endif
-#define UFLAG_OP1(A) if(dyn->insts && dyn->insts[ninst].x64.need_flags) {STRxw_U12(A, xEmu, offsetof(x64emu_t, op1));}
-#define UFLAG_OP2(A) if(dyn->insts && dyn->insts[ninst].x64.need_flags) {STRxw_U12(A, xEmu, offsetof(x64emu_t, op2));}
-#define UFLAG_OP12(A1, A2) if(dyn->insts && dyn->insts[ninst].x64.need_flags) {STRxw_U12(A1, xEmu, offsetof(x64emu_t, op1));STRxw_U12(A2, 0, offsetof(x64emu_t, op2));}
-#define UFLAG_RES(A) if(dyn->insts && dyn->insts[ninst].x64.need_flags) {STRxw_U12(A, xEmu, offsetof(x64emu_t, res));}
-#define UFLAG_DF(r, A) if(dyn->insts && dyn->insts[ninst].x64.need_flags) {SET_DF(r, A)}
-#define UFLAG_IF if(dyn->insts && dyn->insts[ninst].x64.need_flags)
+#define UFLAG_OP1(A) if(dyn->insts[ninst].x64.need_flags) {STRxw_U12(A, xEmu, offsetof(x64emu_t, op1));}
+#define UFLAG_OP2(A) if(dyn->insts[ninst].x64.need_flags) {STRxw_U12(A, xEmu, offsetof(x64emu_t, op2));}
+#define UFLAG_OP12(A1, A2) if(dyn->insts[ninst].x64.need_flags) {STRxw_U12(A1, xEmu, offsetof(x64emu_t, op1));STRxw_U12(A2, 0, offsetof(x64emu_t, op2));}
+#define UFLAG_RES(A) if(dyn->insts[ninst].x64.need_flags) {STRxw_U12(A, xEmu, offsetof(x64emu_t, res));}
+#define UFLAG_DF(r, A) if(dyn->insts[ninst].x64.need_flags) {SET_DF(r, A)}
+#define UFLAG_IF if(dyn->insts[ninst].x64.need_flags)
 #ifndef DEFAULT
 #define DEFAULT      *ok = -1; BARRIER(2)
 #endif
@@ -553,6 +667,7 @@
             TABLE64(xRIP, (A));                         \
     }
 #endif
+#define CLEARIP()   dyn->last_ip=0
 
 #if STEP < 2
 #define PASS2IF(A, B) if(A)
@@ -573,7 +688,7 @@ void* arm64_next(x64emu_t* emu, uintptr_t addr);
 #define STEPNAME(N) STEPNAME2(N, STEP)
 #endif
 
-#define arm_pass        STEPNAME(arm_pass)
+#define native_pass        STEPNAME(native_pass)
 
 #define dynarec64_00       STEPNAME(dynarec64_00)
 #define dynarec64_0F       STEPNAME(dynarec64_0F)
@@ -595,16 +710,17 @@ void* arm64_next(x64emu_t* emu, uintptr_t addr);
 #define dynarec64_F20F     STEPNAME(dynarec64_F20F)
 #define dynarec64_F30F     STEPNAME(dynarec64_F30F)
 
-#define geted           STEPNAME(geted_)
-#define geted32         STEPNAME(geted32_)
-#define geted16         STEPNAME(geted16_)
-#define jump_to_epilog  STEPNAME(jump_to_epilog_)
-#define jump_to_next    STEPNAME(jump_to_next_)
-#define ret_to_epilog   STEPNAME(ret_to_epilog_)
-#define retn_to_epilog  STEPNAME(retn_to_epilog_)
-#define iret_to_epilog  STEPNAME(iret_to_epilog_)
-#define call_c          STEPNAME(call_c_)
-#define grab_segdata    STEPNAME(grab_segdata_)
+#define geted           STEPNAME(geted)
+#define geted32         STEPNAME(geted32)
+#define geted16         STEPNAME(geted16)
+#define jump_to_epilog  STEPNAME(jump_to_epilog)
+#define jump_to_next    STEPNAME(jump_to_next)
+#define ret_to_epilog   STEPNAME(ret_to_epilog)
+#define retn_to_epilog  STEPNAME(retn_to_epilog)
+#define iret_to_epilog  STEPNAME(iret_to_epilog)
+#define call_c          STEPNAME(call_c)
+#define call_n          STEPNAME(call_n)
+#define grab_segdata    STEPNAME(grab_segdata)
 #define emit_cmp8       STEPNAME(emit_cmp8)
 #define emit_cmp16      STEPNAME(emit_cmp16)
 #define emit_cmp32      STEPNAME(emit_cmp32)
@@ -680,12 +796,16 @@ void* arm64_next(x64emu_t* emu, uintptr_t addr);
 #define x87_do_push     STEPNAME(x87_do_push)
 #define x87_do_push_empty STEPNAME(x87_do_push_empty)
 #define x87_do_pop      STEPNAME(x87_do_pop)
+#define x87_get_current_cache   STEPNAME(x87_get_current_cache)
 #define x87_get_cache   STEPNAME(x87_get_cache)
+#define x87_get_neoncache STEPNAME(x87_get_neoncache)
 #define x87_get_st      STEPNAME(x87_get_st)
+#define x87_get_st_empty  STEPNAME(x87_get_st)
 #define x87_refresh     STEPNAME(x87_refresh)
 #define x87_forget      STEPNAME(x87_forget)
 #define x87_reget_st    STEPNAME(x87_reget_st)
 #define x87_stackcount  STEPNAME(x87_stackcount)
+#define x87_swapreg     STEPNAME(x87_swapreg)
 #define x87_setround    STEPNAME(x87_setround)
 #define x87_restoreround STEPNAME(x87_restoreround)
 #define sse_setround    STEPNAME(sse_setround)
@@ -693,6 +813,7 @@ void* arm64_next(x64emu_t* emu, uintptr_t addr);
 #define mmx_get_reg_empty STEPNAME(mmx_get_reg_empty)
 #define sse_get_reg     STEPNAME(sse_get_reg)
 #define sse_get_reg_empty STEPNAME(sse_get_reg_empty)
+#define sse_forget_reg   STEPNAME(sse_forget_reg)
 #define sse_purge07cache STEPNAME(sse_purge07cache)
 
 #define fpu_pushcache   STEPNAME(fpu_pushcache)
@@ -705,14 +826,16 @@ void* arm64_next(x64emu_t* emu, uintptr_t addr);
 #define fpu_reflectcache STEPNAME(fpu_reflectcache)
 #endif
 
-/* setup r2 to address pointed by */
-uintptr_t geted(dynarec_arm_t* dyn, uintptr_t addr, int ninst, uint8_t nextop, uint8_t* ed, uint8_t hint, int* fixaddress, int absmax, uint32_t mask, rex_t rex, int s, int delta);
+#define fpuCacheTransform       STEPNAME(fpuCacheTransform)
 
 /* setup r2 to address pointed by */
-uintptr_t geted32(dynarec_arm_t* dyn, uintptr_t addr, int ninst, uint8_t nextop, uint8_t* ed, uint8_t hint, int* fixaddress, int absmax, uint32_t mask, rex_t rex, int s, int delta);
+uintptr_t geted(dynarec_arm_t* dyn, uintptr_t addr, int ninst, uint8_t nextop, uint8_t* ed, uint8_t hint, int64_t* fixaddress, int absmax, uint32_t mask, rex_t rex, int s, int delta);
 
 /* setup r2 to address pointed by */
-uintptr_t geted16(dynarec_arm_t* dyn, uintptr_t addr, int ninst, uint8_t nextop, uint8_t* ed, uint8_t hint, int* fixaddress, int absmax, uint32_t mask, int s);
+uintptr_t geted32(dynarec_arm_t* dyn, uintptr_t addr, int ninst, uint8_t nextop, uint8_t* ed, uint8_t hint, int64_t* fixaddress, int absmax, uint32_t mask, rex_t rex, int s, int delta);
+
+/* setup r2 to address pointed by */
+uintptr_t geted16(dynarec_arm_t* dyn, uintptr_t addr, int ninst, uint8_t nextop, uint8_t* ed, uint8_t hint, int64_t* fixaddress, int absmax, uint32_t mask, int s);
 
 
 // generic x64 helper
@@ -720,8 +843,9 @@ void jump_to_epilog(dynarec_arm_t* dyn, uintptr_t ip, int reg, int ninst);
 void jump_to_next(dynarec_arm_t* dyn, uintptr_t ip, int reg, int ninst);
 void ret_to_epilog(dynarec_arm_t* dyn, int ninst);
 void retn_to_epilog(dynarec_arm_t* dyn, int ninst, int n);
-void iret_to_epilog(dynarec_arm_t* dyn, int ninst);
+void iret_to_epilog(dynarec_arm_t* dyn, int ninst, int is64bits);
 void call_c(dynarec_arm_t* dyn, int ninst, void* fnc, int reg, int ret, int saveflags, int save_reg);
+void call_n(dynarec_arm_t* dyn, int ninst, void* fnc, int w);
 void grab_segdata(dynarec_arm_t* dyn, uintptr_t addr, int ninst, int reg, int segment);
 void emit_cmp8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int s5);
 void emit_cmp16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int s5);
@@ -790,8 +914,8 @@ void emit_shr32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
 void emit_sar32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, int s3, int s4);
 void emit_rol32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, int s3, int s4);
 void emit_ror32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, int s3, int s4);
-//void emit_shrd32c(dynarec_arm_t* dyn, int ninst, int s1, int s2, int32_t c, int s3, int s4);
-//void emit_shld32c(dynarec_arm_t* dyn, int ninst, int s1, int s2, int32_t c, int s3, int s4);
+void emit_shrd32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int32_t c, int s3, int s4);
+void emit_shld32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int32_t c, int s3, int s4);
 
 void emit_pf(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
 
@@ -799,21 +923,29 @@ void emit_pf(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4);
 // cache of the local stack counter, to avoid upadte at every call
 void x87_stackcount(dynarec_arm_t* dyn, int ninst, int scratch);
 // fpu push. Return the Dd value to be used
-int x87_do_push(dynarec_arm_t* dyn, int ninst);
+int x87_do_push(dynarec_arm_t* dyn, int ninst, int s1, int t);
 // fpu push. Do not allocate a cache register. Needs a scratch register to do x87stack synch (or 0 to not do it)
 void x87_do_push_empty(dynarec_arm_t* dyn, int ninst, int s1);
 // fpu pop. All previous returned Dd should be considered invalid
-void x87_do_pop(dynarec_arm_t* dyn, int ninst);
+void x87_do_pop(dynarec_arm_t* dyn, int ninst, int s1);
+// get cache index for a x87 reg, return -1 if cache doesn't exist
+int x87_get_current_cache(dynarec_arm_t* dyn, int ninst, int st, int t);
 // get cache index for a x87 reg, create the entry if needed
-int x87_get_cache(dynarec_arm_t* dyn, int ninst, int s1, int s2, int a);
+int x87_get_cache(dynarec_arm_t* dyn, int ninst, int populate, int s1, int s2, int a, int t);
+// get neoncache index for a x87 reg
+int x87_get_neoncache(dynarec_arm_t* dyn, int ninst, int s1, int s2, int a);
 // get vfpu register for a x87 reg, create the entry if needed
-int x87_get_st(dynarec_arm_t* dyn, int ninst, int s1, int s2, int a);
+int x87_get_st(dynarec_arm_t* dyn, int ninst, int s1, int s2, int a, int t);
+// get vfpu register for a x87 reg, create the entry if needed. Do not fetch the Stx if not already in cache
+int x87_get_st_empty(dynarec_arm_t* dyn, int ninst, int s1, int s2, int a, int t);
 // refresh a value from the cache ->emu (nothing done if value is not cached)
 void x87_refresh(dynarec_arm_t* dyn, int ninst, int s1, int s2, int st);
 // refresh a value from the cache ->emu and then forget the cache (nothing done if value is not cached)
 void x87_forget(dynarec_arm_t* dyn, int ninst, int s1, int s2, int st);
 // refresh the cache value from emu
 void x87_reget_st(dynarec_arm_t* dyn, int ninst, int s1, int s2, int st);
+// swap 2 x87 regs
+void x87_swapreg(dynarec_arm_t* dyn, int ninst, int s1, int s2, int a, int b);
 // Set rounding according to cw flags, return reg to restore flags
 int x87_setround(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3);
 // Restore round flag
@@ -821,38 +953,72 @@ void x87_restoreround(dynarec_arm_t* dyn, int ninst, int s1);
 // Set rounding according to mxcsr flags, return reg to restore flags
 int sse_setround(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3);
 
+void fpuCacheTransform(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3);
+
+#if STEP < 2
+#define CHECK_CACHE()   0
+#else
+#define CHECK_CACHE()   fpuCacheNeedsTransform(dyn, ninst)
+#endif
+
+#define neoncache_st_coherency STEPNAME(neoncache_st_coherency)
+int neoncache_st_coherency(dynarec_arm_t* dyn, int ninst, int a, int b);
+
+#if STEP == 0
+#define ST_IS_F(A)          0
+#define X87_COMBINE(A, B)   NEON_CACHE_ST_D
+#define X87_ST0             NEON_CACHE_ST_D
+#define X87_ST(A)           NEON_CACHE_ST_D
+#elif STEP == 1
+#define ST_IS_F(A) (neoncache_get_current_st(dyn, ninst, A)==NEON_CACHE_ST_F)
+#define X87_COMBINE(A, B) neoncache_combine_st(dyn, ninst, A, B)
+#define X87_ST0     neoncache_get_current_st(dyn, ninst, 0)
+#define X87_ST(A)   neoncache_get_current_st(dyn, ninst, A)
+#else
+#define ST_IS_F(A) (neoncache_get_st(dyn, ninst, A)==NEON_CACHE_ST_F)
+#if STEP == 3
+#define X87_COMBINE(A, B) neoncache_st_coherency(dyn, ninst, A, B)
+#else
+#define X87_COMBINE(A, B) neoncache_get_st(dyn, ninst, A)
+#endif
+#define X87_ST0     neoncache_get_st(dyn, ninst, 0)
+#define X87_ST(A)   neoncache_get_st(dyn, ninst, A)
+#endif
+
 //MMX helpers
 // get neon register for a MMX reg, create the entry if needed
-int mmx_get_reg(dynarec_arm_t* dyn, int ninst, int s1, int a);
+int mmx_get_reg(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int a);
 // get neon register for a MMX reg, but don't try to synch it if it needed to be created
-int mmx_get_reg_empty(dynarec_arm_t* dyn, int ninst, int s1, int a);
+int mmx_get_reg_empty(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int a);
 
 //SSE/SSE2 helpers
 // get neon register for a SSE reg, create the entry if needed
-int sse_get_reg(dynarec_arm_t* dyn, int ninst, int s1, int a);
+int sse_get_reg(dynarec_arm_t* dyn, int ninst, int s1, int a, int forwrite);
 // get neon register for a SSE reg, but don't try to synch it if it needed to be created
 int sse_get_reg_empty(dynarec_arm_t* dyn, int ninst, int s1, int a);
+// forget neon register for a SSE reg, create the entry if needed
+void sse_forget_reg(dynarec_arm_t* dyn, int ninst, int a);
 // purge the XMM0..XMM7 cache (before function call)
 void sse_purge07cache(dynarec_arm_t* dyn, int ninst, int s1);
 
 // common coproc helpers
 // reset the cache
-void fpu_reset(dynarec_arm_t* dyn, int ninst);
+void fpu_reset(dynarec_arm_t* dyn);
 // purge the FPU cache (needs 3 scratch registers)
-void fpu_purgecache(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3);
+void fpu_purgecache(dynarec_arm_t* dyn, int ninst, int next, int s1, int s2, int s3);
 // purge MMX cache
-void mmx_purgecache(dynarec_arm_t* dyn, int ninst, int s1);
+void mmx_purgecache(dynarec_arm_t* dyn, int ninst, int next, int s1);
 // purge x87 cache
-void x87_purgecache(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3);
+void x87_purgecache(dynarec_arm_t* dyn, int ninst, int next, int s1, int s2, int s3);
 #ifdef HAVE_TRACE
 void fpu_reflectcache(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3);
 #endif
-void fpu_pushcache(dynarec_arm_t* dyn, int ninst, int s1);
-void fpu_popcache(dynarec_arm_t* dyn, int ninst, int s1);
+void fpu_pushcache(dynarec_arm_t* dyn, int ninst, int s1, int not07);
+void fpu_popcache(dynarec_arm_t* dyn, int ninst, int s1, int not07);
 
 uintptr_t dynarec64_00(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog);
 uintptr_t dynarec64_0F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog);
-uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep,int* ok, int* need_epilog);
+uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int seg, int* ok, int* need_epilog);
 //uintptr_t dynarec64_65(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep,int* ok, int* need_epilog);
 uintptr_t dynarec64_66(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog);
 uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog);
@@ -860,7 +1026,7 @@ uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
 uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog);
 //uintptr_t dynarec64_DA(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog);
 uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog);
-//uintptr_t dynarec64_DC(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog);
+uintptr_t dynarec64_DC(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog);
 uintptr_t dynarec64_DD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog);
 //uintptr_t dynarec64_DE(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog);
 uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog);
@@ -978,4 +1144,4 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             , cNE, cEQ, X_SF|X_OF|X_ZF)                     \
         break
 
-#endif //__DYNAREC_ARM64_HELPER_H__
+#endif //__DYNAREC_ARM64_HELPER_H__

src/dynarec/arm64/dynarec_arm64_pass0.h

@@ -0,0 +1,54 @@
+
+#define INIT    uintptr_t sav_addr=addr
+#define FINI    \
+    dyn->isize = addr-sav_addr;         \
+    dyn->insts[ninst].x64.addr = addr;  \
+    if(ninst) dyn->insts[ninst-1].x64.size = dyn->insts[ninst].x64.addr - dyn->insts[ninst-1].x64.addr
+
+#define MESSAGE(A, ...)  
+#define READFLAGS(A)    \
+        dyn->insts[ninst].x64.use_flags = A; dyn->f.dfnone = 1;\
+        dyn->f.pending=SF_SET
+#define SETFLAGS(A,B)   \
+        dyn->insts[ninst].x64.set_flags = A;            \
+        if(B!=SF_MAYSET) {                              \
+                dyn->insts[ninst].x64.state_flags = B;  \
+                dyn->f.pending=(B)&SF_SET_PENDING;      \
+                dyn->f.dfnone=((B)&SF_SET)?1:0;         \
+        }
+#define EMIT(A)     
+#define JUMP(A, C)         add_next(dyn, (uintptr_t)A); dyn->insts[ninst].x64.jmp = A; dyn->insts[ninst].x64.jmp_cond = C
+#define BARRIER(A)      if(A!=BARRIER_MAYBE) {fpu_purgecache(dyn, ninst, 0, x1, x2, x3); dyn->insts[ninst].x64.barrier = A;} else dyn->insts[ninst].barrier_maybe = 1
+#define BARRIER_NEXT(A) dyn->insts[ninst+1].x64.barrier = A
+#define NEW_INST \
+        ++dyn->size;                            \
+        if(dyn->size+3>=dyn->cap) {             \
+                dyn->insts = (instruction_native_t*)realloc(dyn->insts, sizeof(instruction_native_t)*dyn->cap*2);     \
+                memset(&dyn->insts[dyn->cap], 0, sizeof(instruction_native_t)*dyn->cap);   \
+                dyn->cap *= 2;                  \
+        }                                       \
+        dyn->insts[ninst].x64.addr = ip;        \
+        dyn->n.combined1 = dyn->n.combined2 = 0;\
+        dyn->n.swapped = 0; dyn->n.barrier = 0; \
+        dyn->insts[ninst].f_entry = dyn->f;     \
+        if(ninst) {dyn->insts[ninst-1].x64.size = dyn->insts[ninst].x64.addr - dyn->insts[ninst-1].x64.addr;}
+
+#define INST_EPILOG                             \
+        dyn->insts[ninst].f_exit = dyn->f;      \
+        dyn->insts[ninst].n = dyn->n;           \
+        dyn->insts[ninst].x64.has_next = (ok>0)?1:0;
+#define INST_NAME(name) 
+#define DEFAULT                         \
+        --dyn->size;                    \
+        *ok = -1;                       \
+        if(box64_dynarec_log>=LOG_INFO) {\
+        dynarec_log(LOG_NONE, "%p: Dynarec stopped because of Opcode %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X", \
+        (void*)ip, PKip(0),             \
+        PKip(1), PKip(2), PKip(3),      \
+        PKip(4), PKip(5), PKip(6),      \
+        PKip(7), PKip(8), PKip(9),      \
+        PKip(10),PKip(11),PKip(12),     \
+        PKip(13),PKip(14));             \
+        printFunctionAddr(ip, " => ");  \
+        dynarec_log(LOG_NONE, "\n");    \
+        }

src/dynarec/arm64/dynarec_arm64_pass1.h

@@ -0,0 +1,14 @@
+#define INIT    
+#define FINI
+#define MESSAGE(A, ...)  
+#define EMIT(A)     
+#define NEW_INST                                \
+        dyn->insts[ninst].f_entry = dyn->f;     \
+        dyn->n.combined1 = dyn->n.combined2 = 0;\
+        dyn->n.swapped = 0; dyn->n.barrier = 0
+
+#define INST_EPILOG                             \
+        dyn->insts[ninst].n = dyn->n;           \
+        dyn->insts[ninst].f_exit = dyn->f
+
+#define INST_NAME(name)  

src/dynarec/arm64/dynarec_arm64_pass2.h

@@ -0,0 +1,17 @@
+#define INIT        dyn->native_size = 0
+#define FINI        if(ninst) {dyn->insts[ninst].address = (dyn->insts[ninst-1].address+dyn->insts[ninst-1].size);}
+
+#define MESSAGE(A, ...)  
+#define EMIT(A)     dyn->insts[ninst].size+=4; dyn->native_size+=4
+#define NEW_INST                                                                                        \
+        if(ninst) {                                                                                     \
+                dyn->insts[ninst].address = (dyn->insts[ninst-1].address+dyn->insts[ninst-1].size);     \
+                if(ninst && isInstClean(dyn, ninst)) {                                                  \
+                        dyn->last_ip = 0;                                                               \
+                        ++dyn->sons_size;                                                               \
+                }                                                                                       \
+        }
+#define INST_EPILOG dyn->insts[ninst].epilog = dyn->native_size; 
+#define INST_NAME(name) 
+#define TABLE64(A, V)   {Table64(dyn, (V)); EMIT(0);}
+#define FTABLE64(A, V)  {mmx87_regs_t v = {.d = V}; Table64(dyn, v.q); EMIT(0);}

src/dynarec/arm64/dynarec_arm64_pass3.h

@@ -0,0 +1,65 @@
+#define INIT    
+#define FINI
+#define EMIT(A)     \
+    if(box64_dynarec_dump) {dynarec_log(LOG_NONE, "\t%08x\t%s\n", (uint32_t)(A), arm64_print(A, (uintptr_t)dyn->block));} \
+    *(uint32_t*)(dyn->block) = (uint32_t)(A);       \
+    dyn->block += 4; dyn->native_size += 4;         \
+    dyn->insts[ninst].size2 += 4
+
+#define MESSAGE(A, ...)  if(box64_dynarec_dump) dynarec_log(LOG_NONE, __VA_ARGS__)
+#define NEW_INST        \
+    if(ninst && isInstClean(dyn, ninst)) {                      \
+        dyn->last_ip = 0;                                       \
+        dyn->sons_x64[dyn->sons_size] = (uintptr_t)ip;          \
+        dyn->sons_native[dyn->sons_size] = dyn->block;          \
+        MESSAGE(LOG_DUMP, "----> potential Son here %p/%p\n", (void*)ip, dyn->block);  \
+        ++dyn->sons_size;                                       \
+    }
+#define INST_EPILOG     
+#define INST_NAME(name) \
+    if(box64_dynarec_dump) {\
+        printf_x64_instruction(my_context->dec, &dyn->insts[ninst].x64, name); \
+        dynarec_log(LOG_NONE, "%s%p: %d emited opcodes, inst=%d, barrier=%d state=%d/%d(%d), set=%X, use=%X, need=%X", \
+            (box64_dynarec_dump>1)?"\e[32m":"", \
+            (void*)(dyn->native_start+dyn->insts[ninst].address),  \
+            dyn->insts[ninst].size/4,           \
+            ninst,                              \
+            dyn->insts[ninst].x64.barrier,      \
+            dyn->insts[ninst].x64.state_flags,  \
+            dyn->f.pending,                     \
+            dyn->f.dfnone,                      \
+            dyn->insts[ninst].x64.set_flags,    \
+            dyn->insts[ninst].x64.use_flags,    \
+            dyn->insts[ninst].x64.need_flags);  \
+        if(dyn->insts[ninst].pred_sz) {         \
+            dynarec_log(LOG_NONE, ", pred=");   \
+            for(int ii=0; ii<dyn->insts[ninst].pred_sz; ++ii)\
+                dynarec_log(LOG_NONE, "%s%d", ii?"/":"", dyn->insts[ninst].pred[ii]);\
+        }                                       \
+        if(dyn->insts[ninst].x64.jmp && dyn->insts[ninst].x64.jmp_insts>=0)\
+            dynarec_log(LOG_NONE, ", jmp=%d", dyn->insts[ninst].x64.jmp_insts);\
+        if(dyn->insts[ninst].x64.jmp && dyn->insts[ninst].x64.jmp_insts==-1)\
+            dynarec_log(LOG_NONE, ", jmp=out"); \
+        if(dyn->last_ip)                        \
+            dynarec_log(LOG_NONE, ", last_ip=%p", (void*)dyn->last_ip);\
+        for(int ii=0; ii<24; ++ii) {            \
+            switch(dyn->insts[ninst].n.neoncache[ii].t) {    \
+                case NEON_CACHE_ST_D: dynarec_log(LOG_NONE, " D%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;  \
+                case NEON_CACHE_ST_F: dynarec_log(LOG_NONE, " S%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;  \
+                case NEON_CACHE_MM: dynarec_log(LOG_NONE, " D%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;    \
+                case NEON_CACHE_XMMW: dynarec_log(LOG_NONE, " Q%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;  \
+                case NEON_CACHE_XMMR: dynarec_log(LOG_NONE, " Q%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;  \
+                case NEON_CACHE_SCR: dynarec_log(LOG_NONE, " D%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;   \
+                case NEON_CACHE_NONE:           \
+                default:    break;              \
+            }                                   \
+        }                                       \
+        if(dyn->n.stack || dyn->insts[ninst].n.stack_next || dyn->insts[ninst].n.x87stack)     \
+            dynarec_log(LOG_NONE, " X87:%d/%d(+%d/-%d)%d", dyn->n.stack, dyn->insts[ninst].n.stack_next, dyn->insts[ninst].n.stack_push, dyn->insts[ninst].n.stack_pop, dyn->insts[ninst].n.x87stack); \
+        if(dyn->insts[ninst].n.combined1 || dyn->insts[ninst].n.combined2)                     \
+            dynarec_log(LOG_NONE, " %s:%d/%d", dyn->insts[ninst].n.swapped?"SWP":"CMB", dyn->insts[ninst].n.combined1, dyn->insts[ninst].n.combined2);   \
+        dynarec_log(LOG_NONE, "%s\n", (box64_dynarec_dump>1)?"\e[m":"");                       \
+    }
+
+#define TABLE64(A, V)   {int val64offset = Table64(dyn, (V)); MESSAGE(LOG_DUMP, "  Table64: 0x%lx\n", (V)); LDRx_literal(A, val64offset);}
+#define FTABLE64(A, V)  {mmx87_regs_t v = {.d = V}; int val64offset = Table64(dyn, v.q); MESSAGE(LOG_DUMP, "  FTable64: %g\n", v.d); VLDR64_literal(A, val64offset);}

src/dynarec/arm64/dynarec_arm64_private.h

@@ -0,0 +1,124 @@
+#ifndef __DYNAREC_ARM_PRIVATE_H_
+#define __DYNAREC_ARM_PRIVATE_H_
+
+#include "../dynarec_private.h"
+
+typedef struct x64emu_s x64emu_t;
+typedef struct dynablock_s dynablock_t;
+
+#define BARRIER_MAYBE   8
+
+#define NEON_CACHE_NONE 0
+#define NEON_CACHE_ST_D 1
+#define NEON_CACHE_ST_F 2
+#define NEON_CACHE_MM   3
+#define NEON_CACHE_XMMW 4
+#define NEON_CACHE_XMMR 5
+#define NEON_CACHE_SCR  6
+typedef union neon_cache_s {
+    int8_t           v;
+    struct {
+        unsigned int t:4;   // reg type
+        unsigned int n:4;   // reg number
+    };
+} neon_cache_t;
+typedef union sse_cache_s {
+    int8_t      v;
+    struct {
+        unsigned int reg:7;
+        unsigned int write:1;
+    };
+} sse_cache_t;
+typedef struct neoncache_s {
+    // Neon cache
+    neon_cache_t        neoncache[24];
+    int8_t              stack;
+    int8_t              stack_next;
+    int8_t              stack_pop;
+    int8_t              stack_push;
+    uint8_t             combined1;
+    uint8_t             combined2;
+    uint8_t             swapped;        // the combined reg were swapped
+    uint8_t             barrier;        // is there a barrier at instruction epilog?
+    uint32_t            news;           // bitmask, wich neoncache are new for this opcode
+    // fpu cache
+    int8_t              x87cache[8];    // cache status for the 8 x87 register behind the fpu stack
+    int8_t              x87reg[8];      // reg used for x87cache entry
+    int8_t              mmxcache[8];    // cache status for the 8 MMX registers
+    sse_cache_t         ssecache[16];   // cache status for the 16 SSE(2) registers
+    int8_t              fpuused[24];    // all 0..24 double reg from fpu, used by x87, sse and mmx
+    int8_t              x87stack;       // cache stack counter
+    int8_t              mmxcount;       // number of mmx register used (not both mmx and x87 at the same time)
+    int8_t              fpu_scratch;    // scratch counter
+    int8_t              fpu_extra_qscratch; // some opcode need an extra quad scratch register
+    int8_t              fpu_reg;        // x87/sse/mmx reg counter
+} neoncache_t;
+
+typedef struct flagcache_s {
+    int                 pending;    // is there a pending flags here, or to check?
+    int                 dfnone;     // if defered flags is already set to df_none
+} flagcache_t;
+
+typedef struct instruction_arm64_s {
+    instruction_x64_t   x64;
+    uintptr_t           address;    // (start) address of the arm emited instruction
+    uintptr_t           epilog;     // epilog of current instruction (can be start of next, or barrier stuff)
+    int                 size;       // size of the arm emited instruction
+    int                 size2;      // size of the arm emited instrucion after pass2
+    int                 pred_sz;    // size of predecessor list
+    int                 *pred;      // predecessor array
+    uintptr_t           mark, mark2, mark3;
+    uintptr_t           markf;
+    uintptr_t           markseg;
+    uintptr_t           marklock;
+    int                 pass2choice;// value for choices that are fixed on pass2 for pass3
+    uintptr_t           natcall;
+    int                 retn;
+    int                 barrier_maybe;
+    flagcache_t         f_exit;     // flags status at end of intruction
+    neoncache_t         n;          // neoncache at end of intruction (but before poping)
+    flagcache_t         f_entry;    // flags status before the instruction begin
+} instruction_arm64_t;
+
+typedef struct dynarec_arm_s {
+    instruction_arm64_t *insts;
+    int32_t             size;
+    int32_t             cap;
+    uintptr_t           start;      // start of the block
+    uint32_t            isize;      // size in byte of x64 instructions included
+    void*               block;      // memory pointer where next instruction is emited
+    uintptr_t           native_start;  // start of the arm code
+    size_t              native_size;   // size of emitted arm code
+    uintptr_t           last_ip;    // last set IP in RIP (or NULL if unclean state) TODO: move to a cache something
+    uint64_t            *table64;   // table of 64bits value
+    int                 table64size;// size of table (will be appended at end of executable code)
+    int                 table64cap;
+    uintptr_t           tablestart;
+    flagcache_t         f;
+    neoncache_t         n;          // cache for the 8..31 double reg from fpu, plus x87 stack delta
+    uintptr_t*          next;       // variable array of "next" jump address
+    int                 next_sz;
+    int                 next_cap;
+    uintptr_t*          sons_x64;   // the x64 address of potential dynablock sons
+    void**              sons_native;   // the arm address of potential dynablock sons
+    int                 sons_size;  // number of potential dynablock sons
+    int*                predecessor;// single array of all predecessor
+    dynablock_t*        dynablock;
+} dynarec_arm_t;
+
+void add_next(dynarec_arm_t *dyn, uintptr_t addr);
+uintptr_t get_closest_next(dynarec_arm_t *dyn, uintptr_t addr);
+int is_nops(dynarec_arm_t *dyn, uintptr_t addr, int n);
+int is_instructions(dynarec_arm_t *dyn, uintptr_t addr, int n);
+
+int Table64(dynarec_arm_t *dyn, uint64_t val);  // add a value to etable64 (if needed) and gives back the imm19 to use in LDR_literal
+
+#define GO_TRACE() \
+    GETIP_(ip);             \
+    MOVx_REG(x1, xRIP);     \
+    STORE_XEMU_CALL(xRIP);  \
+    MOV32w(x2, 1);          \
+    CALL(PrintTrace, -1);   \
+    LOAD_XEMU_CALL(xRIP)
+
+#endif //__DYNAREC_ARM_PRIVATE_H_

src/dynarec/dynablock.c

@@ -2,6 +2,7 @@
 #include <stdlib.h>
 #include <pthread.h>
 #include <errno.h>
+#include <setjmp.h>
 
 #include "debug.h"
 #include "box64context.h"
@@ -18,12 +19,10 @@
 #include "dynablock_private.h"
 #include "dynarec_private.h"
 #include "elfloader.h"
-#ifdef ARM64
-#include "dynarec_arm64.h"
-#include "arm64_lock.h"
-#else
-#error Unsupported architecture!
-#endif
+
+#include "dynarec_native.h"
+#include "native_lock.h"
+
 #include "custommem.h"
 #include "khash.h"
 
@@ -47,6 +46,8 @@ dynablocklist_t* NewDynablockList(uintptr_t text, int textsz, int direct)
     dynablocklist_t* ret = (dynablocklist_t*)calloc(1, sizeof(dynablocklist_t));
     ret->text = text;
     ret->textsz = textsz;
+    ret->minstart = text;
+    ret->maxend = text+textsz-1;
     if(direct && textsz) {
         ret->direct = (dynablock_t**)calloc(textsz, sizeof(dynablock_t*));
         if(!ret->direct) {printf_log(LOG_NONE, "Warning, fail to create direct block for dynablock @%p\n", (void*)text);}
@@ -55,12 +56,14 @@ dynablocklist_t* NewDynablockList(uintptr_t text, int textsz, int direct)
     return ret;
 }
 
-void FreeDynablock(dynablock_t* db)
+void FreeDynablock(dynablock_t* db, int need_lock)
 {
     if(db) {
-        dynarec_log(LOG_DEBUG, "FreeDynablock(%p), db->block=%p x64=%p:%p parent=%p, father=%p, with %d son(s) already gone=%d\n", db, db->block, db->x64_addr, db->x64_addr+db->x64_size, db->parent, db->father, db->sons_size, db->gone);
         if(db->gone)
             return; // already in the process of deletion!
+        dynarec_log(LOG_DEBUG, "FreeDynablock(%p), db->block=%p x64=%p:%p parent=%p, father=%p, with %d son(s) already gone=%d\n", db, db->block, db->x64_addr, db->x64_addr+db->x64_size-1, db->parent, db->father, db->sons_size, db->gone);
+        if(need_lock)
+            pthread_mutex_lock(&my_context->mutex_dyndump);
         db->done = 0;
         db->gone = 1;
         // remove from direct if there
@@ -69,23 +72,25 @@ void FreeDynablock(dynablock_t* db)
         if(db->parent->direct) {
             uintptr_t addr = (uintptr_t)db->x64_addr;
             if(addr>=startdb && addr<enddb)
-                arm64_lock_xchg(&db->parent->direct[addr-startdb], 0);   // secured write
+                native_lock_xchg(&db->parent->direct[addr-startdb], 0);   // secured write
         }
         // remove jumptable
         setJumpTableDefault64(db->x64_addr);
         // remove and free the sons
         for (int i=0; i<db->sons_size; ++i) {
-            dynablock_t *son = (dynablock_t*)arm64_lock_xchg(&db->sons[i], 0);
-            FreeDynablock(son);
+            dynablock_t *son = (dynablock_t*)native_lock_xchg(&db->sons[i], 0);
+            FreeDynablock(son, 0);
         }
         // only the father free the DynarecMap
         if(!db->father) {
             dynarec_log(LOG_DEBUG, " -- FreeDyrecMap(%p, %d)\n", db->block, db->size);
             FreeDynarecMap(db, (uintptr_t)db->block, db->size);
+            free(db->sons);
+            free(db->instsize);
         }
-        free(db->sons);
-        free(db->instsize);
         free(db);
+        if(need_lock)
+            pthread_mutex_unlock(&my_context->mutex_dyndump);
     }
 }
 
@@ -99,7 +104,7 @@ void FreeDynablockList(dynablocklist_t** dynablocks)
     if((*dynablocks)->direct) {
         for (int i=0; i<(*dynablocks)->textsz; ++i) {
             if((*dynablocks)->direct[i] && !(*dynablocks)->direct[i]->father) 
-                FreeDynablock((*dynablocks)->direct[i]);
+                FreeDynablock((*dynablocks)->direct[i], 1);
         }
         free((*dynablocks)->direct);
     }
@@ -116,7 +121,8 @@ void MarkDynablock(dynablock_t* db)
             db = db->father;    // mark only father
         if(db->need_test)
             return; // already done
-        db->need_test = 1;  // test only blocks that can be marked (and so deleted)
+        dynarec_log(LOG_DEBUG, "MarkDynablock %p with %d son(s) %p-%p\n", db, db->sons_size, db->x64_addr, db->x64_addr+db->x64_size-1);
+        db->need_test = 1;
         setJumpTableDefault64(db->x64_addr);
         for(int i=0; i<db->sons_size; ++i)
             setJumpTableDefault64(db->sons[i]->x64_addr);
@@ -145,30 +151,25 @@ int IntervalIntersects(uintptr_t start1, uintptr_t end1, uintptr_t start2, uintp
 
 void MarkDirectDynablock(dynablocklist_t* dynablocks, uintptr_t addr, uintptr_t size)
 {
+    // Mark will try to find *any* blocks that intersect the range to mark
     if(!dynablocks)
         return;
     if(!dynablocks->direct)
         return;
     uintptr_t startdb = dynablocks->text;
-    uintptr_t enddb = startdb + dynablocks->textsz -1;
-    uintptr_t start = addr;
-    uintptr_t end = addr+size-1;
-    if(start<startdb)
-        start = startdb;
-    if(end>enddb)
-        end = enddb;
+    uintptr_t sizedb = dynablocks->textsz;
     dynablock_t *db;
-    if(end>startdb && start<enddb)
-        for(uintptr_t i = start; i<end; ++i)
-            if((db=dynablocks->direct[i-startdb]))
-                if(IntervalIntersects((uintptr_t)db->x64_addr, (uintptr_t)db->x64_addr+db->x64_size-1, addr, addr+size+1))
-                    MarkDynablock(db);
+    dynarec_log(LOG_DEBUG, "MarkDirectDynablock %p-%p .. startdb=%p, sizedb=%p\n", (void*)addr, (void*)addr+size-1, (void*)startdb, (void*)sizedb);
+    for(uintptr_t i = 0; i<sizedb; ++i)
+        if((db=dynablocks->direct[i]))
+            if(IntervalIntersects((uintptr_t)db->x64_addr, (uintptr_t)db->x64_addr+db->x64_size-1, addr, addr+size+1))
+                MarkDynablock(db);
 }
 
-void FreeRangeDynablock(dynablocklist_t* dynablocks, uintptr_t addr, uintptr_t size)
+int FreeRangeDynablock(dynablocklist_t* dynablocks, uintptr_t addr, uintptr_t size)
 {
     if(!dynablocks)
-        return;
+        return 1;
 
     if(dynablocks->direct) {
         dynablock_t* db;
@@ -176,46 +177,51 @@ void FreeRangeDynablock(dynablocklist_t* dynablocks, uintptr_t addr, uintptr_t s
         khint_t k;
         kh_dynablocks_t *blocks = kh_init(dynablocks);
         // copy in a temporary list
-        if(dynablocks->direct) {
-            uintptr_t startdb = dynablocks->text;
-            uintptr_t enddb = startdb + dynablocks->textsz;
-            uintptr_t start = addr;
-            uintptr_t end = addr+size;
-            if(start<startdb)
-                start = startdb;
-            if(end>enddb)
-                end = enddb;
-            if(end>startdb && start<enddb)
-                for(uintptr_t i = start; i<end; ++i) {
-                    db = (dynablock_t*)arm64_lock_xchg(&dynablocks->direct[i-startdb], 0);
-                    if(db) {
-                        if(db->father)
-                            db = db->father;
-                        if(db->parent==dynablocks) {
-                            k = kh_put(dynablocks, blocks, (uintptr_t)db, &ret);
-                            kh_value(blocks, k) = db;
-                        }
+        uintptr_t startdb = dynablocks->text;
+        uintptr_t enddb = startdb + dynablocks->textsz;
+        uintptr_t start = addr;
+        uintptr_t end = addr+size;
+        if(start<startdb)
+            start = startdb;
+        if(end>enddb)
+            end = enddb;
+        if(end>startdb && start<enddb)
+            for(uintptr_t i = start; i<end; ++i) {
+                db = (dynablock_t*)native_lock_xchg(&dynablocks->direct[i-startdb], 0);
+                if(db) {
+                    if(db->father)
+                        db = db->father;
+                    if(db->parent==dynablocks) {
+                        k = kh_put(dynablocks, blocks, (uintptr_t)db, &ret);
+                        kh_value(blocks, k) = db;
                     }
                 }
-        }
+            }
         // purge the list
         kh_foreach_value(blocks, db,
-            FreeDynablock(db);
+            FreeDynablock(db, 1);
         );
         kh_destroy(dynablocks, blocks);
+        // check emptyness
+        for(uintptr_t i=0; i<dynablocks->textsz; ++i)
+            if(dynablocks->direct[i])
+                return 0;
+        return 1;
     }
+    return 1;
 }
 void MarkRangeDynablock(dynablocklist_t* dynablocks, uintptr_t addr, uintptr_t size)
 {
     if(!dynablocks)
         return;
+    dynarec_log(LOG_DEBUG, "MarkRangeDynablock %p-%p\n", (void*)addr, (void*)addr+size-1);
     if(dynablocks->direct) {
-        uintptr_t new_addr = addr - dynablocks->maxsz;
-        uintptr_t new_size = size + dynablocks->maxsz;
-        MarkDirectDynablock(dynablocks, new_addr, new_size);
+        uintptr_t new_addr = dynablocks->minstart;
+        uintptr_t new_size = dynablocks->maxend - new_addr + 1;
+        MarkDirectDynablock(dynablocks, addr, size);
         // the blocks check before
-        for(int idx=(new_addr)>>DYNAMAP_SHIFT; idx<(addr>>DYNAMAP_SHIFT); ++idx)
-            MarkDirectDynablock(getDB(idx), new_addr, new_size);
+        for(unsigned idx=(new_addr)>>DYNAMAP_SHIFT; idx<(addr>>DYNAMAP_SHIFT); ++idx)
+            MarkDirectDynablock(getDB(idx), addr, size);
     }
 }
 
@@ -254,7 +260,7 @@ dynablock_t *AddNewDynablock(dynablocklist_t* dynablocks, uintptr_t addr, int* c
     if(dynablocks->direct) {
         block = dynablocks->direct[addr-dynablocks->text];
         if(block) {
-            dynarec_log(LOG_DUMP, "Block already exist in Direct Map\n");
+            dynarec_log(LOG_VERBOSE, "Block already exist in Direct Map\n");
             *created = 0;
             return block;
         }
@@ -263,34 +269,45 @@ dynablock_t *AddNewDynablock(dynablocklist_t* dynablocks, uintptr_t addr, int* c
     if (!*created)
         return block;
     
+    pthread_mutex_lock(&my_context->mutex_dyndump);
     if(!dynablocks->direct) {
         dynablock_t** p = (dynablock_t**)calloc(dynablocks->textsz, sizeof(dynablock_t*));
-        if(arm64_lock_storeifnull(&dynablocks->direct, p)!=p)
+        if(native_lock_storeifnull(&dynablocks->direct, p)!=p)
             free(p);    // someone already create the direct array, too late...
     }
 
     // create and add new block
-    dynarec_log(LOG_DUMP, "Ask for DynaRec Block creation @%p\n", (void*)addr);
+    dynarec_log(LOG_VERBOSE, "Ask for DynaRec Block creation @%p\n", (void*)addr);
 
     block = (dynablock_t*)calloc(1, sizeof(dynablock_t));
     block->parent = dynablocks; 
-    dynablock_t* tmp = (dynablock_t*)arm64_lock_storeifnull(&dynablocks->direct[addr-dynablocks->text], block);
+    dynablock_t* tmp = (dynablock_t*)native_lock_storeifnull(&dynablocks->direct[addr-dynablocks->text], block);
     if(tmp !=  block) {
         // a block appeard!
+        pthread_mutex_unlock(&my_context->mutex_dyndump);
         free(block);
         *created = 0;
         return tmp;
     }
 
     *created = 1;
+    pthread_mutex_lock(&my_context->mutex_dyndump);
     return block;
 }
 
+//TODO: move this to dynrec_arm.c and track allocated structure to avoid memory leak
+static __thread struct __jmp_buf_tag dynarec_jmpbuf;
+
+void cancelFillBlock()
+{
+    longjmp(&dynarec_jmpbuf, 1);
+}
+
 /* 
     return NULL if block is not found / cannot be created. 
     Don't create if create==0
 */
-static dynablock_t* internalDBGetBlock(x64emu_t* emu, uintptr_t addr, uintptr_t filladdr, int create, dynablock_t* current)
+static dynablock_t* internalDBGetBlock(x64emu_t* emu, uintptr_t addr, uintptr_t filladdr, int create, dynablock_t* current, int need_lock)
 {
     // try the quickest way first: get parent of current and check if ok!
     dynablocklist_t *dynablocks = NULL;
@@ -319,80 +336,188 @@ static dynablock_t* internalDBGetBlock(x64emu_t* emu, uintptr_t addr, uintptr_t
     if(!created)
         return block;   // existing block...
 
-    #if 0
-    if(box64_dynarec_dump)
-        pthread_mutex_lock(&my_context->mutex_dyndump);
-    #endif
     // fill the block
     block->x64_addr = (void*)addr;
-    pthread_mutex_lock(&my_context->mutex_dyndump);
+    if(need_lock)
+        pthread_mutex_lock(&my_context->mutex_dyndump);
+    if(sigsetjmp(&dynarec_jmpbuf, 1)) {
+        printf_log(LOG_INFO, "FillBlock at %p triggered a segfault, cancelling\n", (void*)addr);
+        if(need_lock)
+            pthread_mutex_unlock(&my_context->mutex_dyndump);
+        return NULL;
+    }
     void* ret = FillBlock64(block, filladdr);
-    pthread_mutex_unlock(&my_context->mutex_dyndump);
+    if(need_lock)
+        pthread_mutex_unlock(&my_context->mutex_dyndump);
     if(!ret) {
         dynarec_log(LOG_DEBUG, "Fillblock of block %p for %p returned an error\n", block, (void*)addr);
-        void* old = (void*)arm64_lock_storeifref(&dynablocks->direct[addr-dynablocks->text], 0, block);
+        void* old = (void*)native_lock_storeifref(&dynablocks->direct[addr-dynablocks->text], 0, block);
         if(old!=block && old) {// put it back in place, strange things are happening here!
             dynarec_log(LOG_INFO, "Warning, a wild block appeared at %p: %p\n", (void*)addr, old);
-            // doing nothing else, the block as not be writen
+            // doing nothing else, the block has not be writen
         }
         free(block);
         block = NULL;
     }
-    #if 0
-    if(box64_dynarec_dump)
-        pthread_mutex_unlock(&my_context->mutex_dyndump);
-    #endif
     // check size
     if(block && block->x64_size) {
+        if(dynablocks->minstart>addr)
+            dynablocks->minstart = addr;
         int blocksz = block->x64_size;
-        if(dynablocks->maxsz<blocksz) {
-            dynablocks->maxsz = blocksz;
-            for(int idx=(addr>>DYNAMAP_SHIFT)+1; idx<=((addr+blocksz)>>DYNAMAP_SHIFT); ++idx) {
+        if(dynablocks->maxend<addr+blocksz) {
+            dynablocks->maxend = addr+blocksz;
+            for(unsigned idx=(addr>>DYNAMAP_SHIFT)+1; idx<=((addr+blocksz-1)>>DYNAMAP_SHIFT); ++idx) {
                 dynablocklist_t* dblist;
                 if((dblist = getDB(idx)))
-                    if(dblist->maxsz<blocksz)
-                        dblist->maxsz = blocksz;
+                    if(dblist->minstart>addr)
+                        dblist->minstart = addr;
             }
         }
-        lockDB();
-        protectDBnolock((uintptr_t)block->x64_addr, block->x64_size);
         // fill-in jumptable
         addJumpTableIfDefault64(block->x64_addr, block->block);
-        for(int i=0; i<block->sons_size; ++i)
+        for(int i=0; i<block->sons_size; ++i) {
             addJumpTableIfDefault64(block->sons[i]->x64_addr, block->sons[i]->block);
-        unlockDB();
+            block->sons[i]->done = 1;
+        }
+        block->done = 1;
     }
 
-    dynarec_log(LOG_DEBUG, " --- DynaRec Block %s @%p:%p (%p, 0x%x bytes, with %d son(s))\n", created?"created":"recycled", (void*)addr, (void*)(addr+((block)?block->x64_size:0)), (block)?block->block:0, (block)?block->size:0, (block)?block->sons_size:0);
+    dynarec_log(LOG_DEBUG, "%04d| --- DynaRec Block %s @%p:%p (%p, 0x%x bytes, with %d son(s))\n", GetTID(), created?"created":"recycled", (void*)addr, (void*)(addr+((block)?block->x64_size:1)-1), (block)?block->block:0, (block)?block->size:0, (block)?block->sons_size:0);
 
     return block;
 }
 
+#define MAX_HOTPAGE 64
+#define HOTPAGE_STEP 64
+static int volatile hotpage_count[MAX_HOTPAGE] = {0};
+static uintptr_t volatile hotpage[MAX_HOTPAGE] = {0};
+static uintptr_t volatile hotpage_size[MAX_HOTPAGE] = {0};
+static volatile int hotpages = 0;
+
+int IsInHotPage(uintptr_t addr) {
+    if(!hotpages)
+        return 0;
+    for(int i=0; i<MAX_HOTPAGE; ++i) {
+        if((hotpage_count[i]>0) && (addr>=hotpage[i]) && (addr<hotpage[i]+0x1000*(hotpage_size[i]+1))) {
+            --hotpage_count[i];
+            if(!hotpage_count[i]) {
+                --hotpages;
+                hotpage_size[i] = 0;
+                dynarec_log(LOG_DEBUG, "End of Hotpage %p\n", (void*)hotpage[i]);
+            }
+            __sync_synchronize();
+            return 1;
+        }
+    }
+    return 0;
+}
+
+int AreaInHotPage(uintptr_t start, uintptr_t end) {
+    if(!hotpages)
+        return 0;
+    for(int i=0; i<MAX_HOTPAGE; ++i) {
+        if(hotpage_count[i]>0)
+            if(IntervalIntersects(start, end, hotpage[i], hotpage[i]+0x1000*(hotpage_size[i]+1)-1)) {
+                --hotpage_count[i];
+                if(!hotpage_count[i]) {
+                    --hotpages;
+                    hotpage_size[i] = 0;
+                    dynarec_log(LOG_DEBUG, "End of Hotpage %p\n", (void*)hotpage[i]);
+                }
+                return 1;
+        }
+    }
+    return 0;
+}
+
+void AddHotPage(uintptr_t addr) {
+    addr&=~0xfff;
+    // look for same address
+    for(int i=0; i<MAX_HOTPAGE; ++i) {
+        if(addr>=hotpage[i] && addr<hotpage[i]+0x1000*(hotpage_size[i]+1)) {
+            if(!hotpage_count[i])
+                ++hotpages;
+            hotpage_count[i] = HOTPAGE_STEP;
+            __sync_synchronize();
+            return;
+        }
+        if(addr==hotpage[i]+0x1000*(hotpage_size[i]+1)) {
+            ++hotpage_size[i];
+            hotpage_count[i] = HOTPAGE_STEP;
+            __sync_synchronize();
+            return;
+        }
+        if(addr+0x1000==hotpage[i]) {
+            ++hotpage_size[i];
+            hotpage[i] = addr;
+            hotpage_count[i] = HOTPAGE_STEP;
+            __sync_synchronize();
+            return;
+        }
+    }
+    // look for empty spot / minium
+    int mincnt = hotpage_count[0];
+    int minidx = 0;
+    for(int i=1; i<MAX_HOTPAGE; ++i)
+        if(hotpage_count[i]<mincnt) {
+            mincnt = hotpage_count[i];
+            minidx = i;
+        }
+    if(hotpage_count[minidx]) {
+        static int cnt = 0;
+        if(cnt<50) {
+            dynarec_log(LOG_NONE, "Warning, not enough Hotpage, replacing %p(%p/%d) with %p\n", (void*)hotpage[minidx], (void*)(0x1000*(hotpage_size[minidx]+1)), hotpage_count[minidx], (void*)addr);
+            ++cnt;
+            if(cnt==50)   // stop spamming console with message...
+                dynarec_log(LOG_NONE, "    will stop warning about not enough Hotpage now\n");
+        }
+        hotpage_size[minidx] = 0;
+    } else
+        ++hotpages;
+    hotpage[minidx] = addr;
+    hotpage_count[minidx] = HOTPAGE_STEP;
+    __sync_synchronize();
+}
+
 dynablock_t* DBGetBlock(x64emu_t* emu, uintptr_t addr, int create, dynablock_t** current)
 {
-    dynablock_t *db = internalDBGetBlock(emu, addr, addr, create, *current);
-    if(db && db->done && db->block && (db->need_test || (db->father && db->father->need_test))) {
-        dynablock_t *father = db->father?db->father:db;
+    dynablock_t *db = internalDBGetBlock(emu, addr, addr, create, *current, 1);
+    dynablock_t *father = (db && db->father)?db->father:db;
+    if(father && father->done && db->block && father->need_test) {
+        if(pthread_mutex_trylock(&my_context->mutex_dyndump)) {
+            dynarec_log(LOG_DEBUG, "mutex_dyndump not available when trying to validate block %p from %p:%p (hash:%X) with %d son(s) for %p\n", db, db->x64_addr, db->x64_addr+db->x64_size-1, db->hash, db->sons_size, (void*)addr);
+            return NULL;
+        }
+        if(AreaInHotPage((uintptr_t)father->x64_addr, (uintptr_t)father->x64_addr + father->x64_size - 1)) {
+            dynarec_log(LOG_DEBUG, "Not running block %p from %p:%p with %d son(s) for %p because it's in a hotpage\n", father, father->x64_addr, father->x64_addr+father->x64_size-1, father->sons_size, (void*)addr);
+            pthread_mutex_unlock(&my_context->mutex_dyndump);
+            return NULL;
+        }
         uint32_t hash = X31_hash_code(father->x64_addr, father->x64_size);
         if(hash!=father->hash) {
-            dynarec_log(LOG_DEBUG, "Invalidating block %p from %p:%p (hash:%X/%X) with %d son(s) for %p\n", father, father->x64_addr, father->x64_addr+father->x64_size, hash, father->hash, father->sons_size, (void*)addr);
+            father->done = 0;   // invalidating the block
+            dynarec_log(LOG_DEBUG, "Invalidating block %p from %p:%p (hash:%X/%X) with %d son(s) for %p\n", father, father->x64_addr, father->x64_addr+father->x64_size-1, hash, father->hash, father->sons_size, (void*)addr);
             // no more current if it gets invalidated too
-            if(*current && father->x64_addr>=(*current)->x64_addr && (father->x64_addr+father->x64_size)<(*current)->x64_addr)
+            if(*current && IntervalIntersects(
+             (uintptr_t)father->x64_addr, 
+             (uintptr_t)father->x64_addr+father->x64_size-1, 
+             (uintptr_t)(*current)->x64_addr, 
+             (uintptr_t)(*current)->x64_addr+(*current)->x64_size-1))
                 *current = NULL;
             // Free father, it's now invalid!
-            FreeDynablock(father);
+            FreeDynablock(father, 0);
             // start again... (will create a new block)
-            db = internalDBGetBlock(emu, addr, addr, create, *current);
+            db = internalDBGetBlock(emu, addr, addr, create, *current, 0);
         } else {
             father->need_test = 0;
-            lockDB();
-            protectDBnolock((uintptr_t)father->x64_addr, father->x64_size);
+            dynarec_log(LOG_DEBUG, "Validating block %p from %p:%p (hash:%X) with %d son(s) for %p\n", father, father->x64_addr, father->x64_addr+father->x64_size-1, father->hash, father->sons_size, (void*)addr);
+            protectDB((uintptr_t)father->x64_addr, father->x64_size);
             // fill back jumptable
             addJumpTableIfDefault64(father->x64_addr, father->block);
             for(int i=0; i<father->sons_size; ++i)
                 addJumpTableIfDefault64(father->sons[i]->x64_addr, father->sons[i]->block);
-            unlockDB();
         }
+        pthread_mutex_unlock(&my_context->mutex_dyndump);
     } 
     return db;
 }
@@ -401,26 +526,28 @@ dynablock_t* DBAlternateBlock(x64emu_t* emu, uintptr_t addr, uintptr_t filladdr)
 {
     dynarec_log(LOG_DEBUG, "Creating AlternateBlock at %p for %p\n", (void*)addr, (void*)filladdr);
     int create = 1;
-    dynablock_t *db = internalDBGetBlock(emu, addr, filladdr, create, NULL);
-    if(db && db->done && db->block && (db->need_test || (db->father && db->father->need_test))) {
-        dynablock_t *father = db->father?db->father:db;
+    dynablock_t *db = internalDBGetBlock(emu, addr, filladdr, create, NULL, 1);
+    dynablock_t *father = (db && db->father)?db->father:db;
+    if(father && father->done && db->block && father->need_test) {
+        if(pthread_mutex_trylock(&my_context->mutex_dyndump))
+            return NULL;
         uint32_t hash = X31_hash_code(father->x64_addr, father->x64_size);
         if(hash!=father->hash) {
+            father->done = 0;   // invalidating the block
             dynarec_log(LOG_DEBUG, "Invalidating alt block %p from %p:%p (hash:%X/%X) with %d son(s) for %p\n", father, father->x64_addr, father->x64_addr+father->x64_size, hash, father->hash, father->sons_size, (void*)addr);
             // Free father, it's now invalid!
-            FreeDynablock(father);
+            FreeDynablock(father, 0);
             // start again... (will create a new block)
-            db = internalDBGetBlock(emu, addr, filladdr, create, NULL);
+            db = internalDBGetBlock(emu, addr, filladdr, create, NULL, 0);
         } else {
             father->need_test = 0;
-            lockDB();
-            protectDBnolock((uintptr_t)father->x64_addr, father->x64_size);
+            protectDB((uintptr_t)father->x64_addr, father->x64_size);
             // fill back jumptable
             addJumpTableIfDefault64(father->x64_addr, father->block);
             for(int i=0; i<father->sons_size; ++i)
                 addJumpTableIfDefault64(father->sons[i]->x64_addr, father->sons[i]->block);
-            unlockDB();
         }
+        pthread_mutex_unlock(&my_context->mutex_dyndump);
     } 
     return db;
 }

src/dynarec/dynablock_private.h

@@ -29,7 +29,8 @@ typedef struct dynablock_s {
 typedef struct dynablocklist_s {
     uintptr_t           text;
     int                 textsz;
-    int                 maxsz;     // maxblock size (for this block or previous block)
+    uintptr_t           maxend;    // max address end for anyblock on this blocklist
+    uintptr_t           minstart;  // min start address for block overlapping this blocklist
     dynablock_t**       direct;    // direct mapping (waste of space, so the array is created at first write)
 } dynablocklist_t;
 

src/dynarec/dynarec.c

@@ -19,21 +19,29 @@
 #ifdef DYNAREC
 #include "dynablock.h"
 #include "dynablock_private.h"
+#include "bridge.h"
 #endif
 
 #ifdef DYNAREC
 #ifdef ARM64
 void arm64_prolog(x64emu_t* emu, void* addr) EXPORTDYN;
 void arm64_epilog() EXPORTDYN;
-void arm64_epilog_fast() EXPORTDYN;
+#define native_prolog       arm64_prolog
+#define native_epilog       arm64_epilog
+#elif defined(LA464)
+void la464_prolog(x64emu_t* emu, void* addr) EXPORTDYN;
+void la464_epilog() EXPORTDYN;
+#define native_prolog       la464_prolog
+#define native_epilog       la464_epilog
+#else
+#error Unsupported architecture
 #endif
 #endif
 
 #ifdef DYNAREC
-#ifdef HAVE_TRACE
 uintptr_t getX64Address(dynablock_t* db, uintptr_t arm_addr);
-#endif
-void* LinkNext(x64emu_t* emu, uintptr_t addr, void* x2)
+
+void* LinkNext(x64emu_t* emu, uintptr_t addr, void* x2, uintptr_t* x3)
 {
     #ifdef HAVE_TRACE
     if(!addr) {
@@ -46,25 +54,41 @@ void* LinkNext(x64emu_t* emu, uintptr_t addr, void* x2)
     dynablock_t* block = DBGetBlock(emu, addr, 1, &current);
     if(!block) {
         // no block, let link table as is...
-dynablock_t* db = FindDynablockFromNativeAddress(x2-4);
-printf_log(LOG_NONE, "Warning, jumping to a no-block address %p from %p (db=%p, x64addr=%p)\n", (void*)addr, x2-4, db, db?(void*)getX64Address(db, (uintptr_t)x2-4):NULL);
-        //tableupdate(arm64_epilog, addr, table);
-        return arm64_epilog;
+        if(hasAlternate((void*)addr)) {
+            printf_log(LOG_DEBUG, "Jmp address has alternate: %p", (void*)addr);
+            addr = (uintptr_t)getAlternate((void*)addr);    // set new address
+            R_RIP = addr;   // but also new RIP!
+            *x3 = addr; // and the RIP in x27 register
+            printf_log(LOG_DEBUG, " -> %p\n", (void*)addr);
+            block = DBGetBlock(emu, addr, 1, &current);
+        }
+        if(!block) {
+            #ifdef HAVE_TRACE
+            dynablock_t* db = FindDynablockFromNativeAddress(x2-4);
+            dynarec_log(LOG_INFO, "Warning, jumping to a no-block address %p from %p (db=%p, x64addr=%p)\n", (void*)addr, x2-4, db, db?(void*)getX64Address(db, (uintptr_t)x2-4):NULL);
+            #endif
+            //tableupdate(native_epilog, addr, table);
+            return native_epilog;
+        }
     }
     if(!block->done) {
         // not finished yet... leave linker
-        //tableupdate(arm_linker, addr, table);
-        return arm64_epilog;
+        return native_epilog;
     }
     if(!(jblock=block->block)) {
         // null block, but done: go to epilog, no linker here
-        return arm64_epilog;
+        return native_epilog;
     }
     //dynablock_t *father = block->father?block->father:block;
     return jblock;
 }
 #endif
 
+#ifdef __GNUC__
+// Disable "clobbered" warnings
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wclobbered"
+#endif
 void DynaCall(x64emu_t* emu, uintptr_t addr)
 {
     // prepare setjump for signal handling
@@ -76,7 +100,7 @@ void DynaCall(x64emu_t* emu, uintptr_t addr)
             ejb->emu = emu;
             ejb->jmpbuf_ok = 1;
             jmpbuf_reset = 1;
-            if(setjmp((struct __jmp_buf_tag*)ejb->jmpbuf)) {
+            if(sigsetjmp((struct __jmp_buf_tag*)ejb->jmpbuf, 1)) {
                 printf_log(LOG_DEBUG, "Setjmp DynaCall, fs=0x%x\n", ejb->emu->segs[_FS]);
                 addr = R_RIP;   // not sure if it should still be inside DynaCall!
             }
@@ -97,23 +121,23 @@ void DynaCall(x64emu_t* emu, uintptr_t addr)
         PushExit(emu);
         R_RIP = addr;
         emu->df = d_none;
-        dynablock_t* block = NULL;
         dynablock_t* current = NULL;
+        dynablock_t* block = DBGetBlock(emu, R_RIP, 1, &current);
+        current = block;
         while(!emu->quit) {
-            block = DBGetBlock(emu, R_RIP, 1, &current);
-            current = block;
             if(!block || !block->block || !block->done) {
                 // no block, of block doesn't have DynaRec content (yet, temp is not null)
                 // Use interpreter (should use single instruction step...)
                 dynarec_log(LOG_DEBUG, "%04d|Calling Interpretor @%p, emu=%p\n", GetTID(), (void*)R_RIP, emu);
                 Run(emu, 1);
+                block = DBGetBlock(emu, R_RIP, 1, &current);
+                current = block;
             } else {
                 dynarec_log(LOG_DEBUG, "%04d|Calling DynaRec Block @%p (%p) of %d x64 instructions (father=%p) emu=%p\n", GetTID(), (void*)R_RIP, block->block, block->isize ,block->father, emu);
                 CHECK_FLAGS(emu);
                 // block is here, let's run it!
-                #ifdef ARM64
-                arm64_prolog(emu, block->block);
-                #endif
+                native_prolog(emu, block->block);
+                block = NULL;
             }
             if(emu->fork) {
                 int forktype = emu->fork;
@@ -125,7 +149,7 @@ void DynaCall(x64emu_t* emu, uintptr_t addr)
                     ejb->emu = emu;
                     ejb->jmpbuf_ok = 1;
                     jmpbuf_reset = 1;
-                    if(setjmp((struct __jmp_buf_tag*)ejb->jmpbuf)) {
+                    if(sigsetjmp((struct __jmp_buf_tag*)ejb->jmpbuf, 1)) {
                         printf_log(LOG_DEBUG, "Setjmp inner DynaCall, fs=0x%x\n", ejb->emu->segs[_FS]);
                         addr = R_RIP;
                     }
@@ -135,7 +159,8 @@ void DynaCall(x64emu_t* emu, uintptr_t addr)
         emu->quit = 0;  // reset Quit flags...
         emu->df = d_none;
         if(emu->quitonlongjmp && emu->longjmp) {
-            emu->longjmp = 0;   // don't change anything because of the longjmp
+            if(emu->quitonlongjmp==1)
+                emu->longjmp = 0;   // don't change anything because of the longjmp
         } else {
             R_RBX = old_rbx;
             R_RDI = old_rdi;
@@ -166,7 +191,7 @@ int DynaRun(x64emu_t* emu)
 #ifdef DYNAREC
             jmpbuf_reset = 1;
 #endif
-            if(setjmp((struct __jmp_buf_tag*)ejb->jmpbuf))
+            if(sigsetjmp((struct __jmp_buf_tag*)ejb->jmpbuf, 1))
                 printf_log(LOG_DEBUG, "Setjmp DynaRun, fs=0x%x\n", ejb->emu->segs[_FS]);
         }
     }
@@ -176,22 +201,22 @@ int DynaRun(x64emu_t* emu)
         return Run(emu, 0);
 #ifdef DYNAREC
     else {
-        dynablock_t* block = NULL;
         dynablock_t* current = NULL;
+        dynablock_t* block = DBGetBlock(emu, R_RIP, 1, &current);;
+        current = block;
         while(!emu->quit) {
-            block = DBGetBlock(emu, R_RIP, 1, &current);
-            current = block;
             if(!block || !block->block || !block->done) {
                 // no block, of block doesn't have DynaRec content (yet, temp is not null)
                 // Use interpreter (should use single instruction step...)
                 dynarec_log(LOG_DEBUG, "%04d|Running Interpretor @%p, emu=%p\n", GetTID(), (void*)R_RIP, emu);
                 Run(emu, 1);
+                block = DBGetBlock(emu, R_RIP, 1, &current);
+                current = block;
             } else {
                 dynarec_log(LOG_DEBUG, "%04d|Running DynaRec Block @%p (%p) of %d x64 insts (father=%p) emu=%p\n", GetTID(), (void*)R_RIP, block->block, block->isize, block->father, emu);
                 // block is here, let's run it!
-                #ifdef ARM64
-                arm64_prolog(emu, block->block);
-                #endif
+                native_prolog(emu, block->block);
+                block = NULL;
             }
             if(emu->fork) {
                 int forktype = emu->fork;
@@ -203,7 +228,7 @@ int DynaRun(x64emu_t* emu)
                     ejb->emu = emu;
                     ejb->jmpbuf_ok = 1;
                     jmpbuf_reset = 1;
-                    if(setjmp((struct __jmp_buf_tag*)ejb->jmpbuf))
+                    if(sigsetjmp((struct __jmp_buf_tag*)ejb->jmpbuf, 1))
                         printf_log(LOG_DEBUG, "Setjmp inner DynaRun, fs=0x%x\n", ejb->emu->segs[_FS]);
                 }
             }
@@ -214,4 +239,7 @@ int DynaRun(x64emu_t* emu)
         ejb->jmpbuf_ok = 0;
     return 0;
 #endif
-}
+}
+#ifdef __GNUC__
+#pragma GCC diagnostic pop
+#endif

src/dynarec/dynarec_arch.h

@@ -0,0 +1,25 @@
+#ifndef __DYNAREC_ARCH__H_
+#define __DYNAREC_ARCH__H_
+
+#ifdef ARM64
+#include "arm64/arm64_printer.h"
+#include "arm64/dynarec_arm64_private.h"
+#include "arm64/dynarec_arm64_functions.h"
+
+#define instruction_native_t        instruction_arm64_t
+#define dynarec_native_t            dynarec_arm_t
+
+#elif defined(LA464)
+#include "la464/la464_printer.h"
+#include "la464/dynarec_la464_private.h"
+#include "la464/dynarec_la464_functions.h"
+
+#define instruction_native_t        instruction_la464_t
+#define dynarec_native_t            dynarec_la464_t
+
+
+#else
+#error Unsupported platform
+#endif
+
+#endif //__DYNAREC_ARCH__H_

src/dynarec/dynarec_arm64_64.c

@@ -1,222 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <stddef.h>
-#include <pthread.h>
-#include <errno.h>
-
-#include "debug.h"
-#include "box64context.h"
-#include "dynarec.h"
-#include "emu/x64emu_private.h"
-#include "emu/x64run_private.h"
-#include "x64run.h"
-#include "x64emu.h"
-#include "box64stack.h"
-#include "callback.h"
-#include "emu/x64run_private.h"
-#include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
-
-#include "dynarec_arm64_helper.h"
-#include "dynarec_arm64_functions.h"
-
-
-uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
-{
-    uint8_t opcode = F8;
-    uint8_t nextop;
-    uint8_t u8;
-    int32_t j32;
-    uint8_t gd, ed, eb1, eb2;
-    uint8_t wback;
-    int64_t i64;
-    int fixedaddress;
-    MAYUSE(j32);
-    MAYUSE(eb1);
-    MAYUSE(eb2);
-
-    while((opcode==0xF2) || (opcode==0xF3)) {
-        rep = opcode-0xF1;
-        opcode = F8;
-    }
-    // REX prefix before the F0 are ignored
-    rex.rex = 0;
-    while(opcode>=0x40 && opcode<=0x4f) {
-        rex.rex = opcode;
-        opcode = F8;
-    }
-
-    switch(opcode) {
-
-        case 0x03:
-            INST_NAME("ADD Gd, FS:Ed");
-            SETFLAGS(X_ALL, SF_SET);
-            grab_segdata(dyn, addr, ninst, x4, _FS);
-            nextop = F8;
-            GETGD;
-            GETEDO(x4, 0);
-            emit_add32(dyn, ninst, rex, gd, ed, x3, x4);
-            break;
-
-        case 0x33:
-            INST_NAME("XOR Gd, FS:Ed");
-            SETFLAGS(X_ALL, SF_SET);
-            grab_segdata(dyn, addr, ninst, x4, _FS);
-            nextop = F8;
-            GETGD;
-            GETEDO(x4, 0);
-            emit_xor32(dyn, ninst, rex, gd, ed, x3, x4);
-            break;
-                    
-        case 0x81:
-        case 0x83:
-            nextop = F8;
-            grab_segdata(dyn, addr, ninst, x6, _FS);
-            switch((nextop>>3)&7) {
-                case 0: //ADD
-                    if(opcode==0x81) {INST_NAME("ADD Ed, Id");} else {INST_NAME("ADD Ed, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
-                    GETEDO(x6, (opcode==0x81)?4:1);
-                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                    emit_add32c(dyn, ninst, rex, ed, i64, x3, x4, x5);
-                    WBACKO(x6);
-                    break;
-                case 1: //OR
-                    if(opcode==0x81) {INST_NAME("OR Ed, Id");} else {INST_NAME("OR Ed, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
-                    GETEDO(x6, (opcode==0x81)?4:1);
-                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                    emit_or32c(dyn, ninst, rex, ed, i64, x3, x4);
-                    WBACKO(x6);
-                    break;
-                case 2: //ADC
-                    if(opcode==0x81) {INST_NAME("ADC Ed, Id");} else {INST_NAME("ADC Ed, Ib");}
-                    READFLAGS(X_CF);
-                    SETFLAGS(X_ALL, SF_SET);
-                    GETEDO(x6, (opcode==0x81)?4:1);
-                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                    MOV64xw(x5, i64);
-                    emit_adc32(dyn, ninst, rex, ed, x5, x3, x4);
-                    WBACKO(x6);
-                    break;
-                case 3: //SBB
-                    if(opcode==0x81) {INST_NAME("SBB Ed, Id");} else {INST_NAME("SBB Ed, Ib");}
-                    READFLAGS(X_CF);
-                    SETFLAGS(X_ALL, SF_SET);
-                    GETEDO(x6, (opcode==0x81)?4:1);
-                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                    MOV64xw(x5, i64);
-                    emit_sbb32(dyn, ninst, rex, ed, x5, x3, x4);
-                    WBACKO(x6);
-                    break;
-                case 4: //AND
-                    if(opcode==0x81) {INST_NAME("AND Ed, Id");} else {INST_NAME("AND Ed, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
-                    GETEDO(x6, (opcode==0x81)?4:1);
-                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                    emit_and32c(dyn, ninst, rex, ed, i64, x3, x4);
-                    WBACKO(x6);
-                    break;
-                case 5: //SUB
-                    if(opcode==0x81) {INST_NAME("SUB Ed, Id");} else {INST_NAME("SUB Ed, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
-                    GETEDO(x6, (opcode==0x81)?4:1);
-                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                    emit_sub32c(dyn, ninst, rex, ed, i64, x3, x4, x5);
-                    WBACKO(x6);
-                    break;
-                case 6: //XOR
-                    if(opcode==0x81) {INST_NAME("XOR Ed, Id");} else {INST_NAME("XOR Ed, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
-                    GETEDO(x6, (opcode==0x81)?4:1);
-                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                    emit_xor32c(dyn, ninst, rex, ed, i64, x3, x4);
-                    WBACKO(x6);
-                    break;
-                case 7: //CMP
-                    if(opcode==0x81) {INST_NAME("CMP Ed, Id");} else {INST_NAME("CMP Ed, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
-                    GETEDO(x6, (opcode==0x81)?4:1);
-                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                    if(i64) {
-                        MOV64xw(x2, i64);
-                        emit_cmp32(dyn, ninst, rex, ed, x2, x3, x4, x5);
-                    } else
-                        emit_cmp32_0(dyn, ninst, rex, ed, x3, x4);
-                    break;
-            }
-            break;
-            
-        case 0x89:
-            INST_NAME("MOV FS:Ed, Gd");
-            grab_segdata(dyn, addr, ninst, x4, _FS);
-            nextop=F8;
-            GETGD;
-            if(MODREG) {   // reg <= reg
-                MOVxw_REG(xRAX+(nextop&7)+(rex.b<<3), gd);
-            } else {                    // mem <= reg
-                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0, rex, 0, 0);
-                STRxw_REG(gd, ed, x4);
-            }
-            break;
-
-        case 0x8B:
-            INST_NAME("MOV Gd, FS:Ed");
-            grab_segdata(dyn, addr, ninst, x4, _FS);
-            nextop=F8;
-            GETGD;
-            if(MODREG) {   // reg <= reg
-                MOVxw_REG(gd, xRAX+(nextop&7)+(rex.b<<3));
-            } else {                    // mem <= reg
-                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0, rex, 0, 0);
-                LDRxw_REG(gd, ed, x4);
-            }
-            break;
-
-        case 0xC6:
-            INST_NAME("MOV FS:Eb, Ib");
-            grab_segdata(dyn, addr, ninst, x4, _FS);
-            nextop=F8;
-            if(MODREG) {   // reg <= u8
-                u8 = F8;
-                if(!rex.rex) {
-                    ed = (nextop&7);
-                    eb1 = xRAX+(ed&3);  // Ax, Cx, Dx or Bx
-                    eb2 = (ed&4)>>2;    // L or H
-                } else {
-                    eb1 = xRAX+(nextop&7)+(rex.b<<3);
-                    eb2 = 0;            
-                }
-                MOV32w(x3, u8);
-                BFIx(eb1, x3, eb2*8, 8);
-            } else {                    // mem <= u8
-                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 1);
-                u8 = F8;
-                MOV32w(x3, u8);
-                STRB_REG(x3, ed, x4);
-            }
-            break;
-        case 0xC7:
-            INST_NAME("MOV FS:Ed, Id");
-            grab_segdata(dyn, addr, ninst, x4, _FS);
-            nextop=F8;
-            if(MODREG) {   // reg <= i32
-                i64 = F32S;
-                ed = xRAX+(nextop&7)+(rex.b<<3);
-                MOV64xw(ed, i64);
-            } else {                    // mem <= i32
-                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0, rex, 0, 4);
-                i64 = F32S;
-                MOV64xw(x3, i64);
-                STRxw_REG(x3, ed, x4);
-            }
-            break;
-
-        default:
-            DEFAULT;
-    }
-    return addr;
-}
-

src/dynarec/dynarec_arm64_67.c

@@ -1,120 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <stddef.h>
-#include <pthread.h>
-#include <errno.h>
-
-#include "debug.h"
-#include "box64context.h"
-#include "dynarec.h"
-#include "emu/x64emu_private.h"
-#include "emu/x64run_private.h"
-#include "x64run.h"
-#include "x64emu.h"
-#include "box64stack.h"
-#include "callback.h"
-#include "emu/x64run_private.h"
-#include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
-
-#include "dynarec_arm64_helper.h"
-#include "dynarec_arm64_functions.h"
-
-
-uintptr_t dynarec64_67(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
-{
-    uint8_t opcode = F8;
-    uint8_t nextop;
-    uint8_t gd, ed;
-    int fixedaddress;
-    int8_t  i8;
-    int32_t i32, j32;
-    MAYUSE(j32);
-    MAYUSE(i32);
-
-    // REX prefix before the 67 are ignored
-    rex.rex = 0;
-    while(opcode>=0x40 && opcode<=0x4f) {
-        rex.rex = opcode;
-        opcode = F8;
-    }
-
-    switch(opcode) {
-
-        case 0x8D:
-            INST_NAME("LEA Gd, Ed");
-            nextop=F8;
-            GETGD;
-            if(MODREG) {   // reg <= reg? that's an invalid operation
-                DEFAULT;
-            } else {                    // mem <= reg
-                // should a geted32 be created, to use 32bits regs instead of 64bits?
-                addr = geted32(dyn, addr, ninst, nextop, &ed, gd, &fixedaddress, 0, 0, rex, 0, 0);
-                if(ed!=gd) {
-                    MOVw_REG(gd, ed);
-                }
-            }
-            break;
-
-        #define GO(NO, YES)   \
-            BARRIER(2); \
-            JUMP(addr+i8);\
-            if(dyn->insts) {    \
-                if(dyn->insts[ninst].x64.jmp_insts==-1) {   \
-                    /* out of the block */                  \
-                    i32 = dyn->insts[ninst+1].address-(dyn->arm_size); \
-                    Bcond(NO, i32);     \
-                    jump_to_next(dyn, addr+i8, 0, ninst); \
-                } else {    \
-                    /* inside the block */  \
-                    i32 = dyn->insts[dyn->insts[ninst].x64.jmp_insts].address-(dyn->arm_size);    \
-                    Bcond(YES, i32);    \
-                }   \
-            }
-        case 0xE0:
-            INST_NAME("LOOPNZ (32bits)");
-            READFLAGS(X_ZF);
-            i8 = F8S;
-            MOVw_REG(x1, xRCX);
-            SUBSw_U12(x1, x1, 1);
-            BFIx(xRCX, x1, 0, 32);
-            B_NEXT(cEQ);    // ECX is 0, no LOOP
-            TSTw_mask(xFlags, 0b011010, 0); //mask=0x40
-            GO(cNE, cEQ);
-            break;
-        case 0xE1:
-            INST_NAME("LOOPZ (32bits)");
-            READFLAGS(X_ZF);
-            i8 = F8S;
-            MOVw_REG(x1, xRCX);
-            SUBSw_U12(x1, x1, 1);
-            BFIx(xRCX, x1, 0, 32);
-            B_NEXT(cEQ);    // ECX is 0, no LOOP
-            TSTw_mask(xFlags, 0b011010, 0); //mask=0x40
-            GO(cEQ, cNE);
-            break;
-        case 0xE2:
-            INST_NAME("LOOP (32bits)");
-            i8 = F8S;
-            MOVw_REG(x1, xRCX);
-            SUBSw_U12(x1, x1, 1);
-            BFIx(xRCX, x1, 0, 32);
-            GO(cEQ, cNE);
-            break;
-        case 0xE3:
-            INST_NAME("JECXZ");
-            i8 = F8S;
-            MOVw_REG(x1, xRCX);
-            TSTw_REG(x1, x1);
-            GO(cNE, cEQ);
-            break;
-        #undef GO
-
-        default:
-            DEFAULT;
-    }
-    return addr;
-}
-

src/dynarec/dynarec_arm64_f0.c

@@ -1,444 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <stddef.h>
-#include <pthread.h>
-#include <errno.h>
-
-#include "debug.h"
-#include "box64context.h"
-#include "dynarec.h"
-#include "emu/x64emu_private.h"
-#include "emu/x64run_private.h"
-#include "x64run.h"
-#include "x64emu.h"
-#include "box64stack.h"
-#include "callback.h"
-#include "emu/x64run_private.h"
-#include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
-
-#include "dynarec_arm64_helper.h"
-#include "dynarec_arm64_functions.h"
-
-
-uintptr_t dynarec64_F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
-{
-    uint8_t opcode = F8;
-    uint8_t nextop;
-    int32_t j32;
-    uint8_t gd, ed;
-    uint8_t wback, wb2, gb1, gb2;
-    int64_t i64;
-    int fixedaddress;
-    MAYUSE(gb1);
-    MAYUSE(gb2);
-    MAYUSE(wb2);
-    MAYUSE(j32);
-
-    while((opcode==0xF2) || (opcode==0xF3)) {
-        rep = opcode-0xF1;
-        opcode = F8;
-    }
-    // REX prefix before the F0 are ignored
-    rex.rex = 0;
-    while(opcode>=0x40 && opcode<=0x4f) {
-        rex.rex = opcode;
-        opcode = F8;
-    }
-
-    switch(opcode) {
-        case 0x00:
-            INST_NAME("LOCK ADD Eb, Gb");
-            SETFLAGS(X_ALL, SF_SET);
-            nextop = F8;
-            GETGB(x2);
-            if((nextop&0xC0)==0xC0) {
-                if(rex.rex) {
-                    wback = xRAX + (nextop&7) + (rex.b<<3);
-                    wb2 = 0;
-                } else {
-                    wback = (nextop&7);    
-                    wb2 = (wback>>2);      
-                    wback = xRAX+(wback&3);
-                }
-                UBFXw(x1, wback, wb2*8, 8);   
-                emit_add8(dyn, ninst, x1, x2, x4, x3);
-                BFIx(wback, x1, wb2*8, 8);
-            } else {                   
-                addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0, 0, rex, 0, 0);
-                MARKLOCK;
-                LDAXRB(x1, wback);
-                emit_add8(dyn, ninst, x1, x2, x4, x3);
-                STLXRB(x4, x1, wback);
-                CBNZx_MARKLOCK(x4);
-            }
-            break;
-        case 0x01:
-            INST_NAME("LOCK ADD Ed, Gd");
-            SETFLAGS(X_ALL, SF_SET);
-            nextop = F8;
-            GETGD;
-            if((nextop&0xC0)==0xC0) {
-                ed = xRAX+(nextop&7)+(rex.b<<3);
-                emit_add32(dyn, ninst, rex, ed, gd, x3, x4);
-            } else {
-                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, 0);
-                MARKLOCK;
-                LDAXRxw(x1, wback);
-                emit_add32(dyn, ninst, rex, x1, gd, x3, x4);
-                STLXRxw(x3, x1, wback);
-                CBNZx_MARKLOCK(x3);
-            }
-            break;
-
-        case 0x0F:
-            nextop = F8;
-            switch(nextop) {
-
-                case 0xB1:
-                    INST_NAME("LOCK CMPXCHG Ed, Gd");
-                    SETFLAGS(X_ALL, SF_SET);
-                    nextop = F8;
-                    GETGD;
-                    if(MODREG) {
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
-                        wback = 0;
-                        UFLAG_IF {emit_cmp32(dyn, ninst, rex, xRAX, ed, x3, x4, x5);}
-                        MOVxw_REG(x1, ed);  // save value
-                        CMPSxw_REG(xRAX, x1);
-                        B_MARK2(cNE);
-                        MOVxw_REG(ed, gd);
-                        MARK2;
-                        MOVxw_REG(xRAX, x1);
-                        B_NEXT_nocond;
-                    } else {
-                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, 0);
-                        TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
-                        B_MARK3(cNE);
-                        // Aligned version
-                        MARKLOCK;
-                        LDAXRxw(x1, wback);
-                        CMPSxw_REG(xRAX, x1);
-                        B_MARK(cNE);
-                        // EAX == Ed
-                        STLXRxw(x4, gd, wback);
-                        CBNZx_MARKLOCK(x4);
-                        // done
-                        B_MARK_nocond;
-                        // Unaligned version
-                        MARK3;
-                        LDRxw_U12(x1, wback, 0);
-                        LDAXRB(x3, wback); // dummy read, to arm the write...
-                        CMPSxw_REG(xRAX, x1);
-                        B_MARK(cNE);
-                        // EAX == Ed
-                        STLXRB(x4, gd, wback);
-                        CBNZx_MARK3(x4);
-                        STRxw_U12(gd, wback, 0);
-                        MARK;
-                        // Common part (and fallback for EAX != Ed)
-                        UFLAG_IF {emit_cmp32(dyn, ninst, rex, xRAX, x1, x3, x4, x5);}
-                        MOVxw_REG(xRAX, x1);    // upper par of RAX will be erase on 32bits, no mater what
-                    }
-                    break;
-
-                case 0xC1:
-                    INST_NAME("LOCK XADD Gd, Ed");
-                    SETFLAGS(X_ALL, SF_SET);
-                    nextop = F8;
-                    GETGD;
-                    if(MODREG) {
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
-                        MOVxw_REG(x1, ed);
-                        MOVxw_REG(ed, gd);
-                        MOVxw_REG(gd, x1);
-                        emit_add32(dyn, ninst, rex, ed, gd, x3, x4);
-                    } else {
-                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, 0);
-                        TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
-                        B_MARK(cNE);    // unaligned
-                        MARKLOCK;
-                        LDAXRxw(x1, wback);
-                        ADDxw_REG(x4, x1, gd);
-                        STLXRxw(x3, x4, wback);
-                        CBNZx_MARKLOCK(x3);
-                        B_MARK2_nocond;
-                        MARK;
-                        LDRxw_U12(x1, wback, 0);
-                        LDAXRB(x4, wback);
-                        BFIxw(x1, x4, 0, 8);
-                        ADDxw_REG(x4, x1, gd);
-                        STLXRB(x3, x4, wback);
-                        CBNZx_MARK(x3);
-                        STRxw_U12(x4, wback, 0);
-                        MARK2;
-                        IFX(X_ALL|X_PEND) {
-                            MOVxw_REG(x2, x1);
-                            emit_add32(dyn, ninst, rex, x2, gd, x3, x4);
-                        }
-                        MOVxw_REG(gd, x1);
-                    }
-                    break;
-
-                case 0xC7:
-                    INST_NAME("LOCK CMPXCHG8B Gq, Eq");
-                    SETFLAGS(X_ZF, SF_SET);
-                    nextop = F8;
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x1, &fixedaddress, 0, 0, rex, 0, 0);
-                    MARKLOCK;
-                    LDAXPxw(x2, x3, wback);
-                    CMPSxw_REG(xRAX, x2);
-                    B_MARK(cNE);    // EAX != Ed[0]
-                    CMPSxw_REG(xRDX, x3);
-                    B_MARK(cNE);    // EDX != Ed[1]
-                    STLXPxw(x4, xRBX, xRCX, wback);
-                    CBNZx_MARKLOCK(x4);
-                    MOV32w(x1, 1);
-                    B_MARK3_nocond;
-                    MARK;
-                    MOVxw_REG(xRAX, x2);
-                    MOVxw_REG(xRDX, x3);
-                    MOV32w(x1, 0);
-                    MARK3;
-                    BFIw(xFlags, x1, F_ZF, 1);
-                    break;
-
-                default:
-                    DEFAULT;
-            }
-            break;
-                    
-        case 0x29:
-            INST_NAME("LOCK SUB Ed, Gd");
-            SETFLAGS(X_ALL, SF_SET);
-            nextop = F8;
-            GETGD;
-            if(MODREG) {
-                ed = xRAX+(nextop&7)+(rex.b<<3);
-                emit_sub32(dyn, ninst, rex, ed, gd, x3, x4);
-            } else {
-                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, 0);
-                MARKLOCK;
-                LDAXRxw(x1, wback);
-                emit_sub32(dyn, ninst, rex, x1, gd, x3, x4);
-                STLXRxw(x3, x1, wback);
-                CBNZx_MARKLOCK(x3);
-            }
-            break;
-
-        case 0x81:
-        case 0x83:
-            nextop = F8;
-            switch((nextop>>3)&7) {
-                case 0: //ADD
-                    if(opcode==0x81) {
-                        INST_NAME("LOCK ADD Ed, Id");
-                    } else {
-                        INST_NAME("LOCK ADD Ed, Ib");
-                    }
-                    SETFLAGS(X_ALL, SF_SET);
-                    if(MODREG) {
-                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
-                        MOV64xw(x5, i64);
-                        emit_add32(dyn, ninst, rex, ed, x5, x3, x4);
-                    } else {
-                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?4:1);
-                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        MOV64xw(x5, i64);
-                        TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
-                        B_MARK(cNE);
-                        MARKLOCK;
-                        LDAXRxw(x1, wback);
-                        emit_add32(dyn, ninst, rex, x1, x5, x3, x4);
-                        STLXRxw(x3, x1, wback);
-                        CBNZx_MARKLOCK(x3);
-                        B_NEXT_nocond;
-                        MARK;   // unaligned! also, not enough 
-                        LDRxw_U12(x1, wback, 0);
-                        LDAXRB(x4, wback);
-                        BFIxw(x1, x4, 0, 8); // re-inject
-                        emit_add32(dyn, ninst, rex, x1, x5, x3, x4);
-                        STLXRB(x3, x1, wback);
-                        CBNZx_MARK(x3);
-                        STRxw_U12(x1, wback, 0);    // put the whole value
-                    }
-                    break;
-                case 1: //OR
-                    if(opcode==0x81) {INST_NAME("LOCK OR Ed, Id");} else {INST_NAME("LOCK OR Ed, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
-                    if(MODREG) {
-                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
-                        MOV64xw(x5, i64);
-                        emit_or32(dyn, ninst, rex, ed, x5, x3, x4);
-                    } else {
-                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?4:1);
-                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        MOV64xw(x5, i64);
-                        MARKLOCK;
-                        LDAXRxw(x1, wback);
-                        emit_or32(dyn, ninst, rex, x1, x5, x3, x4);
-                        STLXRxw(x3, x1, wback);
-                        CBNZx_MARKLOCK(x3);
-                    }
-                    break;
-                case 2: //ADC
-                    if(opcode==0x81) {INST_NAME("LOCK ADC Ed, Id");} else {INST_NAME("LOCK ADC Ed, Ib");}
-                    READFLAGS(X_CF);
-                    SETFLAGS(X_ALL, SF_SET);
-                    if(MODREG) {
-                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
-                        MOV64xw(x5, i64);
-                        emit_adc32(dyn, ninst, rex, ed, x5, x3, x4);
-                    } else {
-                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?4:1);
-                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        MOV64xw(x5, i64);
-                        MARKLOCK;
-                        LDAXRxw(x1, wback);
-                        emit_adc32(dyn, ninst, rex, x1, x5, x3, x4);
-                        STLXRxw(x3, x1, wback);
-                        CBNZx_MARKLOCK(x3);
-                    }
-                    break;
-                case 3: //SBB
-                    if(opcode==0x81) {INST_NAME("LOCK SBB Ed, Id");} else {INST_NAME("LOCK SBB Ed, Ib");}
-                    READFLAGS(X_CF);
-                    SETFLAGS(X_ALL, SF_SET);
-                    if(MODREG) {
-                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
-                        MOV64xw(x5, i64);
-                        emit_sbb32(dyn, ninst, rex, ed, x5, x3, x4);
-                    } else {
-                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?4:1);
-                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        MOV64xw(x5, i64);
-                        MARKLOCK;
-                        LDAXRxw(x1, wback);
-                        emit_sbb32(dyn, ninst, rex, x1, x5, x3, x4);
-                        STLXRxw(x3, x1, wback);
-                        CBNZx_MARKLOCK(x3);
-                    }
-                    break;
-                case 4: //AND
-                    if(opcode==0x81) {INST_NAME("LOCK AND Ed, Id");} else {INST_NAME("LOCK AND Ed, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
-                    if(MODREG) {
-                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
-                        MOV64xw(x5, i64);
-                        emit_and32(dyn, ninst, rex, ed, x5, x3, x4);
-                    } else {
-                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?4:1);
-                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        MOV64xw(x5, i64);
-                        MARKLOCK;
-                        LDAXRxw(x1, wback);
-                        emit_and32(dyn, ninst, rex, x1, x5, x3, x4);
-                        STLXRxw(x3, x1, wback);
-                        CBNZx_MARKLOCK(x3);
-                    }
-                    break;
-                case 5: //SUB
-                    if(opcode==0x81) {INST_NAME("LOCK SUB Ed, Id");} else {INST_NAME("LOCK SUB Ed, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
-                    if(MODREG) {
-                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
-                        MOV64xw(x5, i64);
-                        emit_sub32(dyn, ninst, rex, ed, x5, x3, x4);
-                    } else {
-                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?4:1);
-                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        MOV64xw(x5, i64);
-                        TSTx_mask(wback, 1, 0, 1+rex.w);    // mask=3 or 7
-                        B_MARK(cNE);
-                        MARKLOCK;
-                        LDAXRxw(x1, wback);
-                        emit_sub32(dyn, ninst, rex, x1, x5, x3, x4);
-                        STLXRxw(x3, x1, wback);
-                        CBNZx_MARKLOCK(x3);
-                        B_NEXT_nocond;
-                        MARK;   // unaligned! also, not enough 
-                        LDRxw_U12(x1, wback, 0);
-                        LDAXRB(x4, wback);
-                        BFIxw(x1, x4, 0, 8); // re-inject
-                        emit_sub32(dyn, ninst, rex, x1, x5, x3, x4);
-                        STLXRB(x3, x1, wback);
-                        CBNZx_MARK(x3);
-                        STRxw_U12(x1, wback, 0);    // put the whole value
-                    }
-                    break;
-                case 6: //XOR
-                    if(opcode==0x81) {INST_NAME("LOCK XOR Ed, Id");} else {INST_NAME("LOCK XOR Ed, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
-                    if(MODREG) {
-                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        ed = xRAX+(nextop&7)+(rex.b<<3);
-                        MOV64xw(x5, i64);
-                        emit_xor32(dyn, ninst, rex, ed, x5, x3, x4);
-                    } else {
-                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, 0, 0, rex, 0, (opcode==0x81)?4:1);
-                        if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                        MOV64xw(x5, i64);
-                        MARKLOCK;
-                        LDAXRxw(x1, wback);
-                        emit_xor32(dyn, ninst, rex, x1, x5, x3, x4);
-                        STLXRxw(x3, x1, wback);
-                        CBNZx_MARKLOCK(x3);
-                    }
-                    break;
-                case 7: //CMP
-                    if(opcode==0x81) {INST_NAME("(LOCK) CMP Ed, Id");} else {INST_NAME("(LOCK) CMP Ed, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
-                    GETED(0);
-                    // No need to LOCK, this is readonly
-                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                    if(i64) {
-                        MOV64xw(x5, i64);
-                        emit_cmp32(dyn, ninst, rex, ed, x5, x3, x4, x6);
-                    } else {
-                        emit_cmp32_0(dyn, ninst, rex, ed, x3, x4);
-                    }
-                    break;
-            }
-            break;
-            
-        case 0x87:
-            INST_NAME("LOCK XCHG Ed, Gd");
-            nextop = F8;
-            if(MODREG) {
-                GETGD;
-                GETED(0);
-                MOVxw_REG(x1, gd);
-                MOVxw_REG(gd, ed);
-                MOVxw_REG(ed, x1);
-            } else {
-                GETGD;
-                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0, rex, 0, 0);
-                TSTx_mask(ed, 1, 0, 1+rex.w);    // mask=3 or 7
-                B_MARK(cNE);
-                MARKLOCK;
-                LDAXRxw(x1, ed);
-                STLXRxw(x3, gd, ed);
-                CBNZx_MARKLOCK(x3);
-                B_MARK2_nocond;
-                MARK;
-                LDRxw_U12(x1, ed, 0);
-                STRxw_U12(gd, ed, 0);
-                MARK2;
-                MOVxw_REG(gd, x1);
-            }
-            break;
-            
-        default:
-            DEFAULT;
-    }
-    return addr;
-}
-

src/dynarec/dynarec_arm64_functions.c

@@ -1,335 +0,0 @@
-#define _GNU_SOURCE
-#include <stdio.h>
-#include <stdlib.h>
-#include <pthread.h>
-#include <errno.h>
-#include <string.h>
-#include <math.h>
-#include <signal.h>
-#include <sys/types.h>
-#include <unistd.h>
-
-#include "debug.h"
-#include "box64context.h"
-#include "dynarec.h"
-#include "emu/x64emu_private.h"
-#include "tools/bridge_private.h"
-#include "x64run.h"
-#include "x64emu.h"
-#include "box64stack.h"
-#include "callback.h"
-#include "emu/x64run_private.h"
-#include "emu/x87emu_private.h"
-#include "x64trace.h"
-#include "signals.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "dynarec_arm64_functions.h"
-
-void arm_fstp(x64emu_t* emu, void* p)
-{
-    if(ST0.q!=STld(0).ref)
-        D2LD(&ST0.d, p);
-    else
-        memcpy(p, &STld(0).ld, 10);
-}
-
-void arm_print_armreg(x64emu_t* emu, uintptr_t reg, uintptr_t n)
-{
-    dynarec_log(LOG_DEBUG, "R%ld=0x%lx (%ld)\n", n, reg, reg);
-}
-
-void arm_f2xm1(x64emu_t* emu)
-{
-    ST0.d = exp2(ST0.d) - 1.0;
-}
-void arm_fyl2x(x64emu_t* emu)
-{
-    ST(1).d = log2(ST0.d)*ST(1).d;
-}
-void arm_ftan(x64emu_t* emu)
-{
-    ST0.d = tan(ST0.d);
-}
-void arm_fpatan(x64emu_t* emu)
-{
-    ST1.d = atan2(ST1.d, ST0.d);
-}
-void arm_fxtract(x64emu_t* emu)
-{
-    int32_t tmp32s = (ST1.q&0x7ff0000000000000LL)>>52;
-    tmp32s -= 1023;
-    ST1.d /= exp2(tmp32s);
-    ST0.d = tmp32s;
-}
-void arm_fprem(x64emu_t* emu)
-{
-    int32_t tmp32s = ST0.d / ST1.d;
-    ST0.d -= ST1.d * tmp32s;
-    emu->sw.f.F87_C2 = 0;
-    emu->sw.f.F87_C0 = (tmp32s&1);
-    emu->sw.f.F87_C3 = ((tmp32s>>1)&1);
-    emu->sw.f.F87_C1 = ((tmp32s>>2)&1);
-}
-void arm_fyl2xp1(x64emu_t* emu)
-{
-    ST(1).d = log2(ST0.d + 1.0)*ST(1).d;
-}
-void arm_fsincos(x64emu_t* emu)
-{
-    sincos(ST1.d, &ST1.d, &ST0.d);
-}
-void arm_frndint(x64emu_t* emu)
-{
-    ST0.d = fpu_round(emu, ST0.d);
-}
-void arm_fscale(x64emu_t* emu)
-{
-    ST0.d *= exp2(trunc(ST1.d));
-}
-void arm_fsin(x64emu_t* emu)
-{
-    ST0.d = sin(ST0.d);
-}
-void arm_fcos(x64emu_t* emu)
-{
-    ST0.d = cos(ST0.d);
-}
-
-void arm_fbld(x64emu_t* emu, uint8_t* ed)
-{
-    fpu_fbld(emu, ed);
-}
-
-void arm_fild64(x64emu_t* emu, int64_t* ed)
-{
-    int64_t tmp;
-    memcpy(&tmp, ed, sizeof(tmp));
-    ST0.d = tmp;
-    STll(0).ll = tmp;
-    STll(0).ref = ST0.q;
-}
-
-void arm_fbstp(x64emu_t* emu, uint8_t* ed)
-{
-    fpu_fbst(emu, ed);
-}
-
-void arm_fistp64(x64emu_t* emu, int64_t* ed)
-{
-    // used of memcpy to avoid aligments issues
-    if(STll(0).ref==ST(0).q) {
-        memcpy(ed, &STll(0).ll, sizeof(int64_t));
-    } else {
-        int64_t tmp;
-        if(isgreater(ST0.d, (double)(int64_t)0x7fffffffffffffffLL) || isless(ST0.d, (double)(int64_t)0x8000000000000000LL) || !isfinite(ST0.d))
-            tmp = 0x8000000000000000LL;
-        else
-            tmp = fpu_round(emu, ST0.d);
-        memcpy(ed, &tmp, sizeof(tmp));
-    }
-}
-
-void arm_fistt64(x64emu_t* emu, int64_t* ed)
-{
-    // used of memcpy to avoid aligments issues
-    int64_t tmp = ST0.d;
-    memcpy(ed, &tmp, sizeof(tmp));
-}
-
-void arm_fld(x64emu_t* emu, uint8_t* ed)
-{
-    memcpy(&STld(0).ld, ed, 10);
-    LD2D(&STld(0), &ST(0).d);
-    STld(0).ref = ST0.q;
-}
-
-void arm_ud(x64emu_t* emu)
-{
-    emit_signal(emu, SIGILL, (void*)R_RIP, 0);
-}
-
-void arm_fsave(x64emu_t* emu, uint8_t* ed)
-{
-    fpu_savenv(emu, (char*)ed, 0);
-
-    uint8_t* p = ed;
-    p += 28;
-    for (int i=0; i<8; ++i) {
-        LD2D(p, &ST(i).d);
-        p+=10;
-    }
-}
-void arm_frstor(x64emu_t* emu, uint8_t* ed)
-{
-    fpu_loadenv(emu, (char*)ed, 0);
-
-    uint8_t* p = ed;
-    p += 28;
-    for (int i=0; i<8; ++i) {
-        D2LD(&ST(i).d, p);
-        p+=10;
-    }
-
-}
-
-void arm_fprem1(x64emu_t* emu)
-{
-    // simplified version
-    int32_t tmp32s = round(ST0.d / ST1.d);
-    ST0.d -= ST1.d*tmp32s;
-    emu->sw.f.F87_C2 = 0;
-    emu->sw.f.F87_C0 = (tmp32s&1);
-    emu->sw.f.F87_C3 = ((tmp32s>>1)&1);
-    emu->sw.f.F87_C1 = ((tmp32s>>2)&1);
-}
-#define XMM0    0
-#define XMM8    16
-#define X870    8
-#define EMM0    8
-#define SCRATCH0    24
-
-// Get a FPU scratch reg
-int fpu_get_scratch(dynarec_arm_t* dyn)
-{
-    return SCRATCH0 + dyn->fpu_scratch++;  // return an Sx
-}
-// Reset scratch regs counter
-void fpu_reset_scratch(dynarec_arm_t* dyn)
-{
-    dyn->fpu_scratch = 0;
-}
-// Get a x87 double reg
-int fpu_get_reg_x87(dynarec_arm_t* dyn)
-{
-    int i=X870;
-    while (dyn->fpuused[i]) ++i;
-    dyn->fpuused[i] = 1;
-    return i; // return a Dx
-}
-// Free a FPU double reg
-void fpu_free_reg(dynarec_arm_t* dyn, int reg)
-{
-    // TODO: check upper limit?
-    dyn->fpuused[reg] = 0;
-}
-// Get an MMX double reg
-int fpu_get_reg_emm(dynarec_arm_t* dyn, int emm)
-{
-    dyn->fpuused[EMM0 + emm] = 1;
-    return EMM0 + emm;
-}
-// Get an XMM quad reg
-int fpu_get_reg_xmm(dynarec_arm_t* dyn, int xmm)
-{
-    if(xmm>7) {
-        dyn->fpuused[XMM8 + xmm - 8] = 1;
-        return XMM8 + xmm - 8;
-    } else {
-        dyn->fpuused[XMM0 + xmm] = 1;
-        return XMM0 + xmm;
-    }
-}
-// Reset fpu regs counter
-void fpu_reset_reg(dynarec_arm_t* dyn)
-{
-    dyn->fpu_reg = 0;
-    for (int i=0; i<32; ++i)
-        dyn->fpuused[i]=0;
-}
-
-#define F8      *(uint8_t*)(addr++)
-#define F32     *(uint32_t*)(addr+=4, addr-4)
-#define F32S64  (uint64_t)(int64_t)*(int32_t*)(addr+=4, addr-4)
-// Get if ED will have the correct parity. Not emiting anything. Parity is 2 for DWORD or 3 for QWORD
-int getedparity(dynarec_arm_t* dyn, int ninst, uintptr_t addr, uint8_t nextop, int parity, int delta)
-{
-
-    uint32_t tested = (1<<parity)-1;
-    if((nextop&0xC0)==0xC0)
-        return 0;   // direct register, no parity...
-    if(!(nextop&0xC0)) {
-        if((nextop&7)==4) {
-            uint8_t sib = F8;
-            int sib_reg = (sib>>3)&7;
-            if((sib&0x7)==5) {
-                uint64_t tmp = F32S64;
-                if (sib_reg!=4) {
-                    // if XXXXXX+reg<<N then check parity of XXXXX and N should be enough
-                    return ((tmp&tested)==0 && (sib>>6)>=parity)?1:0;
-                } else {
-                    // just a constant...
-                    return (tmp&tested)?0:1;
-                }
-            } else {
-                if(sib_reg==4 && parity<3)
-                    return 0;   // simple [reg]
-                // don't try [reg1 + reg2<<N], unless reg1 is ESP
-                return ((sib&0x7)==4 && (sib>>6)>=parity)?1:0;
-            }
-        } else if((nextop&7)==5) {
-            uint64_t tmp = F32S64;
-            tmp+=addr+delta;
-            return (tmp&tested)?0:1;
-        } else {
-            return 0;
-        }
-    } else {
-        return 0; //Form [reg1 + reg2<<N + XXXXXX]
-    }
-}
-
-// Do the GETED, but don't emit anything...
-uintptr_t fakeed(dynarec_arm_t* dyn, uintptr_t addr, int ninst, uint8_t nextop) 
-{
-    if((nextop&0xC0)==0xC0)
-        return addr;
-    if(!(nextop&0xC0)) {
-        if((nextop&7)==4) {
-            uint8_t sib = F8;
-            if((sib&0x7)==5) {
-                addr+=4;
-            }
-        } else if((nextop&7)==5) {
-            addr+=4;
-        }
-    } else {
-        if((nextop&7)==4) {
-            ++addr;
-        }
-        if(nextop&0x80) {
-            addr+=4;
-        } else {
-            ++addr;
-        }
-    }
-    return addr;
-}
-#undef F8
-#undef F32
-
-int isNativeCall(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t* calladdress, int* retn)
-{
-#define PK(a)       *(uint8_t*)(addr+a)
-#define PK32(a)     *(int32_t*)(addr+a)
-
-    if(!addr)
-        return 0;
-    if(PK(0)==0xff && PK(1)==0x25) {            // "absolute" jump, maybe the GOT (well, RIP relative in fact)
-        uintptr_t a1 = addr + 6 + (PK32(2));    // need to add a check to see if the address is from the GOT !
-        addr = *(uintptr_t*)a1; 
-    }
-    if(addr<0x10000)    // too low, that is suspicious
-        return 0;
-    onebridge_t *b = (onebridge_t*)(addr);
-    if(b->CC==0xCC && b->S=='S' && b->C=='C' && b->w!=(wrapper_t)0 && b->f!=(uintptr_t)PltResolver) {
-        // found !
-        if(retn) *retn = (b->C3==0xC2)?b->N:0;
-        if(calladdress) *calladdress = addr+1;
-        return 1;
-    }
-    return 0;
-#undef PK32
-#undef PK
-}
-

src/dynarec/dynarec_arm64_pass.c

@@ -1,136 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <stddef.h>
-#include <pthread.h>
-#include <errno.h>
-
-#include "debug.h"
-#include "box64context.h"
-#include "dynarec.h"
-#include "emu/x64emu_private.h"
-#include "emu/x64run_private.h"
-#include "x64run.h"
-#include "x64emu.h"
-#include "box64stack.h"
-#include "emu/x64run_private.h"
-#include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
-#include "dynarec_arm64_functions.h"
-#include "dynarec_arm64_helper.h"
-#include "custommem.h"
-
-#ifndef STEP
-#error No STEP defined
-#endif
-
-uintptr_t arm_pass(dynarec_arm_t* dyn, uintptr_t addr)
-{
-    int ok = 1;
-    int ninst = 0;
-    uintptr_t ip = addr;
-    uintptr_t init_addr = addr;
-    rex_t rex;
-    int rep;    // 0 none, 1=F2 prefix, 2=F3 prefix
-    int need_epilog = 1;
-    dyn->sons_size = 0;
-    // Clean up (because there are multiple passes)
-    dyn->state_flags = 0;
-    dyn->dfnone = 0;
-    dyn->last_ip = ip;  // RIP is always set at start of block!
-    MAYUSE(init_addr);
-    fpu_reset(dyn, ninst);
-    // ok, go now
-    INIT;
-    while(ok) {
-        ip = addr;
-        if(dyn->insts && (dyn->insts[ninst].x64.barrier==1)) {
-            dyn->last_ip = 0;
-            NEW_BARRIER_INST;
-        }
-        NEW_INST;
-        fpu_reset_scratch(dyn);
-#ifdef HAVE_TRACE
-        if(my_context->dec && box64_dynarec_trace) {
-        if((trace_end == 0) 
-            || ((ip >= trace_start) && (ip < trace_end)))  {
-                MESSAGE(LOG_DUMP, "TRACE ----\n");
-                fpu_reflectcache(dyn, ninst, x1, x2, x3);
-                GETIP(ip);
-                MOVx_REG(x1, xRIP);
-                STORE_XEMU_CALL(xRIP);
-                MOV32w(x2, 1);
-                CALL(PrintTrace, -1);
-                LOAD_XEMU_CALL(xRIP);
-                MESSAGE(LOG_DUMP, "----------\n");
-            }
-        }
-#endif
-
-        rep = 0;
-        uint8_t pk = PK(0);
-        while((pk==0xF2) || (pk==0xF3)) {
-            rep = pk-0xF1;
-            ++addr;
-            pk = PK(0);
-        }
-        rex.rex = 0;
-        while(pk>=0x40 && pk<=0x4f) {
-            rex.rex = pk;
-            ++addr;
-            pk = PK(0);
-        }
-
-        addr = dynarec64_00(dyn, addr, ip, ninst, rex, rep, &ok, &need_epilog);
-
-        INST_EPILOG;
-
-        if(dyn->insts && dyn->insts[ninst+1].x64.barrier) {
-            fpu_purgecache(dyn, ninst, x1, x2, x3);
-            if(dyn->insts[ninst+1].x64.barrier!=2) {
-                dyn->state_flags = 0;
-                dyn->dfnone = 0;
-            }
-        }
-        if(!ok && !need_epilog && dyn->insts && (addr < (dyn->start+dyn->isize))) {
-            ok = 1;
-        }
-        if(!ok && !need_epilog && !dyn->insts && getProtection(addr+3))
-            if(*(uint32_t*)addr!=0) {   // check if need to continue (but is next 4 bytes are 0, stop)
-                uintptr_t next = get_closest_next(dyn, addr);
-                if(next && (
-                    (((next-addr)<15) && is_nops(dyn, addr, next-addr)) 
-                    ||(((next-addr)<30) && is_instructions(dyn, addr, next-addr)) ))
-                {
-                    dynarec_log(LOG_DEBUG, "Extend block %p, %p -> %p (ninst=%d)\n", dyn, (void*)addr, (void*)next, ninst);
-                    ok = 1;
-                } else if(next && (next-addr)<30) {
-                    dynarec_log(LOG_DEBUG, "Cannot extend block %p -> %p (%02X %02X %02X %02X %02X %02X %02X %02x)\n", (void*)addr, (void*)next, PK(0), PK(1), PK(2), PK(3), PK(4), PK(5), PK(6), PK(7));
-                }
-            }
-        if(ok<0)  {ok = 0; need_epilog=1;}
-        ++ninst;
-        #if STEP == 0
-        if(ok && !isJumpTableDefault64((void*)addr))
-        #else
-        if(ok && dyn->insts && (ninst==dyn->size))
-        #endif
-        {
-            #if STEP == 3
-            dynarec_log(LOG_DEBUG, "Stopping block %p (%d / %d)\n",(void*)init_addr, ninst, dyn->size); 
-            #endif
-            BARRIER(2);
-            fpu_purgecache(dyn, ninst, x1, x2, x3);
-            jump_to_next(dyn, addr, 0, ninst);
-            ok=0; need_epilog=0;
-        }
-    }
-    if(need_epilog) {
-        fpu_purgecache(dyn, ninst, x1, x2, x3);
-        jump_to_epilog(dyn, ip, 0, ninst);  // no linker here, it's an unknow instruction
-    }
-    FINI;
-    MESSAGE(LOG_DUMP, "---- END OF BLOCK ---- (%d, %d sons)\n", dyn->size, dyn->sons_size);
-    return addr;
-}

src/dynarec/dynarec_arm64_pass0.h

@@ -1,25 +0,0 @@
-
-#define INIT    uintptr_t sav_addr=addr
-#define FINI    dyn->isize = addr-sav_addr
-#define MESSAGE(A, ...)  
-#define SETFLAGS(A, B)  
-#define READFLAGS(A)    
-#define EMIT(A)     
-#define JUMP(A)         add_next(dyn, (uintptr_t)A)
-#define NEW_INST        ++dyn->size
-#define INST_EPILOG         
-#define INST_NAME(name) 
-#define DEFAULT                         \
-        --dyn->size;                    \
-        *ok = -1;                       \
-        if(box64_dynarec_log>=LOG_INFO) {\
-        dynarec_log(LOG_NONE, "%p: Dynarec stopped because of Opcode %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X", \
-        (void*)ip, PKip(0),             \
-        PKip(1), PKip(2), PKip(3),      \
-        PKip(4), PKip(5), PKip(6),      \
-        PKip(7), PKip(8), PKip(9),      \
-        PKip(10),PKip(11),PKip(12),     \
-        PKip(13),PKip(14));             \
-        printFunctionAddr(ip, " => ");  \
-        dynarec_log(LOG_NONE, "\n");    \
-        }

src/dynarec/dynarec_arm64_pass1.h

@@ -1,17 +0,0 @@
-#define INIT    
-#define FINI     \
-    dyn->insts[ninst].x64.addr = addr; \
-    if(ninst) dyn->insts[ninst-1].x64.size = dyn->insts[ninst].x64.addr - dyn->insts[ninst-1].x64.addr;
-#define MESSAGE(A, ...)  
-#define EMIT(A)     
-#define READFLAGS(A)    dyn->insts[ninst].x64.use_flags = A
-#define SETFLAGS(A,B)   {dyn->insts[ninst].x64.set_flags = A; dyn->insts[ninst].x64.state_flags = B;}
-#define JUMP(A)         dyn->insts[ninst].x64.jmp = A
-#define BARRIER(A)      dyn->insts[ninst].x64.barrier = A
-#define BARRIER_NEXT(A) if(ninst<dyn->size) dyn->insts[ninst+1].x64.barrier = A
-
-#define NEW_INST \
-    dyn->insts[ninst].x64.addr = ip; \
-    if(ninst) dyn->insts[ninst-1].x64.size = dyn->insts[ninst].x64.addr - dyn->insts[ninst-1].x64.addr;
-#define INST_EPILOG 
-#define INST_NAME(name)  

src/dynarec/dynarec_arm64_pass2.h

@@ -1,11 +0,0 @@
-#define INIT        dyn->arm_size = 0
-#define FINI        if(ninst) {dyn->insts[ninst].address = (dyn->insts[ninst-1].address+dyn->insts[ninst-1].size);}
-
-#define MESSAGE(A, ...)  
-#define EMIT(A)     dyn->insts[ninst].size+=4; dyn->arm_size+=4
-#define NEW_INST    if(ninst) {dyn->insts[ninst].address = (dyn->insts[ninst-1].address+dyn->insts[ninst-1].size);}
-#define INST_EPILOG dyn->insts[ninst].epilog = dyn->arm_size; 
-#define INST_NAME(name) 
-#define NEW_BARRIER_INST    if(ninst) ++dyn->sons_size
-#define TABLE64(A, V)   {Table64(dyn, (V)); EMIT(0);}
-#define FTABLE64(A, V)  {mmx87_regs_t v = {.d = V}; Table64(dyn, v.q); EMIT(0);}

src/dynarec/dynarec_arm64_pass3.h

@@ -1,36 +0,0 @@
-#define INIT    
-#define FINI
-#define EMIT(A)     \
-    if(box64_dynarec_dump) {dynarec_log(LOG_NONE, "\t%08x\t%s\n", (uint32_t)(A), arm64_print(A, (uintptr_t)dyn->block));} \
-    *(uint32_t*)(dyn->block) = (uint32_t)(A);       \
-    dyn->block += 4; dyn->arm_size += 4;\
-    dyn->insts[ninst].size2 += 4
-
-#define MESSAGE(A, ...)  if(box64_dynarec_dump) dynarec_log(LOG_NONE, __VA_ARGS__)
-#define NEW_INST        
-#define INST_EPILOG     
-#define INST_NAME(name) \
-    if(box64_dynarec_dump) {\
-        printf_x64_instruction(my_context->dec, &dyn->insts[ninst].x64, name); \
-        dynarec_log(LOG_NONE, "%s%p: %d emited opcodes, state=%d/%d, set=%X, use=%X, need=%X%s\n", \
-            (box64_dynarec_dump>1)?"\e[32m":"", \
-            (void*)(dyn->arm_start+dyn->insts[ninst].address),  \
-            dyn->insts[ninst].size/4,           \
-            dyn->insts[ninst].x64.state_flags,  \
-            dyn->state_flags,                   \
-            dyn->insts[ninst].x64.set_flags,    \
-            dyn->insts[ninst].x64.use_flags,    \
-            dyn->insts[ninst].x64.need_flags,   \
-            (box64_dynarec_dump>1)?"\e[m":"");  \
-    }
-
-#define NEW_BARRIER_INST                            \
-    if(ninst) {                                     \
-    dyn->sons_x64[dyn->sons_size] = (uintptr_t)ip;  \
-    dyn->sons_arm[dyn->sons_size] = dyn->block;     \
-    MESSAGE(LOG_DUMP, "----> potential Son here\n");\
-    ++dyn->sons_size;                               \
-    }
-
-#define TABLE64(A, V)   {int val64offset = Table64(dyn, (V)); MESSAGE(LOG_DUMP, "  Table64: 0x%lx\n", (V)); LDRx_literal(A, val64offset);}
-#define FTABLE64(A, V)  {mmx87_regs_t v = {.d = V}; int val64offset = Table64(dyn, v.q); MESSAGE(LOG_DUMP, "  FTable64: %g\n", v.d); VLDR64_literal(A, val64offset);}

src/dynarec/dynarec_arm64_private.h

@@ -1,62 +0,0 @@
-#ifndef __DYNAREC_ARM_PRIVATE_H_
-#define __DYNAREC_ARM_PRIVATE_H_
-
-#include "dynarec_private.h"
-
-typedef struct x64emu_s x64emu_t;
-
-typedef struct instruction_arm_s {
-    instruction_x64_t   x64;
-    uintptr_t           address;    // (start) address of the arm emited instruction
-    uintptr_t           epilog;     // epilog of current instruction (can be start of next, of barrier stuff)
-    int                 size;       // size of the arm emited instruction
-    int                 size2;      // size of the arm emited instrucion after pass2
-    uintptr_t           mark, mark2, mark3;
-    uintptr_t           markf;
-    uintptr_t           markseg;
-    uintptr_t           marklock;
-    int                 pass2choice;// value for choices that are fixed on pass2 for pass3
-    uintptr_t           natcall;
-    int                 retn;
-} instruction_arm64_t;
-
-typedef struct dynarec_arm_s {
-    instruction_arm64_t *insts;
-    int32_t             size;
-    int32_t             cap;
-    uintptr_t           start;      // start of the block
-    uint32_t            isize;      // size in byte of x64 instructions included
-    void*               block;      // memory pointer where next instruction is emited
-    uintptr_t           arm_start;  // start of the arm code
-    int                 arm_size;   // size of emitted arm code
-    int                 state_flags;// actual state for on-demand flags
-    uintptr_t           last_ip;    // last set IP in RIP (or NULL if unclean state)
-    int8_t              x87cache[8];// cache status for the 8 x87 register behind the fpu stack
-    int8_t              x87reg[8];  // reg used for x87cache entry
-    int8_t              mmxcache[8];// cache status for the 8 MMX registers
-    int8_t              ssecache[16];// cache status for the 16 SSE(2) registers
-    int8_t              fpuused[32];// all 8..31 Q reg from fpu, used by x87, sse and mmx
-    int                 x87stack;   // cache stack counter
-    int                 fpu_scratch;// scratch counter
-    int                 fpu_reg;    // x87/sse/mmx reg counter
-    int                 dfnone;     // if defered flags is already set to df_none
-    uint64_t            *table64;   // table of 64bits value
-    int                 table64size;// size of table (will be appended at end of executable code)
-    int                 table64cap;
-    uintptr_t           tablestart;
-    uintptr_t*          next;       // variable array of "next" jump address
-    int                 next_sz;
-    int                 next_cap;
-    uintptr_t*          sons_x64;   // the x64 address of potential dynablock sons
-    void**              sons_arm;   // the arm address of potential dynablock sons
-    int                 sons_size;  // number of potential dynablock sons
-} dynarec_arm_t;
-
-void add_next(dynarec_arm_t *dyn, uintptr_t addr);
-uintptr_t get_closest_next(dynarec_arm_t *dyn, uintptr_t addr);
-int is_nops(dynarec_arm_t *dyn, uintptr_t addr, int n);
-int is_instructions(dynarec_arm_t *dyn, uintptr_t addr, int n);
-
-int Table64(dynarec_arm_t *dyn, uint64_t val);  // add a value to etable64 (if needed) and gives back the imm19 to use in LDR_literal
-
-#endif //__DYNAREC_ARM_PRIVATE_H_

src/dynarec/dynarec_helper.h

@@ -0,0 +1,12 @@
+#ifndef __DYNAREC_HELPER__H_
+#define __DYNAREC_HELPER__H_
+
+#ifdef ARM64
+#include "arm64/dynarec_arm64_helper.h"
+#elif defined(LA464)
+#include "la464/dynarec_la464_helper.h"
+#else
+#error Unsupported architecture
+#endif
+
+#endif //__DYNAREC_HELPER__H_