Bumped version to v0.2.4

Added some opcodes

.github/FUNDING.yml

@@ -0,0 +1,12 @@
+# These are supported funding model platforms
+
+github: ptitSeb
+patreon: # Replace with a single Patreon username
+open_collective: # Replace with a single Open Collective username
+ko_fi: # Replace with a single Ko-fi username
+tidelift: # Replace with a single Tidelift platform-name/package-name e.g., npm/babel
+community_bridge: # Replace with a single Community Bridge project-name e.g., cloud-foundry
+liberapay: # Replace with a single Liberapay username
+issuehunt: # Replace with a single IssueHunt username
+otechie: # Replace with a single Otechie username
+custom: paypal.me/0ptitSeb

.github/workflows/manual.yml

@@ -0,0 +1,96 @@
+### Manual build Box64 with Github Action
+name: Custom build Box64
+
+on:
+  workflow_dispatch:
+    inputs:
+      platform:
+        description: 'Target platform name'
+        required: true
+        default: 'GENERIC_ARM'
+        type: choice
+        options:
+        - X64
+        - GENERIC_ARM
+        - PHYTIUM
+        - RK3326
+        - RK3399
+        - RK3588
+        - RPI4ARM64
+        - SD845
+        - TEGRAX1
+        - ARM64
+      build_type:
+        description: 'Build type'
+        required: true
+        default: 'RelWithDebInfo'
+        type: choice
+        options:
+        - RelWithDebInfo
+        - Release
+        - Debug
+        - MinSizeRel
+      dynarec:
+        description: 'Enable dynarec'
+        required: false
+        default: 'true'
+        type: boolean
+      trace:
+        description: 'Enable trace'
+        required: false
+        default: 'false'
+        type: boolean
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    steps:
+      - name: "Checkout Box64 Repository"
+        uses: actions/checkout@v2
+
+      - name: "Environment preparation"
+        run: |
+          sudo apt-get update
+          if [[ ${{ github.event.inputs.platform }} != 'X64' && ${{ github.event.inputs.platform }} != 'GENERIC_ARM' ]]; then
+            echo "BOX64_PLATFORM_MARCRO=-D${{ github.event.inputs.platform }}=1" >> $GITHUB_ENV
+            echo "BOX64_COMPILER=aarch64-linux-gnu-gcc" >> $GITHUB_ENV
+            sudo apt-get -y install git gcc-aarch64-linux-gnu cmake make python3
+          else
+            if [[ ${{ github.event.inputs.platform }} == 'X64' ]]; then
+              echo "BOX64_PLATFORM_MARCRO=-DLD80BITS=1 -DNOALIGN=1" >> $GITHUB_ENV
+              echo "BOX64_COMPILER=gcc" >> $GITHUB_ENV
+              sudo apt-get -y install git cmake make python3
+            else
+              echo BOX64_PLATFORM_MARCRO="-DARM_DYNAREC=ON" >> $GITHUB_ENV
+              echo "BOX64_COMPILER=aarch64-linux-gnu-gcc" >> $GITHUB_ENV
+              sudo apt-get -y install git gcc-aarch64-linux-gnu cmake make python3
+            fi
+          fi
+
+      - name: "Display Build info"
+        run: |
+          echo "CMake Platform Macro: ${{ env.BOX64_PLATFORM_MARCRO }}"
+          echo "CMake C Compiler: ${{ env.BOX64_COMPILER }}"
+          echo "Build type: ${{ github.event.inputs.build_type }}"
+          echo "Dynarec Enabled: ${{ github.event.inputs.dynarec }}"
+          echo "Trace Enabled: ${{ github.event.inputs.trace }}"
+
+      - name: "Build Box64"
+        run: |
+          mkdir build
+          cd build
+          cmake .. -DCMAKE_C_COMPILER=${{ env.BOX64_COMPILER }} ${{ env.BOX64_PLATFORM_MARCRO }}\
+                   -DCMAKE_BUILD_TYPE=${{ github.event.inputs.build_type }}\
+                   -DARM_DYNAREC:BOOL=${{ github.event.inputs.dynarec }}\
+                   -DHAVE_TRACE:BOOL=${{ github.event.inputs.trace }}\
+                   -DCMAKE_VERBOSE_MAKEFILE:BOOL=ON
+          make -j$(nproc) VERBOSE=1
+
+      - name: "Upload Artifact"
+        uses: actions/upload-artifact@v2
+        with:
+          name: box64-${{ github.event.inputs.platform }}-${{ github.event.inputs.build_type }}
+          path: build/box64
+
+
+

.github/workflows/release.yml

@@ -0,0 +1,114 @@
+### Auto build Box64 and release its binary with Github Action
+name: Build and Release Box64
+
+on:
+  workflow_dispatch:
+  release:
+  push:
+    paths:
+      - "**/*.c"
+      - "**/*.h"
+      - "**/*.S"
+      - "**/*.py"
+      - "CMakeLists.txt"
+      - "**/*.yml"
+  pull_request:
+    types: [assigned, opened, synchronize, reopened]
+    paths:
+      - "**/*.c"
+      - "**/*.h"
+      - "**/*.S"
+      - "**/*.py"
+      - "CMakeLists.txt"
+      - "**/*.yml"
+
+jobs:
+  build:
+    strategy:
+      fail-fast: false
+      matrix:
+        platform: [X64, OTHER_ARM, RISCV, RPI4ARM64, RK3326, RK3399, RK3588, PHYTIUM, SD845, ARM64]
+        type: [Release, Trace]
+        os: [ubuntu-latest]
+        include:
+          - platform: TEGRAX1
+            type: Release
+            os: ubuntu-20.04
+          - platform: TEGRAX1
+            type: Trace
+            os: ubuntu-20.04
+
+    runs-on: ${{ matrix.os }}
+    steps:
+      - name: "Checkout Box64 Repository"
+        uses: actions/checkout@v3
+
+      - name: "Environment preparation"
+        run: |
+          sudo apt-get update
+          if [[ ${{ matrix.platform }} != 'X64' && ${{ matrix.platform }} != 'OTHER_ARM' && ${{ matrix.platform }} != 'RISCV' ]]; then
+            echo "BOX64_PLATFORM_MARCRO=-D${{ matrix.platform }}=1" >> $GITHUB_ENV
+            echo "BOX64_COMPILER=aarch64-linux-gnu-gcc" >> $GITHUB_ENV
+            sudo apt-get -y install git gcc-aarch64-linux-gnu cmake make python3
+          else
+            if [[ ${{ matrix.platform }} == 'X64' ]]; then
+              echo "BOX64_PLATFORM_MARCRO=-DLD80BITS=1 -DNOALIGN=1" >> $GITHUB_ENV
+              echo "BOX64_COMPILER=gcc" >> $GITHUB_ENV
+              sudo apt-get -y install git cmake make python3
+            elif [[ ${{ matrix.platform }} == 'RISCV' ]]; then
+              echo BOX64_PLATFORM_MARCRO="-DRV64=ON" >> $GITHUB_ENV
+              echo "BOX64_COMPILER=riscv64-linux-gnu-gcc" >> $GITHUB_ENV
+              sudo apt-get -y install git gcc-riscv64-linux-gnu cmake make python3
+            else
+              echo BOX64_PLATFORM_MARCRO="-DARM_DYNAREC=ON" >> $GITHUB_ENV
+              echo "BOX64_COMPILER=aarch64-linux-gnu-gcc" >> $GITHUB_ENV
+              sudo apt-get -y install git gcc-aarch64-linux-gnu cmake make python3
+            fi
+          fi
+          if [[ ${{ matrix.type }} == 'Release' ]]; then
+            echo BOX64_BUILD_TYPE=Release >> $GITHUB_ENV
+            echo BOX64_HAVE_TRACE=0 >> $GITHUB_ENV
+          else
+            echo BOX64_BUILD_TYPE=RelWithDebInfo >> $GITHUB_ENV
+            echo BOX64_HAVE_TRACE=1 >> $GITHUB_ENV
+          fi
+
+      - name: "Display Build info"
+        run: |
+          echo "CMake Platform Macro: ${{ env.BOX64_PLATFORM_MARCRO }}"
+          echo "CMake C Compiler: ${{ env.BOX64_COMPILER }}"
+          echo "Build type: ${{ env.BOX64_BUILD_TYPE }}"
+          echo "Trace Enabled: ${{ env.BOX64_HAVE_TRACE }}"
+
+      - name: "Build Box64"
+        run: |
+          mkdir build
+          cd build
+          cmake .. -DCMAKE_C_COMPILER=${{ env.BOX64_COMPILER }}\
+                   ${{ env.BOX64_PLATFORM_MARCRO }}\
+                   -DCMAKE_BUILD_TYPE=${{ env.BOX64_BUILD_TYPE }}\
+                   -DHAVE_TRACE=${{ env.BOX64_HAVE_TRACE }}\
+                   -DCMAKE_VERBOSE_MAKEFILE:BOOL=ON
+          make -j$(nproc) VERBOSE=1
+
+      - name: "Test Box64"
+        if: ${{ matrix.platform != 'TEGRAX1' }}
+        run: |
+          if [[ ${{ matrix.platform }} != 'X64' ]]; then
+            sudo apt-get -y install qemu-user
+          fi
+
+          cd build
+          if [[ ${{ matrix.platform }} == 'RISCV' ]]; then
+            QEMU_LD_PREFIX=/usr/riscv64-linux-gnu/ ctest -j$(nproc) --rerun-failed --output-on-failure
+          elif [[ ${{ matrix.platform }} != 'X64' ]]; then
+            QEMU_LD_PREFIX=/usr/aarch64-linux-gnu/ ctest -j$(nproc) --rerun-failed --output-on-failure
+          else
+            ctest -j$(nproc) --rerun-failed --output-on-failure
+          fi
+
+      - name: "Upload Artifact"
+        uses: actions/upload-artifact@v3
+        with:
+          name: box64-${{ matrix.platform }}-${{ matrix.type }}
+          path: build/box64

.gitignore

@@ -55,7 +55,16 @@ dkms.conf
 build/
 build*/
 .vscode
+.cache
 .gdb_history
 src/git_head.h
 backup/
 
+# LLVMprivateGenerator
+/LLVMprivateGenerator/*
+!/LLVMprivateGenerator/Makefile
+!/LLVMprivateGenerator/main.cpp
+!/LLVMprivateGenerator/registered_structs.cpp
+
+# macOS
+.DS_Store

.travis.yml

@@ -0,0 +1,24 @@
+language: c
+arch:
+  - amd64
+  - arm64-graviton2
+os: linux
+dist: focal
+
+compiler:
+    - gcc
+
+addons:
+  apt:
+    packages:
+      - python3
+
+      #Build steps
+before_script:
+    - mkdir build
+    - cd build
+    - if [ "$TRAVIS_CPU_ARCH" = "arm64" ]; then cmake .. -DRK3399=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo ; else cmake .. -DLD80BITS=1 -DNOALIGN=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo ; fi
+
+script:
+    - make
+    - ctest --output-on-failure

CHANGELOG.md

@@ -1,27 +0,0 @@
-v0.0.6
-======
-* Added Dynarec for ARM64
-* Many general CPU opcode added to the Dynarec
-* Many SSEx opcodes added to the Dynarec
-* Added a few more symbols in libc
-* A few changes to the "thread once" handling
-* New Logo and Icon from @grayduck
-
-v0.0.4
-======
-* Added a lot of opcodes
-* Added SDL1 and SDL2 wrapping
-* OpenGL/GLU wrapping done
-* libasound / libpulse wrapping done
-* libopenal / libalure / libalut wrapping done
-* Many X11 libs wrapped
-* Added "install" with binfmt integration
-* A few games are actualy starting now (old WorldOfGoo, Into The Breach, VVVVVV and Thimbeweed Park)
-
-v0.0.2
-======
-* Using box86 as a base, implemented most planned box64 part except dynarec
-* Wrapped a few libs
-* ELF loader a bit crude, but seems working
-* Signal handling implemented
-* MMX and x87 are sharing their registers

COMPILE.md

@@ -1,75 +0,0 @@
-Compiling
-----
-#### for RK3399
-
-Using a 64bits OS:
-```
-git clone https://github.com/ptitSeb/box64
-cd box64
-mkdir build; cd build; cmake .. -DRK3399=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
-make -j4
-sudo make install
-```
-If it's the first install, you also need:
-```
-sudo systemctl restart systemd-binfmt
-```
-
-#### for PI4
-
-Warning, you need a 64bits OS:
-
-```
-git clone https://github.com/ptitSeb/box64
-cd box64
-mkdir build; cd build; cmake .. -DRPI4ARM64=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo
-make -j4
-sudo make install
-```
-If it's the first install, you also need:
-```
-sudo systemctl restart systemd-binfmt
-```
-
-#### for Other ARM64 Linux platforms
-
- `mkdir build; cd build; cmake .. -DARM_DYNAREC=ON -DCMAKE_BUILD_TYPE=RelWithDebInfo; make -j$(nproc)`
-
-#### for x86_64 Linux
-
- `mkdir build; cd build; cmake .. -DLD80BITS=1 -DNOALIGN=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo; make -j$(nproc)`
-
-#### use ccmake
-
-Alternatively, you can use the curses-bases ccmake (or any other gui frontend for cmake) to select wich platform to use interactively.
-
-#### Customize your build
-
-*use ccache if you have it* 
-
-Add `-DUSE_CCACHE=1` if you have ccache (it's better if you plan to touch the sources)
-
-*have some debug info* 
-
-The `-DCMAKE_BUILD_TYPE=RelWithDebInfo` argument makes a build that is both optimized for speed, and has debug information embedded. That way, if you have a crash or try to analyse performance, you'll have some symbols.
-
-*to have a Trace Enabled build* 
-
-To have a trace enabled build ( ***it will be slower***), add `-DHAVE_TRACE=1` but you will need, at runtime, to have the [Zydis library](https://github.com/zyantific/zydis) library in your `LD_LIBRARY_PATH` or in the system library folders.
-
-*to have ARM Dynarec*
-
-The Dynarec is only available on the ARM architecture(Right now, anyways.). Notes also that VFPv3 and NEON are required for the Dynarec. Activate it by using `-DARM_DYNAREC=1`. Also, be sure to use `-marm` in compilation flags (because many compileur use Thumb as default, and the dynarec will not work in this mode).
-
-*not building from a git clone*
-
-If you are not building from a git clone (for example, downloading a release source zipped from github), you need to activate `-DNOGIT=1` from cmake to be able to build (normal process include git sha1 of HEAD in the version that box64 print).
-
-----
-
-Testing
-----
-A few tests are included.
-They can be launched with `ctest`
-They are very basic and don't test much for now.
-

LLVMprivateGenerator/Makefile

@@ -0,0 +1,12 @@
+all: dumpSigs
+
+dumpSigs: main.o registered_structs.o
+	g++ -g3 -std=gnu++17 -fno-rtti main.o registered_structs.o -o dumpSigs "-L$(LLVM_install_dir)/lib" -lclang-cpp -lclangTooling -Wl,-rpath "-Wl,$(LLVM_install_dir)/lib"
+
+main.o: main.cpp
+	g++ -g3 -std=gnu++17 -fno-rtti -c main.cpp -Wfatal-errors "-I$(LLVM_install_dir)/include" -o main.o
+registered_structs.o: registered_structs.cpp
+	g++ -g3 -std=gnu++17 -fno-rtti -c registered_structs.cpp -Wfatal-errors -o registered_structs.o
+
+clean:
+	$(RM) dumpSigs main.o registered_structs.o

LLVMprivateGenerator/main.cpp

@@ -0,0 +1,458 @@
+#include <algorithm>
+#include <fstream>
+#include <iostream>
+#include <numeric>
+#include <unordered_map>
+#include <utility>
+#include <vector>
+
+#include <llvm/Support/raw_ostream.h>
+#include <clang/AST/ASTConsumer.h>
+#include <clang/AST/Decl.h>
+#include <clang/AST/Mangle.h>
+#include <clang/AST/PrettyPrinter.h>
+#include <clang/AST/RecursiveASTVisitor.h>
+#include <clang/Frontend/CompilerInstance.h>
+#include <clang/Frontend/FrontendActions.h>
+#include <clang/Tooling/CommonOptionsParser.h>
+#include <clang/Tooling/Tooling.h>
+
+clang::MangleContext *mangler = nullptr;
+
+std::unordered_map<std::string, std::pair<std::string, bool>> funMap;
+std::vector<std::string> funList;
+
+bool isTypeTrivial(const clang::QualType &q, const clang::QualType *qorig);
+clang::QualType getPointedType(const clang::QualType q) {
+	if (const clang::PointerType *p = q->getAs<clang::PointerType>())
+		return getPointedType(p->getPointeeType());
+	else if (const clang::ReferenceType *r = q->getAs<clang::ReferenceType>())
+		return getPointedType(r->getPointeeType());
+	else
+		return q;
+}
+
+std::string record2name(const clang::RecordDecl &q, const clang::QualType *qorig) {
+	std::string s = q.getNameAsString();
+	if (s == "") {
+		if (!qorig) return "????.!";
+		if (const clang::TypedefType *tt = (*qorig)->getAs<clang::TypedefType>()) {
+			// Typedef
+			if (clang::TypedefNameDecl *td = tt->getDecl()) {
+				return td->getNameAsString();
+			} else {
+				return "<typedef with no declaration>";
+			}
+		} else {
+			return std::string("<unknown type ") + (*qorig)->getTypeClassName() + ">";
+		}
+	} else {
+		return s;
+	}
+}
+
+char ptr2char(const std::string &str) __attribute__((const));
+const char *ptr2str(const std::string &str) __attribute__((const));
+char type2char(const clang::QualType &qual /* Canonical */, const clang::QualType *qorig) {
+	if (qual->isBuiltinType()) {
+		switch (static_cast<const clang::BuiltinType&>(*qual).getKind()) {
+		case clang::BuiltinType::Kind::Void:
+			return 'v';
+		case clang::BuiltinType::Kind::Bool:
+			return 'i';
+		case clang::BuiltinType::Kind::Char_U:
+			return 'C';
+		case clang::BuiltinType::Kind::Char_S:
+			return 'c';
+		case clang::BuiltinType::Kind::Char8:
+			return 'c';
+		case clang::BuiltinType::Kind::UChar:
+			return 'C';
+		case clang::BuiltinType::Kind::SChar:
+			return 'c';
+		case clang::BuiltinType::Kind::WChar_U:
+			return 'W';
+		case clang::BuiltinType::Kind::UShort:
+			return 'W';
+		case clang::BuiltinType::Kind::WChar_S:
+			return 'w';
+		case clang::BuiltinType::Kind::Char16:
+			return 'w';
+		case clang::BuiltinType::Kind::Short:
+			return 'w';
+		case clang::BuiltinType::Kind::UInt:
+			return 'u';
+		case clang::BuiltinType::Kind::Char32:
+			return 'i';
+		case clang::BuiltinType::Kind::Int:
+			return 'i';
+		case clang::BuiltinType::Kind::ULong:
+			return 'L';
+		case clang::BuiltinType::Kind::Long:
+			return 'l';
+		case clang::BuiltinType::Kind::ULongLong:
+			return 'U';
+		case clang::BuiltinType::Kind::LongLong:
+			return 'I';
+		case clang::BuiltinType::Kind::UInt128:
+			return 'H';
+		case clang::BuiltinType::Kind::Int128:
+			return 'H';
+		case clang::BuiltinType::Kind::Float:
+			return 'f';
+		case clang::BuiltinType::Kind::Double:
+			return 'd';
+		case clang::BuiltinType::Kind::LongDouble:
+			return 'D';
+		case clang::BuiltinType::Kind::NullPtr:
+			return 'p'; // nullptr_t
+		
+		case clang::BuiltinType::Kind::Half:
+		case clang::BuiltinType::Kind::BFloat16:
+		case clang::BuiltinType::Kind::ShortAccum:
+		case clang::BuiltinType::Kind::Accum:
+		case clang::BuiltinType::Kind::LongAccum:
+		case clang::BuiltinType::Kind::UShortAccum:
+		case clang::BuiltinType::Kind::UAccum:
+		case clang::BuiltinType::Kind::ULongAccum:
+		case clang::BuiltinType::Kind::ShortFract:
+		case clang::BuiltinType::Kind::Fract:
+		case clang::BuiltinType::Kind::LongFract:
+		case clang::BuiltinType::Kind::UShortFract:
+		case clang::BuiltinType::Kind::UFract:
+		case clang::BuiltinType::Kind::ULongFract:
+		case clang::BuiltinType::Kind::SatShortAccum:
+		case clang::BuiltinType::Kind::SatAccum:
+		case clang::BuiltinType::Kind::SatLongAccum:
+		case clang::BuiltinType::Kind::SatUShortAccum:
+		case clang::BuiltinType::Kind::SatUAccum:
+		case clang::BuiltinType::Kind::SatULongAccum:
+		case clang::BuiltinType::Kind::SatShortFract:
+		case clang::BuiltinType::Kind::SatFract:
+		case clang::BuiltinType::Kind::SatLongFract:
+		case clang::BuiltinType::Kind::SatUShortFract:
+		case clang::BuiltinType::Kind::SatUFract:
+		case clang::BuiltinType::Kind::SatULongFract:
+		case clang::BuiltinType::Kind::Float16:
+		case clang::BuiltinType::Kind::Float128:
+		case clang::BuiltinType::Kind::Overload:
+		case clang::BuiltinType::Kind::BoundMember:
+		case clang::BuiltinType::Kind::PseudoObject:
+		case clang::BuiltinType::Kind::Dependent:
+		case clang::BuiltinType::Kind::UnknownAny:
+		case clang::BuiltinType::Kind::ARCUnbridgedCast:
+		case clang::BuiltinType::Kind::BuiltinFn:
+		case clang::BuiltinType::Kind::ObjCId:
+		case clang::BuiltinType::Kind::ObjCClass:
+		case clang::BuiltinType::Kind::ObjCSel:
+#define IMAGE_TYPE(it, id, si, a, s) case clang::BuiltinType::Kind::id:
+#include <clang/Basic/OpenCLImageTypes.def>
+#undef IMAGE_TYPE
+		case clang::BuiltinType::Kind::OCLSampler:
+		case clang::BuiltinType::Kind::OCLEvent:
+		case clang::BuiltinType::Kind::OCLClkEvent:
+		case clang::BuiltinType::Kind::OCLQueue:
+		case clang::BuiltinType::Kind::OCLReserveID:
+		case clang::BuiltinType::Kind::IncompleteMatrixIdx:
+		case clang::BuiltinType::Kind::OMPArraySection:
+		case clang::BuiltinType::Kind::OMPArrayShaping:
+		case clang::BuiltinType::Kind::OMPIterator:
+#define EXT_OPAQUE_TYPE(et, id, e) case clang::BuiltinType::Kind::id:
+#include <clang/Basic/OpenCLExtensionTypes.def>
+#define SVE_TYPE(n, id, si) case clang::BuiltinType::Kind::id:
+#include <clang/Basic/AArch64SVEACLETypes.def>
+#define PPC_VECTOR_TYPE(n, id, s) case clang::BuiltinType::Kind::id:
+#include <clang/Basic/PPCTypes.def>
+#undef EXT_OPAQUE_TYPE
+#undef SVE_TYPE
+#undef PPC_VECTOR_TYPE
+			return '!';
+		default:
+			return ':';
+		}
+	} else if (qual->isEnumeralType()) {
+		const clang::EnumDecl *ed = qual->getAs<clang::EnumType>()->getDecl();
+		if (!ed) {
+			return 'i';
+		} else {
+			return type2char(ed->getIntegerType().getCanonicalType(), qorig);
+		}
+	} else if (qual->isFunctionPointerType()) {
+		return '@';
+	} else if (qual->isAnyPointerType() || qual->isReferenceType()) {
+		const clang::QualType &pointed = getPointedType(qual);
+		if (isTypeTrivial(pointed, qorig)) {
+			return 'p';
+		} else if (const clang::RecordType *rct = pointed->getAs<clang::RecordType>()) {
+			clang::RecordDecl *rc = rct->getDecl();
+			if (!rc) {
+				return '!';
+			} else if (!rc->isCompleteDefinition()) {
+				return 'p';
+			} else {
+				std::string str;
+				if (qorig) {
+					const clang::QualType qpted = getPointedType(*qorig);
+					str = record2name(*rc, &qpted);
+				} else {
+					str = record2name(*rc, nullptr);
+				}
+				char ret = ptr2char(str);
+				if (ret) return ret;
+				else {
+					return '!';
+				}
+			}
+		} else {
+			return '!';
+		}
+	} else if (const clang::RecordType *rct = qual->getAs<clang::RecordType>()) {
+		clang::RecordDecl *rc = rct->getDecl();
+		if (!rc) {
+			return '?';
+		} else if (rc->getNameAsString() == "__builtin_va_list") {
+			// va_list
+			return 'A';
+		} else {
+			return '?';
+		}
+	} else {
+		return '?';
+	}
+}
+bool isTypeTrivial(const clang::QualType &q, const clang::QualType *qorig) {
+	const char c = type2char(q, qorig);
+#define GO(chr) || (c == chr)
+	return (c == 'v')
+		GO('i') GO('u')
+		GO('I') GO('U')
+		GO('l') GO('L')
+		GO('f') GO('d')
+		GO('D') GO('K')
+		GO('0') GO('1')
+		GO('C') GO('c')
+		GO('W') GO('w')
+		GO('H')
+		GO('p');
+#undef GO
+}
+bool isTypeValid(const clang::QualType &q, const clang::QualType *qorig) {
+	const char c = type2char(q, qorig);
+	if (c == 'A') return false;
+	if (c == 'V') return false;
+	return ((c >= '0') && (c <= '9')) || ((c >= 'A') && (c <= 'Z')) || ((c >= 'a') && (c <= 'z'));
+}
+
+const std::string type2string(const clang::QualType &qual, const clang::QualType *qorig) {
+	if (qual->isBuiltinType()) {
+		return std::string("(builtin) ") + static_cast<const clang::BuiltinType&>(*qual).getName(clang::PrintingPolicy{{}}).data();
+	} else if (qual->isFunctionPointerType()) {
+		return "Callback (function pointer)";
+	} else if (qual->isAnyPointerType() || qual->isReferenceType()) {
+		std::string prefix = qual->isAnyPointerType() ? "Pointer to " : "Reference to ";
+		const clang::QualType &pointed = getPointedType(qual);
+		if (isTypeTrivial(pointed, qorig)) {
+			return prefix + "trivial object " + type2string(pointed, qorig) + " (" + type2char(pointed, qorig) + ")";
+		} else if (const clang::RecordType *rct = pointed->getAs<clang::RecordType>()) {
+			clang::RecordDecl *rc = rct->getDecl();
+			if (!rc) {
+				return prefix + "unknown record";
+			} else if (!rc->isCompleteDefinition()) {
+				return prefix + "incomplete record " + rc->getNameAsString();
+			} else {
+				std::string str;
+				if (qorig) {
+					const clang::QualType qpted = getPointedType(*qorig);
+					str = record2name(*rc, &qpted);
+				} else {
+					str = record2name(*rc, nullptr);
+				}
+				const char *ret = ptr2str(str);
+				if (ret[0] != '\0') {
+					return prefix + ret;
+				} else {
+					if (mangler && mangler->shouldMangleDeclName(rc)) {
+						std::string mangled;
+						{
+							llvm::raw_string_ostream strstr{mangled};
+							mangler->mangleName(rc, strstr);
+						}
+						return prefix + "unknown record " + str + " (=== " + mangled + ")";
+					} else {
+						return prefix + "unknown record " + str;
+					}
+				}
+			}
+		} else {
+			return prefix + "non-trivial or typedef'ed object " + type2string(pointed, qorig) + " (" + type2char(pointed, qorig) + ")";
+			//return "Pointer (maybe to callback)";
+		}
+	} else if (qual->isEnumeralType()) {
+		const clang::EnumDecl *ed = qual->getAs<clang::EnumType>()->getDecl();
+		if (!ed) {
+			return "Enumeration with unknown underlying integer type (assuming int)";
+		} else {
+			return "Enumeration with underlying type " + type2string(ed->getIntegerType().getCanonicalType(), nullptr);
+		}
+	} else if (const clang::RecordType *rct = qual->getAs<clang::RecordType>()) {
+		clang::RecordDecl *rc = rct->getDecl();
+		if (!rc) {
+			return "Unknown record";
+		} else if (rc->getNameAsString() == "__builtin_va_list") {
+			return "va_list";
+		} else {
+			return "Unknown record " + std::string(rc->getName().data());
+		}
+	} else {
+		return std::string("??? ") + qual->getTypeClassName();
+	}
+}
+
+class Visitor : public clang::RecursiveASTVisitor<Visitor> {
+public:
+	clang::ASTContext &context;
+	
+	bool shouldVisitTemplateInstantiations() const /* override */ { return true; }
+	
+	Visitor(clang::CompilerInstance &ci) : context(ci.getASTContext()) {
+		if (!mangler) {
+			mangler = clang::ItaniumMangleContext::create(context, ci.getDiagnostics());
+		}
+	}
+	
+	~Visitor() {
+		if (mangler) {
+			delete mangler;
+			mangler = nullptr;
+		}
+	}
+	
+	bool VisitDecl(clang::Decl *decl) /* override */ {
+		std::cerr << std::flush;
+		if (!decl) return true;
+		
+		if ((decl->getKind() >= clang::Decl::Kind::firstFunction) && (decl->getKind() <= clang::Decl::Kind::lastFunction)) {
+			clang::DeclaratorDecl *ddecl = static_cast<clang::DeclaratorDecl*>(decl);
+			std::cout << "Function detected!\n";
+			
+			std::string funName{ddecl->getName()};
+			
+			auto niceprint = [](const std::string &infotype, const auto &dat){ std::cout << "    " << infotype << ": " << dat << "\n"; };
+			niceprint("Function name", funName);
+			if (mangler && mangler->shouldMangleDeclName(ddecl)) {
+				std::string mangled;
+				{
+					llvm::raw_string_ostream strstr{mangled};
+					mangler->mangleName(ddecl, strstr);
+				}
+				niceprint("Function mangled name", mangled);
+				funName = std::move(mangled);
+			}
+			
+			bool valid;
+			std::string funTypeStr{""};
+			if (ddecl->getFunctionType()->isFunctionNoProtoType()) {
+				const clang::FunctionNoProtoType *funType = static_cast<const clang::FunctionNoProtoType*>(ddecl->getFunctionType());
+				const auto &retType = funType->getReturnType();
+				
+				niceprint("Function return type", type2string(retType, &retType));
+				niceprint("Canonical function return type",
+					type2string(retType.getCanonicalType(), &retType) +
+					" (" + type2char(retType.getCanonicalType(), &retType) + ")");
+				niceprint("Is sugared", funType->isSugared());
+				if (funType->isSugared()) {
+					clang::QualType qft{funType, 0};
+					niceprint("Desugared", type2string(funType->desugar(), &qft));
+				}
+				
+				funTypeStr = type2char(retType.getCanonicalType(), &retType) + std::string("Fv");
+				valid = isTypeValid(retType.getCanonicalType(), &retType);
+			} else {
+				const clang::FunctionProtoType *funType = static_cast<const clang::FunctionProtoType*>(ddecl->getFunctionType());
+				const auto &retType = funType->getReturnType();
+				
+				niceprint("Function return type", type2string(retType, &retType));
+				niceprint("Canonical function return type",
+					type2string(retType.getCanonicalType(), &retType)
+					+ " (" + type2char(retType.getCanonicalType(), &retType) + ")");
+				niceprint("Parameter count", funType->getNumParams());
+				for (const clang::QualType &type : funType->getParamTypes()) {
+					niceprint("  " + type2string(type, &type),
+						type2string(type.getCanonicalType(), &type) + " (" + type2char(type.getCanonicalType(), &type) + ")");
+				}
+				niceprint("Variadic function", funType->isVariadic() ? "yes" : "no");
+				
+				funTypeStr =
+					type2char(retType.getCanonicalType(), &retType) +
+					((funType->getNumParams() == 0)
+					 ? std::string("Fv") : std::accumulate(funType->getParamTypes().begin(), funType->getParamTypes().end(), std::string("F"),
+											[](const std::string &acc, const clang::QualType &qual){ return acc + type2char(qual.getCanonicalType(), &qual); }));
+				if (funType->isVariadic()) funTypeStr += "V";
+				valid = !funType->isVariadic() &&
+					std::accumulate(funType->getParamTypes().begin(), funType->getParamTypes().end(), isTypeValid(retType.getCanonicalType(), &retType),
+						[](bool acc, const clang::QualType &qual){ return acc && isTypeValid(qual.getCanonicalType(), &qual); });
+			}
+			
+			niceprint("Conclusion", "");
+			niceprint("Function final name", funName);
+			niceprint("Function type", funTypeStr);
+			niceprint("Valid function type", valid ? "yes" : "no");
+			std::cout << "\n";
+			
+			funMap[funName] = std::make_pair(funTypeStr, valid);
+			funList.push_back(funName);
+		}
+		
+		return true;
+	}
+};
+
+class Consumer : public clang::ASTConsumer {
+public:
+	Visitor visitor;
+	
+	Consumer(clang::CompilerInstance &ci) : visitor(ci) {
+	}
+	
+	void HandleTranslationUnit(clang::ASTContext &context) override {
+		visitor.TraverseDecl(context.getTranslationUnitDecl());
+	}
+};
+
+class Action : public clang::ASTFrontendAction {
+public:
+	virtual std::unique_ptr<clang::ASTConsumer> CreateASTConsumer(clang::CompilerInstance &ci, llvm::StringRef inFile) override {
+		return std::make_unique<Consumer>(ci);
+	}
+};
+
+int main(int argc, const char **argv) {
+	if (argc < 2) {
+		std::cerr << "Usage: " << argv[0] << " (filenames) -- [-I...]" << std::endl;
+		return 2;
+	}
+	
+	/*int fakeargc = argc + 1;
+	const char **fakeargv = new const char*[fakeargc];
+	memcpy(fakeargv, argv, argc * sizeof(char*));
+	fakeargv[fakeargc - 1] = "--";*/
+	llvm::cl::OptionCategory opcat{""};
+	clang::tooling::CommonOptionsParser op{argc, argv, opcat};
+	std::vector<std::string> paths; for (int i = 1; i < argc; ++i) paths.push_back(argv[i]);
+	
+	clang::tooling::ClangTool tool{op.getCompilations(), paths};
+	
+	tool.run(clang::tooling::newFrontendActionFactory<Action>().get());
+	
+	std::cout << "Done, outputing output.h" << std::endl;
+	std::sort(funList.begin(), funList.end());
+	std::fstream file{"output.h", std::ios_base::out};
+	for (const std::string &funName : funList) {
+		if (!funMap[funName].second) {
+			file << "//";
+		}
+		file << "GO(" << funName << ", " << funMap[funName].first << ")\n";
+	}
+	
+	return 0;
+}

LLVMprivateGenerator/registered_structs.cpp

@@ -0,0 +1,267 @@
+#include <string>
+
+#define ALL START() \
+	/* libc */ \
+	STRUCT("_IO_FILE", "a FILE") \
+	STRUCT("_G_fpos_t", "a file position") \
+	STRUCT("sockaddr", "a socket address") \
+	STRUCT("itimerspec", "an itimerspec") \
+	STRUCT("timespec", "a timespec") \
+	STRUCT("itimerval", "an itimerval") \
+	STRUCT("timeval", "a timeval") \
+	STRUCT("timex", "a timex") \
+	STRUCT("timezone", "a timezone") \
+	STRUCT("dirent", "a dirent") \
+	STRUCT("dirent64", "a dirent64") \
+	STRUCT("__dirstream", "a dir stream") \
+	STRUCT("tm", "a time structure (tm)") \
+	STRUCT("cmsghdr", "a cmsghdr") \
+	STRUCT("msghdr", "a msghdr") \
+	STRUCT("rpcent", "an rpcent") \
+	STRUCT("random_data", "a random_data structure") \
+	STRUCT("drand48_data", "a drand48_data structure") \
+	STRUCT("termios", "a termios") \
+	STRUCT("iovec", "an iovec") \
+	STRUCT("file_handle", "a file handle") \
+	STRUCT("lconv", "an lconv") \
+	STRUCT("__locale_struct", "a locale structure") \
+	STRUCT("aliasent", "an alias") \
+	STRUCT("fstab", "an fstab") \
+	STRUCT("group", "a group") \
+	STRUCT("hostent", "a hostent") \
+	STRUCT("protoent", "a protoent") \
+	STRUCT("passwd", "a password") \
+	STRUCT("spwd", "an spwd") \
+	STRUCT("ttyent", "a ttyent") \
+	STRUCT("utmp", "an utmp structure") \
+	STRUCT("utmpx", "an utmpx structure") \
+	STRUCT("ifaddrs", "an ifaddrs structure") \
+	STRUCT("statfs", "a statfs structure") \
+	STRUCT("statfs64", "a statfs64 structure") \
+	STRUCT("statvfs", "a statvfs structure") \
+	STRUCT("statvfs64", "a statvfs64 structure") \
+	STRUCT("timeb", "a timeb structure") \
+	STRUCT("_ftsent", "an _ftsent structure") \
+	STRUCT("sysinfo", "a sysinfo structure") \
+	STRUCT("rlimit", "an rlimit structure") \
+	STRUCT("rlimit64", "an rlimit64 structure") \
+	STRUCT("rusage", "an rusage structure") \
+	STRUCT("entry", "an entry structure") \
+	STRUCT("pollfd", "a pollfd structure") \
+	STRUCT("re_pattern_buffer", "a re_pattern_buffer structure") \
+	STRUCT("sembuf", "a sembuf structure") \
+	STRUCT("tms", "a tms structure") \
+	STRUCT("utsname", "an utsname structure") \
+	STRUCT("utimbuf", "an utimbuf structure") \
+	STRUCT2("__va_list_tag", "__va_list_tag (aka, a va_list)", 'A') \
+	/* ncurses */ \
+	STRUCT("_win_st", "a _win_st structure") \
+	STRUCT("MEVENT", "an MEVENT structure") \
+	TYPEDEF("cchar_t", "a cchar_t") \
+	/* zlib */ \
+	STRUCT("gz_header_s", "a gz_header_s structure") \
+	STRUCT("gzFile_s", "a gzFile_s structure") \
+	STRUCT("z_stream_s", "a z_stream_s structure") \
+	\
+	END()
+
+#define START()
+#define STRUCT(s, ret) if (str == s) { return 'p'; } else
+#define STRUCT2(s, ret, c) if (str == s) { return c; } else
+#define TYPEDEF(s, ret) if (str == s) { return 'p'; } else
+#define END() { return 0; }
+char ptr2char(const std::string &str) {
+	/*if ((str == "_IO_FILE")
+	 || (str == "_G_fpos_t")
+	 || (str == "sockaddr")
+	 || (str == "itimerspec")
+	 || (str == "timespec")
+	 || (str == "itimerval")
+	 || (str == "timeval")
+	 || (str == "timex")
+	 || (str == "timezone")
+	 || (str == "dirent")
+	 || (str == "dirent64")
+	 || (str == "__dirstream")
+	 || (str == "tm")
+	 || (str == "cmsghdr")
+	 || (str == "msghdr")
+	 || (str == "rpcent")
+	 || (str == "random_data")
+	 || (str == "drand48_data")
+	 || (str == "termios")
+	 || (str == "iovec")
+	 || (str == "file_handle")
+	 || (str == "lconv")
+	 || (str == "__locale_struct")
+	 || (str == "aliasent")
+	 || (str == "fstab")
+	 || (str == "group")
+	 || (str == "hostent")
+	 || (str == "protoent")
+	 || (str == "passwd")
+	 || (str == "spwd")
+	 || (str == "ttyent")
+	 || (str == "utmp")
+	 || (str == "utmpx")
+	 || (str == "ifaddrs")
+	 || (str == "statfs")
+	 || (str == "statfs64")
+	 || (str == "statvfs")
+	 || (str == "timeb")
+	 || (str == "_ftsent")
+	 || (str == "sysinfo")
+	 || (str == "rlimit")
+	 || (str == "rlimit64")
+	 || (str == "rusage")
+	 || (str == "entry")
+	 || (str == "pollfd")
+	 || (str == "re_pattern_buffer")
+	 || (str == "sembuf")
+	 || (str == "tms")
+	 || (str == "utsname")
+	 || (str == "utimbuf")
+	// ncurses
+	 || (str == "_win_st")
+	 
+	 || (str == "cchar_t")
+	) {
+		// FILE*, fpos_t*, ...
+		return 'p';
+	} else if (str == "__va_list_tag") {
+		return 'A';
+	} else {
+		return 0;
+	}*/
+	ALL
+}
+#undef END
+#undef TYPEDEF
+#undef STRUCT2
+#undef STRUCT
+#undef START
+
+#define START()
+#define STRUCT(s, ret) if (str == s) { return ret; } else
+#define STRUCT2(s, ret, c) if (str == s) { return ret; } else
+#define TYPEDEF(s, ret) if (str == s) { return ret; } else
+#define END() return "";
+const char *ptr2str(const std::string &str) {
+	/*if (str == "_IO_FILE") {
+		return "a FILE";
+	} else if (str == "_G_fpos_t") {
+		return "a file position";
+	} else if (str == "sockaddr") {
+		return "a socket address";
+	} else if (str == "itimerspec") {
+		return "an itimerspec";
+	} else if (str == "timespec") {
+		return "a timespec";
+	} else if (str == "itimerval") {
+		return "an itimerval";
+	} else if (str == "timeval") {
+		return "a timeval";
+	} else if (str == "timex") {
+		return "a timex";
+	} else if (str == "timezone") {
+		return "a timezone";
+	} else if (str == "dirent") {
+		return "a dirent";
+	} else if (str == "dirent64") {
+		return "a dirent64";
+	} else if (str == "__dirstream") {
+		return "a dir stream";
+	} else if (str == "tm") {
+		return "a time structure (tm)";
+	} else if (str == "cmsghdr") {
+		return "a cmsghdr";
+	} else if (str == "msghdr") {
+		return "a msghdr";
+	} else if (str == "rpcent") {
+		return "an rpcent";
+	} else if (str == "random_data") {
+		return "a random_data structure";
+	} else if (str == "drand48_data") {
+		return "a drand48_data structure";
+	} else if (str == "termios") {
+		return "a termios";
+	} else if (str == "iovec") {
+		return "an iovec";
+	} else if (str == "file_handle") {
+		return "a file handle";
+	} else if (str == "lconv") {
+		return "an lconv";
+	} else if (str == "__locale_struct") {
+		return "a locale structure";
+	} else if (str == "aliasent") {
+		return "an alias";
+	} else if (str == "fstab") {
+		return "an fstab";
+	} else if (str == "group") {
+		return "a group";
+	} else if (str == "hostent") {
+		return "a hostent";
+	} else if (str == "protoent") {
+		return "a protoent";
+	} else if (str == "passwd") {
+		return "a password";
+	} else if (str == "spwd") {
+		return "an spwd";
+	} else if (str == "ttyent") {
+		return "a ttyent";
+	} else if (str == "utmp") {
+		return "an utmp structure";
+	} else if (str == "utmpx") {
+		return "an utmpx structure";
+	} else if (str == "ifaddrs") {
+		return "an ifaddrs structure";
+	} else if (str == "statfs") {
+		return "a statfs structure";
+	} else if (str == "statfs64") {
+		return "a statfs64 structure";
+	} else if (str == "statvfs") {
+		return "a statvfs structure";
+	} else if (str == "statvfs64") {
+		return "a statvfs64 structure";
+	} else if (str == "timeb") {
+		return "a timeb structure";
+	} else if (str == "_ftsent") {
+		return "an _ftsent structure";
+	} else if (str == "sysinfo") {
+		return "a sysinfo structure";
+	} else if (str == "rlimit") {
+		return "an rlimit structure";
+	} else if (str == "rlimit64") {
+		return "an rlimit64 structure";
+	} else if (str == "rusage") {
+		return "an rusage structure";
+	} else if (str == "entry") {
+		return "an entry structure";
+	} else if (str == "pollfd") {
+		return "a pollfd structure";
+	} else if (str == "re_pattern_buffer") {
+		return "a re_pattern_buffer structure";
+	} else if (str == "sembuf") {
+		return "a sembuf structure";
+	} else if (str == "tms") {
+		return "a tms structure";
+	} else if (str == "utsname") {
+		return "an utsname structure";
+	} else if (str == "utimbuf") {
+		return "an utimbuf structure";
+	} else if (str == "__va_list_tag") {
+		return "__va_list_tag (aka, a va_list)";
+	// ncurses
+	} else if (str == "_win_st") {
+		return "a _win_st structure";
+		
+	} else if (str == "cchar_t") {
+		return "a cchar_t";
+	} else return "";*/
+	ALL
+}
+#undef END
+#undef TYPEDEF
+#undef STRUCT2
+#undef STRUCT
+#undef START

README.md

@@ -1,19 +1,24 @@
-# box64
+![Official logo](docs/img/Box64Logo.png "Official Logo")
 
-![Official logo](Box64Logo.png "Official Logo")
 Linux Userspace x86_64 Emulator with a twist
 
+[View changelog](https://github.com/ptitSeb/box64/blob/main/docs/CHANGELOG.md) | [中文](https://github.com/ptitSeb/box64/blob/main/README_CN.md) | [Українська](https://github.com/ptitSeb/box64/blob/main/README_UK.md) | [Report an error](https://github.com/ptitSeb/box64/issues/new)
+
+![build](https://app.travis-ci.com/ptitSeb/box64.svg?branch=main) ![stars](https://img.shields.io/github/stars/ptitSeb/box64) ![forks](https://img.shields.io/github/forks/ptitSeb/box64) ![contributors](https://img.shields.io/github/contributors/ptitSeb/box64) ![prs](https://img.shields.io/github/issues-pr/ptitSeb/box64) ![issues](https://img.shields.io/github/issues/ptitSeb/box64)
+
 ----
 
-Box64 lets you run x86_64 Linux programs (such as games) on non-x86_64 Linux systems, like ARM (host system needs to be 64bit little-endian).
+Box64 lets you run x86_64 Linux programs (such as games) on non-x86_64 Linux systems, like ARM (host system needs to be 64-bit little-endian).
 
-Because Box64 uses the native versions of some "system" libraries, like libc, libm, SDL, and OpenGL, it's easy to integrate and use with most applications, and performance can be surprisingly high in some cases.
+You can find many Box64 videos on the [MicroLinux](https://www.youtube.com/channel/UCwFQAEj1lp3out4n7BeBatQ), [Pi Labs](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g) or [The Byteman](https://www.youtube.com/channel/UCEr8lpIJ3B5Ctc5BvcOHSnA) YouTube channels.
 
-Box64 integrates a DynaRec (dynamic recompiler) for the ARM64 platform, providing a speed boost between 5 to 10 times faster than only using the interpreter.
+Since Box64 uses the native versions of some "system" libraries, like libc, libm, SDL, and OpenGL, it's easy to integrate and use with most applications, and performance can be surprisingly high in many cases. Take a look at thoses bench analysis for an example [here](https://box86.org/index.php/2021/06/game-performances/).
 
-Some x86 internal opcodes use parts of "Realmode X86 Emulator Library", see [x86primop.c](src/emu/x86primop.c) for copyright details
+Box64 integrates with DynaRec (dynamic recompiler) for the ARM64 and RV64 platform, providing a speed boost between 5 to 10 times faster than using only the interpreter. Some high level information on how DynaRec works can be found [here](https://box86.org/2021/07/inner-workings-a-high%e2%80%91level-view-of-box86-and-a-low%e2%80%91level-view-of-the-dynarec/).
 
-<img src="Box64Icon.png" width="96" height="96">
+Some x64 internal opcodes use parts of "Realmode X86 Emulator Library", see [x64primop.c](src/emu/x64primop.c) for copyright details
+
+<img src="docs/img/Box64Icon.png" width="96" height="96">
 
 Logo and Icon made by @grayduck, thanks!
 
@@ -24,7 +29,7 @@ Usage
 
 There are a few environment variables to control the behaviour of Box64.
 
-See [here](USAGE.md) for all environment variables and what they do.
+See [here](docs/USAGE.md) for all the environment variables and what they do.
 
 Note: Box64's Dynarec uses a mechanism with Memory Protection and a SegFault signal handler to handle JIT code. In simpler terms, if you want to use GDB to debug a running program that use JIT'd code (like mono/Unity3D), you will still have many "normal" segfaults triggering. It is suggested to use something like `handle SIGSEGV nostop` in GDB to not stop at each segfault, and maybe put a breakpoint inside `my_memprotectionhandler` in `signals.c` if you want to trap SegFaults.
 
@@ -32,18 +37,87 @@ Note: Box64's Dynarec uses a mechanism with Memory Protection and a SegFault sig
 
 Compiling/Installation
 ----
-> Compilation instructions can be found [here](COMPILE.md)  
+> Compilation instructions can be found [here](docs/COMPILE.md)\
+> Instructions for installing Wine for Box64 can be found [here](docs/X64WINE.md)
 
 ----
 
-Version history
+Version history/Change log
 ----
 
-The change log is available [here](CHANGELOG.md)
+The change log is available [here](docs/CHANGELOG.md).
 
 ----
 
-Final words
+Notes about 32-bit platforms
 ----
 
-(If you use Box64 in your project, please don't forget to mention Box64!)
+Because Box64 works by directly translating function calls from x86_64 to host system, the host system (the one Box64 is running on) needs to have 64-bit libraries. Box64 doesn't include any 64-bit <-> 32-bit translation. 
+
+So understand that box64 will only runs 64-bit linux binaries. For 32-bit binaries, you need box86 (with all the multiarch or proot trickery it imply on 64-bit OS).
+Note that many installer (mojo setup based) will fall back to "x86" when detecting ARM64 OS, and so will try to use box86 for the setup, even if an x86_64 version exist. You can hack your way around with a fake "uname" that return "x86_64" when the argument is "-m"
+
+----
+
+Notes about Box64 configuration
+----
+
+Box64 now have configurations files. There are 2 files loaded. `/etc/box4.box64rc` and `~/.box64rc`. Both files have the same syntax, and is basicaly an ini files. Section in square brakets define the process name, and the rest is the env. var. to set. Looke at [Usage](USAGE.md) for detail on what parameters can be put. Box64 comes with a default file that should be installed for better stability. The file in in `system/box64.box64rc` and should be installed to `/etc/box64.box64rc` If, for some reasons, you don't want to install that file here, at least copy it to `~/.box64rc` or some game may not function correctly.
+Note that the priority is: `~/.bashrc` > `/etc/box64.box64rc` > command line
+So, your settings in `~/.bashrc` may override the setting from your command line...
+
+----
+
+Notes about Unity game emulation
+----
+
+Running Unity games should just works, but you should also note that many Unity3D games require OpenGL 3+ which can be tricky to provide on ARM SBC (single-board computers). Also many newer Unity3D (like KSP) games use the BC7 compressed textures, wich is not supported on many ARM integrated GPU.
+Hint: on Pi4, use `MESA_GL_VERSION_OVERRIDE=3.2` and with Panfrost use `PAN_MESA_DEBUG=gl3` to use higher profile if the game starts then quits before showing anything.
+
+----
+
+Notes about GTK programs
+----
+
+GTK libraries are now wrapped on box64, both gtk2 and gtk3.
+
+----
+
+Notes about Steam
+----
+
+Note that Steam is a hybrid 32-bit / 64-bit. You NEED box86 to run Steam, as the client app is a 32-bit binary. It also uses a 64-bit local server binaries, and that steamwebhelper process is now mendatory, even on the "small mode". And that process will eat lots of memory. So machine with less the 6Gb of RAM will need a swapfile tp use Steam.
+
+----
+
+Notes about Wine
+----
+
+Wine64 is supported on box64. Proton too. Be aware that 64-bit Wine also includes 32-bit components, to be able to run 32-bit Windows programs. The 32-bit apps will need box86 and will not run without it. On a system where both box64 and box86 are present and working, a wine 64-bit setup can run both 32-bit and 64-bit Windows programs (just use `wine` and `wine64` respectively).
+Note that the new 32bits PE in 64bits process that the Wine time in currently implementing in Wine 7.+ is now supported, but the support is quite young so there might be some residual issues.
+
+----
+
+Notes about Vulkan
+----
+
+Box64 wraps Vulkan libraries, but note that it as mostly been tested with a AMD RX550 card and on the Freedreno driver, so some extensions may be missing depending on your graphics card.
+
+----
+
+Final word
+----
+
+I want to thank everyone who has contributed to box64 development.
+There are many ways to contribute: code contribution, financial, hardware and advertisement!
+So, in no particular order, I want to thank:
+ * For their major code contribution: rajdakin, mogery
+ * For their major financial contribution: FlyingFathead, stormchaser3000, dennis1248, sll00, [libre-computer-project](https://libre.computer/)
+ * For hardware contribution and LoongArch migration: [xiaoji](https://www.linuxgame.cn/), Deepin Beijing Develop Team
+ * For their major code contribution on the RV64 Dynarec: ksco, xctan
+ * For their hardware contribution: [Radxa](https://rockpi.org/), [Pine64](https://www.pine64.org/), [StarFive](https://rvspace.org/)
+ * For their continous advertisement of box64 project: salva ([microLinux](https://www.youtube.com/channel/UCwFQAEj1lp3out4n7BeBatQ)), [PILab](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g)/[TwisterOS](https://twisteros.com/) team, [The Byteman](https://www.youtube.com/channel/UCEr8lpIJ3B5Ctc5BvcOHSnA), [NicoD](https://www.youtube.com/channel/UCpv7NFr0-9AB5xoklh3Snhg), ekianjo ([Boilingsteam](https://boilingsteam.com/))
+
+And I also thank the many other people who participated even once in this project.
+
+(If you use Box64 in your project, please don't forget to mention it!)

README_CN.md

@@ -0,0 +1,113 @@
+# box64
+
+![Official logo](docs/img/Box64Logo.png "Official Logo")
+Linux 上用户空间的 x86_64 应用模拟器（支持运行原生库）
+
+----
+![box64 build status](https://app.travis-ci.com/ptitSeb/box64.svg?branch=main)
+
+[English](docs/README.md) | [Українська](https://github.com/ptitSeb/box64/blob/main/README_UK.md) 
+
+Box64 可以在非 x86_64 Linux 系统（比如 ARM64）上运行 x86_64 Linux 程序（比如游戏），注意主机系统需要是 64 位小端。
+
+您可以在 [MicroLinux](https://www.youtube.com/channel/UCwFQAEj1lp3out4n7BeBatQ)、[Pi Labs](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g) 和 [The Byteman](https://www.youtube.com/channel/UCEr8lpIJ3B5Ctc5BvcOHSnA) YouTube 频道上找到许多 Box64 视频。
+
+由于 Box64 使用一些“系统”库的原生版本，如 libc、libm、SDL 和 OpenGL 等，因此很容易与大多数应用程序集成和使用，并且在许多情况下性能会相当不错。可以在[这里](https://box86.org/index.php/2021/06/game-performances/)查看一些性能测试的样例。
+
+Box64 集成了适用于 ARM64 平台的 DynaRec（动态重编译器），速度可以比纯解释模式快 5 到 10 倍。可以在[这里](https://box86.org/2021/07/inner-workings-a-high%E2%80%91level-view-of-box86-and-a-low%E2%80%91level-view-of-the-dynarec/)找到有关 DynaRec 工作原理的一些信息。
+
+一些 x64 内部操作码使用 “Realmode X86 Emulator Library” 的部分内容，有关版权详细信息，请参见 [x64primop.c](../src/emu/x64primop.c)。
+
+<img src="docs/img/Box64Icon.png" width="96" height="96">
+
+LOGO 由 @grayduck 制作，感谢！
+
+----
+
+使用方法
+----
+
+有若干环境变量可以控制 Box64 的行为。
+
+可在[这里](docs/USAGE.md)查看所有环境变量及其作用。
+
+注意：Box64 的 Dynarec 使用具有内存保护和段错误信号处理的机制来执行 JIT 代码。所以，如果想使用 GDB 调试使用 JIT 代码的程序（如 Mono/Unity3D），这会触发许多“正常”的段错误。建议在 GDB 中使用类似 `handle SIGSEGV nostop` 来防止它每个段错误处停止。如果你想捕获段错误，可以在 `signals.c` 的 `my_memprotectionhandler` 中设置断点。
+
+----
+
+编译/安装
+----
+
+编译说明可以在[这里](docs/COMPILE.md)查看。
+
+----
+
+版本历史
+----
+
+版本日志在[这里](docs/CHANGELOG.md)。
+
+----
+
+32位平台的注意事项
+----
+
+因为 Box64 的工作原理是直接将函数调用从 x86_64 转换为主机系统，所以主机系统（运行 Box64 的系统）需要有 64 位库。Box64 不包含任何 64 位 <-> 32 位的转换。
+
+所以 box64 只能运行 64 位的 Linux 二进制。对于 32 位二进制则需要使用 box86 来运行（它在 64 位操作系统上使用了 multiarch 和 proot 等技巧来实现运行）。请注意，许多（基于 mojo 的）安装程序在检测到 ARM64 操作系统时将回退到 “x86”，因此即使存在 x86_64 版本，也会尝试使用 box86。这时你可以使用一个假的 `uname`，当它的参数为 `-m` 时返回 `x86_64`。
+
+----
+
+关于 Unity 游戏模拟的注意事项
+----
+
+运行 Unity 游戏应该没什么问题，但还应该注意，许多 Unity3D 游戏需要 OpenGL 3+，这在 ARM SBC 上可能会比较棘手。同时许多较新的 Unity3D游戏（如 KSP）也使用 BC7 压缩纹理，很多 ARM 的集成显卡并不支持。
+
+> 提示：如果游戏开始后没有显示任何东西就退出了，在 Pi4 上可以使用 `MESA_GL_VERSION_OVERRIDE=3.2`，在 Panfrost 上则可以使用 `PAN_MESA_DEBUG=gl3` 来使用更高的配置。
+
+----
+
+关于GTK程序的注意事项
+----
+
+box64 封装了 GTK，包括 gtk2 和 gtk3。
+
+----
+
+关于 Steam 的注意事项
+----
+
+请注意，Steam 是 32/64 位的混合体，所以还需要 box86 才能运行，因为客户端应用程序是 32 位的。它还使用 64 位本地服务器，但与大多数使用 libcef/chromium 的东西一样，它目前无法在 box64 上正常工作。所以，现在 box64 上暂时不能运行 Steam。
+
+----
+
+关于 Wine 的注意事项
+----
+
+box64 支持 Wine64，Proton 应该也能运行。请注意，64 位 Wine 包含有 32 位组件，以便能够运行 32 位 Windows 程序。32 位应用程序需要 box86，否则无法运行。在 box64 和 box86 都存在并工作的系统上，64 位的 Wine 可以同时运行 32 位和 64 位 Windows 程序（分别使用 `wine` 和 `wine64`）。请注意，目前在 Wine 7.+ 中实现的 Wine 时间在 64 位进程中的新 32bit PE 尚不支持。我测试了 Wine 7.5 64 位可以正常工作，但是更新的版本可能还不行。
+
+----
+
+关于 Vulkan 注意事项
+----
+
+Box64 封装了 Vulkan 库，但请注意，它仅在 RX550 显卡上进行过测试，因此根据您的显卡，某些扩展可能会丢失。
+
+----
+
+结语
+----
+
+我要感谢所有为 box64 开发做出贡献的人。
+贡献方式有很多种：代码贡献、财务帮助、捐赠捐赠和广告合作！
+以下感谢不分先后： 
+
+ * 代码贡献：rajdakin, mogery
+ * 财务帮助：FlyingFathead, stormchaser3000, dennis1248, sll00, [libre-computer-project](https://libre.computer/)
+ * 硬件捐赠和 LoongArch 迁移：[xiaoji](https://www.linuxgame.cn/), Deepin Beijing Develop Team
+ * 硬件捐赠：[Radxa](https://rockpi.org/), [Pine64](https://www.pine64.org/), [StarFive](https://rvspace.org/)
+ * 为本项目持续的宣传：salva ([microLinux](https://www.youtube.com/channel/UCwFQAEj1lp3out4n7BeBatQ)), [PILab](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g)/[TwisterOS](https://twisteros.com/) team, [The Byteman](https://www.youtube.com/channel/UCEr8lpIJ3B5Ctc5BvcOHSnA), [NicoD](https://www.youtube.com/channel/UCpv7NFr0-9AB5xoklh3Snhg), ekianjo ([Boilingsteam](https://boilingsteam.com/))
+
+我还要感谢很多人，即使他们只参与了一次本项目。
+
+(如果你的项目中使用了Box64，请不要忘记提及！)

README_UK.md

@@ -0,0 +1,119 @@
+![Official logo](docs/img/Box64Logo.png "Official Logo")
+
+Емулятор простіра користувача x86_64 із родзинкою
+
+[Дивитись журнал змін](https://github.com/ptitSeb/box64/blob/main/docs/CHANGELOG.md) | [中文](https://github.com/ptitSeb/box64/blob/main/README_CN.md) | [Українська](https://github.com/ptitSeb/box64/blob/main/README_UK.md) | [Повідомити про помилку](https://github.com/ptitSeb/box64/issues/new)
+
+![build](https://app.travis-ci.com/ptitSeb/box64.svg?branch=main) ![stars](https://img.shields.io/github/stars/ptitSeb/box64) ![forks](https://img.shields.io/github/forks/ptitSeb/box64) ![contributors](https://img.shields.io/github/contributors/ptitSeb/box64) ![prs](https://img.shields.io/github/issues-pr/ptitSeb/box64) ![issues](https://img.shields.io/github/issues/ptitSeb/box64)
+
+----
+
+Box64 дозволяє запускати x86_64 Linux програми (наприклад, ігри) на системах Linux відмінних від x86_64, наприклад ARM (хост-система має мати 64-розрядний порядок редагування).
+
+Ви можете знайти багато відео про Box64 в YouTube каналах [MicroLinux](https://www.youtube.com/channel/UCwFQAEj1lp3out4n7BeBatQ), [Pi Labs](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g) або [The Byteman](https://www.youtube.com/channel/UCEr8lpIJ3B5Ctc5BvcOHSnA)
+
+Оскільки Box64 використовує рідні версії деяких «системних» бібліотек, таких як libc, libm, SDL і OpenGL, його легко інтегрувати та використовувати з більшістю програм, а продуктивність у багатьох випадках може бути напрочуд високою. Подивіться на цей стендовий аналіз для прикладу [тут](https://box86.org/index.php/2021/06/game-performances/).
+
+Box64 інтегрується з DynaRec (динамічний рекомпілятор) для платформ ARM64 і RV64 забезпечуючи підвищення швидкості в 5-10 разів, ніж використання лише інтерпретатора. Деякі високорівневі відомості про те, як працює DynaRec, можна знайти [тут](https://box86.org/2021/07/inner-workings-a-high%e2%80%91level-view-of-box86-and-a-low%e2%80%91level-view-of-the-dynarec/).
+
+Деякі внутрішні коди операцій x64 використовують частини «Бібліотеки емулятора Realmode X86», дивіться [x64primop.c](src/emu/x64primop.c) для детальної інформації про авторські права.
+
+<img src="docs/img/Box64Icon.png" width="96" height="96">
+
+Логотип і піктограма зроблені @grayduck, дякую!
+
+----
+
+Використання
+----
+
+Є кілька змінних середовища для керування поведінкою Box64.
+
+Дивіться [тут](docs/USAGE.md) для перегляду всіх змінних середовища та того, що вони роблять.
+
+Примітка: Dynarec від Box64 використовує механізм із захистом пам’яті та обробником сигналу помилки сегментів для обробки JIT коду. Простіше кажучи, якщо ви хочете використовувати GDB для налагодження запущеної програми, яка використовує JIT-код (наприклад, mono/Unity3D), ви все одно матимете багато «звичайних» помилок сегментів. Пропонується використовувати щось на зразок `handle SIGSEGV nostop` в GDB, щоб не зупинятися на кожній помилці сегмента, і, можливо, поставити точку зупину всередині `my_memprotectionhandler` в `signals.c`, якщо ви хочете перехопити помилки сегментів.
+
+----
+Компіляція/Встановлення
+----
+> Інструкцію зі складання Box64 можна знайти [тут](docs/COMPILE.md).\
+> Інструкцію з встановлення Wine для Box64 можна знайти [тут](docs/X64WINE.md).
+
+----
+
+Історія версій/Журнал змін
+----
+
+Історія версій доступна [тут](docs/CHANGELOG.md).
+
+----
+
+Примітки щодо 32 бітних платформ
+----
+Оскільки Box64 працює шляхом прямого перекладу викликів функцій з x86_64 на хост-систему, хост-система (та, на якій працює Box64) повинна мати 64-розрядні бібліотеки. Box64 не містить 64-біт <-> 32-біт перекладу.
+
+Також розумійте що Box64 запускатиме лише 64-розрядні двійкові Linux файли. Для 32-розрядних двійкових файлів вам потрібен Box86 (з усіма хитрощами з мультиархітектурною системою або корінними правами). Зауважте, що багато інсталяторів (на основі mojo) повертаються до "x86" при виявленні ОС ARM64, і тому намагатимуться використовувати Box86 для налаштування, навіть якщо існує версія x86_64. Ви можете зламати свій шлях за допомогою фальшивого "uname", який повертає "x86_64", коли аргумент "-m"
+
+----
+
+Примітки щодо конфігурації Box64
+----
+
+Обидва файли мають однаковий синтаксис і в основному є файлами ini. Розділ у квадратних дужках визначає назву процесу, а решта — встановлють змінну середовища. Подивіться [використання](USAGE.md), щоб дізнатися, які параметри можна завдати. Box64 поставляється з файлом за замовчуванням, який слід встановити для кращої стабільності. Файл знаходиться в `system/box64.box64rc` і має бути встановлен в `/etc/box64.box64rc`. Якщо з певних причин ви не хочете встановлювати цей файл у `/etc`, принаймні скопіюйте його в `~/.box64rc` або гра може не працювати належним чином. Зауважте, що пріоритетом є: `~/.bashrc` > `/etc/box64.box64rc` > командний рядок
+Таким чином, ваші налаштування в `~/.bashrc` можуть замінити налаштування з вашого командного рядка...
+
+----
+
+Примітки щодо емуляції ігор Unity
+----
+
+Запуск ігор Unity має працювати, але ви також повинні зауважити, що для багатьох ігор Unity3D потрібен OpenGL 3+, який може бути складно забезпечити на ARM SBC (одноплатних комп’ютерах). Крім того, багато нових ігор Unity3D (наприклад, KSP) використовують стиснуті текстури BC7, які не підтримуються багатьма інтегрованими GPU ARM.
+Підказка: в Pi4 використовуйте `MESA_GL_VERSION_OVERRIDE=3.2`, а в Panfrost — `PAN_MESA_DEBUG=gl3`, щоб використовувати вищий профіль, якщо гра запускається, а потім завершується, перш ніж щось показує.
+
+----
+
+Примітки щодо програм GTK
+----
+
+Бібліотеки GTK2 і GTK3 тепер використовуються в Box64.
+
+----
+
+Примітки щодо Steam
+----
+
+Зауважте, що Steam є гібридом 32-біт / 64-біт. Вам ПОТРІБЕН box86, щоб запустити Steam, оскільки клієнта є 32-розрядною двійковою програмою. Він також використовує 64-розрядні двійкові файли локального сервера, і цей процес steamwebhelper тепер є обов’язковим навіть у «малому режимі». І цей процес з’їсть багато оперативної пам’яті, таким чином машині з 6 Гб оперативної пам’яті знадобиться файл підкачки для використання Steam.
+
+----
+
+Примітки щодо Wine
+----
+
+Wine64 підтримується Box64, Proton теж. Майте на увазі, що 64-розрядний Wine також містить 32-розрядні компоненти щоб мати можливість запускати 32-розрядні програми Windows. Для 32-розрядних програм потрібен Box86, і вони не працюватимуть без нього. У системі, де присутні і працюють Box64, і Box86, 64-розрядне встановлення Wine може запускати як 32-розрядні, так і 64-розрядні програми Windows (просто використовуйте `wine` і `wine64` відповідно).
+Зауважте, що новий 32-бітний PE в 64-бітному процесі, який Wine зараз реалізує у Wine 7+ тепер підтримується, але підтримка є досить молодою тому можуть виникнути деякі проблеми.
+
+----
+
+Примітки щодо Vulkan
+----
+
+Box64 використовує бібліотеки Vulkan, але зауважте що він тестувався з картою AMD Radeon RX550 і драйвером Freedreno, тому деякі розширення можуть бути відсутні залежно від вашої відеокарти.
+
+----
+
+Останнє слово
+----
+
+Я хочу подякувати всім, хто зробив внесок у розвиток box64.
+Є багато способів зробити внесок: внесок коду, фінансовий внесок, апаратне забезпечення та реклама!
+Отже, без особливого порядку, я хочу подякувати:
+* За основний внесок у код: rajdakin, mogery
+* За великий фінансовий внесок: FlyingFathead, stormchaser3000, dennis1248, sll00, [libre-computer-project](https://libre.computer/)
+* За апаратне забезпечення та міграцію LoongArch: [xiaoji](https://www.linuxgame.cn/), команда розробників Deepin Beijing
+* За основний внесок у код RV64 Dynarec: ksco, xctan
+* За внесок у апаратне забезпечення: [Radxa](https://rockpi.org/), [Pine64](https://www.pine64.org/), [StarFive](https://rvspace.org/)
+* За безперервну рекламу Box64: salva ([microLinux](https://www.youtube.com/channel/UCwFQAEj1lp3out4n7BeBatQ)), [PILab](https://www.youtube.com/channel/UCgfQjdc5RceRlTGfuthBs7g)/Команда [TwisterOS](https://twisteros.com/), [The Byteman](https://www.youtube.com/channel/UCEr8lpIJ3B5Ctc5BvcOHSnA), [NicoD](https://www.youtube.com/channel/UCpv7NFr0-9AB5xoklh3Snhg), ekianjo ([Boilingsteam](https://boilingsteam.com/))
+
+І я також дякую багатьом іншим людям, які хоч раз брали участь у цьому проекті.
+
+(Якщо ви використовуєте Box64 у своєму проекті, будь ласка, не забудьте згадати про це!)

USAGE.md

@@ -1,146 +0,0 @@
-
-Usage
-----
-
-There are many environment variables to control Box64 behaviour. 
-
-#### BOX64_LOG
-Controls the Verbosity level of the logs
- * 0: NONE : No message (except some fatal error). (Default.)
- * 1: INFO : Show some minimum log (Example: librairies not found)
- * 2: DEBUG : Details a lot of stuff (Example: relocations or functions called).
- * 3: DUMP : All DEBUG plus DUMP of all ELF Info.
-
-#### BOX64_NOBANNER
-Disables Box64 printing its version and build
- * 0 : Enable printing its banner. (Default.)
- * 1 : Disable printing its banner. 
-
-#### BOX64_LD_LIBRARY_PATH
-Path to look for x86_64 libraries. Default is current folder and `lib` in current folder.
-Also, `/usr/lib/x86_64-linux-gnu` and `/lib/x86_64-linux-gnu` are added if they exist.
-
-#### BOX64_PATH
-Path to look for x86_64 executable. Default is current folder and `bin` in current folder.
-
-#### BOX64_DLSYM_ERROR
-Enables/Disables the logging of `dlsym` errors.
- * 0 : Don't log `dlsym` errors. (Default.)
- * 1 : Log dlsym errors.
-
-#### BOX64_TRACE_FILE
-Send all log and trace to a file instead of `stdout`
-Also, if name contains `%pid` then this is replaced by the actual PID of box64 instance
-
-#### BOX64_TRACE
-Only on build with trace enabled. Trace allow the logging of all instruction executed, along with register dump
- * 0 : No trace. (Default.) 
- * 1 : Trace enabled. Trace start after the initialisation of all depending libraries is done.
- * symbolname : Trace only `symbolname` (trace is disable if the symbol is not found).
- * 0xXXXXXXX-0xYYYYYYY : Trace only between the 2 addresses.
-
-#### BOX64_TRACE_INIT
-Use BOX64_TRACE_INIT instead of BOX_TRACE to start trace before the initialisation of libraries and the running program
- * 0 : No trace. (Default.)
- * 1 : Trace enabled. The trace start with the initialisation of all depending libraries is done.
-
-#### BOX64_TRACE_START
-Only on builds with trace enabled.
- * NNNNNNN : Start trace only after NNNNNNNN opcode execute (number is an `uint64_t`).
-
-#### BOX64_TRACE_XMM
-Only on builds with trace enabled.
- * 0 : The XMM (i.e. SSE/SSE2) register will not be logged with the general and x86 registers. (Default.)
- * 1 : Dump the XMM registers.
-
-#### BOX64_TRACE_EMM
-Only on builds with trace enabled.
- * 0 : The EMM (i.e. XMM/x87) register will not be logged with the general and x86 registers. (Default.)
- * 1 : Dump the EMM registers.
-
-#### BOX64_TRACE_COLOR
-Only on builds with trace enabled.
- * 0 : The general registers will always be the default white color. (Default.)
- * 1 : The general registers will change color in the dumps when they changed value.
-
-#### BOX64_LOAD_ADDR
-Try to load at 0xXXXXXX main binary (if binary is a PIE)
- * 0xXXXXXXXX : The load address . (Only active on PIE programs.)
-
-#### BOX64_NOSIGSEGV
-Disable handling of SigSEGV. (Very useful for debugging.)
- * 0 : Let the x86 program set sighandler for SEGV (Default.)
- * 1 : Disable the handling of SigSEGV.
-
-#### BOX64_NOSIGILL
-Disable handling of SigILL (to ease debugging mainly).
- * 0 : Let x86 program set sighandler for Illegal Instruction
- * 1 : Disables the handling of SigILL 
-
-#### BOX64_X11THREADS
-Call XInitThreads when loading X11. (This is mostly for old Loki games with the Loki_Compat library.)
- * 0 : Don't force call XInitThreads. (Default.)
- * 1 : Call XInitThreads as soon as libX11 is loaded.
-
-#### BOX64_X11GLX
-Force libX11's GLX extension to be present.
-* 0 : Do not force libX11's GLX extension to be present. 
-* 1 : GLX will always be present when using XQueryExtension. (Default.)
-
-#### BOX64_DYNAREC_DUMP
-Enables/disables Box64's Dynarec's dump.
- * 0 : Disable Dynarec's blocks dump. (Default.)
- * 1 : Enable Dynarec's blocks dump.
- * 2 : Enable Dynarec's blocks dump with some colors.
-
-#### BOX64_DYNAREC_LOG
-Set the level of DynaRec's logs.
- * 0 : NONE : No Logs for DynaRec. (Default.)
- * 1 :INFO : Minimum Dynarec Logs (only unimplemented OpCode).
- * 2 : DEBUG : Debug Logs for Dynarec (with details on block created / executed).
- * 3 : VERBOSE : All of the above plus more.
-
-#### BOX64_DYNAREC
-Enables/Disables Box64's Dynarec.
- * 0 : Disables Dynarec.
- * 1 : Enable Dynarec. (Default.)
-
-#### BOX64_DYNAREC_TRACE
-Enables/Disables trace for generated code.
- * 0 : Disable trace for generated code. (Default.)
- * 1 : Enable trace for generated code (like regular Trace, this will slow down the program a lot and generate huge logs).
-
-#### BOX64_NODYNAREC 
-Forbid dynablock creation in the interval specified (helpfull for debugging behaviour difference between Dynarec and Interpretor)
- * 0xXXXXXXXX-0xYYYYYYYY : define the interval where dynablock cannot start (inclusive-exclusive)
-
-#### BOX64_LIBGL
- * libXXXX set the name for libGL (defaults to libGL.so.1).
- * /PATH/TO/libGLXXX : Sets the name and path for libGL
- You can also use SDL_VIDEO_GL_DRIVER
-
-#### BOX64_LD_PRELOAD
- * XXXX[:YYYYY] force loading XXXX (and YYYY...) libraries with the binary
- PreLoaded libs can be emulated or native, and are treated the same way as if they were comming from the binary
- 
-#### BOX64_EMULATED_LIBS
- * XXXX[:YYYYY] force lib XXXX (and YYYY...) to be emulated (and not wrapped)
-Some games uses an old version of some libraries, with an ABI incompatible with native version.
-Note that LittleInferno for example is auto detected, and libvorbis.so.0 is automatical added to emulated libs, and same for Don't Starve (and Together / Server variant) that use an old SDL2 too
-
-#### BOX64_ALLOWMISSINGLIBS
-Allow Box64 to continue even if a library is missing.
- * 0 : Box64 will stop if a library cannot be loaded. (Default.)
- * 1 : Continue even if a needed library cannot be loaded. Unadvised, this will, in most cases, crash later on.
-
-#### BOX64_JITGDB
-
- * 0 : Just print the Segfault message on segfault (default)
- * 1 : Launch `gdb` when a segfault, bus error or illegal instruction signal is trapped, attached to the offending process and go in an endless loop, waiting.
- When in gdb, you need to find the correct thread yourself (the one with `my_box64signalhandler` in is stack)
- then probably need to `finish` 1 or 2 functions (inside `usleep(..)`) and then you'll be in `my_box64signalhandler`, 
- just before the printf of the Segfault message. Then simply 
- `set waiting=0` to exit the infinite loop.
- * 2 : Launch `gdbserver` when a segfault, bus error or illegal instruction signal is trapped, attached to the offending process, and go in an endless loop, waiting.
- Use `gdb /PATH/TO/box64` and then `target remote 127.0.0.1:1234` to connect to the gdbserver (or use actual IP if not on the machine). After that, the procedure is the same as with ` BOX64_JITGDB=1`.
- This mode can be usefullwhen programs redirect all console output to a file (like Unity3D Games)

debian/changelog

@@ -0,0 +1,98 @@
+box64 (0.2.2) unstable; urgency=low
+
+ * Added a hacked version for overridden malloc/free functions, enabling libcef (and derivative) to work.
+ * Added rcfile handling: box64 now read "/etc/box64.box64rc" and "~/.box64rc" and apply per process parameters
+ * Added BOX64_DYNAREC_CALLRET to optimized CALL/RET opcode using semi-direct native CALL/RET (get more than 10% speedup)
+ * Added BOX64_DYNAREC_FORWARD to allow bigger Dynarec block to be build (can get more then 30% of Speedup!)
+ * Improved memory protection tracking and signal handling, again
+ * Simplified mutex handling (faster, cleaner)
+ * Reduce memory used by the memory tracking (memory almost divide by 4 is some critical use case)
+ * Added d3dadaptor9 wrapping
+ * More wrapped libs (especially on the gtk familly)
+ * Improved/fixed some Syscall handling
+ * Refactored Strong Memory Model emulation (faster and more accurate)
+ * Added some more opcode to ARM64 Dynarec, and fixed some other
+ * Some fixes to flags handling in the Dynarec on some special cases
+ * Refactor library loading/unloading, with refcount.
+ * Some special cases fixes for dlopen (fixes deadcells, maybe others too)
+ * Improved mmap mapping, espcially with MAP_32BITS flag
+ * More wrapped functions and syscalls
+ * Lots of improvment in the Rounding of float & double (Dynarec and Interpreter), and proper handling of denormals when converting to/from 80 bits long double
+ * Added specific suppport for RK3588 board (needed some hack in signal handling, probably due to the use of a non mainlined kernel)
+ * More support on the RV64 port
+ * More support to build under musl environment
+
+-- Sebastien Chevalier <[email protected]>  Thu, 10 Mar 2023 10:20:33 -0500
+
+box64 (0.2.0) unstable; urgency=low
+
+ * Wrapped more vulkan function, dxvk 2.0 now works
+ * Added support for overridden malloc/free functions
+ * Refactor Dynarec memory management, reducing memory footprint (from 20% to 40% of Dynarec size)
+ * Improved elf loader
+ * Improved dlsym handling with RTLD_NEXT
+ * Added BOX64_DYNAREC_SAFEFLAGS to allow finetuning Dynarec generated code handling of flags accross function calls and returns.
+ * Added BOX64_BASH to setup x86_64 bash binary, so shell script can be run in x86_64 world
+ * Added BOX64_ROLLING_LOG to have details log only on crash
+ * Work on alignment for some of pthread structures
+ * More wrapped libraries in the gtk family
+ * Some fixes on the Dynarec x87 code (fixing a bunch of games like ut2004 or Piczle Puzzle)
+ * Improved TLS Size handling (Unity3D games now works)
+ * More PageSize Compile options
+ * Improved execv family of function to have better box64 integration
+ * Added support for wrapped libfuse so AppImage works
+ * Adjusted the binfmt integration so AppImage are automaticaly picked
+ * Improved FAudio, SDL2, GL (and more) wrapping
+ * More wrapped libs, like libEGL.so, to helps emulated Qt4/5 libs to load
+ * Improved Signal Handling and memory protection traking
+ * Some signature fixes to some wrapped functions (in libc)
+ * Added more syscalls
+ * Added a lot of new opcodes to the ARM64 Dynarec
+ * docs: add instructions for Debian-based Linux by @ryanfortner in #306
+ * Fix typos and arch type string by @archanox in #321
+ * Fix grammar by @Jai-JAP in #326
+ * Enable 64k page size by @martinmanyhats in #334
+ * Align address when call mprotect by @wannacu in #336
+ * Add wrapped functions needed for 'ls -l'. by @stiltr in #294
+ * add 18.04 tegra X1 github actions by @theofficialgman in #345
+ * change order of matrix (to preview better under checkmark dropdown by @theofficialgman in #346
+ * Backport SDL_DYNAPI_entry wrapper from box86. by @JohnnyonFlame in #374
+ * Add SW64 base support by @wannacu in #382
+ * fix overzealous replace in wrappers pathnames by @NobodyNada in #415
+ * Create X64WINE.md by @WheezyE in #423
+ * src: asm: Rename lr & fp registers to their x-equivalents by @fredldotme in #426
+ * Malloc override by @ptitSeb in #437
+ * Remove dynablocklist by @ptitSeb in #438
+ * Fix Pkgbuilds by @Jai-JAP in #452
+
+ -- Sebastien Chevalier <[email protected]>  Thu, 17 Nov 2022 11:20:33 -0500
+
+box64 (0.1.8) unstable; urgency=low
+
+  * Added an option to get generated -NAN on SSE2 operation
+  * Many small fixes and improvement to get SteamPlay (i.e. proton) working (along with box86)
+  * Added some workaround for program calling uname to mimic x86_64 system
+  * Added some granularity to mmap, and generic memory protection tracking improvment, to mimic x86 system (for wine stagging and proton)
+  * Better clone syscall and libc implementation
+  * Improved wrapping of GTK libs
+  * More wrapped libs (more gtk libs, like gstreamer-1.0 among other non-gtk libs too)
+  * More wrapped functions(with some tricky one, like dladdr1)
+  * Some fixes and improvment to some wrapped functions
+  * Refactor Dynarec:
+  *   - better handling of SSE/x87 registers
+  *   - optimisation to limit float/double conversion
+  *   - better handling of "internal" jump inside a dynablock
+  *   - make adding new architecture easier, by sharing as much infrastructure as possible
+  * Improved elfloader
+  * Improved some tests
+  * Improved a bit the "Hotpage" handling and messages
+  * Added more dynarec opcodes
+  * A few fixes in some Dynarec opcodes
+  * A bit more optimisation in some Dynarec opcodes
+  * Don't quit on unsupported syscall, return -1 / ENOSYS error
+  * Added some more Syscall
+  * Wrapped Vulkan library. Vulkan and dxvk now supported!
+  * Support building on PPC64LE (interpreter only)
+  * Added support for Risc-V (interpreter only)
+
+ -- Sebastien Chevalier <[email protected]>  Tue, 18 Jan 2022 11:20:33 -0500

debian/compat

@@ -0,0 +1 @@
+11

debian/control

@@ -0,0 +1,14 @@
+Source: box64
+Section: utils
+Priority: optional
+Maintainer: Ryan Fortner <[email protected]>
+Build-Depends: cmake, debhelper (>=11~), python3
+Standards-Version: 4.1.4
+Homepage: https://github.com/ptitSeb/box64
+
+Package: box64
+Architecture: any
+Multi-Arch: foreign
+Depends: ${misc:Depends}, ${shlibs:Depends}
+Description: Linux Userspace x86_64 Emulator with a twist, targeted at ARM Linux devices 
+ Box86 lets you run x86_64 Linux programs (such as games) on non-x86 Linux systems, like ARM (host system needs to be 64bit little-endian).

debian/copyright

@@ -0,0 +1,26 @@
+Format-Specification: http://dep.debian.net/deps/dep5/
+
+Files: *
+Copyright: © 2022 Sebastien Chevalier
+License: MIT
+
+License: MIT
+ Copyright (c) 2018-2021 Sebastien Chevalier ("ptitSeb")
+ .
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+ .
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+ .
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ THE SOFTWARE.

debian/lintian-override

@@ -0,0 +1 @@
+box64: no-manual-page

debian/rules

@@ -0,0 +1,13 @@
+#!/usr/bin/make -f
+
+%:
+	dh $@  
+
+override_dh_auto_configure:
+	dh_auto_configure -- \
+	      -DCMAKE_BUILD_TYPE=RelWithDebInfo \
+	      -DARM_DYNAREC=1 \
+		  -DNOGIT=1
+
+override_dh_shlibdeps:
+	dh_shlibdeps --exclude=libgcc_s.so.1 --exclude=libpng12.so.0 --exclude=libstdc++.so.5 --exclude=libstdc++.so.6

debian/source/format

@@ -0,0 +1 @@
+3.0 (quilt)

debian/upstream/metadata

@@ -0,0 +1,5 @@
+Bug-Database: https://github.com/ptitSeb/box64/issues
+Bug-Submit: https://github.com/ptitSeb/box64/issues/new
+Repository: https://github.com/ptitSeb/box64.git
+Repository-Browse: https://github.com/ptitSeb/box64
+Security-Contact: [email protected]

debian/watch

@@ -0,0 +1 @@
+version=3

docs/CHANGELOG.md

@@ -0,0 +1,196 @@
+v0.2.4
+======
+* Added Dynarec for RISC-V
+* Added partial 32 bits support (WoW64 works)
+* Changed cpuid to display box64
+* Fixed steam, again
+* Improved hacked version for overridden malloc/free functions
+* More wrapped libs
+* More wrapped functions and syscalls
+* Reduced memory footprint
+* Added support for the BIND_NOW flags in ELF files
+* Added RTLD_NOLOAD support
+* Fixed some typos and general cleanup, again
+* Added a cosimulation mode (to compare the behaviour of the dynarec with the interpreter)
+* Added FASTNAN/FASTROUND handling for more opcodes
+* Better float/double/long double handling
+* Better dlopen/dlclose handling
+* More games in the rc file
+* Added BOX64_DYNAREC_MISSING to show only missing opcode, independantly of the log level
+* Added BOX64_RESERVE_HIGH to reserve addresses above 47bits
+* Improved multitreading support
+* Ukrainian translation of the README
+=> Dynarec now support RISC-V, large speedup on RISC-V 64, were games are now playable (like Stardew Valley on a Vision Five 2)
+=> Improved compatibility with more fixes in elf handling, more wrapped libs and functiond, more fixed opcodes and refined profile
+
+v0.2.2
+======
+* Added a hacked version for overridden malloc/free functions, enabling libcef (and derivative) to work.
+    => Steam Large mode and new BigPicture are working
+    => Heroic Launcher is working
+* Added rcfile handling: box64 now read `/etc/box64.box64rc` and `~/.box64rc` and apply per process parameters
+    => Every program can be finetuned, for speed or just to make them work
+* Added BOX64_DYNAREC_CALLRET to optimized CALL/RET opcode using semi-direct native CALL/RET (get more than 10% speedup)
+* Added BOX64_DYNAREC_FORWARD to allow bigger Dynarec block to be build (can get more then 30% of Speedup!)
+* Improved memory protection tracking and signal handling, again
+* Box64 now return a custom name for the CPU instal of P4, build with Box64 and the cpu name it's running on
+* Simplified mutex handling (faster, cleaner)
+* Reduce memory used by the memory tracking (memory almost divide by 4 is some critical use case)
+* Added d3dadapter9 wrapping
+    => gallium nine is now supported on box64 too
+* More wrapped libs (especially on the gtk familly)
+* Improved/fixed some Syscall handling
+* Refactored Strong Memory Model emulation (faster and more accurate)
+* Added some more opcode to ARM64 Dynarec, and fixed some other
+* Some fixes to flags handling in the Dynarec on some special cases
+* Refactor library loading/unloading, with refcount.
+* Some special cases fixes for dlopen (fixes deadcells, maybe others too)
+* Improved mmap mapping, espcially with MAP_32BITS flag
+* More wrapped functions and syscalls
+* Lots of improvment in the Rounding of float & double (Dynarec and Interpreter), and proper handling of denormals when converting to/from 80 bits long double
+* Added specific suppport for RK3588 board (needed some hack in signal handling, probably due to the use of a non mainlined kernel)
+* More support on the RV64 port
+* More support to build under musl environment
+
+v0.2.0
+======
+* Wrapped more vulkan function, dxvk 2.0 now works
+* Added support for overridden malloc/free functions
+* Refactor Dynarec memory management, reducing memory footprint (from 20% to 40% of Dynarec size)
+* Improved elf loader
+* Improved dlsym handling with RTLD_NEXT
+* Added BOX64_DYNAREC_SAFEFLAGS to allow finetuning Dynarec generated code handling of flags accross function calls and returns.
+* Added BOX64_BASH to setup x86_64 bash binary, so shell script can be run in x86_64 world 
+* Added BOX64_ROLLING_LOG to have details log only on crash
+* Work on alignment for some of pthread structures
+* More wrapped libraries in the gtk family
+* Some fixes on the Dynarec x87 code (fixing a bunch of games like ut2004 or Piczle Puzzle)
+* Improved TLS Size handling (Unity3D games now works)
+* More PageSize Compile options
+* Improved `execv` family of function to have better box64 integration
+* Added support for wrapped libfuse so AppImage works
+* Adjusted the binfmt integration so AppImage are automaticaly picked
+* Improved FAudio, SDL2, GL (and more) wrapping
+* More wrapped libs, like libEGL.so, to helps emulated Qt4/5 libs to load
+* Improved Signal Handling and memory protection traking
+* Some signature fixes to some wrapped functions (in libc)
+* Added more syscalls
+* Added a lot of new opcodes to the ARM64 Dynarec
+=> Lot's of new games stat working, to name a few: Surviving Mars, Piczle Cross Adventure (using Proton experimental), UT2004, Obduction, Machinarium, Silicon Zero, Hacknet, Absolute Drift, Art of Rally, Dota2
+=> Some apps also runs now, like TeamSpeak 3 Client and Server or Discord
+=> The bash integration is usefull for device with no binfmt integration or for script that check the machine it's running on
+
+v0.1.8
+======
+* Added an option to get generated -NAN on SSE2 operation
+* Many small fixes and improvement to get SteamPlay (i.e. proton) working (along with box86)
+* Added some workaround for program calling uname to mimic x86_64 system
+* Added some granularity to mmap, and generic memory protection tracking improvment, to mimic x86 system (for wine stagging and proton)
+* Better clone syscall and libc implementation
+* Improved wrapping of GTK libs
+* More wrapped libs (more gtk libs, like gstreamer-1.0 among other non-gtk libs too)
+* More wrapped functions(with some tricky one, like dladdr1)
+* Some fixes and improvment to some wrapped functions
+* Refactor Dynarec:
+    * better handling of SSE/x87 registers
+    * optimisation to limit float/double conversion
+    * better handling of "internal" jump inside a dynablock
+    * make adding new architecture easier, by sharing as much infrastructure as possible
+* Improved elfloader
+* Improved some tests
+* Improved a bit the "Hotpage" handling and messages
+* Added more dynarec opcodes
+* A few fixes in some Dynarec opcodes
+* A bit more optimisation in some Dynarec opcodes
+* Don't quit on unsupported syscall, return -1 / ENOSYS error
+* Added some more Syscall
+* Wrapped Vulkan library. Vulkan and dxvk now supported!
+* Support building on PPC64LE (interpreter only)
+* Added support for Risc-V (interpreter only)
+
+v0.1.6
+======
+* Introduce "HotPage", to temporarily disable Dynarec on a page were writing is also occuring (can help speed up C# code)
+* Some work on Dynarec to limit the number of mutex use, and also allow smaller block to be built (for JIT'd programs)
+* Introduce BOX64_DYNAREC_STRONGMEM for the (Arm) dynarec to emulate StrngMemory Model (needed by some games, like RimWorld)
+* More functions wrapped
+* Improve speed of the custom allocator used by dynarec and Hash (speedup loading)
+* Added a workaround for streamwebhelper to not load it
+* More opcodes added
+* More wrapped libraries, including gtk2
+* Added a fix for linking box64 on system using glibc 2.34+
+* Some residual fixes on thread attribute handling
+* Better handling of app that want 32bits jumps, like unity3d/mono (thanks mogery)
+* More ARM hardware option in CMake (Phytium, NX...)
+* Added loongarch64 support (interpreter only)
+* Some fixes to elfloader
+* Added a mecanism to cancel a Dynarec block construction if it triggers a segfault (instead of a crash)
+
+v0.1.4
+======
+* Reworked README a bit
+* Added some more wrapped libs
+* Added some SSE4x opcodes
+* Preliminary support for VSyscall (still missing VDSO)
+* Added support for AES-NI cpu extension, also in Dynarec (and using ARM extension if present)
+* Added some syscall
+* Added some more wrapped functions
+* Improvment to the handling of longjmp inside signal handlers
+* Improved wrapper helpers (from rajdakin)
+* Some fixes to opcodes (especially C2 flags for some x87 opcodes)
+* Handling of some specific opcode as privileged instruction (instead of NOP)
+* Fixed ELF signature detection
+* Some fixes to a few env. var. handling
+
+v0.1.2
+======
+* OpenSource!
+* A few more opcode added to the Interpreter and the Dynarec
+* Improved Native Function calling
+* Added some function to limit allocated memory to 47bits space (for Wine)
+* Improved and Fixed the functions to limit allocated memory to 32bits space
+* Wine is starting now, but not everything and every version works
+
+v0.1.0
+======
+* Improvement to ElfLoader
+* More opcode added to the Dynarec
+* More lib wrapping
+* Some fixes to a few function signature
+* Improvement to Signal handling, and internal mutex handling
+* A few fixes to some dynarec opcodes
+* A few fixes to some interpreter opcodes
+
+v0.0.8
+======
+* Improvement to SSE/x87 handling
+* More opcode added to the Dynarec
+* More lib wrapping
+
+v0.0.6
+======
+* Added Dynarec for ARM64
+* Many general CPU opcode added to the Dynarec
+* Many SSEx opcodes added to the Dynarec
+* Added a few more symbols in libc
+* A few changes to the "thread once" handling
+* New Logo and Icon from @grayduck
+
+v0.0.4
+======
+* Added a lot of opcodes
+* Added SDL1 and SDL2 wrapping
+* OpenGL/GLU wrapping done
+* libasound / libpulse wrapping done
+* libopenal / libalure / libalut wrapping done
+* Many X11 libs wrapped
+* Added "install" with binfmt integration
+* A few games are actualy starting now (old WorldOfGoo, Into The Breach, VVVVVV and Thimbeweed Park)
+
+v0.0.2
+======
+* Using box86 as a base, implemented most planned box64 part except dynarec
+* Wrapped a few libs
+* ELF loader a bit crude, but seems working
+* Signal handling implemented
+* MMX and x87 are sharing their registers

docs/COMPILE.md

@@ -0,0 +1,210 @@
+Compiling/Installing
+----
+
+### Debian-based Linux 
+You can use [@ryanfortner](https://github.com/ryanfortner)'s apt repository to install precompiled box64 debs, updated every 24 hours. 
+
+```
+sudo wget https://ryanfortner.github.io/box64-debs/box64.list -O /etc/apt/sources.list.d/box64.list
+wget -qO- https://ryanfortner.github.io/box64-debs/KEY.gpg | sudo gpg --dearmor -o /etc/apt/trusted.gpg.d/box64-debs-archive-keyring.gpg
+sudo apt update && sudo apt install box64-arm64 -y
+```
+
+Alternatively, you can generate your own package using the [instructions below](https://github.com/ptitSeb/box64/blob/main/docs/COMPILE.md#debian-packaging). 
+
+----
+
+### The general approach is:
+```
+git clone https://github.com/ptitSeb/box64
+cd box64
+mkdir build; cd build; cmake .. ${OPTIONS}
+make -j4  
+sudo make install
+```
+If it's the first install, you also need:
+```
+sudo systemctl restart systemd-binfmt
+```
+- You can use `make -j1`, `make -j2` to prevent running out of memory
+- You can also add `-DBAD_SIGNAL=ON` to the cmake command if you are on Linux Kernel mixed with Android, like on RK3588 or maybe Termux
+
+#### For instance, if you want to build box64 for Generic ARM64 Linux platforms, it would look like this:
+```
+git clone https://github.com/ptitSeb/box64
+cd box64
+mkdir build; cd build; cmake .. -D ARM_DYNAREC=ON -D CMAKE_BUILD_TYPE=RelWithDebInfo
+make -j4
+sudo make install
+sudo systemctl restart systemd-binfmt
+```
+----
+
+#### for RK3399
+
+Using a 64bit OS:
+```
+-D RK3399=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
+```
+
+#### for RK3588 / RK3588S
+
+Using a 64bit OS:
+```
+-D RK3588=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
+```
+
+#### for Raspberry Pi 3
+
+Warning, you need a 64bit OS:
+
+If building on the Pi, you will also need a large swap (3 GB+)
+[optionally reduce GPU memory to a minimum (e.g. 16 MB) using `raspi-config`
+(and reboot) before starting the build]:
+
+You can use e.g. '`make -j4`' to speed up the build, but on a Pi 3 with 1GB memory you will likely
+run out of memory at some point and need to run the build again.
+Still, this can be faster if your build is attended.
+
+```
+-D RPI3ARM64=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
+make 
+```
+
+#### for Raspberry Pi 4
+
+Warning, you need a 64bit OS:
+
+```
+-D RPI4ARM64=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
+```
+
+#### for TEGRA X1
+
+Using a 64bit OS:
+
+```
+-D TEGRAX1=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
+```
+
+
+#### for ODROID N2/N2+
+
+Using a 64bit OS:
+
+```
+-D ODROIDN2=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
+```
+
+#### for Snapdragon 845
+
+Using a 64bit OS:
+
+```
+-D SD845=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
+```
+
+#### for Phytium
+
+Using a 64bit OS:
+```
+-D PHYTIUM=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
+```
+
+#### for a generic ARM64 machine
+
+Using a 64bit OS:
+```
+-D ARM64=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
+```
+
+#### for M1
+
+Only test on Asahi for now, using the default "16K page" kernel
+
+```
+-D M1=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
+```
+
+#### for LoongArch
+
+Using a 64bit OS:
+
+```
+-D LARCH64=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
+```
+
+#### for RISC-V
+
+Using a 64bit OS:
+
+```
+-D RV64=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
+```
+
+#### for PowerPC 64 LE
+
+Using a 64bit OS:
+
+```
+-D PPC64LE=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
+```
+
+#### for LX2160A
+
+Using a 64bit OS:
+
+```
+-D LX2160A=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
+```
+
+#### for x86_64 Linux
+```
+-D LD80BITS=1 -D NOALIGN=1 -D CMAKE_BUILD_TYPE=RelWithDebInfo
+```
+If you encounter some linking errors, try using `NOLOADADDR=ON` (`cmake -D NOLOADADDR=ON; make -j$(nproc)`).
+
+----
+
+### use ccmake
+
+Alternatively, you can **use the curses-bases ccmake (or any other gui frontend for cmake)** to select wich platform to use interactively.
+
+### Customize your build
+
+#### Use ccache if you have it
+
+Add `-DUSE_CCACHE=1` if you have ccache (it's better if you plan to touch the sources)
+
+#### To have some debug info
+
+The `-DCMAKE_BUILD_TYPE=RelWithDebInfo` argument makes a build that is both optimized for speed, and has debug information embedded. That way, if you have a crash or try to analyse performance, you'll have some symbols.
+
+#### To have a Trace Enabled build 
+
+To have a trace enabled build (***the interpreter will be slightly slower***), add `-DHAVE_TRACE=1`. But you will need to have the [Zydis library](https://github.com/zyantific/zydis) in your `LD_LIBRARY_PATH` or in the system library folders at runtime. Use version v3.2.1, as later version changed the API and will no longer work with box64
+
+#### To have ARM Dynarec
+
+Dynarec is only available on ARM (for the meantime), Activate it by using `-DARM_DYNAREC=1`.
+###### *Note: VFPv3 and NEON are required for Dynarec.*
+
+#### Not building from a git clone
+
+If you are not building from a git clone (for example, downloading a release source code zip from github), you need to use `-DNOGIT=1` from cmake to be able to build (box64 uses git SHA1 to show last commit in version number).
+
+----
+
+Testing
+----
+A few tests are included with box64.
+
+They can be launched using the `ctest` command.
+
+The tests are very basic and only tests some functionality for now.
+
+----
+
+Debian Packaging
+----
+Box64 can also be packaged into a .deb file ***using the source code zip from the releases page*** with `DEB_BUILD_OPTIONS=nostrip dpkg-buildpackage -us -uc -nc`. Configure any additional cmake options you might want in `debian/rules`.

docs/USAGE.md

@@ -0,0 +1,327 @@
+
+Usage
+----
+
+There are many environment variables to control Box64 behaviour. 
+Env. var with * can also be put inside box64rc files
+
+#### BOX64_LOG *
+Controls the Verbosity level of the logs
+ * 0: NONE : No message (except some fatal error). (Default.)
+ * 1: INFO : Show some minimum log (Example: librairies not found)
+ * 2: DEBUG : Details a lot of stuff (Example: relocations or functions called).
+ * 3: DUMP : All DEBUG plus DUMP of all ELF Info.
+
+#### BOX64_ROLLING_LOG *
+Show last few wrapped function call when a Signal is caught
+ * 0: No last function call printed (Default.)
+ * 1: Last 16 wrapped functions calls printed when a signal is printed. Incompatible with BOX64_LOG>1 (may need BOX64_SHOWSEGV=1 also)
+ * N: Last N wrapped functions calls printed when a signal is printed. Incompatible with BOX64_LOG>1 (may need BOX64_SHOWSEGV=1 also)
+
+#### BOX64_NOBANNER
+Disables Box64 printing its version and build
+ * 0 : Enable printing its banner. (Default.)
+ * 1 : Disable printing its banner. 
+
+#### BOX64_LD_LIBRARY_PATH *
+Path to look for x86_64 libraries. Default is current folder and `lib` in current folder.
+Also, `/usr/lib/x86_64-linux-gnu` and `/lib/x86_64-linux-gnu` are added if they exist.
+
+#### BOX64_PATH *
+Path to look for x86_64 executable. Default is current folder and `bin` in current folder.
+
+#### BOX64_DLSYM_ERROR *
+Enables/Disables the logging of `dlsym` errors.
+ * 0 : Don't log `dlsym` errors. (Default.)
+ * 1 : Log dlsym errors.
+
+#### BOX64_TRACE_FILE *
+Send all log and trace to a file instead of `stdout`
+Also, if name contains `%pid` then this is replaced by the actual PID of box64 instance
+End the filename with `+` to have thetrace appended instead of overwritten
+Use `stderr` to use this instead of default `stdout` 
+
+#### BOX64_TRACE *
+Only on build with trace enabled. Trace allow the logging of all instruction executed, along with register dump
+ * 0 : No trace. (Default.) 
+ * 1 : Trace enabled. Trace start after the initialisation of all depending libraries is done.
+ * symbolname : Trace only `symbolname` (trace is disable if the symbol is not found).
+ * 0xXXXXXXX-0xYYYYYYY : Trace only between the 2 addresses.
+
+#### BOX64_TRACE_INIT *
+Use BOX64_TRACE_INIT instead of BOX_TRACE to start trace before the initialisation of libraries and the running program
+ * 0 : No trace. (Default.)
+ * 1 : Trace enabled. The trace start with the initialisation of all depending libraries is done.
+
+#### BOX64_TRACE_START *
+Only on builds with trace enabled.
+ * NNNNNNN : Start trace only after NNNNNNNN opcode execute (number is an `uint64_t`).
+
+#### BOX64_TRACE_XMM *
+Only on builds with trace enabled.
+ * 0 : The XMM (i.e. SSE/SSE2) register will not be logged with the general and x86 registers. (Default.)
+ * 1 : Dump the XMM registers.
+
+#### BOX64_TRACE_EMM *
+Only on builds with trace enabled.
+ * 0 : The EMM (i.e. MMX) register will not be logged with the general and x86 registers. (Default.)
+ * 1 : Dump the EMM registers.
+
+#### BOX64_TRACE_COLOR *
+Only on builds with trace enabled.
+ * 0 : The general registers will always be the default white color. (Default.)
+ * 1 : The general registers will change color in the dumps when they changed value.
+
+#### BOX64_LOAD_ADDR *
+Try to load at 0xXXXXXX main binary (if binary is a PIE)
+ * 0xXXXXXXXX : The load address . (Only active on PIE programs.)
+
+#### BOX64_NOSIGSEGV *
+Disable handling of SigSEGV. (Very useful for debugging.)
+ * 0 : Let the x86 program set sighandler for SEGV (Default.)
+ * 1 : Disable the handling of SigSEGV.
+
+#### BOX64_NOSIGILL *
+Disable handling of SigILL (to ease debugging mainly).
+ * 0 : Let x86 program set sighandler for Illegal Instruction
+ * 1 : Disables the handling of SigILL 
+
+#### BOX64_SHOWSEGV *
+Show Segfault signal even if a signal handler is present
+ * 0 : Don"t force show the SIGSEGV analysis (Default.)
+ * 1 : Show SIGSEGV detail, even if a signal handler is present
+
+#### BOX64_SHOWBT *
+Show some Backtrace (Nativ e and Emulated) whgen a signal (SEGV, ILL or BUS) is caught
+ * 0 : Don"t show backtraces (Default.)
+ * 1 : Show Backtrace detail (for native, box64 is rename as the x86_64 binary run)
+
+#### BOX64_X11THREADS *
+Call XInitThreads when loading X11. (This is mostly for old Loki games with the Loki_Compat library.)
+ * 0 : Don't force call XInitThreads. (Default.)
+ * 1 : Call XInitThreads as soon as libX11 is loaded.
+
+#### BOX64_X11GLX *
+Force libX11's GLX extension to be present.
+* 0 : Do not force libX11's GLX extension to be present. 
+* 1 : GLX will always be present when using XQueryExtension. (Default.)
+
+#### BOX64_DYNAREC_DUMP *
+Enables/disables Box64's Dynarec's dump.
+ * 0 : Disable Dynarec's blocks dump. (Default.)
+ * 1 : Enable Dynarec's blocks dump.
+ * 2 : Enable Dynarec's blocks dump with some colors.
+
+#### BOX64_DYNAREC_LOG *
+Set the level of DynaRec's logs.
+ * 0 : NONE : No Logs for DynaRec. (Default.)
+ * 1 :INFO : Minimum Dynarec Logs (only unimplemented OpCode).
+ * 2 : DEBUG : Debug Logs for Dynarec (with details on block created / executed).
+ * 3 : VERBOSE : All of the above plus more.
+
+#### BOX64_DYNAREC *
+Enables/Disables Box64's Dynarec.
+ * 0 : Disables Dynarec.
+ * 1 : Enable Dynarec. (Default.)
+
+#### BOX64_DYNAREC_TRACE *
+Enables/Disables trace for generated code.
+ * 0 : Disable trace for generated code. (Default.)
+ * 1 : Enable trace for generated code (like regular Trace, this will slow down the program a lot and generate huge logs).
+
+#### BOX64_NODYNAREC  *
+Forbid dynablock creation in the interval specified (helpfull for debugging behaviour difference between Dynarec and Interpreter)
+ * 0xXXXXXXXX-0xYYYYYYYY : define the interval where dynablock cannot start (inclusive-exclusive)
+
+#### BOX64_DYNAREC_TEST *
+Dynarec will compare it's execution with the interpreter (super slow, only for testing)
+ * 0 : No comparison
+ * 1 : Each opcode runs on interepter and on Dynarec, and regs and memory are compared and print if different
+
+#### BOX64_DYNAREC_BIGBLOCK *
+Enables/Disables Box64's Dynarec building BigBlock.
+ * 0 : Don't try to build block as big as possible (can help program using lots of thread and a JIT, like C#/Unity) (Default when libmonobdwgc-2.0.so is loaded)
+ * 1 : Build Dynarec block as big as possible (Default.)
+ * 2 : Build Dynarec block bigger (don't stop when block overlaps, but only for blocks in elf memory)
+ * 3 : Build Dynarec block bigger (don't stop when block overlaps, for all type of memory)
+
+#### BOX64_DYNAREC_FORWARD *
+Define Box64's Dynarec max allowed forward value when building Block.
+ * 0 : No forward value. When current block end, don't try to go further even if there are previous forward jumps
+ * XXX : Allow up to XXXX bytes of gap when building a Block after the block end to next forward jump (Default: 128)
+ 
+#### BOX64_DYNAREC_STRONGMEM *
+Enable/Disable simulation of Strong Memory model
+* 0 : Don't try anything special (Default.)
+* 1 : Enable some Memory Barrier when reading from memory (on some MOV opcode) to simulate Strong Memory Model while trying to limit performance impact (Default when libmonobdwgc-2.0.so is loaded)
+* 2 : Enable some Memory Barrier when reading from memory (on some MOV opcode) to simulate Strong Memory Model
+
+#### BOX64_DYNAREC_X87DOUBLE *
+Force the use of Double for x87 emulation
+* 0 : Try to use float when possible for x87 emulation (default, faster)
+* 1 : Only use Double for x87 emulation (slower, may be needed for some specific games, like Crysis)
+
+#### BOX64_DYNAREC_FASTNAN *
+Enable/Disable generation of -NAN
+* 0 : Generate -NAN like on x86
+* 1 : Don't do anything special with NAN, to go as fast as possible (default, faster)
+
+#### BOX64_DYNAREC_FASTROUND *
+Enable/Disable generation of precise x86 rounding
+* 0 : Generate float/double -> int rounding like on x86
+* 1 : Don't do anything special with edge case Rounding, to go as fast as possible (no INF/NAN/Overflow -> MIN_INT conversion) (default, faster)
+
+#### BOX64_DYNAREC_SAFEFLAGS *
+Handling of flags on CALL/RET opcodes
+* 0 : Treat CALL/RET as if it never needs any flags (faster but not advised)
+* 1 : most of RET will need flags, most of CALLS will not (Default)
+* 2 : All CALL/RET will need flags (slower, but might be needed. Automatically enabled for Vara.exe)
+
+#### BOX64_DYNAREC_CALLRET *
+Optimisation of CALL/RET opcodes (not compatible with jit/dynarec/smc)
+* 0 : Don't optimize CALL/RET, use Jump Table for boths (Default)
+* 1 : Try to optimized CALL/RET, skipping the use of the JumpTable when possible (will crash if blacks are invalidate, so probably incompatible with JIT/Dynarec)
+
+#### BOX64_DYNAREC_HOTPAGE *
+Handling of HotPage (Page being both executed and written)
+* 0 : Don't track hotpage (Default)
+* 1-255 : Track HotPage, and disable execution of a page being written for N attempts
+
+#### BOX64_DYNAREC_FASTPAGE *
+Will use a faster handling of HotPage (Page being both executed and written)
+* 0 : use regular hotpage (Default)
+* 1 : Use faster hotpage, taking the risk of running obsolete JIT code (might be faster, but more prone to crash)
+
+#### BOX64_DYNAREC_BLEEDING_EDGE *
+Detect MonoBleedingEdge and apply conservative settings
+* 0 : Don't detect MonoBleedingEdge
+* 1 : Detect MonoBleedingEdge, and apply BIGBLOCK=0 STRONGMEM=1 if detected (Default)
+
+#### BOX64_DYNAREC_JVM *
+Detect libjvm and apply conservative settings
+* 0 : Don't detect libjvm
+* 1 : Detect libjvm, and apply BIGBLOCK=0 STRONGMEM=1 if detected (Default)
+
+#### BOX64_DYNAREC_WAIT *
+Behavior with FillBlock is not availble (FillBlock build Dynarec blocks and is not multithreaded)
+* 0 : Dynarec will not wait for FillBlock to ready and use Interpreter instead (might speedup a bit massive multithread or JIT programs)
+* 1 : Dynarec will wait for FillBlock to be ready (Default)
+
+#### BOX64_DYNAREC_MISSING *
+Dynarec print the missing opcodes
+* 0 : not print the missing opcode (Default, unless DYNAREC_LOG>=1 or DYNAREC_DUMP>=1 is used)
+* 1 : Will print the missing opcodes
+
+#### BOX64_SSE_FLUSHTO0 *
+Handling of SSE Flush to 0 flags
+* 0 : Just track the flag (Default)
+* 1 : Direct apply of SSE Flush to 0 flag
+
+#### BOX64_X87_NO80BITS *
+Handling of x87 80bits long double
+* 0 : Try to handle 80bits long double as precise as possible (Default)
+* 1 : Handle them as double
+
+#### BOX64_LIBCEF *
+Detect libcef and apply malloc_hack settings
+* 0 : Don't detect libcef
+* 1 : Detect libcef, and apply MALLOC_HACK=2 if detected (Default)
+
+#### BOX64_LIBGL *
+ * libXXXX set the name for libGL (defaults to libGL.so.1).
+ * /PATH/TO/libGLXXX : Sets the name and path for libGL
+ You can also use SDL_VIDEO_GL_DRIVER
+
+#### BOX64_LD_PRELOAD
+ * XXXX[:YYYYY] force loading XXXX (and YYYY...) libraries with the binary
+ PreLoaded libs can be emulated or native, and are treated the same way as if they were comming from the binary
+ 
+#### BOX64_EMULATED_LIBS *
+ * XXXX[:YYYYY] force lib XXXX (and YYYY...) to be emulated (and not wrapped)
+Some games uses an old version of some libraries, with an ABI incompatible with native version.
+Note that LittleInferno for example is auto detected, and libvorbis.so.0 is automatical added to emulated libs, and same for Don't Starve (and Together / Server variant) that use an old SDL2 too
+
+#### BOX64_ALLOWMISSINGLIBS *
+Allow Box64 to continue even if a library is missing.
+ * 0 : Box64 will stop if a library cannot be loaded. (Default.)
+ * 1 : Continue even if a needed library cannot be loaded. Unadvised, this will, in most cases, crash later on.
+
+#### BOX64_PREFER_WRAPPED *
+Box64 will use wrapped libs even if the lib is specified with absolute path
+ * 0 : Try to use emulated libs when they are defined with absolute path  (Default.)
+ * 1 : Use Wrapped native libs even if path is absolute
+
+#### BOX64_PREFER_EMULATED *
+Box64 will prefer emulated libs first (execpt for glibc, alsa, pulse, GL, vulkan and X11
+ * 0 : Native libs are prefered (Default.)
+ * 1 : Emulated libs are prefered (Default for program running inside pressure-vessel)
+
+#### BOX64_CRASHHANDLER *
+Box64 will use a dummy crashhandler.so library
+ * 0 : Use Emulated crashhandler.so library if needed
+ * 1 : Use an internal dummy (completly empty) crashhandler.so library (defaut)
+
+#### BOX64_MALLOC_HACK *
+How Box64 will handle hooking of malloc operators
+ * 0 : Don't allow malloc operator to be redirected, rewriting code to use regular function (Default)
+ * 1 : Allow malloc operator to be redirected (not advised)
+ * 2 : Like 0, but track special mmap / free (some redirected functions were inlined and cannot be redirected)
+
+#### BOX64_NOPULSE *
+Disables the load of pulseaudio libraries.
+ * 0 : Load pulseaudio libraries if found. (Default.)
+ * 1 : Disables the load of pulse audio libraries (libpulse and libpulse-simple), both the native library and the x86 library
+
+#### BOX64_NOGTK *
+Disables the loading of wrapped GTK libraries.
+ * 0 : Load wrapped GTK libraries if found. (Default.)
+ * 1 : Disables loading wrapped GTK libraries.
+
+#### BOX64_NOVULKAN *
+Disables the load of vulkan libraries.
+ * 0 : Load vulkan libraries if found.
+ * 1 : Disables the load of vulkan libraries, both the native and the i386 version (can be useful on Pi4, where the vulkan driver is not quite there yet.)
+
+#### BOX64_BASH *
+Define x86_64 bash to launch script
+ * yyyy
+ Will use yyyy as x86_64 bash to launch script. yyyy needs to be a full path to a valid x86_64 version of bash
+
+#### BOX64_ENV
+ * XXX=yyyy
+ will add XXX=yyyy env. var.
+
+#### BOX64_ENV1
+ * XXX=yyyy
+ will add XXX=yyyy env. var. and continue with BOX86_ENV2 ... until var doesn't exist
+
+#### BOX64_JITGDB *
+ * 0 : Just print the Segfault message on segfault (default)
+ * 1 : Launch `gdb` when a segfault, bus error or illegal instruction signal is trapped, attached to the offending process and go in an endless loop, waiting.
+ When in gdb, you need to find the correct thread yourself (the one with `my_box64signalhandler` in is stack)
+ then probably need to `finish` 1 or 2 functions (inside `usleep(..)`) and then you'll be in `my_box64signalhandler`, 
+ just before the printf of the Segfault message. Then simply 
+ `set waiting=0` to exit the infinite loop.
+ * 2 : Launch `gdbserver` when a segfault, bus error or illegal instruction signal is trapped, attached to the offending process, and go in an endless loop, waiting.
+ Use `gdb /PATH/TO/box64` and then `target remote 127.0.0.1:1234` to connect to the gdbserver (or use actual IP if not on the machine). After that, the procedure is the same as with ` BOX64_JITGDB=1`.
+ This mode can be usefullwhen programs redirect all console output to a file (like Unity3D Games)
+
+#### BOX64_NORCFILES
+If the env var exist, no rc files (like /etc/box64.box64rc and ~/.box64rc) will be loaded
+
+----
+
+Those variables are only valid inside a rcfile:
+----
+
+#### BOX64_NOSANDBOX
+ * 0 : Nothing special
+ * 1 : Added "--no-sandbox" to command line arguments (usefull for chrome based programs)
+
+#### BOX64_EXIT
+ * 0 : Nothing special
+ * 1 : Just exit, don't try to run the program
+
+#### BOX64_RESERVE_HIGH
+* 0 : Don't try to pe-reserve high memory (beyond 47bits) (Default)
+* 1 : Try to reserve (without allocating it) memory beyond 47bits (seems unstable)

docs/X64WINE.md

@@ -0,0 +1,177 @@
+# Installing Wine64
+Running Wine64/Wine with Box64/Box86 allows x64/x86 Windows programs to run on 64-bit ARM Linux devices.
+ - Box64 needs `wine-amd64` to be installed **manually** on ARM64 (aarch64) devices.  This will run 64-bit Windows programs (aka x86_64).
+ - Box86 needs `wine-i386` to be installed **manually** on ARM32 (armhf) devices (or on ARM64 with multiarch or chroot).  This will run 32-bit Windows programs (aka x86).
+ - _Note that `wine:arm64` and `wine:armhf` will not work with Box64/Box86. Your device's package manager might try to install those if you ask it to install wine._
+
+See installation steps below (in the [Examples](#examples) section).
+
+## Overview
+The general procedure for installing Wine64 & Wine for Box64 & Box86 is to...
+ - Download all the install files for the version of Wine you wish to install
+ - Unzip or dpkg the install files into one folder
+ - Move that folder to the directory that you wish Wine to run from (often `~/wine/` by default)
+ - Go to `/usr/local/bin` and make symlinks or scripts that will point to your main wine binaries.
+ - Boot wine to create a new wineprefix.
+ - Download winetricks (which is just a complicated bash script), make it executable, then copy it to `/usr/local/bin`.
+
+## Examples
+### Installing Wine64 & Wine for Box64 & Box86 on Raspberry Pi OS from WineHQ .deb files
+_Links from the [WineHQ repo](https://dl.winehq.org/wine-builds/debian/dists/)_
+
+This install method allows you to install different versions of Wine64/Wine.  You may install any version/branch of Wine that you wish.
+```
+	# NOTE: Can only run on aarch64 (since box64 can only run on aarch64)
+	# box64 runs wine-amd64, box86 runs wine-i386.
+
+	### User-defined Wine version variables ################
+	# - Replace the variables below with your system's info.
+	# - Note that we need the amd64 version for Box64 even though we're installing it on our ARM processor.
+	# - Note that we need the i386 version for Box86 even though we're installing it on our ARM processor.
+	# - Wine download links from WineHQ: https://dl.winehq.org/wine-builds/
+  
+	local branch="devel" #example: devel, staging, or stable (wine-staging 4.5+ requires libfaudio0:i386)
+	local version="7.1" #example: "7.1"
+	local id="debian" #example: debian, ubuntu
+	local dist="bullseye" #example (for debian): bullseye, buster, jessie, wheezy, ${VERSION_CODENAME}, etc 
+	local tag="-1" #example: -1 (some wine .deb files have -1 tag on the end and some don't)
+
+  ########################################################
+
+	# Clean up any old wine instances
+	wineserver -k # stop any old wine installations from running
+	rm -rf ~/.cache/wine # remove any old wine-mono/wine-gecko install files
+	rm -rf ~/.local/share/applications/wine # remove any old program shortcuts
+
+	# Backup any old wine installs
+	rm -rf ~/wine-old 2>/dev/null; mv ~/wine ~/wine-old 2>/dev/null
+	rm -rf ~/.wine-old 2>/dev/null; mv ~/.wine ~/.wine-old 2>/dev/null
+	sudo mv /usr/local/bin/wine /usr/local/bin/wine-old 2>/dev/null
+	sudo mv /usr/local/bin/wine64 /usr/local/bin/wine-old 2>/dev/null
+	sudo mv /usr/local/bin/wineboot /usr/local/bin/wineboot-old 2>/dev/null
+	sudo mv /usr/local/bin/winecfg /usr/local/bin/winecfg-old 2>/dev/null
+	sudo mv /usr/local/bin/wineserver /usr/local/bin/wineserver-old 2>/dev/null
+
+	# Wine download links from WineHQ: https://dl.winehq.org/wine-builds/
+	LNKA="https://dl.winehq.org/wine-builds/${id}/dists/${dist}/main/binary-amd64/" #amd64-wine links
+	DEB_A1="wine-${branch}-amd64_${version}~${dist}${tag}_amd64.deb" #wine64 main bin
+	DEB_A2="wine-${branch}_${version}~${dist}${tag}_amd64.deb" #wine64 support files (required for wine64 / can work alongside wine_i386 main bin)
+		#DEB_A3="winehq-${branch}_${version}~${dist}${tag}_amd64.deb" #shortcuts & docs
+	LNKB="https://dl.winehq.org/wine-builds/${id}/dists/${dist}/main/binary-i386/" #i386-wine links
+	DEB_B1="wine-${branch}-i386_${version}~${dist}${tag}_i386.deb" #wine_i386 main bin
+	DEB_B2="wine-${branch}_${version}~${dist}${tag}_i386.deb" #wine_i386 support files (required for wine_i386 if no wine64 / CONFLICTS WITH wine64 support files)
+		#DEB_B3="winehq-${branch}_${version}~${dist}${tag}_i386.deb" #shortcuts & docs
+
+	# Install amd64-wine (64-bit) alongside i386-wine (32-bit)
+	echo -e "Downloading wine . . ."
+	wget -q ${LNKA}${DEB_A1} 
+	wget -q ${LNKA}${DEB_A2} 
+	wget -q ${LNKB}${DEB_B1} 
+	echo -e "Extracting wine . . ."
+	dpkg-deb -x ${DEB_A1} wine-installer
+	dpkg-deb -x ${DEB_A2} wine-installer
+	dpkg-deb -x ${DEB_B1} wine-installer
+	echo -e "Installing wine . . ."
+	mv wine-installer/opt/wine* ~/wine
+	
+	# Download wine dependencies
+	# - these packages are needed for running box86/wine-i386 on a 64-bit RPiOS via multiarch
+	sudo dpkg --add-architecture armhf && sudo apt-get update # enable multi-arch
+	sudo apt-get install -y libasound2:armhf libc6:armhf libglib2.0-0:armhf libgphoto2-6:armhf libgphoto2-port12:armhf \
+		libgstreamer-plugins-base1.0-0:armhf libgstreamer1.0-0:armhf libldap-2.4-2:armhf libopenal1:armhf libpcap0.8:armhf \
+		libpulse0:armhf libsane1:armhf libudev1:armhf libusb-1.0-0:armhf libvkd3d1:armhf libx11-6:armhf libxext6:armhf \
+		libasound2-plugins:armhf ocl-icd-libopencl1:armhf libncurses6:armhf libncurses5:armhf libcap2-bin:armhf libcups2:armhf \
+		libdbus-1-3:armhf libfontconfig1:armhf libfreetype6:armhf libglu1-mesa:armhf libglu1:armhf libgnutls30:armhf \
+		libgssapi-krb5-2:armhf libkrb5-3:armhf libodbc1:armhf libosmesa6:armhf libsdl2-2.0-0:armhf libv4l-0:armhf \
+		libxcomposite1:armhf libxcursor1:armhf libxfixes3:armhf libxi6:armhf libxinerama1:armhf libxrandr2:armhf \
+		libxrender1:armhf libxxf86vm1 libc6:armhf libcap2-bin:armhf # to run wine-i386 through box86:armhf on aarch64
+		# This list found by downloading...
+		#	wget https://dl.winehq.org/wine-builds/debian/dists/bullseye/main/binary-i386/wine-devel-i386_7.1~bullseye-1_i386.deb
+		#	wget https://dl.winehq.org/wine-builds/debian/dists/bullseye/main/binary-i386/winehq-devel_7.1~bullseye-1_i386.deb
+		#	wget https://dl.winehq.org/wine-builds/debian/dists/bullseye/main/binary-i386/wine-devel_7.1~bullseye-1_i386.deb
+		# then `dpkg-deb -I package.deb`. Read output, add `:armhf` to packages in dep list, then try installing them on Pi aarch64.
+		
+	# - these packages are needed for running box64/wine-amd64 on RPiOS (box64 only runs on 64-bit OS's)
+	sudo apt-get install -y libasound2:arm64 libc6:arm64 libglib2.0-0:arm64 libgphoto2-6:arm64 libgphoto2-port12:arm64 \
+		libgstreamer-plugins-base1.0-0:arm64 libgstreamer1.0-0:arm64 libldap-2.4-2:arm64 libopenal1:arm64 libpcap0.8:arm64 \
+		libpulse0:arm64 libsane1:arm64 libudev1:arm64 libunwind8:arm64 libusb-1.0-0:arm64 libvkd3d1:arm64 libx11-6:arm64 libxext6:arm64 \
+		ocl-icd-libopencl1:arm64 libasound2-plugins:arm64 libncurses6:arm64 libncurses5:arm64 libcups2:arm64 \
+		libdbus-1-3:arm64 libfontconfig1:arm64 libfreetype6:arm64 libglu1-mesa:arm64 libgnutls30:arm64 \
+		libgssapi-krb5-2:arm64 libjpeg62-turbo:arm64 libkrb5-3:arm64 libodbc1:arm64 libosmesa6:arm64 libsdl2-2.0-0:arm64 libv4l-0:arm64 \
+		libxcomposite1:arm64 libxcursor1:arm64 libxfixes3:arm64 libxi6:arm64 libxinerama1:arm64 libxrandr2:arm64 \
+		libxrender1:arm64 libxxf86vm1:arm64 libc6:arm64 libcap2-bin:arm64
+		# This list found by downloading...
+		#	wget https://dl.winehq.org/wine-builds/debian/dists/bullseye/main/binary-amd64/wine-devel_7.1~bullseye-1_amd64.deb
+		#	wget https://dl.winehq.org/wine-builds/debian/dists/bullseye/main/binary-amd64/wine-devel-amd64_7.1~bullseye-1_amd64.deb
+		# then `dpkg-deb -I package.deb`. Read output, add `:arm64` to packages in dep list, then try installing them on Pi aarch64.	
+
+	# These packages are needed for running wine-staging on RPiOS (Credits: chills340)
+	sudo apt install libstb0 -y
+	cd ~/Downloads
+	wget -r -l1 -np -nd -A "libfaudio0_*~bpo10+1_i386.deb" http://ftp.us.debian.org/debian/pool/main/f/faudio/ # Download libfaudio i386 no matter its version number
+	dpkg-deb -xv libfaudio0_*~bpo10+1_i386.deb libfaudio
+	sudo cp -TRv libfaudio/usr/ /usr/
+	rm libfaudio0_*~bpo10+1_i386.deb # clean up
+	rm -rf libfaudio # clean up
+
+	# Install symlinks
+	sudo ln -s ~/wine/bin/wine /usr/local/bin/wine
+	sudo ln -s ~/wine/bin/wine64 /usr/local/bin/wine64
+	sudo ln -s ~/wine/bin/wineboot /usr/local/bin/wineboot
+	sudo ln -s ~/wine/bin/winecfg /usr/local/bin/winecfg
+	sudo ln -s ~/wine/bin/wineserver /usr/local/bin/wineserver
+	sudo chmod +x /usr/local/bin/wine /usr/local/bin/wine64 /usr/local/bin/wineboot /usr/local/bin/winecfg /usr/local/bin/wineserver
+```
+
+## Installing winetricks
+Winetricks is a bash script which makes it easier to install & configure any desired Windows core system software packages which may be dependencies for certain Windows programs.  You can either install it with `apt`, or manually using the steps below.
+
+```
+sudo apt-get install cabextract -y                                                                   # winetricks needs this installed
+sudo mv /usr/local/bin/winetricks /usr/local/bin/winetricks-old                                      # Backup old winetricks
+cd ~/Downloads && wget https://raw.githubusercontent.com/Winetricks/winetricks/master/src/winetricks # Download
+sudo chmod +x winetricks && sudo mv winetricks /usr/local/bin/                                       # Install
+```
+
+Whenever we run winetricks, we must tell Box86 to supress its info banner, otherwise winetricks will crash.  Box86's info banner can be suppressed using the `BOX86_NOBANNER=1` environment variable before invoking winetricks (example: `BOX86_NOBANNER=1 winetricks`).
+
+If `apt` installed a desktop menu shortcut for winetricks (or if you make your own desktop shortcut for winetricks) then you may need to edit that shortcut to include Box86's BOX86_NOBANNER=1 env var.  With your favorite text editor, edit `/usr/share/applications/winetricks.desktop` and change `Exec=winetricks --gui` to `Exec=env BOX86_NOBANNER=1 winetricks --gui`.
+
+## Example commands
+Creating a 64-bit wineprefix:
+`wine64 wineboot` or `wine wineboot` (wineprefix is created in `~/.wine/`)
+`WINEPREFIX="$HOME/prefix64" wine wineboot` (wineprefix is created in `~/prefix64/`) _Note: You will need to invoke `WINEPREFIX="$HOME/prefix64"` before every command to use this wineprefix._
+
+Creating a 32-bit wineprefix:
+`WINEARCH=win32 wine wineboot` (wineprefix is created in `~/.wine/`)
+
+Fore-quitting wine:
+`wineserver -k`
+
+Running Wine Configuration:
+`winecfg`
+
+Using winetricks:
+`winetricks -q corefonts vcrun2010 dotnet20sp1`  
+_This command will silently install three packages in series: Windows core fonts, VC++ 2010 Runtimes, and .NET 2.0 SP1.  `-q` is the "install silent/quiet" command._
+
+Invoking Box86's logging features (with `BOX86_LOG=1` or similar) will cause winetricks to crash.
+
+For a list of all the different Windows packages & libraries that winetricks can help you install, run `winetricks list-all`  
+
+## Other notes
+
+### Wineprefixes (and Wine initialization)
+When you first run or boot Wine (`wine wineboot`), Wine will create a new user environment within which to install Windows software.  This user environment is called a "wineprefix" (or "wine bottle") and is located (by default) in `~/.wine` (note that Linux folders with a `.` in front of them are "hidden" folders).  Think of a wineprefix as Wine's virtual 'harddrive' where it installs software and saves settings.  Wineprefixes are portable and deletable.  For more Wine documentation, see [WineHQ](https://www.winehq.org/documentation).
+
+If you at any point corrupt something inside your default wineprefix, you can start "fresh" by deleting your `~/.wine` directory (with the `rm -rf ~/.wine` command) and boot wine again to create a new default wineprefix.
+
+### Transplanting wineprefixes
+If software isn't installing in Wine with Box86, but is installing for you in Wine on a regular x86 Linux computer, you can copy a wineprefix from your x86 Linux computer to the device you're running Box86 on. This is most easily done by tarring the `~/.wine` folder on your x86 Linux computer (`tar -cvf winebottle.tar ~/.wine`), transferring the tar file to your device, then un-tarring the tar file (`tar -xf winebottle.tar`) on your device running Box86 & Wine. Tarring the wineprefix preserves any symlinks that are inside it.
+
+### Swapping out different versions of Wine
+Some versions of Wine work better with certain software. It is best to install a version of Wine that is known to work with the software you would like to run. There are three main development branches of Wine you can pick from, referred to as wine-stable, wine-devel, and wine-staging. _Note that the wine-staging branch requires extra installation steps on Raspberry Pi._
+
+Your entire Wine installation can reside within a single folder on your Linux computer. TwisterOS assumes that your Wine installation is located inside the `~/wine/` directory. The actual directory where you put your `wine` folder doesn't matter as long as you have symlinks within the `/usr/local/bin/` directory which point to the `wine` folder so that Linux can find Wine when you type `wine` into the terminal).
+
+You can change which version of Wine you are running simply by renaming your old `wine` and `.wine` folders to something else, then putting a new `wine` folder (containing your new version of Wine) in its place. Running `wine wineboot` again will migrate a wineprefix from an older version of Wine to be usable by the newer version of Wine you just installed.  You can check which version of Wine you're running with the `wine --version` command.

docs/box64.pod

@@ -0,0 +1,465 @@
+=head1 NAME
+
+box64 - Linux Userspace x86_64 Emulator with a twist
+
+=head1 SYNOPSIS
+
+B<box64> [B<--help>] [B<--version>] I<executable>
+
+=head1 DESCRIPTION
+
+B<Box64> lets you run x86_64 Linux programs (such as games) on non-x86_64 Linux
+systems, like ARM (host system needs to be 64-bit little-endian). Since B<Box64>
+uses the native versions of some "system" libraries, like libc, libm, SDL, and
+OpenGL, it's easy to integrate and use with most applications, and performance
+can be surprisingly high in many cases. B<Box64> integrates with DynaRec (dynamic
+recompiler) for the ARM64 platform, providing a speed boost between 5 to 10
+times faster than using only the interpreter.
+
+=head1 OPTIONS
+
+=over 8
+
+=item B<-h,--help>
+
+Print box64 help and quit.
+
+=item B<-v,--version>
+
+Print box64 version and quit.
+
+=back
+
+=head1 CONFIGURATION FILE
+
+B<Box64> now have configurations files. There are 2 files loaded.
+F</etc/box4.box64rc> and F<~/.box64rc>. Both files have the same syntax, and is
+basically an ini files. Section in square brackets define the process name, and
+the rest is the environment variable. B<Box64> comes with a default file that
+should be installed for better stability. Note that the priority is:
+F<~/.bashrc> > F</etc/box64.box64rc> > command line So, your settings in
+F<~/.bashrc> may override the setting from your command line. Example:
+
+    [factorio]
+    BOX64_DYNAREC_SAFEFLAGS=0
+    BOX64_DYNAREC_BIGBLOCK=2
+    BOX64_DYNAREC_FORWARD=1024
+    BOX64_DYNAREC_CALLRET=1
+
+=head1 VARIABLES FOR RCFILE ONLY
+
+=over 8
+
+=item B<BOX64_NOSANDBOX=0|1>
+
+When set to 1, add C<--no-sandbox> to command line arguments (useful for chrome
+based programs).
+
+=item B<BOX64_EXIT>=I<0|1>
+
+When set to 1, just exit, don't try to run the program.
+
+=back
+
+=head1 VARIABLES ONLY FOR ENVIRONMENT AND NOT RCFILE
+
+=over 8
+
+=item B<BOX64_NOBANNER>=I<0|1>
+
+When set to 1, don't prints the banner including version and build.
+
+=item B<BOX64_LD_PRELOAD>=I<lib1>[:I<lib2>:...]
+
+Force loading libraries with the  binary. PreLoaded libs can be emulated or
+native, and are treated the same way as if they were comming from the binary.
+
+=item B<BOX64_ENV>=I<env=val>
+
+Add an variable with value to the environment.
+
+=item B<BOX64_ENV1>=I<env=val> B<BOX64_ENV2>=I<env=val> ...
+
+Add arbitrary many variables using B<BOX64_ENV1>, B<BOX64_ENV2>, ...
+
+=item B<BOX64_NORCFILES>
+
+No rc files (like F</etc/box64.box64rc> and F<~/.box64rc>) will be loaded.
+
+=back
+
+=head1 VARIABLES FOR BOTH ENVIRONMENT AND RCFILE
+
+=over 8
+
+=item B<BOX64_LOG>=I<0|NONE|1|INFO|2|DEBUG|3|DUMP>
+
+Controls the Verbosity level of the logs
+
+    * 0 or NONE : No message (except some fatal error). (Default.)
+    * 1 or INFO : Show some minimum log (Example: libraries not found)
+    * 2 or DEBUG : Details a lot of stuff (Example: relocations or functions called).
+    * 3 or DUMP : All DEBUG plus DUMP of all ELF Info.
+
+=item B<BOX64_ROLLING_LOG>=I<0|1|N>
+
+Show last few wrapped function call when a Signal is caught. Incompatible with
+B<BOX64_LOG> > 1 (may need B<BOX64_SHOWSEGV=1> also)
+
+    * 0: No last function call printed (Default.)
+    * 1: Last 16 wrapped functions calls printed when a signal is printed.
+    * N: Last N wrapped functions calls printed when a signal is printed.
+
+=item B<BOX64_LD_LIBRARY_PATH>=I</path/to/libs>
+
+Path to look for x86_64 libraries. Default is current folder and C<lib> in
+current folder.  Also, F</usr/lib/x86_64-linux-gnu> and
+F</lib/x86_64-linux-gnu> are added if they exist.
+
+=item B<BOX64_PATH>=I</path/to/bins>
+
+Path to look for x86_64 executable. Default is current folder and C<bin> in
+current folder.
+
+=item B<BOX64_DLSYM_ERROR>=I<0|1>
+
+Enables/Disables the logging of `dlsym` errors.
+
+    * 0 : Don't log `dlsym` errors. (Default.)
+    * 1 : Log dlsym errors.
+
+=item B<BOX64_TRACE_FILE>=I</path/to/file>
+
+Send all log and trace to a file instead of C<stdout>.  Also, if name contains
+C<%pid> then this is replaced by the actual C<PID> of B<box64> instance.  End
+the filename with `+` to have thetrace appended instead of overwritten Use
+C<stderr> to use this instead of default C<stdout>.
+
+=item B<BOX64_TRACE>=I<0|1|symbolname|0xXXXXXXX-0xYYYYYYY>
+
+Only on build with trace enabled. Trace allow the logging of all instruction executed, along with register dump
+
+    * 0 : No trace. (Default.)
+    * 1 : Trace enabled. Trace start after the initialisation of all depending libraries is done.
+    * symbolname : Trace only `symbolname` (trace is disable if the symbol is not found).
+    * 0xXXXXXXX-0xYYYYYYY : Trace only between the 2 addresses.
+
+=item B<BOX64_TRACE_INIT>=I<0|1>
+
+Use B<BOX64_TRACE_INIT> instead of B<BOX_TRACE> to start trace before the
+initialization of libraries and the running program
+
+    * 0 : No trace. (Default.)
+    * 1 : Trace enabled. The trace start with the initialisation of all depending libraries is done.
+
+=item B<BOX64_TRACE_START>=I<NNNNNNN>
+
+Only on builds with trace enabled. Start trace only after I<NNNNNNNN> opcode
+execute (number is an `uint64_t`).
+
+=item B<BOX64_TRACE_XMM>=I<0|1>
+
+Only on builds with trace enabled.
+
+    * 0 : The XMM (i.e. SSE/SSE2) register will not be logged with the general and x86 registers. (Default.)
+    * 1 : Dump the XMM registers.
+
+=item B<BOX64_TRACE_EMM>=I<0|1>
+
+Only on builds with trace enabled.
+
+    * 0 : The EMM (i.e. MMX) register will not be logged with the general and x86 registers. (Default.)
+    * 1 : Dump the EMM registers.
+
+=item B<BOX64_TRACE_COLOR>=I<0|1>
+
+Only on builds with trace enabled.
+
+    * 0 : The general registers will always be the default white color. (Default.)
+    * 1 : The general registers will change color in the dumps when they changed value.
+
+=item B<BOX64_LOAD_ADDR>=I<0xXXXXXXXX>
+
+Try to load at C<0xXXXXXX> main binary (if binary is a PIE). 
+
+=item B<BOX64_NOSIGSEGV>=I<0|1>
+
+Disable handling of SigSEGV. (Very useful for debugging.)
+
+    * 0 : Let the x86 program set sighandler for SEGV (Default.)
+    * 1 : Disable the handling of SigSEGV.
+
+=item B<BOX64_NOSIGILL>=I<0|1>
+
+Disable handling of SigILL (to ease debugging mainly).
+
+    * 0 : Let x86 program set sighandler for Illegal Instruction
+    * 1 : Disables the handling of SigILL
+
+=item B<BOX64_SHOWSEGV>=I<0|1>
+
+Show Segfault signal even if a signal handler is present
+
+    * 0 : Don"t force show the SIGSEGV analysis (Default.)
+    * 1 : Show SIGSEGV detail, even if a signal handler is present
+
+=item B<BOX64_SHOWBT>=I<0|1>
+
+Show some Backtrace (Nativ e and Emulated) whgen a signal (SEGV, ILL or BUS) is caught
+
+    * 0 : Don"t show backtraces (Default.)
+    * 1 : Show Backtrace detail (for native, box64 is rename as the x86_64 binary run)
+
+=item B<BOX64_X11THREADS>=I<0|1>
+
+Call XInitThreads when loading X11. (This is mostly for old Loki games with the Loki_Compat library.)
+
+    * 0 : Don't force call XInitThreads. (Default.)
+    * 1 : Call XInitThreads as soon as libX11 is loaded.
+
+=item B<BOX64_X11GLX>=I<0|1>
+
+Force libX11's GLX extension to be present.
+
+    * 0 : Do not force libX11's GLX extension to be present. 
+    * 1 : GLX will always be present when using XQueryExtension. (Default.)
+
+=item B<BOX64_DYNAREC_DUMP>=I<0|1|2>
+
+Enables/disables Box64's Dynarec's dump.
+
+    * 0 : Disable Dynarec's blocks dump. (Default.)
+    * 1 : Enable Dynarec's blocks dump.
+    * 2 : Enable Dynarec's blocks dump with some colors.
+
+=item B<BOX64_DYNAREC_LOG>=I<0|1|2|3>
+
+Set the level of DynaRec's logs.
+
+    * 0 : NONE : No Logs for DynaRec. (Default.)
+    * 1 :INFO : Minimum Dynarec Logs (only unimplemented OpCode).
+    * 2 : DEBUG : Debug Logs for Dynarec (with details on block created / executed).
+    * 3 : VERBOSE : All of the above plus more.
+
+=item B<BOX64_DYNAREC>=I<0|1>
+
+Enables/Disables Box64's Dynarec.
+
+    * 0 : Disables Dynarec.
+    * 1 : Enable Dynarec. (Default.)
+
+=item B<BOX64_DYNAREC_TRACE>=I<0|1>
+
+Enables/Disables trace for generated code. Like regular Trace, this will slow
+down the program a lot and generate huge logs.
+
+    * 0 : Disable trace for generated code. (Default.)
+    * 1 : Enable trace for generated code
+
+=item B<BOX64_NODYNAREC>=I<0xXXXXXXXX-0xYYYYYYYY>
+
+Forbid dynablock creation in the interval specified (helpfull for debugging
+behaviour difference between Dynarec and Interpretor)
+
+=item B<BOX64_DYNAREC_TEST>=I<0|1>
+
+Enables/Disables test for generated code. This will run interpreter along the Dynacrec, so this will slow
+down the program a lot.
+
+    * 0 : No test for generated code. (Default.)
+    * 1 : Enable Tests for generated code
+
+=item B<BOX64_DYNAREC_BIGBLOCK>=I<0|1|2|3>
+
+Enables/Disables Box64's Dynarec building BigBlock.
+
+ * 0 : Don't try to build block as big as possible (can help program using lots of thread and a JIT, like C#/Unity) (Default when libmonobdwgc-2.0.so is loaded)
+ * 1 : Build Dynarec block as big as possible (Default.)
+ * 2 : Build Dynarec block bigger (don't stop when block overlaps, but only for blocks in elf memory)
+ * 3 : Build Dynarec block bigger (don't stop when block overlaps, for all type of memory)
+
+=item B<BOX64_DYNAREC_FORWARD>=I<0|XXX>
+
+Define Box64's Dynarec max allowed forward value when building Block.
+
+    * 0 : No forward value. When current block end, don't try to go further even if there are previous forward jumps
+    * XXX : Allow up to XXXX bytes of gap when building a Block after the block end to next forward jump (Default: 128)
+ 
+=item B<BOX64_DYNAREC_STRONGMEM>=I<0|1|2>
+
+Enable/Disable simulation of Strong Memory model
+
+    * 0 : Don't try anything special (Default.)
+    * 1 : Enable some Memory Barrier when reading from memory (on some MOV opcode) to simulate Strong Memory Model while trying to limit performance impact (Default when libmonobdwgc-2.0.so is loaded)
+    * 2 : Enable some Memory Barrier when reading from memory (on some MOV opcode) to simulate Strong Memory Model
+
+=item B<BOX64_DYNAREC_X87DOUBLE>=I<0|1>
+
+Force the use of Double for x87 emulation
+
+    * 0 : Try to use float when possible for x87 emulation (default, faster)
+    * 1 : Only use Double for x87 emulation (slower, may be needed for some specific games, like Crysis)
+
+=item B<BOX64_DYNAREC_FASTNAN>=I<0|1>
+
+Enable/Disable generation of -NAN
+
+    * 0 : Generate -NAN like on x86
+    * 1 : Don't do anything special with NAN, to go as fast as possible (default, faster)
+
+=item B<BOX64_DYNAREC_FASTROUND>=I<0|1>
+
+Enable/Disable generation of precise x86 rounding
+
+    * 0 : Generate float/double -> int rounding like on x86
+    * 1 : Don't do anything special with edge case Rounding, to go as fast as possible (no INF/NAN/Overflow -> MIN_INT conversion) (default, faster)
+
+=item B<BOX64_DYNAREC_SAFEFLAGS>=I<0|1|2>
+
+Handling of flags on CALL/RET opcodes
+
+    * 0 : Treat CALL/RET as if it never needs any flags (faster but not advised)
+    * 1 : most of RET will need flags, most of CALLS will not (Default)
+    * 2 : All CALL/RET will need flags (slower, but might be needed. Automatically enabled for Vara.exe)
+
+=item B<BOX64_DYNAREC_CALLRET>=I<0|1>
+
+Optimisation of CALL/RET opcodes (not compatible with jit/dynarec/smc)
+
+    * 0 : Don't optimize CALL/RET, use Jump Table for boths (Default)
+    * 1 : Try to optimized CALL/RET, skipping the use of the JumpTable when possible (will crash if blacks are invalidate, so probably incompatible with JIT/Dynarec)
+
+=item B<BOX64_DYNAREC_HOTPAGE>=I<0|1-255>
+
+Handling of HotPage (Page beeing both executed and writen)
+
+    * 0 : Don't track hotpage
+    * 1-255 : Track HotPage, and disable execution of a page beeing writen for N attempts (default is 4)
+
+=item B<BOX64_DYNAREC_FASTPAGE>=I<0|1>
+
+Will use a faster handling of HotPage (Page beeing both executed and writen)
+
+    * 0 : use regular hotpage (Default)
+    * 1 : Use faster hotpage, taking the risk of running obsolete JIT code (might be faster, but more prone to crash)
+
+=item B<BOX64_DYNAREC_BLEEDING_EDGE>=I<0|1>
+
+Detect MonoBleedingEdge and apply conservative settings
+
+    * 0 : Don't detect MonoBleedingEdge
+    * 1 : Detect MonoBleedingEdge, and apply BIGBLOCK=0 STRONGMEM=1 if detected (Default)
+
+=item B<BOX64_DYNAREC_WAIT>=I<0|1>
+
+Behavior with FillBlock is not availble (FillBlock build Dynarec blocks and is not multithreaded)
+
+    * 0 : Dynarec will not wait for FillBlock to ready and use Interpreter instead (might speedup a bit massive multithread or JIT programs)
+    * 1 : Dynarec will wait for FillBlock to be ready (Default)
+
+=item B<BOX64_SSE_FLUSHTO0>=I<0|1>
+
+Handling of SSE Flush to 0 flags
+
+    * 0 : Just track the flag (Default)
+    * 1 : Direct apply of SSE Flush to 0 flag
+
+=item B<BOX64_X87_NO80BITS>=I<0|1>
+
+Handling of x87 80bits long double
+
+    * 0 : Try to handle 80bits long double as precise as possible (Default)
+    * 1 : Handle them as double
+
+=item B<BOX64_LIBCEF>=I<0|1>
+
+Detect libcef and apply malloc_hack settings
+
+    * 0 : Don't detect libcef
+    * 1 : Detect libcef, and apply MALLOC_HACK=2 if detected (Default)
+
+=item B<BOX64_LIBGL>=I<libXXXX|/PATH/TO/libGLXXX>
+
+You can also use B<SDL_VIDEO_GL_DRIVER>
+
+     * libXXXX set the name for libGL (defaults to libGL.so.1).
+     * /PATH/TO/libGLXXX : Sets the name and path for libGL
+
+=item B<BOX64_EMULATED_LIBS>=I<XXXX[:YYYY:...]>
+
+Force lib XXXX (and YYYY...) to be emulated (and not wrapped) Some games uses
+an old version of some libraries, with an ABI incompatible with native version.
+Note that LittleInferno for example is auto detected, and libvorbis.so.0 is
+automatical added to emulated libs, and same for Don't Starve (and Together /
+Server variant) that use an old SDL2 too
+
+=item B<BOX64_ALLOWMISSINGLIBS>=I<0|1>
+
+Allow Box64 to continue even if a library is missing.
+
+    * 0 : Box64 will stop if a library cannot be loaded. (Default.)
+    * 1 : Continue even if a needed library cannot be loaded. Unadvised, this will, in most cases, crash later on.
+
+=item B<BOX64_PREFER_WRAPPED>=I<0|1>
+
+Box64 will use wrapped libs even if the lib is specified with absolute path
+
+    * 0 : Try to use emulated libs when they are defined with absolute path  (Default.)
+    * 1 : Use Wrapped native libs even if path is absolute
+
+=item B<BOX64_PREFER_EMULATED>=I<0|1>
+
+Box64 will prefer emulated libs first (execpt for glibc, alsa, pulse, GL,
+vulkan and X11
+
+   * 0 : Native libs are prefered (Default.)
+   * 1 : Emulated libs are prefered (Default for program running inside pressure-vessel)
+
+=item B<BOX64_CRASHHANDLER>=I<0|1>
+
+Box64 will use a dummy crashhandler.so library
+
+    * 0 : Use Emulated crashhandler.so library if needed
+    * 1 : Use an internal dummy (completly empty) crashhandler.so library (defaut)
+
+=item B<BOX64_MALLOC_HACK>=I<0|1|2>
+
+How Box64 will handle hooking of malloc operators
+
+    * 0 : Don't allow malloc operator to be redirected, rewriting code to use regular function (Default)
+    * 1 : Allow malloc operator to be redirected (not advised)
+    * 2 : Like 0, but track special mmap / free (some redirected functions were inlined and cannot be redirected)
+
+=item B<BOX64_NOPULSE>=I<0|1>
+
+Disables the load of pulseaudio libraries.
+
+    * 0 : Load pulseaudio libraries if found. (Default.)
+    * 1 : Disables the load of pulse audio libraries (libpulse and libpulse-simple), both the native library and the x86 library
+
+=item B<BOX64_NOGTK>=I<0|1>
+
+Disables the loading of wrapped GTK libraries.
+
+    * 0 : Load wrapped GTK libraries if found. (Default.)
+    * 1 : Disables loading wrapped GTK libraries.
+
+=item B<BOX64_NOVULKAN>=I<0|1>
+
+Disables the load of vulkan libraries.
+
+    * 0 : Load vulkan libraries if found.
+    * 1 : Disables the load of vulkan libraries, both the native and the i386 version (can be useful on Pi4, where the vulkan driver is not quite there yet.)
+
+=item B<BOX64_BASH>=I<yyyy>
+
+Define x86_64 bash to launch script. Will use yyyy as x86_64 bash to launch
+script. yyyy needs to be a full path to a valid x86_64 version of bash
+
+=item B<BOX64_JITGDB>=I<0|1|2>
+
+    * 0 : Just print the Segfault message on segfault (default)
+    * 1 : Launch `gdb` when a segfault, bus error or illegal instruction signal is trapped, attached to the offending process and go in an endless loop, waiting. When in gdb, you need to find the correct thread yourself (the one with `my_box64signalhandler` in is stack) then probably need to `finish` 1 or 2 functions (inside `usleep(..)`) and then you'll be in `my_box64signalhandler`, just before the printf of the Segfault message. Then simply  `set waiting=0` to exit the infinite loop.
+    * 2 : Launch `gdbserver` when a segfault, bus error or illegal instruction signal is trapped, attached to the offending process, and go in an endless loop, waiting. Use `gdb /PATH/TO/box64` and then `target remote 127.0.0.1:1234` to connect to the gdbserver (or use actual IP if not on the machine). After that, the procedure is the same as with ` BOX64_JITGDB=1`. This mode can be usefullwhen programs redirect all console output to a file (like Unity3D Games)
+
+=cut

pkgbuilds/PKGBUILD-arm64

@@ -0,0 +1,36 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-arm64-git
+pkgver=r2431.60c6858
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-arm64-git}-git" "${pkgname%-arm64-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-arm64-git}-git" "${pkgname%-arm64-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "${srcdir}/${pkgname%-arm64-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-arm64-git}"
+	[[ ! -d ./build ]] && mkdir build
+	cmake -B build -DARM_DYNAREC=ON -DCMAKE_BUILD_TYPE=RelWithDebInfo -DCMAKE_INSTALL_PREFIX=/usr
+}
+
+build() {
+	cd "${srcdir}/${pkgname%-arm64-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "${srcdir}/${pkgname%-arm64-git}/build"
+	make DESTDIR="${pkgdir}/" install
+}

pkgbuilds/PKGBUILD-asahi

@@ -0,0 +1,36 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-asahi-git
+pkgver=r2431.60c6858
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-asahi-git}-git" "${pkgname%-asahi-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-asahi-git}-git" "${pkgname%-asahi-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "${srcdir}/${pkgname%-asahi-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-asahi-git}"
+	[[ ! -d ./build ]] && mkdir build
+	cmake -B build -DM1=ON -DCMAKE_BUILD_TYPE=RelWithDebInfo -DCMAKE_INSTALL_PREFIX=/usr
+}
+
+build() {
+	cd "${srcdir}/${pkgname%-asahi-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "${srcdir}/${pkgname%-asahi-git}/build"
+	make DESTDIR="${pkgdir}/" install
+}

pkgbuilds/PKGBUILD-lx2160a

@@ -0,0 +1,36 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-lx2160a-git
+pkgver=r2431.60c6858
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-lx2160a-git}-git" "${pkgname%-lx2160a-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-lx2160a-git}-git" "${pkgname%-lx2160a-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "${srcdir}/${pkgname%-lx2160a-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-lx2160a-git}"
+	[[ ! -d ./build ]] && mkdir build
+	cmake -B build -DLX2160A=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo -DCMAKE_INSTALL_PREFIX=/usr
+}
+
+build() {
+	cd "${srcdir}/${pkgname%-lx2160a-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "${srcdir}/${pkgname%-lx2160a-git}/build"
+	make DESTDIR="${pkgdir}/" install
+}

pkgbuilds/PKGBUILD-odroid

@@ -0,0 +1,36 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-odroid-git
+pkgver=r2431.60c6858
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-odroid-git}-git" "${pkgname%-odroid-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-odroid-git}-git" "${pkgname%-odroid-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "${srcdir}/${pkgname%-odroid-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-odroid-git}"
+	[[ ! -d ./build ]] && mkdir build
+	cmake -B build -DODROIDN2=ON -DCMAKE_BUILD_TYPE=RelWithDebInfo -DCMAKE_INSTALL_PREFIX=/usr
+}
+
+build() {
+	cd "${srcdir}/${pkgname%-odroid-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "${srcdir}/${pkgname%-odroid-git}/build"
+	make DESTDIR="${pkgdir}/" install
+}

pkgbuilds/PKGBUILD-phytium

@@ -0,0 +1,36 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-phytium-git
+pkgver=r2431.60c6858
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-phytium-git}-git" "${pkgname%-phytium-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-phytium-git}-git" "${pkgname%-phytium-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "${srcdir}/${pkgname%-phytium-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-phytium-git}"
+	[[ ! -d ./build ]] && mkdir build
+	cmake -B build -DPHYTIUM=ON -DCMAKE_BUILD_TYPE=RelWithDebInfo -DCMAKE_INSTALL_PREFIX=/usr
+}
+
+build() {
+	cd "${srcdir}/${pkgname%-phytium-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "${srcdir}/${pkgname%-phytium-git}/build"
+	make DESTDIR="${pkgdir}/" install
+}

pkgbuilds/PKGBUILD-raspberrypi

@@ -0,0 +1,49 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-rpi-git
+pkgver=r2431.60c6858
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-rpi-git}-git" "${pkgname%-rpi-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-rpi-git}-git" "${pkgname%-rpi-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+_pimodel=`tr -d '\0' < /sys/firmware/devicetree/base/model`
+
+pkgver() {
+	cd "${srcdir}/${pkgname%-rpi-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-rpi-git}"
+	# Check for Pi version number
+	if [[ ${_pimodel} =~ "Raspberry Pi 4" ]]; then
+		_piversion=4
+	elif [[ ${_pimodel} =~ "Raspberry Pi 3" ]]; then
+		_piversion=3	
+	else
+		# This RPI is not supported or this device is not a pi.
+		# We should cancel then the build.
+		echo -e "\033[01m\033[01;31m==> ERROR:\033[00;01m Your device is not supported! This script is for RPi model 4/3 (2/1/0 isn't supported).\033[00m"
+		exit 1
+	fi
+	echo -e "\033[01m\033[01;34m==> INFO:\033[00;01m Your detected Pi verion number is: \033[01;31m${_piversion}\033[01m.\033[00m"
+	[[ ! -d ./build ]] && mkdir build
+	cmake -B build -DRPI${_piversion}ARM64=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo -DCMAKE_INSTALL_PREFIX=/usr
+}
+
+build() {
+	cd "${srcdir}/${pkgname%-rpi-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "${srcdir}/${pkgname%-rpi-git}/build"
+	make DESTDIR="${pkgdir}/" install
+}

pkgbuilds/PKGBUILD-rk3xxx

@@ -0,0 +1,51 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box86-rk3xxx-git
+pkgver=r2431.60c6858
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-rk3xxx-git}-git" "${pkgname%-rk3xxx-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-rk3xxx-git}-git" "${pkgname%-rk3xxx-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+_rkmodel=`tr -d '\0' < /proc/device-tree/compatible`
+
+pkgver() {
+	cd "${srcdir}/${pkgname%-rk3xxx-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-rk3xxx-git}"
+	# Check for RockChip version number
+	if [[ ${_rkmodel} =~ "rk3326" ]]; then
+		_rksuffix=3326
+	elif [[ ${_rkmodel} =~ "rk3399" ]]; then
+		_rksuffix=3399	
+	elif [[ ${_rkmodel} =~ "rk3588" ]]; then
+		_rksuffix=3588	
+	else
+		# This RKxxxx is not supported or this device is not RockChip based.
+		# We should cancel then the build.
+		echo -e "\033[01m\033[01;31m==> ERROR:\033[00;01m Your device is not supported! This script is for RockChip model 3326/3399/3588.\033[00m"
+		exit 1
+	fi
+	echo -e "\033[01m\033[01;34m==> INFO:\033[00;01m Your detected RockChip verion number is: \033[01;31m${_rksuffix}\033[01m.\033[00m"
+	[[ ! -d ./build ]] && mkdir build
+    cmake -B build -DRK${_rksuffix}=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo -DCMAKE_INSTALL_PREFIX=/usr
+}
+
+build() {
+	cd "${srcdir}/${pkgname%-rk3xxx-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "${srcdir}/${pkgname%-rk3xxx-git}/build"
+	make DESTDIR="${pkgdir}/" install
+}

pkgbuilds/PKGBUILD-rv64

@@ -0,0 +1,36 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-rv64-git
+pkgver=r2431.60c6858
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('riscv64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-rv64-git}-git" "${pkgname%-rv64-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-rv64-git}-git" "${pkgname%-rv64-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "${srcdir}/${pkgname%-rv64-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-rv64-git}"
+	[[ ! -d ./build ]] && mkdir build
+	cmake -B build -DRV64=ON -DCMAKE_BUILD_TYPE=RelWithDebInfo -DCMAKE_INSTALL_PREFIX=/usr
+}
+
+build() {
+	cd "${srcdir}/${pkgname%-rv64-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "${srcdir}/${pkgname%-rv64-git}/build"
+	make DESTDIR="${pkgdir}/" install
+}

pkgbuilds/PKGBUILD-sd845

@@ -0,0 +1,36 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-sd845-git
+pkgver=r2431.60c6858
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-sd845-git}-git" "${pkgname%-sd845-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-sd845-git}-git" "${pkgname%-sd845-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "${srcdir}/${pkgname%-sd845-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-sd845-git}"
+	[[ ! -d ./build ]] && mkdir build
+	cmake -B build -DSD845=ON -DCMAKE_BUILD_TYPE=RelWithDebInfo -DCMAKE_INSTALL_PREFIX=/usr
+}
+
+build() {
+	cd "${srcdir}/${pkgname%-sd845-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "${srcdir}/${pkgname%-sd845-git}/build"
+	make DESTDIR="${pkgdir}/" install
+}

pkgbuilds/PKGBUILD-tegra

@@ -0,0 +1,36 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-tegra-git
+pkgver=r2431.60c6858
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('aarch64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+optdepends=('gl4es: OpenGL 2 for GLES 2 devices')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-tegra-git}-git" "${pkgname%-tegra-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-tegra-git}-git" "${pkgname%-tegra-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "${srcdir}/${pkgname%-tegra-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-tegra-git}"
+	[[ ! -d ./build ]] && mkdir build
+	cmake -B build -DTEGRAX1=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo -DCMAKE_INSTALL_PREFIX=/usr
+}
+
+build() {
+	cd "${srcdir}/${pkgname%-tegra-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "${srcdir}/${pkgname%-tegra-git}/build"
+	make DESTDIR="${pkgdir}/" install
+}

pkgbuilds/PKGBUILD-x86_64

@@ -0,0 +1,35 @@
+# Maintainer: Jai-JAP <[email protected]>
+# Author: Sebastien Chevalier <[email protected]>
+pkgname=box64-x64-git
+pkgver=r2431.60c6858
+pkgrel=1
+pkgdesc="Linux Userspace x86_64 Emulator with a twist, targeted at ARM64 Linux devices."
+arch=('x86_64')
+url="https://github.com/ptitSeb/box64"
+license=('MIT')
+makedepends=('git' 'cmake' 'make')
+provides=("${pkgname%-git}" "${pkgname%-x64-git}-git" "${pkgname%-x64-git}")
+conflicts=("${pkgname%-git}" "${pkgname%-x64-git}-git" "${pkgname%-x64-git}")
+source=('git+https://github.com/ptitSeb/box64')
+md5sums=('SKIP')
+
+pkgver() {
+	cd "${srcdir}/${pkgname%-x64-git}"
+	printf "r%s.%s" "$(git rev-list --count HEAD)" "$(git rev-parse --short HEAD)"
+}
+
+prepare() {
+	cd "${srcdir}/${pkgname%-x64-git}"
+	[[ ! -d ./build ]] && mkdir build
+	cmake -B build -DLD80BITS=1 -DNOALIGN=1 -DCMAKE_BUILD_TYPE=RelWithDebInfo -DCMAKE_INSTALL_PREFIX=/usr
+}
+
+build() {
+	cd "${srcdir}/${pkgname%-x64-git}/build"
+	make -j$(nproc)
+}
+
+package() {
+	cd "${srcdir}/${pkgname%-x64-git}/build"
+	make DESTDIR="${pkgdir}/" install
+}

pkgbuilds/README.md

@@ -0,0 +1,26 @@
+# The directory containing all PKGBUILDs for BOX64
+## FAQ
+### 1. How to use it?
+Just download the `PKGBUILD-<your-platform>` (no need to download the whole repository), go to directory where you downloaded and type:
+```sh
+mv ./PKGBUILD-<your-platform> ./PKGBUILD
+# use the below line if you need a DEBUG build
+# sed -i 's/RelWithDebInfo/Debug/g' ./PKGBUILD
+cd ..
+makepkg -si
+```
+This will copy the PKGBUILD for your platform (where you type your platform name instead of `<your-platform>`), build it and install the PKGBUILD on 64-bit Archlinux ARM.
+
+In the future, I might try to do an unified PKGBUILD for all platforms that will recognize your platform automatically.
+
+### 2. What platforms are currently supported.
+All specified in [COMPILE.md](../docs/COMPILE.md) except for LARCH64, PPC64LE and SW64.
+
+### 3. Any advantages with this solution?
+This might give you some advantages like:
+- automatic updates (with some AUR frontends like [`pamac-aur`](https://aur.archlinux.org/packages/pamac-aur/) or [`yay`](https://aur.archlinux.org/packages/yay));
+- easily uninstall with `pacman -R` when no needed (no need other scripts nor Makefile to do this);
+- your `box64` installation is recognized as a package (where it wasn't when installing with `make install`).
+
+
+### Note: You can use [makedeb](https://github.com/makedeb/makedeb) (or) [pkgbuild2spec](https://github.com/prozum/pkgbuild2spec) to compile box64 to .deb or .rpm installer files.

postinst

@@ -0,0 +1,2 @@
+#!/bin/sh
+systemctl restart systemd-binfmt

runTest.cmake

@@ -32,6 +32,9 @@ execute_process(
 
 # if the return value is !=0 bail out
 if( TEST_RESULT )
+  get_filename_component(TESTNAME "${TEST_ARGS}" NAME)
+  file(RENAME "${TEST_OUTPUT}" "${CMAKE_BINARY_DIR}/${TESTNAME}.out")
+  file(WRITE  "${CMAKE_BINARY_DIR}/${TESTNAME}.err" ${TEST_ERROR})
   message( FATAL_ERROR "Failed: Test program ${TEST_PROGRAM} exited != 0.\n${TEST_ERROR}" )
 endif( TEST_RESULT )
 
@@ -43,8 +46,16 @@ execute_process(
 
 # again, if return value is !=0 scream and shout
 if( TEST_RESULT )
+  get_filename_component(TESTNAME "${TEST_ARGS}" NAME)
+  file(RENAME "${TEST_OUTPUT}" "${CMAKE_BINARY_DIR}/${TESTNAME}.out")
+  file(WRITE  "${CMAKE_BINARY_DIR}/${TESTNAME}.err" ${TEST_ERROR})
   message( FATAL_ERROR "Failed: The output of ${TEST_PROGRAM} did not match ${TEST_REFERENCE}")
 endif( TEST_RESULT )
 
+# remove the temporary files if they exist
+if( EXISTS ${TEST_OUTPUT} )
+  file(REMOVE "${TEST_OUTPUT}")
+endif()
+
 # everything went fine...
 message( "Passed: The output of ${TEST_PROGRAM} matches ${TEST_REFERENCE}" )

src/box64context.c

@@ -5,6 +5,7 @@
 #include <dlfcn.h>
 #include <signal.h>
 #include <sys/mman.h>
+#include <pthread.h>
 
 #include "box64context.h"
 #include "debug.h"
@@ -18,6 +19,8 @@
 #include "wrapper.h"
 #include "x64emu.h"
 #include "signals.h"
+#include "rcfile.h"
+#include "gltools.h"
 
 EXPORTDYN
 void initAllHelpers(box64context_t* context)
@@ -38,6 +41,7 @@ void finiAllHelpers(box64context_t* context)
     static int finied = 0;
     if(finied)
         return;
+    DeleteParams();
     fini_pthread_helper(context);
     fini_signal_helper();
     fini_bridge_helper();
@@ -62,8 +66,8 @@ void free_tlsdatasize(void* p)
     if(!p)
         return;
     tlsdatasize_t *data = (tlsdatasize_t*)p;
-    free(data->tlsdata);
-    free(p);
+    box_free(data->ptr);
+    box_free(p);
 }
 
 void x64Syscall(x64emu_t *emu);
@@ -72,15 +76,21 @@ int unlockMutex()
 {
     int ret = unlockCustommemMutex();
     int i;
+    #ifdef USE_CUSTOM_MUTEX
+    uint32_t tid = (uint32_t)GetTID();
     #define GO(A, B)                    \
-        i = checkMutex(&A);             \
+        i = (native_lock_storeifref2_d(&A, 0, tid)==tid); \
         if(i) {                         \
-            pthread_mutex_unlock(&A);   \
             ret|=(1<<B);                \
         }
+    #else
+        #define GO(A, B)                \
+        i = checkUnlockMutex(&A);       \
+        if(i) {                         \
+            ret|=(1<<B);                \
+        }
+    #endif
 
-    GO(my_context->mutex_once, 5)
-    GO(my_context->mutex_once2, 6)
     GO(my_context->mutex_trace, 7)
     #ifdef DYNAREC
     GO(my_context->mutex_dyndump, 8)
@@ -89,6 +99,7 @@ int unlockMutex()
     #endif
     GO(my_context->mutex_tls, 9)
     GO(my_context->mutex_thread, 10)
+    GO(my_context->mutex_bridge, 11)
     #undef GO
 
     return ret;
@@ -99,10 +110,8 @@ void relockMutex(int locks)
     relockCustommemMutex(locks);
     #define GO(A, B)                    \
         if(locks&(1<<B))                \
-            pthread_mutex_lock(&A);     \
+            mutex_trylock(&A);          \
 
-    GO(my_context->mutex_once, 5)
-    GO(my_context->mutex_once2, 6)
     GO(my_context->mutex_trace, 7)
     #ifdef DYNAREC
     GO(my_context->mutex_dyndump, 8)
@@ -111,26 +120,43 @@ void relockMutex(int locks)
     #endif
     GO(my_context->mutex_tls, 9)
     GO(my_context->mutex_thread, 10)
+    GO(my_context->mutex_bridge, 11)
     #undef GO
 }
 
 static void init_mutexes(box64context_t* context)
 {
+#ifndef DYNAREC
     pthread_mutexattr_t attr;
     pthread_mutexattr_init(&attr);
     pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_ERRORCHECK);
-    pthread_mutex_init(&context->mutex_once, &attr);
-    pthread_mutex_init(&context->mutex_once2, &attr);
-    pthread_mutex_init(&context->mutex_trace, &attr);
-#ifndef DYNAREC
     pthread_mutex_init(&context->mutex_lock, &attr);
-#else
-    pthread_mutex_init(&context->mutex_dyndump, &attr);
-#endif
+    pthread_mutex_init(&context->mutex_trace, &attr);
     pthread_mutex_init(&context->mutex_tls, &attr);
     pthread_mutex_init(&context->mutex_thread, &attr);
+    pthread_mutex_init(&context->mutex_bridge, &attr);
 
     pthread_mutexattr_destroy(&attr);
+#else
+    #ifdef USE_CUSTOM_MUTEX
+    native_lock_store(&context->mutex_trace, 0);
+    native_lock_store(&context->mutex_tls, 0);
+    native_lock_store(&context->mutex_thread, 0);
+    native_lock_store(&context->mutex_bridge, 0);
+    native_lock_store(&context->mutex_dyndump, 0);
+    #else
+    pthread_mutexattr_t attr;
+    pthread_mutexattr_init(&attr);
+    pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_ERRORCHECK);
+    pthread_mutex_init(&context->mutex_trace, &attr);
+    pthread_mutex_init(&context->mutex_tls, &attr);
+    pthread_mutex_init(&context->mutex_thread, &attr);
+    pthread_mutex_init(&context->mutex_bridge, &attr);
+    pthread_mutex_init(&context->mutex_dyndump, &attr);
+    pthread_mutexattr_destroy(&attr);
+    #endif
+    pthread_mutex_init(&context->mutex_lock, NULL);
+#endif
 }
 
 static void atfork_child_box64context(void)
@@ -139,6 +165,31 @@ static void atfork_child_box64context(void)
     init_mutexes(my_context);
 }
 
+void freeCycleLog(box64context_t* ctx)
+{
+    if(cycle_log) {
+        for(int i=0; i<cycle_log; ++i) {
+            box_free(ctx->log_call[i]);
+            box_free(ctx->log_ret[i]);
+        }
+        box_free(ctx->log_call);
+        box_free(ctx->log_ret);
+        ctx->log_call = NULL;
+        ctx->log_ret = NULL;
+    }
+}
+void initCycleLog(box64context_t* context)
+{
+    if(cycle_log) {
+        context->log_call = (char**)box_calloc(cycle_log, sizeof(char*));
+        context->log_ret = (char**)box_calloc(cycle_log, sizeof(char*));
+        for(int i=0; i<cycle_log; ++i) {
+            context->log_call[i] = (char*)box_calloc(256, 1);
+            context->log_ret[i] = (char*)box_calloc(128, 1);
+        }
+    }
+}
+
 EXPORTDYN
 box64context_t *NewBox64Context(int argc)
 {
@@ -149,23 +200,38 @@ box64context_t *NewBox64Context(int argc)
     }
 #endif
     // init and put default values
-    box64context_t *context = my_context = (box64context_t*)calloc(1, sizeof(box64context_t));
+    box64context_t *context = my_context = (box64context_t*)box_calloc(1, sizeof(box64context_t));
 
-    context->deferedInit = 1;
+    initCycleLog(context);
+
+    context->deferredInit = 1;
     context->sel_serial = 1;
 
     init_custommem_helper(context);
 
     context->maplib = NewLibrarian(context, 1);
     context->local_maplib = NewLibrarian(context, 1);
+    context->versym = NewDictionnary();
     context->system = NewBridge();
+    // Cannot use Bridge name as the map is not initialized yet
     // create vsyscall
-    context->vsyscall = AddBridge(context->system, vFv, x64Syscall, 0, NULL);
+    context->vsyscall = AddBridge(context->system, vFEv, x64Syscall, 0, NULL);
+    // create the vsyscalls
+    context->vsyscalls[0] = AddVSyscall(context->system, 96);
+    context->vsyscalls[1] = AddVSyscall(context->system, 201);
+    context->vsyscalls[2] = AddVSyscall(context->system, 309);
+    // create the alternate to map at address
+    addAlternate((void*)0xffffffffff600000, (void*)context->vsyscalls[0]);
+    addAlternate((void*)0xffffffffff600400, (void*)context->vsyscalls[1]);
+    addAlternate((void*)0xffffffffff600800, (void*)context->vsyscalls[2]);
+    // create exit bridge
+    context->exit_bridge = AddBridge(context->system, NULL, NULL, 0, NULL);
+    // get handle to box64 itself
     context->box64lib = dlopen(NULL, RTLD_NOW|RTLD_GLOBAL);
     context->dlprivate = NewDLPrivate();
 
     context->argc = argc;
-    context->argv = (char**)calloc(context->argc+1, sizeof(char*));
+    context->argv = (char**)box_calloc(context->argc+1, sizeof(char*));
 
     init_mutexes(context);
     pthread_atfork(NULL, NULL, atfork_child_box64context);
@@ -175,13 +241,32 @@ box64context_t *NewBox64Context(int argc)
 
     for (int i=0; i<8; ++i) context->canary[i] = 1 +  getrand(255);
     context->canary[getrand(4)] = 0;
-    printf_log(LOG_DEBUG, "Setting up canary (for Stack protector) at FS:0x14, value:%08X\n", *(uint32_t*)context->canary);
+    printf_log(LOG_DEBUG, "Setting up canary (for Stack protector) at FS:0x28, value:%08X\n", *(uint32_t*)context->canary);
+
+    // init segments
+    for(int i=0; i<16; i++) {
+        context->segtls[i].limit = (uintptr_t)-1LL;
+    }
+    context->segtls[10].key_init = 0;    // 0x53 selector
+    context->segtls[10].present = 1;
+    context->segtls[8].key_init = 0;    // 0x43 selector
+    context->segtls[8].present = 1;
+    context->segtls[6].key_init = 0;    // 0x33 selector
+    context->segtls[6].present = 1;
+    context->segtls[5].key_init = 0;    // 0x2b selector
+    context->segtls[5].present = 1;
+    context->segtls[4].key_init = 0;    // 0x23 selector
+    context->segtls[4].present = 1;
+    context->segtls[4].is32bits = 1;
+
+    context->globdata = NewMapSymbols();
 
     initAllHelpers(context);
 
     return context;
 }
 
+void freeALProcWrapper(box64context_t* context);
 EXPORTDYN
 void FreeBox64Context(box64context_t** context)
 {
@@ -197,11 +282,12 @@ void FreeBox64Context(box64context_t** context)
         FreeLibrarian(&ctx->local_maplib, NULL);
     if(ctx->maplib)
         FreeLibrarian(&ctx->maplib, NULL);
+    FreeDictionnary(&ctx->versym);
 
     for(int i=0; i<ctx->elfsize; ++i) {
         FreeElfHeader(&ctx->elfs[i]);
     }
-    free(ctx->elfs);
+    box_free(ctx->elfs);
 
     FreeCollection(&ctx->box64_path);
     FreeCollection(&ctx->box64_ld_lib);
@@ -209,20 +295,22 @@ void FreeBox64Context(box64context_t** context)
     // stop trace now
     if(ctx->dec)
         DeleteX64TraceDecoder(&ctx->dec);
+    if(ctx->dec32)
+        DeleteX86TraceDecoder(&ctx->dec32);
     if(ctx->zydis)
         DeleteX64Trace(ctx);
 
-    if(ctx->deferedInitList)
-        free(ctx->deferedInitList);
+    if(ctx->deferredInitList)
+        box_free(ctx->deferredInitList);
 
-    free(ctx->argv);
+    /*box_free(ctx->argv);*/
     
-    for (int i=0; i<ctx->envc; ++i)
-        free(ctx->envv[i]);
-    free(ctx->envv);
+    /*for (int i=0; i<ctx->envc; ++i)
+        box_free(ctx->envv[i]);
+    box_free(ctx->envv);*/
 
     if(ctx->atfork_sz) {
-        free(ctx->atforks);
+        box_free(ctx->atforks);
         ctx->atforks = NULL;
         ctx->atfork_sz = ctx->atfork_cap = 0;
     }
@@ -238,14 +326,18 @@ void FreeBox64Context(box64context_t** context)
 
     FreeDLPrivate(&ctx->dlprivate);
 
-    free(ctx->fullpath);
-    free(ctx->box64path);
+    box_free(ctx->fullpath);
+    box_free(ctx->box64path);
+    box_free(ctx->bashpath);
 
     FreeBridge(&ctx->system);
 
     freeGLProcWrapper(ctx);
     freeALProcWrapper(ctx);
 
+    if(ctx->stack_clone)
+        box_free(ctx->stack_clone);
+
 
     void* ptr;
     if ((ptr = pthread_getspecific(ctx->tlskey)) != NULL) {
@@ -255,46 +347,74 @@ void FreeBox64Context(box64context_t** context)
     pthread_key_delete(ctx->tlskey);
 
     if(ctx->tlsdata)
-        free(ctx->tlsdata);
+        box_free(ctx->tlsdata);
 
-    pthread_mutex_destroy(&ctx->mutex_once);
-    pthread_mutex_destroy(&ctx->mutex_once2);
-    pthread_mutex_destroy(&ctx->mutex_trace);
-#ifndef DYNAREC
-    pthread_mutex_destroy(&ctx->mutex_lock);
-#else
-    pthread_mutex_destroy(&ctx->mutex_dyndump);
-#endif
-    pthread_mutex_destroy(&ctx->mutex_tls);
-    pthread_mutex_destroy(&ctx->mutex_thread);
-
-    free_neededlib(&ctx->neededlibs);
+    free_neededlib(ctx->neededlibs);
+    ctx->neededlibs = NULL;
 
     if(ctx->emu_sig)
         FreeX64Emu(&ctx->emu_sig);
 
+    FreeMapSymbols(&ctx->globdata);
+
     finiAllHelpers(ctx);
 
-    free(ctx);
+#ifdef DYNAREC
+    pthread_mutex_destroy(&ctx->mutex_lock);
+#else
+    pthread_mutex_destroy(&ctx->mutex_trace);
+    pthread_mutex_destroy(&ctx->mutex_lock);
+    pthread_mutex_destroy(&ctx->mutex_tls);
+    pthread_mutex_destroy(&ctx->mutex_thread);
+    pthread_mutex_destroy(&ctx->mutex_bridge);
+#endif
+
+    freeCycleLog(ctx);
+
+    box_free(ctx);
 }
 
 int AddElfHeader(box64context_t* ctx, elfheader_t* head) {
-    int idx = ctx->elfsize;
-    if(idx==ctx->elfcap) {
-        // resize...
-        ctx->elfcap += 16;
-        ctx->elfs = (elfheader_t**)realloc(ctx->elfs, sizeof(elfheader_t*) * ctx->elfcap);
+    int idx = 0;
+    while(idx<ctx->elfsize && ctx->elfs[idx]) idx++;
+    if(idx == ctx->elfsize) {
+        if(idx==ctx->elfcap) {
+            // resize...
+            ctx->elfcap += 16;
+            ctx->elfs = (elfheader_t**)box_realloc(ctx->elfs, sizeof(elfheader_t*) * ctx->elfcap);
+        }
+        ctx->elfs[idx] = head;
+        ctx->elfsize++;
+    } else {
+        ctx->elfs[idx] = head;
     }
-    ctx->elfs[idx] = head;
-    ctx->elfsize++;
     printf_log(LOG_DEBUG, "Adding \"%s\" as #%d in elf collection\n", ElfName(head), idx);
     return idx;
 }
 
+void RemoveElfHeader(box64context_t* ctx, elfheader_t* head) {
+    if(GetTLSBase(head)) {
+        // should remove the tls info
+        int tlsbase = GetTLSBase(head);
+        /*if(tlsbase == -ctx->tlssize) {
+            // not really correct, but will do for now
+            ctx->tlssize -= GetTLSSize(head);
+            if(!(++ctx->sel_serial))
+                ++ctx->sel_serial;
+        }*/
+    }
+    for(int i=0; i<ctx->elfsize; ++i)
+        if(ctx->elfs[i] == head) {
+            ctx->elfs[i] = NULL;
+            return;
+        }
+}
+
 int AddTLSPartition(box64context_t* context, int tlssize) {
     int oldsize = context->tlssize;
+    // should in fact first try to map a hole, but rewinding all elfs and checking filled space, like with the mapmem utilities
     context->tlssize += tlssize;
-    context->tlsdata = realloc(context->tlsdata, context->tlssize);
+    context->tlsdata = box_realloc(context->tlsdata, context->tlssize);
     memmove(context->tlsdata+tlssize, context->tlsdata, oldsize);   // move to the top, using memmove as regions will probably overlap
     memset(context->tlsdata, 0, tlssize);           // fill new space with 0 (not mandatory)
     // clean GS segment for current emu
@@ -307,46 +427,3 @@ int AddTLSPartition(box64context_t* context, int tlssize) {
     return -context->tlssize;   // negative offset
 }
 
-void add_neededlib(needed_libs_t* needed, library_t* lib)
-{
-    if(!needed)
-        return;
-    if(needed->size == needed->cap) {
-        needed->cap += 8;
-        needed->libs = (library_t**)realloc(needed->libs, needed->cap*sizeof(library_t*));
-    }
-    needed->libs[needed->size++] = lib;
-}
-
-void free_neededlib(needed_libs_t* needed)
-{
-    if(!needed)
-        return;
-    needed->cap = 0;
-    needed->size = 0;
-    if(needed->libs)
-        free(needed->libs);
-    needed->libs = NULL;
-}
-
-void add_dependedlib(needed_libs_t* depended, library_t* lib)
-{
-    if(!depended)
-        return;
-    if(depended->size == depended->cap) {
-        depended->cap += 8;
-        depended->libs = (library_t**)realloc(depended->libs, depended->cap*sizeof(library_t*));
-    }
-    depended->libs[depended->size++] = lib;
-}
-
-void free_dependedlib(needed_libs_t* depended)
-{
-    if(!depended)
-        return;
-    depended->cap = 0;
-    depended->size = 0;
-    if(depended->libs)
-        free(depended->libs);
-    depended->libs = NULL;
-}

src/box64version.h

@@ -2,7 +2,7 @@
 #define __BOX64_VERSION_H_
 
 #define BOX64_MAJOR 0
-#define BOX64_MINOR 0
-#define BOX64_REVISION 8
+#define BOX64_MINOR 2
+#define BOX64_REVISION 4
 
 #endif //__BOX64_VERSION_H_

src/build_info.h

@@ -1,6 +1,6 @@
 #ifndef __BUILD_INFO_H__
 #define __BUILD_INFO_H__
 
-void PrintBox64Version();
+void PrintBox64Version(void);
 
 #endif //__BUILD_INFO_H__

src/dynarec/arm64/arm64_emitter.h

@@ -24,6 +24,7 @@
 #define xR15    25
 #define xFlags  26
 #define xRIP    27
+#define xSavedSP 28
 // 32bits version
 #define wEAX    xRAX
 #define wECX    xRCX
@@ -110,8 +111,9 @@
 #define MOVKw(Rd, imm16)                    EMIT(MOVK_gen(0, 0, ((uint16_t)imm16)&0xffff, Rd))
 #define MOVKw_LSL(Rd, imm16, shift)         EMIT(MOVK_gen(0, (shift)/16, ((uint16_t)imm16)&0xffff, Rd))
 
+// This macro will give a -Wsign-compare warning, probably bug #38341
 #define MOV32w(Rd, imm32) \
-    if(~((uint32_t)(imm32))<0xffff) {                                       \
+    if(~((uint32_t)(imm32))<0xffffu) {                                      \
         MOVNw(Rd, (~(uint32_t)(imm32))&0xffff);                             \
     } else {                                                                \
         MOVZw(Rd, (imm32)&0xffff);                                          \
@@ -128,6 +130,7 @@
     }
 
 #define MOV64xw(Rd, imm64)   if(rex.w) {MOV64x(Rd, imm64);} else {MOV32w(Rd, imm64);}
+#define MOV64z(Rd, imm64)    if(rex.is32bits) {MOV32w(Rd, imm64);} else {MOV64x(Rd, imm64);}
 
 
 // ADD / SUB
@@ -139,6 +142,7 @@
 #define ADDSw_REG(Rd, Rn, Rm)               EMIT(ADDSUB_REG_gen(0, 0, 1, 0b00, Rm, 0, Rn, Rd))
 #define ADDw_REG_LSL(Rd, Rn, Rm, lsl)       EMIT(ADDSUB_REG_gen(0, 0, 0, 0b00, Rm, lsl, Rn, Rd))
 #define ADDxw_REG(Rd, Rn, Rm)               EMIT(ADDSUB_REG_gen(rex.w, 0, 0, 0b00, Rm, 0, Rn, Rd))
+#define ADDz_REG(Rd, Rn, Rm)                EMIT(ADDSUB_REG_gen(rex.is32bits?0:1, 0, 0, 0b00, Rm, 0, Rn, Rd))
 #define ADDSxw_REG(Rd, Rn, Rm)              EMIT(ADDSUB_REG_gen(rex.w, 0, 1, 0b00, Rm, 0, Rn, Rd))
 #define ADDxw_REG_LSR(Rd, Rn, Rm, lsr)      EMIT(ADDSUB_REG_gen(rex.w, 0, 0, 0b01, Rm, lsr, Rn, Rd))
 
@@ -149,6 +153,7 @@
 #define ADDSw_U12(Rd, Rn, imm12)    EMIT(ADDSUB_IMM_gen(0, 0, 1, 0b00, (imm12)&0xfff, Rn, Rd))
 #define ADDxw_U12(Rd, Rn, imm12)    EMIT(ADDSUB_IMM_gen(rex.w, 0, 0, 0b00, (imm12)&0xfff, Rn, Rd))
 #define ADDSxw_U12(Rd, Rn, imm12)   EMIT(ADDSUB_IMM_gen(rex.w, 0, 1, 0b00, (imm12)&0xfff, Rn, Rd))
+#define ADDz_U12(Rd, Rn, imm12)     EMIT(ADDSUB_IMM_gen(rex.is32bits?0:1, 0, 0, 0b00, (imm12)&0xfff, Rn, Rd))
 
 #define SUBx_REG(Rd, Rn, Rm)                EMIT(ADDSUB_REG_gen(1, 1, 0, 0b00, Rm, 0, Rn, Rd))
 #define SUBSx_REG(Rd, Rn, Rm)               EMIT(ADDSUB_REG_gen(1, 1, 1, 0b00, Rm, 0, Rn, Rd))
@@ -158,6 +163,7 @@
 #define SUBSw_REG(Rd, Rn, Rm)               EMIT(ADDSUB_REG_gen(0, 1, 1, 0b00, Rm, 0, Rn, Rd))
 #define SUBSw_REG_LSL(Rd, Rn, Rm, lsl)      EMIT(ADDSUB_REG_gen(0, 1, 1, 0b00, Rm, lsl, Rn, Rd))
 #define SUBxw_REG(Rd, Rn, Rm)               EMIT(ADDSUB_REG_gen(rex.w, 1, 0, 0b00, Rm, 0, Rn, Rd))
+#define SUBz_REG(Rd, Rn, Rm)                EMIT(ADDSUB_REG_gen(rex.is32bits?0:1, 1, 0, 0b00, Rm, 0, Rn, Rd))
 #define SUBSxw_REG(Rd, Rn, Rm)              EMIT(ADDSUB_REG_gen(rex.w, 1, 1, 0b00, Rm, 0, Rn, Rd))
 #define CMPSx_REG(Rn, Rm)                   SUBSx_REG(xZR, Rn, Rm)
 #define CMPSw_REG(Rn, Rm)                   SUBSw_REG(wZR, Rn, Rm)
@@ -174,6 +180,7 @@
 #define SUBw_U12(Rd, Rn, imm12)     EMIT(ADDSUB_IMM_gen(0, 1, 0, 0b00, (imm12)&0xfff, Rn, Rd))
 #define SUBSw_U12(Rd, Rn, imm12)    EMIT(ADDSUB_IMM_gen(0, 1, 1, 0b00, (imm12)&0xfff, Rn, Rd))
 #define SUBxw_U12(Rd, Rn, imm12)    EMIT(ADDSUB_IMM_gen(rex.w, 1, 0, 0b00, (imm12)&0xfff, Rn, Rd))
+#define SUBz_U12(Rd, Rn, imm12)     EMIT(ADDSUB_IMM_gen(rex.is32bits?0:1, 1, 0, 0b00, (imm12)&0xfff, Rn, Rd))
 #define SUBSxw_U12(Rd, Rn, imm12)   EMIT(ADDSUB_IMM_gen(rex.w, 1, 1, 0b00, (imm12)&0xfff, Rn, Rd))
 #define CMPSx_U12(Rn, imm12)        SUBSx_U12(xZR, Rn, imm12)
 #define CMPSw_U12(Rn, imm12)        SUBSw_U12(wZR, Rn, imm12)
@@ -193,6 +200,10 @@
 #define SBCSw_REG(Rd, Rn, Rm)       EMIT(ADDSUBC_gen(0, 1, 1, Rm, Rn, Rd))
 #define SBCSxw_REG(Rd, Rn, Rm)      EMIT(ADDSUBC_gen(rex.w, 1, 1, Rm, Rn, Rd))
 
+// ADR
+#define ADR_gen(immlo, immhi, Rd)   ((immlo)<<29 | 0b10000<<24 | (immhi)<<5 | (Rd))
+#define ADR_S20(Rd, imm)            EMIT(ADR_gen((imm)&3, ((imm)>>2)&0x7ffff, (Rd)))
+
 // LDR
 #define LDR_gen(size, op1, imm9, op2, Rn, Rt)    ((size)<<30 | 0b111<<27 | (op1)<<24 | 0b01<<22 | (imm9)<<12 | (op2)<<10 | (Rn)<<5 | (Rt))
 #define LDRx_S9_postindex(Rt, Rn, imm9)   EMIT(LDR_gen(0b11, 0b00, (imm9)&0x1ff, 0b01, Rn, Rt))
@@ -210,14 +221,15 @@
 #define LDRSW_S9_preindex(Rt, Rn, imm9)   EMIT(LDRS_gen(0b10, 0b00, (imm9)&0x1ff, 0b11, Rn, Rt))
 
 #define LD_gen(size, op1, imm12, Rn, Rt)        ((size)<<30 | 0b111<<27 | (op1)<<24 | 0b01<<22 | (imm12)<<10 | (Rn)<<5 | (Rt))
-#define LDRx_U12(Rt, Rn, imm12)           EMIT(LD_gen(0b11, 0b01, ((uint32_t)(imm12>>3))&0xfff, Rn, Rt))
-#define LDRw_U12(Rt, Rn, imm12)           EMIT(LD_gen(0b10, 0b01, ((uint32_t)(imm12>>2))&0xfff, Rn, Rt))
-#define LDRB_U12(Rt, Rn, imm12)           EMIT(LD_gen(0b00, 0b01, ((uint32_t)(imm12))&0xfff, Rn, Rt))
-#define LDRH_U12(Rt, Rn, imm12)           EMIT(LD_gen(0b01, 0b01, ((uint32_t)(imm12>>1))&0xfff, Rn, Rt))
-#define LDRxw_U12(Rt, Rn, imm12)          EMIT(LD_gen((rex.w)?0b11:0b10, 0b01, ((uint32_t)(imm12>>(2+rex.w)))&0xfff, Rn, Rt))
+#define LDRx_U12(Rt, Rn, imm12)           EMIT(LD_gen(0b11, 0b01, ((uint32_t)((imm12)>>3))&0xfff, Rn, Rt))
+#define LDRw_U12(Rt, Rn, imm12)           EMIT(LD_gen(0b10, 0b01, ((uint32_t)((imm12)>>2))&0xfff, Rn, Rt))
+#define LDRB_U12(Rt, Rn, imm12)           EMIT(LD_gen(0b00, 0b01, ((uint32_t)((imm12)))&0xfff, Rn, Rt))
+#define LDRH_U12(Rt, Rn, imm12)           EMIT(LD_gen(0b01, 0b01, ((uint32_t)((imm12)>>1))&0xfff, Rn, Rt))
+#define LDRxw_U12(Rt, Rn, imm12)          EMIT(LD_gen((rex.w)?0b11:0b10, 0b01, ((uint32_t)((imm12)>>(2+rex.w)))&0xfff, Rn, Rt))
+#define LDRz_U12(Rt, Rn, imm12)           EMIT(LD_gen((rex.is32bits)?0b10:0b11, 0b01, ((uint32_t)((imm12)>>(rex.is32bits?2:3)))&0xfff, Rn, Rt))
 
 #define LDS_gen(size, op1, imm12, Rn, Rt)       ((size)<<30 | 0b111<<27 | (op1)<<24 | 0b10<<22 | (imm12)<<10 | (Rn)<<5 | (Rt))
-#define LDRSW_U12(Rt, Rn, imm12)          EMIT(LDS_gen(0b10, 0b01, ((uint32_t)(imm12>>2))&0xfff, Rn, Rt))
+#define LDRSW_U12(Rt, Rn, imm12)          EMIT(LDS_gen(0b10, 0b01, ((uint32_t)((imm12)>>2))&0xfff, Rn, Rt))
 
 #define LDR_REG_gen(size, Rm, option, S, Rn, Rt)    ((size)<<30 | 0b111<<27 | 0b01<<22 | 1<<21 | (Rm)<<16 | (option)<<13 | (S)<<12 | (0b10)<<10 | (Rn)<<5 | (Rt))
 #define LDRx_REG(Rt, Rn, Rm)            EMIT(LDR_REG_gen(0b11, Rm, 0b011, 0, Rn, Rt))
@@ -226,20 +238,59 @@
 #define LDRw_REG(Rt, Rn, Rm)            EMIT(LDR_REG_gen(0b10, Rm, 0b011, 0, Rn, Rt))
 #define LDRw_REG_LSL2(Rt, Rn, Rm)       EMIT(LDR_REG_gen(0b10, Rm, 0b011, 1, Rn, Rt))
 #define LDRxw_REG(Rt, Rn, Rm)           EMIT(LDR_REG_gen(0b10+rex.w, Rm, 0b011, 0, Rn, Rt))
+#define LDRz_REG(Rt, Rn, Rm)            EMIT(LDR_REG_gen(rex.is32bits?0b10:0b11, Rm, 0b011, 0, Rn, Rt))
 #define LDRB_REG(Rt, Rn, Rm)            EMIT(LDR_REG_gen(0b00, Rm, 0b011, 0, Rn, Rt))
 #define LDRH_REG(Rt, Rn, Rm)            EMIT(LDR_REG_gen(0b01, Rm, 0b011, 0, Rn, Rt))
 
-#define LDRSH_gen(size, op1, opc, imm12, Rn, Rt)    ((size)<<30 | 0b111<<27 | (op1)<<24 | (opc)<<22 | (imm12)<<10 | (Rn)<<5 | (Rt))
-#define LDRSHx_U12(Rt, Rn, imm12)           EMIT(LDRSH_gen(0b01, 0b01, 0b10, ((uint32_t)(imm12>>1))&0xfff, Rn, Rt))
-#define LDRSHw_U12(Rt, Rn, imm12)           EMIT(LDRSH_gen(0b01, 0b01, 0b11, ((uint32_t)(imm12>>1))&0xfff, Rn, Rt))
-#define LDRSHxw_U12(Rt, Rn, imm12)          EMIT(LDRSH_gen(0b01, 0b01, rex.w?0b10:0b11, ((uint32_t)(imm12>>1))&0xfff, Rn, Rt))
-#define LDRSBx_U12(Rt, Rn, imm12)           EMIT(LDRSH_gen(0b00, 0b01, 0b10, ((uint32_t)(imm12>>0))&0xfff, Rn, Rt))
-#define LDRSBw_U12(Rt, Rn, imm12)           EMIT(LDRSH_gen(0b00, 0b01, 0b11, ((uint32_t)(imm12>>0))&0xfff, Rn, Rt))
-#define LDRSBxw_U12(Rt, Rn, imm12)          EMIT(LDRSH_gen(0b00, 0b01, rex.w?0b10:0b11, ((uint32_t)(imm12>>0))&0xfff, Rn, Rt))
+#define LDRS_U12_gen(size, op1, opc, imm12, Rn, Rt)    ((size)<<30 | 0b111<<27 | (op1)<<24 | (opc)<<22 | (imm12)<<10 | (Rn)<<5 | (Rt))
+#define LDRSHx_U12(Rt, Rn, imm12)           EMIT(LDRS_U12_gen(0b01, 0b01, 0b10, ((uint32_t)(imm12>>1))&0xfff, Rn, Rt))
+#define LDRSHw_U12(Rt, Rn, imm12)           EMIT(LDRS_U12_gen(0b01, 0b01, 0b11, ((uint32_t)(imm12>>1))&0xfff, Rn, Rt))
+#define LDRSHxw_U12(Rt, Rn, imm12)          EMIT(LDRS_U12_gen(0b01, 0b01, rex.w?0b10:0b11, ((uint32_t)(imm12>>1))&0xfff, Rn, Rt))
+#define LDRSBx_U12(Rt, Rn, imm12)           EMIT(LDRS_U12_gen(0b00, 0b01, 0b10, ((uint32_t)(imm12>>0))&0xfff, Rn, Rt))
+#define LDRSBw_U12(Rt, Rn, imm12)           EMIT(LDRS_U12_gen(0b00, 0b01, 0b11, ((uint32_t)(imm12>>0))&0xfff, Rn, Rt))
+#define LDRSBxw_U12(Rt, Rn, imm12)          EMIT(LDRS_U12_gen(0b00, 0b01, rex.w?0b10:0b11, ((uint32_t)(imm12>>0))&0xfff, Rn, Rt))
+
+#define LDRS_REG_gen(size, Rm, option, S, Rn, Rt)    ((size)<<30 | 0b111<<27 | 0b10<<22 | 1<<21 | (Rm)<<16 | (option)<<13 | (S)<<12 | (0b10)<<10 | (Rn)<<5 | (Rt))
+#define LDRSW_REG(Rt, Rn, Rm)           EMIT(LDRS_REG_gen(0b10, Rm, 0b011, 0, Rn, Rt))
 
 #define LDR_PC_gen(opc, imm19, Rt)      ((opc)<<30 | 0b011<<27 | (imm19)<<5 | (Rt))
 #define LDRx_literal(Rt, imm19)         EMIT(LDR_PC_gen(0b01, ((imm19)>>2)&0x7FFFF, Rt))
 
+#define LDU_gen(size, opc, imm9, Rn, Rt)  ((size)<<30 | 0b111<<27 | (opc)<<22 | ((imm9)&0x1ff)<<12 | (Rn)<<5 | (Rt))
+#define LDURx_I9(Rt, Rn, imm9)            EMIT(LDU_gen(0b11, 0b01, imm9, Rn, Rt))
+#define LDURw_I9(Rt, Rn, imm9)            EMIT(LDU_gen(0b10, 0b01, imm9, Rn, Rt))
+#define LDURxw_I9(Rt, Rn, imm9)           EMIT(LDU_gen((rex.w)?0b11:0b10, 0b01, imm9, Rn, Rt))
+#define LDURz_I9(Rt, Rn, imm9)            EMIT(LDU_gen((rex.is32bits)?0b10:0b11, 0b01, imm9, Rn, Rt))
+#define LDURH_I9(Rt, Rn, imm9)            EMIT(LDU_gen(0b01, 0b01, imm9, Rn, Rt))
+#define LDURB_I9(Rt, Rn, imm9)            EMIT(LDU_gen(0b00, 0b01, imm9, Rn, Rt))
+#define LDURSW_I9(Rt, Rn, imm9)           EMIT(LDU_gen(0b10, 0b10, imm9, Rn, Rt))
+#define LDURSHw_I9(Rt, Rn, imm9)          EMIT(LDU_gen(0b01, 0b11, imm9, Rn, Rt))
+#define LDURSHx_I9(Rt, Rn, imm9)          EMIT(LDU_gen(0b01, 0b10, imm9, Rn, Rt))
+#define LDURSHxw_I9(Rt, Rn, imm9)         EMIT(LDU_gen(0b01, (rex.w)?0b10:0b11, imm9, Rn, Rt))
+#define LDURSBw_I9(Rt, Rn, imm9)          EMIT(LDU_gen(0b00, 0b11, imm9, Rn, Rt))
+#define LDURSBx_I9(Rt, Rn, imm9)          EMIT(LDU_gen(0b00, 0b10, imm9, Rn, Rt))
+#define LDURSBxw_I9(Rt, Rn, imm9)         EMIT(LDU_gen(0b00, (rex.w)?0b10:0b11, imm9, Rn, Rt))
+
+#define LDxw(A, B, C)   if(unscaled) {LDURxw_I9(A, B, C);} else {LDRxw_U12(A, B, C);}
+#define LDz(A, B, C)    if(unscaled) {LDURz_I9(A, B, C);} else {LDRz_U12(A, B, C);}
+#define LDx(A, B, C)    if(unscaled) {LDURx_I9(A, B, C);} else {LDRx_U12(A, B, C);}
+#define LDW(A, B, C)    if(unscaled) {LDURw_I9(A, B, C);} else {LDRw_U12(A, B, C);}
+#define LDH(A, B, C)    if(unscaled) {LDURH_I9(A, B, C);} else {LDRH_U12(A, B, C);}
+#define LDB(A, B, C)    if(unscaled) {LDURB_I9(A, B, C);} else {LDRB_U12(A, B, C);}
+#define LDSW(A, B, C)   if(unscaled) {LDURSW_I9(A, B, C);} else {LDRSW_U12(A, B, C);}
+#define LDSHxw(A, B, C) if(unscaled) {LDURSHxw_I9(A, B, C);} else {LDRSHxw_U12(A, B, C);}
+#define LDSHx(A, B, C)  if(unscaled) {LDURSHx_I9(A, B, C);} else {LDRSHx_U12(A, B, C);}
+#define LDSHw(A, B, C)  if(unscaled) {LDURSHw_I9(A, B, C);} else {LDRSHw_U12(A, B, C);}
+#define LDSBxw(A, B, C) if(unscaled) {LDURSBxw_I9(A, B, C);} else {LDRSBxw_U12(A, B, C);}
+#define LDSBx(A, B, C)  if(unscaled) {LDURSBx_I9(A, B, C);} else {LDRSBx_U12(A, B, C);}
+#define LDSBw(A, B, C)  if(unscaled) {LDURSBw_I9(A, B, C);} else {LDRSBw_U12(A, B, C);}
+#define STxw(A, B, C)   if(unscaled) {STURxw_I9(A, B, C);} else {STRxw_U12(A, B, C);}
+#define STz(A, B, C)    if(unscaled) {STURz_I9(A, B, C);} else {STRz_U12(A, B, C);}
+#define STx(A, B, C)    if(unscaled) {STURx_I9(A, B, C);} else {STRx_U12(A, B, C);}
+#define STW(A, B, C)    if(unscaled) {STURw_I9(A, B, C);} else {STRw_U12(A, B, C);}
+#define STH(A, B, C)    if(unscaled) {STURH_I9(A, B, C);} else {STRH_U12(A, B, C);}
+#define STB(A, B, C)    if(unscaled) {STURB_I9(A, B, C);} else {STRB_U12(A, B, C);}
+
 // STR
 #define STR_gen(size, op1, imm9, op2, Rn, Rt)    ((size)<<30 | 0b111<<27 | (op1)<<24 | 0b00<<22 | (imm9)<<12 | (op2)<<10 | (Rn)<<5 | (Rt))
 #define STRx_S9_postindex(Rt, Rn, imm9)   EMIT(STR_gen(0b11, 0b00, (imm9)&0x1ff, 0b01, Rn, Rt))
@@ -248,14 +299,24 @@
 #define STRw_S9_preindex(Rt, Rn, imm9)    EMIT(STR_gen(0b10, 0b00, (imm9)&0x1ff, 0b11, Rn, Rt))
 #define STRxw_S9_postindex(Rt, Rn, imm9)  EMIT(STR_gen(rex.w?0b11:0b10, 0b00, (imm9)&0x1ff, 0b01, Rn, Rt))
 #define STRB_S9_postindex(Rt, Rn, imm9)   EMIT(STR_gen(0b00, 0b00, (imm9)&0x1ff, 0b01, Rn, Rt))
+#define STRH_S9_preindex(Rt, Rn, imm9)    EMIT(STR_gen(0b01, 0b00, (imm9)&0x1ff, 0b11, Rn, Rt))
 #define STRH_S9_postindex(Rt, Rn, imm9)   EMIT(STR_gen(0b01, 0b00, (imm9)&0x1ff, 0b01, Rn, Rt))
 
 #define ST_gen(size, op1, imm12, Rn, Rt)        ((size)<<30 | 0b111<<27 | (op1)<<24 | 0b00<<22 | (imm12)<<10 | (Rn)<<5 | (Rt))
-#define STRx_U12(Rt, Rn, imm12)           EMIT(ST_gen(0b11, 0b01, ((uint32_t)(imm12>>3))&0xfff, Rn, Rt))
-#define STRw_U12(Rt, Rn, imm12)           EMIT(ST_gen(0b10, 0b01, ((uint32_t)(imm12>>2))&0xfff, Rn, Rt))
-#define STRB_U12(Rt, Rn, imm12)           EMIT(ST_gen(0b00, 0b01, ((uint32_t)(imm12))&0xfff, Rn, Rt))
-#define STRH_U12(Rt, Rn, imm12)           EMIT(ST_gen(0b01, 0b01, ((uint32_t)(imm12>>1))&0xfff, Rn, Rt))
+#define STRx_U12(Rt, Rn, imm12)           EMIT(ST_gen(0b11, 0b01, ((uint32_t)((imm12)>>3))&0xfff, Rn, Rt))
+#define STRw_U12(Rt, Rn, imm12)           EMIT(ST_gen(0b10, 0b01, ((uint32_t)((imm12)>>2))&0xfff, Rn, Rt))
+#define STRB_U12(Rt, Rn, imm12)           EMIT(ST_gen(0b00, 0b01, ((uint32_t)((imm12)))&0xfff, Rn, Rt))
+#define STRH_U12(Rt, Rn, imm12)           EMIT(ST_gen(0b01, 0b01, ((uint32_t)((imm12)>>1))&0xfff, Rn, Rt))
 #define STRxw_U12(Rt, Rn, imm12)          EMIT(ST_gen((rex.w)?0b11:0b10, 0b01, ((uint32_t)((imm12)>>(2+rex.w)))&0xfff, Rn, Rt))
+#define STRz_U12(Rt, Rn, imm12)           EMIT(ST_gen((rex.is32bits)?0b10:0b11, 0b01, ((uint32_t)((imm12)>>(rex.is32bits?2:3)))&0xfff, Rn, Rt))
+
+#define STU_gen(size, opc, imm9, Rn, Rt)  ((size)<<30 | 0b111<<27 | (opc)<<22 | ((imm9)&0x1ff)<<12 | (Rn)<<5 | (Rt))
+#define STURx_I9(Rt, Rn, imm9)            EMIT(STU_gen(0b11, 0b00, imm9, Rn, Rt))
+#define STURw_I9(Rt, Rn, imm9)            EMIT(STU_gen(0b10, 0b00, imm9, Rn, Rt))
+#define STURxw_I9(Rt, Rn, imm9)           EMIT(STU_gen((rex.w)?0b11:0b10, 0b00, imm9, Rn, Rt))
+#define STURz_I9(Rt, Rn, imm9)            EMIT(STU_gen((rex.is32bits)?0b10:0b11, 0b00, imm9, Rn, Rt))
+#define STURH_I9(Rt, Rn, imm9)            EMIT(STU_gen(0b01, 0b00, imm9, Rn, Rt))
+#define STURB_I9(Rt, Rn, imm9)            EMIT(STU_gen(0b00, 0b00, imm9, Rn, Rt))
 
 #define STR_REG_gen(size, Rm, option, S, Rn, Rt)    ((size)<<30 | 0b111<<27 | 0b00<<22 | 1<<21 | (Rm)<<16 | (option)<<13 | (S)<<12 | (0b10)<<10 | (Rn)<<5 | (Rt))
 #define STRx_REG(Rt, Rn, Rm)            EMIT(STR_REG_gen(0b11, Rm, 0b011, 0, Rn, Rt))
@@ -266,33 +327,49 @@
 #define STRB_REG(Rt, Rn, Rm)            EMIT(STR_REG_gen(0b00, Rm, 0b011, 0, Rn, Rt))
 #define STRH_REG(Rt, Rn, Rm)            EMIT(STR_REG_gen(0b01, Rm, 0b011, 0, Rn, Rt))
 #define STRxw_REG(Rt, Rn, Rm)           EMIT(STR_REG_gen(rex.w?0b11:0b10, Rm, 0b011, 0, Rn, Rt))
+#define STRz_REG(Rt, Rn, Rm)            EMIT(STR_REG_gen(rex.is32bits?0b10:0b11, Rm, 0b011, 0, Rn, Rt))
 
 // LOAD/STORE PAIR
 #define MEMPAIR_gen(size, L, op2, imm7, Rt2, Rn, Rt)    ((size)<<31 | 0b101<<27 | (op2)<<23 | (L)<<22 | (imm7)<<15 | (Rt2)<<10 | (Rn)<<5 | (Rt))
 
 #define LDPx_S7_postindex(Rt, Rt2, Rn, imm)             EMIT(MEMPAIR_gen(1, 1, 0b01, (((uint32_t)(imm))>>3)&0x7f, Rt2, Rn, Rt))
 #define LDPw_S7_postindex(Rt, Rt2, Rn, imm)             EMIT(MEMPAIR_gen(0, 1, 0b01, (((uint32_t)(imm))>>2)&0x7f, Rt2, Rn, Rt))
-#define LDPxw_S7_postindex(Rt, Rt2, Rn, imm)            EMIT(MEMPAIR_gen(rex.w, 1, 0b01, (((uint32_t)(imm))>>(2+rex.w)), Rt2, Rn, Rt))
+#define LDPxw_S7_postindex(Rt, Rt2, Rn, imm)            EMIT(MEMPAIR_gen(rex.w, 1, 0b01, (((uint32_t)(imm))>>(2+rex.w))&0x7f, Rt2, Rn, Rt))
 #define LDPx_S7_preindex(Rt, Rt2, Rn, imm)              EMIT(MEMPAIR_gen(1, 1, 0b11, (((uint32_t)(imm))>>3)&0x7f, Rt2, Rn, Rt))
 #define LDPw_S7_preindex(Rt, Rt2, Rn, imm)              EMIT(MEMPAIR_gen(0, 1, 0b11, (((uint32_t)(imm))>>2)&0x7f, Rt2, Rn, Rt))
-#define LDPxw_S7_preindex(Rt, Rt2, Rn, imm)             EMIT(MEMPAIR_gen(rex.w, 1, 0b11, (((uint32_t)(imm))>>(2+rex.w)), Rt2, Rn, Rt))
+#define LDPxw_S7_preindex(Rt, Rt2, Rn, imm)             EMIT(MEMPAIR_gen(rex.w, 1, 0b11, (((uint32_t)(imm))>>(2+rex.w))&0x7f, Rt2, Rn, Rt))
 #define LDPx_S7_offset(Rt, Rt2, Rn, imm)                EMIT(MEMPAIR_gen(1, 1, 0b10, (((uint32_t)(imm))>>3)&0x7f, Rt2, Rn, Rt))
 #define LDPw_S7_offset(Rt, Rt2, Rn, imm)                EMIT(MEMPAIR_gen(0, 1, 0b10, (((uint32_t)(imm))>>2)&0x7f, Rt2, Rn, Rt))
-#define LDPxw_S7_offset(Rt, Rt2, Rn, imm)               EMIT(MEMPAIR_gen(rex.w, 1, 0b10, (((uint32_t)(imm))>>(2+rex.w)), Rt2, Rn, Rt))
+#define LDPxw_S7_offset(Rt, Rt2, Rn, imm)               EMIT(MEMPAIR_gen(rex.w, 1, 0b10, (((uint32_t)(imm))>>(2+rex.w))&0x7f, Rt2, Rn, Rt))
 
 #define STPx_S7_postindex(Rt, Rt2, Rn, imm)             EMIT(MEMPAIR_gen(1, 0, 0b01, (((uint32_t)(imm))>>3)&0x7f, Rt2, Rn, Rt))
 #define STPw_S7_postindex(Rt, Rt2, Rn, imm)             EMIT(MEMPAIR_gen(0, 0, 0b01, (((uint32_t)(imm))>>2)&0x7f, Rt2, Rn, Rt))
-#define STPxw_S7_postindex(Rt, Rt2, Rn, imm)            EMIT(MEMPAIR_gen(rex.w, 0, 0b01, (((uint32_t)(imm))>>(2+rex.w)), Rt2, Rn, Rt))
+#define STPxw_S7_postindex(Rt, Rt2, Rn, imm)            EMIT(MEMPAIR_gen(rex.w, 0, 0b01, (((uint32_t)(imm))>>(2+rex.w))&0x7f, Rt2, Rn, Rt))
 #define STPx_S7_preindex(Rt, Rt2, Rn, imm)              EMIT(MEMPAIR_gen(1, 0, 0b11, (((uint32_t)(imm))>>3)&0x7f, Rt2, Rn, Rt))
 #define STPw_S7_preindex(Rt, Rt2, Rn, imm)              EMIT(MEMPAIR_gen(0, 0, 0b11, (((uint32_t)(imm))>>2)&0x7f, Rt2, Rn, Rt))
-#define STPxw_S7_preindex(Rt, Rt2, Rn, imm)             EMIT(MEMPAIR_gen(rex.w, 0, 0b11, (((uint32_t)(imm))>>(2+rex.w)), Rt2, Rn, Rt))
+#define STPxw_S7_preindex(Rt, Rt2, Rn, imm)             EMIT(MEMPAIR_gen(rex.w, 0, 0b11, (((uint32_t)(imm))>>(2+rex.w))&0x7f, Rt2, Rn, Rt))
 #define STPx_S7_offset(Rt, Rt2, Rn, imm)                EMIT(MEMPAIR_gen(1, 0, 0b10, (((uint32_t)(imm))>>3)&0x7f, Rt2, Rn, Rt))
 #define STPw_S7_offset(Rt, Rt2, Rn, imm)                EMIT(MEMPAIR_gen(0, 0, 0b10, (((uint32_t)(imm))>>2)&0x7f, Rt2, Rn, Rt))
-#define STPxw_S7_offset(Rt, Rt2, Rn, imm)               EMIT(MEMPAIR_gen(rex.w, 0, 0b10, (((uint32_t)(imm))>>(2+rex.w)), Rt2, Rn, Rt))
+#define STPxw_S7_offset(Rt, Rt2, Rn, imm)               EMIT(MEMPAIR_gen(rex.w, 0, 0b10, (((uint32_t)(imm))>>(2+rex.w))&0x7f, Rt2, Rn, Rt))
 
 // PUSH / POP helper
 #define POP1(reg)       LDRx_S9_postindex(reg, xRSP, 8)
 #define PUSH1(reg)      STRx_S9_preindex(reg, xRSP, -8)
+#define POP2(reg1, reg2)       LDPx_S7_postindex(reg1, reg2, xRSP, 16)
+#define PUSH2(reg1, reg2)      STPx_S7_preindex(reg2, reg1, xRSP, -16)
+
+#define POP1_32(reg)            LDRw_S9_postindex(reg, xRSP, 4)
+#define PUSH1_32(reg)           STRw_S9_preindex(reg, xRSP, -4)
+#define POP2_32(reg1, reg2)     LDPw_S7_postindex(reg1, reg2, xRSP, 8)
+#define PUSH2_32(reg1, reg2)    STPw_S7_preindex(reg2, reg1, xRSP, -8)
+
+#define POP1_16(reg)            LDRH_S9_postindex(reg, xRSP, 2)
+#define PUSH1_16(reg)           STRH_S9_preindex(reg, xRSP, -2)
+
+#define POP1z(reg)              if(rex.is32bits) {POP1_32(reg);} else {POP1(reg);}
+#define PUSH1z(reg)             if(rex.is32bits) {PUSH1_32(reg);} else {PUSH1(reg);}
+#define POP2z(reg1, reg2)       if(rex.is32bits) {POP2_32(reg1, reg2);} else {POP2(reg1, reg2);}
+#define PUSH2z(reg1, reg2)      if(rex.is32bits) {PUSH2_32(reg1, reg2);} else {PUSH2(reg1, reg2);}
 
 // LOAD/STORE Acquire Exclusive
 #define MEMAX_gen(size, L, Rs, Rn, Rt)      ((size)<<30 | 0b001000<<24 | (L)<<22 | (Rs)<<16 | 1<<15 | 0b11111<<10 | (Rn)<<5 | (Rt))
@@ -345,6 +422,15 @@
 #define PLD_L2_STREAM_U12(Rn, imm12)    EMIT(PRFM_imm(((imm12)>>3)&0xfff, Rn, 0b00011))
 #define PLD_L3_STREAM_U12(Rn, imm12)    EMIT(PRFM_imm(((imm12)>>3)&0xfff, Rn, 0b00101))
 
+#define PST_L1_STREAM_U12(Rn, imm12)    EMIT(PRFM_imm(((imm12)>>3)&0xfff, Rn, 0b01001))
+
+// Data Memory Barrier
+#define DMB_gen(CRm)                    (0b1101010100<<22 | 0b011<<16 | 0b0011<<12 | (CRm)<<8 | 1<<7 | 0b01<<5 | 0b11111)
+#define DMB_ISH()                       EMIT(DMB_gen(0b1011))
+
+// Break
+#define BRK_gen(imm16)                  (0b11010100<<24 | 0b001<<21 | (((imm16)&0xffff)<<5))
+#define BRK(imm16)                      EMIT(BRK_gen(imm16))
 
 // BR and Branches
 #define BR_gen(Z, op, A, M, Rn, Rm)       (0b1101011<<25 | (Z)<<24 | (op)<<21 | 0b11111<<16 | (A)<<11 | (M)<<10 | (Rn)<<5 | (Rm))
@@ -355,9 +441,11 @@
 #define CBNZx(Rt, imm19)                EMIT(CB_gen(1, 1, ((imm19)>>2)&0x7FFFF, Rt))
 #define CBNZw(Rt, imm19)                EMIT(CB_gen(0, 1, ((imm19)>>2)&0x7FFFF, Rt))
 #define CBNZxw(Rt, imm19)               EMIT(CB_gen(rex.w, 1, ((imm19)>>2)&0x7FFFF, Rt))
+#define CBNZz(Rt, imm19)                EMIT(CB_gen(rex.is32bits?0:1, 1, ((imm19)>>2)&0x7FFFF, Rt))
 #define CBZx(Rt, imm19)                 EMIT(CB_gen(1, 0, ((imm19)>>2)&0x7FFFF, Rt))
 #define CBZw(Rt, imm19)                 EMIT(CB_gen(0, 0, ((imm19)>>2)&0x7FFFF, Rt))
 #define CBZxw(Rt, imm19)                EMIT(CB_gen(rex.w, 0, ((imm19)>>2)&0x7FFFF, Rt))
+#define CBZz(Rt, imm19)                 EMIT(CB_gen(rex.is32bits?0:1, 0, ((imm19)>>2)&0x7FFFF, Rt))
 
 #define TB_gen(b5, op, b40, imm14, Rt)  ((b5)<<31 | 0b011011<<25 | (op)<<24  | (b40)<<19 | (imm14)<<5 | (Rt))
 #define TBZ(Rt, bit, imm16)             EMIT(TB_gen(((bit)>>5)&1, 0, (bit)&0x1f, ((imm16)>>2)&0x3FFF, Rt))
@@ -402,9 +490,9 @@
 #define CSNEGx(Rd, Rn, Rm, cond)            EMIT(CSNEG_gen(1, Rm, cond, Rn, Rd))
 #define CSNEGw(Rd, Rn, Rm, cond)            EMIT(CSNEG_gen(0, Rm, cond, Rn, Rd))
 #define CSNEGxw(Rd, Rn, Rm, cond)           EMIT(CSNEG_gen(rex.w, Rm, cond, Rn, Rd))
-#define CNEGx(Rd, Rn, cond)                 CSNEGx(Rn, Rn, Rn, invCond(cond))
-#define CNEGw(Rd, Rn, cond)                 CSNEGw(Rn, Rn, Rn, invCond(cond))
-#define CNEGxw(Rd, Rn, cond)                CSNEGxw(Rn, Rn, Rn, invCond(cond))
+#define CNEGx(Rd, Rn, cond)                 CSNEGx(Rn, Rn, Rd, invCond(cond))
+#define CNEGw(Rd, Rn, cond)                 CSNEGw(Rn, Rn, Rd, invCond(cond))
+#define CNEGxw(Rd, Rn, cond)                CSNEGxw(Rn, Rn, Rd, invCond(cond))
 
 // AND / ORR
 #define LOGIC_gen(sf, opc, N, immr, imms, Rn, Rd)  ((sf)<<31 | (opc)<<29 | 0b100100<<23 | (N)<<22 | (immr)<<16 | (imms)<<10 | (Rn)<<5 | Rd)
@@ -430,11 +518,16 @@
 #define ORRx_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(1, 0b01, 0b00, 0, Rm, 0, Rn, Rd))
 #define ORRx_REG_LSL(Rd, Rn, Rm, lsl)   EMIT(LOGIC_REG_gen(1, 0b01, 0b00, 0, Rm, lsl, Rn, Rd))
 #define ORRw_REG_LSL(Rd, Rn, Rm, lsl)   EMIT(LOGIC_REG_gen(0, 0b01, 0b00, 0, Rm, lsl, Rn, Rd))
+#define ORRxw_REG_LSL(Rd, Rn, Rm, lsl)  EMIT(LOGIC_REG_gen(rex.w, 0b01, 0b00, 0, Rm, lsl, Rn, Rd))
+#define ORRx_REG_LSR(Rd, Rn, Rm, lsr)   EMIT(LOGIC_REG_gen(1, 0b01, 0b01, 0, Rm, lsr, Rn, Rd))
+#define ORRw_REG_LSR(Rd, Rn, Rm, lsr)   EMIT(LOGIC_REG_gen(0, 0b01, 0b01, 0, Rm, lsr, Rn, Rd))
+#define ORRxw_REG_LSR(Rd, Rn, Rm, lsr)  EMIT(LOGIC_REG_gen(rex.w, 0b01, 0b01, 0, Rm, lsr, Rn, Rd))
 #define ORRxw_REG(Rd, Rn, Rm)           EMIT(LOGIC_REG_gen(rex.w, 0b01, 0b00, 0, Rm, 0, Rn, Rd))
 #define ORRw_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(0, 0b01, 0b00, 0, Rm, 0, Rn, Rd))
 #define ORNx_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(1, 0b01, 0b00, 1, Rm, 0, Rn, Rd))
 #define ORNw_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(0, 0b01, 0b00, 1, Rm, 0, Rn, Rd))
 #define ORNxw_REG(Rd, Rn, Rm)           EMIT(LOGIC_REG_gen(rex.w, 0b01, 0b00, 1, Rm, 0, Rn, Rd))
+#define ORNx_REG_LSL(Rd, Rn, Rm, lsl)   EMIT(LOGIC_REG_gen(1, 0b01, 0b00, 1, Rm, lsl, Rn, Rd))
 #define EORx_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(1, 0b10, 0b00, 0, Rm, 0, Rn, Rd))
 #define EORw_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(0, 0b10, 0b00, 0, Rm, 0, Rn, Rd))
 #define EORxw_REG(Rd, Rn, Rm)           EMIT(LOGIC_REG_gen(rex.w, 0b10, 0b00, 0, Rm, 0, Rn, Rd))
@@ -444,9 +537,25 @@
 #define EORx_REG_LSR(Rd, Rn, Rm, lsr)   EMIT(LOGIC_REG_gen(1, 0b10, 0b01, 0, Rm, lsr, Rn, Rd))
 #define EORw_REG_LSR(Rd, Rn, Rm, lsr)   EMIT(LOGIC_REG_gen(0, 0b10, 0b01, 0, Rm, lsr, Rn, Rd))
 #define EORxw_REG_LSR(Rd, Rn, Rm, lsr)  EMIT(LOGIC_REG_gen(rex.w, 0b10, 0b01, 0, Rm, lsr, Rn, Rd))
+#define EONx_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(1, 0b10, 0b00, 1, Rm, 0, Rn, Rd))
+#define EONw_REG(Rd, Rn, Rm)            EMIT(LOGIC_REG_gen(0, 0b10, 0b00, 1, Rm, 0, Rn, Rd))
+#define EONxw_REG(Rd, Rn, Rm)           EMIT(LOGIC_REG_gen(rex.w, 0b10, 0b00, 1, Rm, 0, Rn, Rd))
+#define EONx_REG_LSL(Rd, Rn, Rm, lsl)   EMIT(LOGIC_REG_gen(1, 0b10, 0b00, 1, Rm, lsl, Rn, Rd))
+#define EONw_REG_LSL(Rd, Rn, Rm, lsl)   EMIT(LOGIC_REG_gen(0, 0b10, 0b00, 1, Rm, lsl, Rn, Rd))
+#define EONxw_REG_LSL(Rd, Rn, Rm, lsl)  EMIT(LOGIC_REG_gen(rex.w, 0b10, 0b00, 1, Rm, lsl, Rn, Rd))
+#define EONx_REG_LSR(Rd, Rn, Rm, lsr)   EMIT(LOGIC_REG_gen(1, 0b10, 0b01, 1, Rm, lsr, Rn, Rd))
+#define EONw_REG_LSR(Rd, Rn, Rm, lsr)   EMIT(LOGIC_REG_gen(0, 0b10, 0b01, 1, Rm, lsr, Rn, Rd))
+#define EONxw_REG_LSR(Rd, Rn, Rm, lsr)  EMIT(LOGIC_REG_gen(rex.w, 0b10, 0b01, 1, Rm, lsr, Rn, Rd))
 #define MOVx_REG(Rd, Rm)                ORRx_REG(Rd, xZR, Rm)
 #define MOVw_REG(Rd, Rm)                ORRw_REG(Rd, xZR, Rm)
 #define MOVxw_REG(Rd, Rm)               ORRxw_REG(Rd, xZR, Rm)
+#define MOVz_REG(Rd, Rm)                if(rex.is32bits) {MOVw_REG(Rd, Rm);} else {MOVx_REG(Rd, Rm);}
+#define LSLw_IMM(Rd, Rm, lsl)           ORRw_REG_LSL(Rd, xZR, Rm, lsl)
+#define LSLx_IMM(Rd, Rm, lsl)           ORRx_REG_LSL(Rd, xZR, Rm, lsl)
+#define LSLxw_IMM(Rd, Rm, lsl)          ORRxw_REG_LSL(Rd, xZR, Rm, lsl)
+#define LSRw_IMM(Rd, Rm, lsr)           ORRw_REG_LSR(Rd, xZR, Rm, lsr)
+#define LSRx_IMM(Rd, Rm, lsr)           ORRx_REG_LSR(Rd, xZR, Rm, lsr)
+#define LSRxw_IMM(Rd, Rm, lsr)          ORRxw_REG_LSR(Rd, xZR, Rm, lsr)
 #define MVNx_REG(Rd, Rm)                ORNx_REG(Rd, xZR, Rm)
 #define MVNx_REG_LSL(Rd, Rm, lsl)       ORNx_REG_LSL(Rd, xZR, Rm, lsl)
 #define MVNw_REG(Rd, Rm)                ORNw_REG(Rd, xZR, Rm)
@@ -463,6 +572,12 @@
 #define BICx_REG    BICx
 #define BICw_REG    BICw
 #define BICxw_REG   BICxw
+#define BICx_REG_LSL(Rd, Rn, Rm, lsl)   EMIT(LOGIC_REG_gen(1, 0b00, 0b00, 1, Rm, lsl, Rn, Rd))
+#define BICw_REG_LSL(Rd, Rn, Rm, lsl)   EMIT(LOGIC_REG_gen(0, 0b00, 0b00, 1, Rm, lsl, Rn, Rd))
+#define BICxw_REG_LSL(Rd, Rn, Rm, lsl)  EMIT(LOGIC_REG_gen(rex.w, 0b00, 0b00, 1, Rm, lsl, Rn, Rd))
+#define BICx_REG_LSR(Rd, Rn, Rm, lsl)   EMIT(LOGIC_REG_gen(1, 0b00, 0b01, 1, Rm, lsl, Rn, Rd))
+#define BICw_REG_LSR(Rd, Rn, Rm, lsl)   EMIT(LOGIC_REG_gen(0, 0b00, 0b01, 1, Rm, lsl, Rn, Rd))
+#define BICxw_REG_LSR(Rd, Rn, Rm, lsl)  EMIT(LOGIC_REG_gen(rex.w, 0b00, 0b01, 1, Rm, lsl, Rn, Rd))
 #define TSTx_REG(Rn, Rm)                ANDSx_REG(xZR, Rn, Rm)
 #define TSTw_REG(Rn, Rm)                ANDSw_REG(wZR, Rn, Rm)
 #define TSTxw_REG(Rn, Rm)               ANDSxw_REG(xZR, Rn, Rm)
@@ -575,13 +690,27 @@
 #define UMULH(Xd, Xn, Xm)               EMIT(MULH_gen(1, Xm, Xn, Xd))
 #define SMULH(Xd, Xn, Xm)               EMIT(MULH_gen(0, Xm, Xn, Xd))
 
-#define MADD_gen(sf, Rm, Ra, Rn, Rd)    ((sf)<<31 | 0b11011<<24 | (Rm)<<16 | (Ra)<<10 | (Rn)<<5 | (Rd))
-#define MADDx(Rd, Rn, Rm, Ra)           EMIT(MADD_gen(1, Rm, Ra, Rn, Rd))
-#define MADDw(Rd, Rn, Rm, Ra)           EMIT(MADD_gen(0, Rm, Ra, Rn, Rd))
-#define MADDxw(Rd, Rn, Rm, Ra)          EMIT(MADD_gen(rex.w, Rm, Ra, Rn, Rd))
+#define MADD_gen(sf, Rm, o0, Ra, Rn, Rd)    ((sf)<<31 | 0b11011<<24 | (Rm)<<16 | (o0)<<15 | (Ra)<<10 | (Rn)<<5 | (Rd))
+#define MADDx(Rd, Rn, Rm, Ra)           EMIT(MADD_gen(1, Rm, 0, Ra, Rn, Rd))
+#define MADDw(Rd, Rn, Rm, Ra)           EMIT(MADD_gen(0, Rm, 0, Ra, Rn, Rd))
+#define MADDxw(Rd, Rn, Rm, Ra)          EMIT(MADD_gen(rex.w, Rm, 0, Ra, Rn, Rd))
 #define MULx(Rd, Rn, Rm)                MADDx(Rd, Rn, Rm, xZR)
 #define MULw(Rd, Rn, Rm)                MADDw(Rd, Rn, Rm, xZR)
 #define MULxw(Rd, Rn, Rm)               MADDxw(Rd, Rn, Rm, xZR)
+#define MSUBx(Rd, Rn, Rm, Ra)           EMIT(MADD_gen(1, Rm, 1, Ra, Rn, Rd))
+#define MSUBw(Rd, Rn, Rm, Ra)           EMIT(MADD_gen(0, Rm, 1, Ra, Rn, Rd))
+#define MSUBxw(Rd, Rn, Rm, Ra)          EMIT(MADD_gen(rex.w, Rm, 1, Ra, Rn, Rd))
+#define MNEGx(Rd, Rn, Rm)               EMIT(MADD_gen(1, Rm, 1, xZR, Rn, Rd))
+#define MNEGw(Rd, Rn, Rm)               EMIT(MADD_gen(0, Rm, 1, xZR, Rn, Rd))
+#define MNEGxw(Rd, Rn, Rm)              EMIT(MADD_gen(rex.w, Rm, 1, xZR, Rn, Rd))
+
+
+// DIV
+#define DIV_gen(sf, Rm, o1, Rn, Rd)     ((sf)<<31 | 0b11010110<<21 | (Rm)<<16 | 0b00001<<11 | (o1)<<10 | (Rn)<<5 | (Rd))
+#define UDIVw(Wd, Wn, Wm)               EMIT(DIV_gen(0, Wm, 0, Wn, Wd))
+#define UDIVx(Xd, Xn, Xm)               EMIT(DIV_gen(1, Xm, 0, Xn, Xd))
+#define SDIVw(Wd, Wn, Wm)               EMIT(DIV_gen(0, Wm, 1, Wn, Wd))
+#define SDIVx(Xd, Xn, Xm)               EMIT(DIV_gen(1, Xm, 1, Xn, Xd))
 
 // CLZ
 #define CL_gen(sf, op, Rn, Rd)          ((sf)<<31 | 1<<30 | 0b11010110<<21 | 0b00010<<11 | (op)<<10 | (Rn)<<5 | (Rd))
@@ -600,9 +729,15 @@
 
 // REV
 #define REV_gen(sf, opc, Rn, Rd)        ((sf)<<31 | 1<<30 | 0b11010110<<21 | (opc)<<10 | (Rn)<<5 | (Rd))
-#define REVx(Rd, Rn)                    EMIT(REV_gen(1, 0b11, Rn, Rd))
-#define REVw(Rd, Rn)                    EMIT(REV_gen(0, 0b10, Rn, Rd))
+#define REV64x(Rd, Rn)                  EMIT(REV_gen(1, 0b11, Rn, Rd))
+#define REV32w(Rd, Rn)                  EMIT(REV_gen(0, 0b10, Rn, Rd))
 #define REVxw(Rd, Rn)                   EMIT(REV_gen(rex.w, 0b10|rex.w, Rn, Rd))
+#define REV16w(Rd, Rn)                  EMIT(REV_gen(0, 0b01, Rn, Rd))
+#define REV16x(Rd, Rn)                  EMIT(REV_gen(1, 0b01, Rn, Rd))
+
+// UDF
+#define UDF_gen(imm16)                  ((imm16)&0xffff)
+#define UDF(imm16)                      EMIT(UDF_gen(imm16))
 
 // MRS
 #define MRS_gen(L, o0, op1, CRn, CRm, op2, Rt)  (0b1101010100<<22 | (L)<<21 | 1<<20 | (o0)<<19 | (op1)<<16 | (CRn)<<12 | (CRm)<<8 | (op2)<<5 | (Rt))
@@ -639,7 +774,9 @@
  
 // VLDR
 #define VMEM_gen(size, opc, imm12, Rn, Rt)  ((size)<<30 | 0b111<<27 | 1<<26 | 0b01<<24 | (opc)<<22 | (imm12)<<10 | (Rn)<<5 | (Rt))
-// imm14 must be 3-aligned
+// imm13 must be 1-aligned
+#define VLDR16_U12(Ht, Rn, imm13)           EMIT(VMEM_gen(0b01, 0b01, ((uint32_t)((imm13)>>1))&0xfff, Rn, Ht))
+// imm14 must be 2-aligned
 #define VLDR32_U12(Dt, Rn, imm14)           EMIT(VMEM_gen(0b10, 0b01, ((uint32_t)((imm14)>>2))&0xfff, Rn, Dt))
 // imm15 must be 3-aligned
 #define VLDR64_U12(Dt, Rn, imm15)           EMIT(VMEM_gen(0b11, 0b01, ((uint32_t)((imm15)>>3))&0xfff, Rn, Dt))
@@ -651,22 +788,31 @@
 #define VSTR64_U12(Dt, Rn, imm15)           EMIT(VMEM_gen(0b11, 0b00, ((uint32_t)(imm15>>3))&0xfff, Rn, Dt))
 // imm16 must be 4-aligned
 #define VSTR128_U12(Qt, Rn, imm16)          EMIT(VMEM_gen(0b00, 0b10, ((uint32_t)((imm16)>>4))&0xfff, Rn, Qt))
-// (imm14) must be 1-aligned
-#define VSTR16_U12(Ht, Rn, imm14)           EMIT(VMEM_gen(0b01, 0b00, ((uint32_t)(imm14>>1))&0xfff, Rn, Ht))
+// (imm13) must be 1-aligned
+#define VSTR16_U12(Ht, Rn, imm13)           EMIT(VMEM_gen(0b01, 0b00, ((uint32_t)(imm13>>1))&0xfff, Rn, Ht))
 
 #define VMEMUR_vector(size, opc, imm9, Rn, Rt)  ((size)<<30 | 0b111<<27 | 1<<26 | (opc)<<22 | (imm9)<<12 | (Rn)<<5 | (Rt))
 // signed offset, no alignement!
-#define VLDR8_I9(Vt, Rn, imm9)              EMIT(VMEMUR(0b00, 0b01, (imm9)&0b111111111, Rn, Vt))
-#define VLDR16_I9(Vt, Rn, imm9)             EMIT(VMEMUR(0b01, 0b01, (imm9)&0b111111111, Rn, Vt))
-#define VLDR32_I9(Vt, Rn, imm9)             EMIT(VMEMUR(0b10, 0b01, (imm9)&0b111111111, Rn, Vt))
-#define VLDR64_I9(Vt, Rn, imm9)             EMIT(VMEMUR(0b11, 0b01, (imm9)&0b111111111, Rn, Vt))
-#define VLDR128_I9(Vt, Rn, imm9)            EMIT(VMEMUR(0b00, 0b11, (imm9)&0b111111111, Rn, Vt))
+#define VLDR8_I9(Vt, Rn, imm9)              EMIT(VMEMUR_vector(0b00, 0b01, (imm9)&0b111111111, Rn, Vt))
+#define VLDR16_I9(Vt, Rn, imm9)             EMIT(VMEMUR_vector(0b01, 0b01, (imm9)&0b111111111, Rn, Vt))
+#define VLDR32_I9(Vt, Rn, imm9)             EMIT(VMEMUR_vector(0b10, 0b01, (imm9)&0b111111111, Rn, Vt))
+#define VLDR64_I9(Vt, Rn, imm9)             EMIT(VMEMUR_vector(0b11, 0b01, (imm9)&0b111111111, Rn, Vt))
+#define VLDR128_I9(Vt, Rn, imm9)            EMIT(VMEMUR_vector(0b00, 0b11, (imm9)&0b111111111, Rn, Vt))
 // signed offset, no alignement!
-#define VSTR8_I9(Vt, Rn, imm9)              EMIT(VMEMUR(0b00, 0b00, (imm9)&0b111111111, Rn, Vt))
-#define VSTR16_I9(Vt, Rn, imm9)             EMIT(VMEMUR(0b01, 0b00, (imm9)&0b111111111, Rn, Vt))
-#define VSTR32_I9(Vt, Rn, imm9)             EMIT(VMEMUR(0b10, 0b00, (imm9)&0b111111111, Rn, Vt))
-#define VSTR64_I9(Vt, Rn, imm9)             EMIT(VMEMUR(0b11, 0b00, (imm9)&0b111111111, Rn, Vt))
-#define VSTR128_I9(Vt, Rn, imm9)            EMIT(VMEMUR(0b00, 0b10, (imm9)&0b111111111, Rn, Vt))
+#define VSTR8_I9(Vt, Rn, imm9)              EMIT(VMEMUR_vector(0b00, 0b00, (imm9)&0b111111111, Rn, Vt))
+#define VSTR16_I9(Vt, Rn, imm9)             EMIT(VMEMUR_vector(0b01, 0b00, (imm9)&0b111111111, Rn, Vt))
+#define VSTR32_I9(Vt, Rn, imm9)             EMIT(VMEMUR_vector(0b10, 0b00, (imm9)&0b111111111, Rn, Vt))
+#define VSTR64_I9(Vt, Rn, imm9)             EMIT(VMEMUR_vector(0b11, 0b00, (imm9)&0b111111111, Rn, Vt))
+#define VSTR128_I9(Vt, Rn, imm9)            EMIT(VMEMUR_vector(0b00, 0b10, (imm9)&0b111111111, Rn, Vt))
+
+#define VLD128(A, B, C)     if(unscaled) {VLDR128_I9(A, B, C);} else {VLDR128_U12(A, B, C);}
+#define VLD64(A, B, C)      if(unscaled) {VLDR64_I9(A, B, C);} else {VLDR64_U12(A, B, C);}
+#define VLD32(A, B, C)      if(unscaled) {VLDR32_I9(A, B, C);} else {VLDR32_U12(A, B, C);}
+#define VLD16(A, B, C)      if(unscaled) {VLDR16_I9(A, B, C);} else {VLDR16_U12(A, B, C);}
+#define VST128(A, B, C)     if(unscaled) {VSTR128_I9(A, B, C);} else {VSTR128_U12(A, B, C);}
+#define VST64(A, B, C)      if(unscaled) {VSTR64_I9(A, B, C);} else {VSTR64_U12(A, B, C);}
+#define VST32(A, B, C)      if(unscaled) {VSTR32_I9(A, B, C);} else {VSTR32_U12(A, B, C);}
+#define VST16(A, B, C)      if(unscaled) {VSTR16_I9(A, B, C);} else {VSTR16_U12(A, B, C);}
 
 #define VMEMW_gen(size, opc, imm9, op2, Rn, Rt)  ((size)<<30 | 0b111<<27 | 1<<26 | (opc)<<22 | (imm9)<<12 | (op2)<<10 | 0b01<<10 | (Rn)<<5 | (Rt))
 #define VLDR64_S9_postindex(Rt, Rn, imm9)   EMIT(VMEMW_gen(0b11, 0b01, (imm9)&0x1ff, 0b01, Rn, Rt))
@@ -681,18 +827,18 @@
 #define VMEM_REG_gen(size, opc, Rm, option, S, Rn, Rt)  ((size)<<30 | 0b111<<27 | 1<<26 | (opc)<<22 | 1<<21 | (Rm)<<16 | (option)<<13 | (S)<<12 | 0b10<<10 | (Rn)<<5 | (Rt))
 
 #define VLDR32_REG(Dt, Rn, Rm)              EMIT(VMEM_REG_gen(0b10, 0b01, Rm, 0b011, 0, Rn, Dt))
-#define VLDR32_REG_LSL3(Dt, Rn, Rm)         EMIT(VMEM_REG_gen(0b10, 0b01, Rm, 0b011, 1, Rn, Dt))
+#define VLDR32_REG_LSL2(Dt, Rn, Rm)         EMIT(VMEM_REG_gen(0b10, 0b01, Rm, 0b011, 1, Rn, Dt))
 #define VLDR64_REG(Dt, Rn, Rm)              EMIT(VMEM_REG_gen(0b11, 0b01, Rm, 0b011, 0, Rn, Dt))
 #define VLDR64_REG_LSL3(Dt, Rn, Rm)         EMIT(VMEM_REG_gen(0b11, 0b01, Rm, 0b011, 1, Rn, Dt))
-#define VLDR128_REG(Qt, Rn, Rm)             EMIT(VMEM_REG_gen(0b00, 0b11, Rm, 0b011, 0, Rn, Dt))
-#define VLDR128_REG_LSL4(Qt, Rn, Rm)        EMIT(VMEM_REG_gen(0b00, 0b11, Rm, 0b011, 1, Rn, Dt))
+#define VLDR128_REG(Qt, Rn, Rm)             EMIT(VMEM_REG_gen(0b00, 0b11, Rm, 0b011, 0, Rn, Qt))
+#define VLDR128_REG_LSL4(Qt, Rn, Rm)        EMIT(VMEM_REG_gen(0b00, 0b11, Rm, 0b011, 1, Rn, Qt))
 
 #define VSTR32_REG(Dt, Rn, Rm)              EMIT(VMEM_REG_gen(0b10, 0b00, Rm, 0b011, 0, Rn, Dt))
-#define VSTR32_REG_LSL3(Dt, Rn, Rm)         EMIT(VMEM_REG_gen(0b10, 0b00, Rm, 0b011, 1, Rn, Dt))
+#define VSTR32_REG_LSL2(Dt, Rn, Rm)         EMIT(VMEM_REG_gen(0b10, 0b00, Rm, 0b011, 1, Rn, Dt))
 #define VSTR64_REG(Dt, Rn, Rm)              EMIT(VMEM_REG_gen(0b11, 0b00, Rm, 0b011, 0, Rn, Dt))
 #define VSTR64_REG_LSL3(Dt, Rn, Rm)         EMIT(VMEM_REG_gen(0b11, 0b00, Rm, 0b011, 1, Rn, Dt))
-#define VSTR128_REG(Qt, Rn, Rm)             EMIT(VMEM_REG_gen(0b00, 0b10, Rm, 0b011, 0, Rn, Dt))
-#define VSTR128_REG_LSL4(Qt, Rn, Rm)        EMIT(VMEM_REG_gen(0b00, 0b10, Rm, 0b011, 1, Rn, Dt))
+#define VSTR128_REG(Qt, Rn, Rm)             EMIT(VMEM_REG_gen(0b00, 0b10, Rm, 0b011, 0, Rn, Qt))
+#define VSTR128_REG_LSL4(Qt, Rn, Rm)        EMIT(VMEM_REG_gen(0b00, 0b10, Rm, 0b011, 1, Rn, Qt))
 
 #define VLDR_PC_gen(opc, imm19, Rt)         ((opc)<<30 | 0b011<<27 | 1<<26 | (imm19)<<5 | (Rt))
 #define VLDR32_literal(Vt, imm19)           EMIT(VLDR_PC_gen(0b00, ((imm19)>>2)&0x7FFFF, Vt))
@@ -740,6 +886,7 @@
 
 #define SHL_scalar(U, size, Rm, R, S, Rn, Rd)   (0b01<<30 | (U)<<29 | 0b11110<<24 | (size)<<22 | 1<<21 | (Rm)<<16 | 0b010<<13 | (R)<<12 | (S)<<11 | 1<<10 | (Rn)<<5 | (Rd))
 #define SSHL_R_64(Vd, Vn, Vm)               EMIT(SHL_scalar(0, 0b11, Vm, 0, 0, Vn, Vd))
+#define USHL_R_64(Vd, Vn, Vm)               EMIT(SHL_scalar(1, 0b11, Vm, 0, 0, Vn, Vd))
 
 #define SHL_scalar_imm(U, immh, immb, Rn, Rd)   (0b01<<30 | 0b111110<<23 | (immh)<<19 | (immb)<<16 | 0b01010<<11 | 1<<10 | (Rn)<<5 | (Rd))
 #define SHL_64(Vd, Vn, shift)               EMIT(SHL_scalar_imm(0, 0b1000 | (((shift)>>3)&7), (shift)&7, Vn, Vd))
@@ -752,6 +899,13 @@
 #define SSHLQ_16(Vd, Vn, Vm)                EMIT(SHL_vector_vector(1, 0, 0b01, Vm, 0, 0, Vn, Vd))
 #define SSHLQ_32(Vd, Vn, Vm)                EMIT(SHL_vector_vector(1, 0, 0b10, Vm, 0, 0, Vn, Vd))
 #define SSHLQ_64(Vd, Vn, Vm)                EMIT(SHL_vector_vector(1, 0, 0b11, Vm, 0, 0, Vn, Vd))
+#define USHL_8(Vd, Vn, Vm)                  EMIT(SHL_vector_vector(0, 1, 0b00, Vm, 0, 0, Vn, Vd))
+#define USHL_16(Vd, Vn, Vm)                 EMIT(SHL_vector_vector(0, 1, 0b01, Vm, 0, 0, Vn, Vd))
+#define USHL_32(Vd, Vn, Vm)                 EMIT(SHL_vector_vector(0, 1, 0b10, Vm, 0, 0, Vn, Vd))
+#define USHLQ_8(Vd, Vn, Vm)                 EMIT(SHL_vector_vector(1, 1, 0b00, Vm, 0, 0, Vn, Vd))
+#define USHLQ_16(Vd, Vn, Vm)                EMIT(SHL_vector_vector(1, 1, 0b01, Vm, 0, 0, Vn, Vd))
+#define USHLQ_32(Vd, Vn, Vm)                EMIT(SHL_vector_vector(1, 1, 0b10, Vm, 0, 0, Vn, Vd))
+#define USHLQ_64(Vd, Vn, Vm)                EMIT(SHL_vector_vector(1, 1, 0b11, Vm, 0, 0, Vn, Vd))
 
 #define SHR_vector(Q, U, immh, immb, Rn, Rd)  ((Q)<<30 | (U)<<29 | 0b011110<<23 | (immh)<<19 | (immb)<<16 | 0b00000<<11 | 1<<10 | (Rn)<<5 | (Rd))
 #define VSHRQ_8(Vd, Vn, shift)              EMIT(SHR_vector(1, 1, 0b0001, (8-(shift))&7, Vn, Vd))
@@ -814,6 +968,10 @@
 #define VSUB_16(Vd, Vn, Vm)                 EMIT(ADDSUB_vector(0, 1, 0b01, Vm, Vn, Vd))
 #define VSUB_32(Vd, Vn, Vm)                 EMIT(ADDSUB_vector(0, 1, 0b10, Vm, Vn, Vd))
 
+#define ADDSUB_scalar(U, size, Rm, Rn, Rd)  (01<<30 | (U)<<29 | 0b11110<<24 | (size)<<22 | 1<<21 | (Rm)<<16 | 0b10000<<11 | 1<<10 | (Rn)<<5 | (Rd))
+#define ADD_64(Vd, Vn, Vm)                  EMIT(ADDSUB_scalar(0, 0b11, Vm, Vn, Vd))
+#define SUB_64(Vd, Vn, Vm)                  EMIT(ADDSUB_scalar(1, 0b11, Vm, Vn, Vd))
+
 #define NEGABS_vector(Q, U, size, Rn, Rd)   ((Q)<<30 | (U)<<29 | 0b01110<<24 | (size)<<22 | 0b10000<<17 | 0b01011<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
 #define NEG_8(Vd, Vn)                       EMIT(NEGABS_vector(0, 1, 0b00, Vn, Vd))
 #define NEG_16(Vd, Vn)                      EMIT(NEGABS_vector(0, 1, 0b01, Vn, Vd))
@@ -830,6 +988,10 @@
 #define ABSQ_32(Vd, Vn)                     EMIT(NEGABS_vector(1, 0, 0b10, Vn, Vd))
 #define ABSQ_64(Vd, Vn)                     EMIT(NEGABS_vector(1, 0, 0b11, Vn, Vd))
 
+#define NEGABS_vector_scalar(U, size, Rn, Rd)   (0b01<<30 | (U)<<29 | 0b11110<<24 | (size)<<22 | 0b10000<<17 | 0b01011<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define NEG_64(Vd, Vn)                     EMIT(NEGABS_vector_scalar(1, 0b11, Vn, Vd))
+#define ABS_64(Vd, Vn)                     EMIT(NEGABS_vector_scalar(0, 0b11, Vn, Vd))
+
 // FMOV
 #define FMOV_general(sf, type, mode, opcode, Rn, Rd)    ((sf)<<31 | 0b11110<<24 | (type)<<22 | 1<<21 | (mode)<<19 | (opcode)<<16 | (Rn)<<5 | (Rd))
 // 32-bit to single-precision
@@ -952,6 +1114,11 @@
 #define FMULS(Sd, Sn, Sm)           EMIT(FMUL_scalar(0b00, Sm, Sn, Sd))
 #define FMULD(Dd, Dn, Dm)           EMIT(FMUL_scalar(0b01, Dm, Dn, Dd))
 
+#define FMLA_vector(Q, op, sz, Rm, Rn, Rd)	((Q)<<30 | 0b01110<<24 | (op)<<23 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b11001<<11 | 1<<10 | (Rn)<<5 | (Rd))
+#define VFMLAS(Sd, Sn, Sm)	        EMIT(FMLA_vector(0, 0, 0, Sm, Sn, Sd))
+#define VFMLAQS(Sd, Sn, Sm)	        EMIT(FMLA_vector(1, 0, 0, Sm, Sn, Sd))
+#define VFMLAQD(Dd, Dn, Dm)	        EMIT(FMLA_vector(1, 0, 1, Dm, Dn, Dd))
+
 // DIV
 #define FDIV_vector(Q, sz, Rm, Rn, Rd)  ((Q)<<30 | 1<<29 | 0b01110<<24 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b11111<<11 | 1<<10 | (Rn)<<5 | (Rd))
 #define VFDIVS(Sd, Sn, Sm)          EMIT(FDIV_vector(0, 0, Sm, Sn, Sd))
@@ -962,6 +1129,16 @@
 #define FDIVS(Sd, Sn, Sm)           EMIT(FDIV_scalar(0b00, Sm, Sn, Sd))
 #define FDIVD(Dd, Dn, Dm)           EMIT(FDIV_scalar(0b01, Dm, Dn, Dd))
 
+#define FRECPE_vector(Q, sz, Rn, Rd)   ((Q)<<30 | 0<<29 | 0b01110<<24 | 1<<23 | (sz)<<22 | 0b10000<<17 | 0b11101<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define VFRECPES(Vd, Vn)           EMIT(FRECPE_vector(0, 0, Vn, Vd))
+#define VFRECPEQS(Vd, Vn)          EMIT(FRECPE_vector(1, 0, Vn, Vd))
+#define VFRECPEQD(Vd, Vn)          EMIT(FRECPE_vector(1, 0, Vn, Vd))
+
+#define FRECPS_vector(Q, sz, Rm, Rn, Rd)   ((Q)<<30 | 0<<29 | 0b01110<<24 | 0<<23 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b11111<<11 | 1<<10 | (Rn)<<5 | (Rd))
+#define VFRECPSS(Vd, Vn, Vm)       EMIT(FRECPS_vector(0, 0, Vm, Vn, Vd))
+#define VFRECPSQS(Vd, Vn, Vm)      EMIT(FRECPS_vector(1, 0, Vm, Vn, Vd))
+#define VFRECPSQD(Vd, Vn, Vm)      EMIT(FRECPS_vector(1, 0, Vm, Vn, Vd))
+
 // SQRT
 #define FSQRT_vector(Q, sz, Rn, Rd)     ((Q)<<30 | 1<<29 | 0b01110<<24 | 1<<23 | (sz)<<22 | 0b10000<<17 | 0b11111<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
 #define VFSQRTS(Sd, Sn)             EMIT(FSQRT_vector(0, 0, Sn, Sd))
@@ -972,6 +1149,16 @@
 #define FSQRTS(Sd, Sn)              EMIT(FSQRT_scalar(0b00, Sn, Sd))
 #define FSQRTD(Dd, Dn)              EMIT(FSQRT_scalar(0b01, Dn, Dd))
 
+#define FRSQRTE_vector(Q, sz, Rn, Rd)   ((Q)<<30 | 1<<29 | 0b01110<<24 | 1<<23 | (sz)<<22 | 0b10000<<17 | 0b11101<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define VFRSQRTES(Vd, Vn)           EMIT(FRSQRTE_vector(0, 0, Vn, Vd))
+#define VFRSQRTEQS(Vd, Vn)          EMIT(FRSQRTE_vector(1, 0, Vn, Vd))
+#define VFRSQRTEQD(Vd, Vn)          EMIT(FRSQRTE_vector(1, 0, Vn, Vd))
+
+#define FRSQRTS_vector(Q, sz, Rm, Rn, Rd)   ((Q)<<30 | 0<<29 | 0b01110<<24 | 1<<23 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b11111<<11 | 1<<10 | (Rn)<<5 | (Rd))
+#define VFRSQRTSS(Vd, Vn, Vm)       EMIT(FRSQRTS_vector(0, 0, Vm, Vn, Vd))
+#define VFRSQRTSQS(Vd, Vn, Vm)      EMIT(FRSQRTS_vector(1, 0, Vm, Vn, Vd))
+#define VFRSQRTSQD(Vd, Vn, Vm)      EMIT(FRSQRTS_vector(1, 0, Vm, Vn, Vd))
+
 // CMP
 #define FCMP_scalar(type, Rn, Rm, opc)  (0b11110<<24 | (type)<<22 | 1<<21 | (Rm)<<16 | 0b1000<<10 | (Rn)<<5 | (opc)<<3)
 #define FCMPS(Sn, Sm)               EMIT(FCMP_scalar(0b00, Sn, Sm, 0b00))
@@ -1128,6 +1315,12 @@
 #define FCVT_D_S(Dd, Sn)            EMIT(FCVT_precision(0b00, 0b01, Sn, Dd))
 #define FCVT_S_D(Sd, Dn)            EMIT(FCVT_precision(0b01, 0b00, Dn, Sd))
 
+#define FCVTN_vector(Q, sz, Rn, Rd)   ((Q)<<30 | 0<<29 | 0b01110<<24 | (sz)<<22 | 0b10000<<17 | 0b10110<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+// Convert Vn from 2*Double to lower Vd as 2*float and clears the upper half, use FPCR rounding
+#define FCVTN(Vd, Vn)               EMIT(FCVTN_vector(0, 1, Vn, Vd))
+// Convert Vn from 2*Double to higher Vd as 2*float, use FPCR rounding
+#define FCVTN2(Vd, Vn)              EMIT(FCVTN_vector(1, 1, Vn, Vd))
+
 #define FCVTXN_vector(Q, sz, Rn, Rd)   ((Q)<<30 | 1<<29 | 0b01110<<24 | (sz)<<22 | 0b10000<<17 | 0b10110<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
 // Convert Vn from 2*Double to lower Vd as 2*float and clears the upper half
 #define FCVTXN(Vd, Vn)              EMIT(FCVTXN_vector(0, 1, Vn, Vd))
@@ -1147,7 +1340,9 @@
 #define SCVTFDx(Dd, Xn)             EMIT(SCVTF_scalar(1, 0b01, 0b00, 0b010, Xn, Dd))
 
 #define SCVTF_vector_scalar(U, sz, Rn, Rd)    (1<<30 | (U)<<29 | 0b11110<<24 | (sz)<<22 | 0b10000<<17 | 0b11101<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+// Convert Vn from i32 to Vd float
 #define SCVTFSS(Vd, Vn)             EMIT(SCVTF_vector_scalar(0, 0, Vn, Vd))
+// Convert Vn from i64 to Vd double
 #define SCVTFDD(Vd, Vn)             EMIT(SCVTF_vector_scalar(0, 1, Vn, Vd))
 
 #define SCVTF_vector(Q, U, sz, Rn, Rd)      ((Q)<<30 | (U)<<29 | 0b01110<<24 | (sz)<<22 | 0b10000<<17 | 0b11101<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
@@ -1161,6 +1356,15 @@
 #define VFRINTIS(Vd,Vn)             EMIT(FRINT_vector(0, 1, 1, 0, 1, Vn, Vd))
 #define VFRINTISQ(Vd,Vn)            EMIT(FRINT_vector(1, 1, 1, 0, 1, Vn, Vd))
 #define VFRINTIDQ(Vd,Vn)            EMIT(FRINT_vector(1, 1, 1, 1, 1, Vn, Vd))
+// round with mode, mode is 0 = TieEven, 1=+inf, 2=-inf, 3=zero
+#define VFRINTRDQ(Vd,Vn, mode)      EMIT(FRINT_vector(1, 0, (mode)&1, 1, ((mode)>>1)&1, Vn, Vd))
+// round with mode, mode is 0 = TieEven, 1=+inf, 2=-inf, 3=zero
+#define VFRINTRSQ(Vd,Vn, mode)      EMIT(FRINT_vector(1, 0, (mode)&1, 0, ((mode)>>1)&1, Vn, Vd))
+
+#define FRINTI_scalar(type, Rn, Rd)  (0b11110<<24 | (type)<<22 | 1<<21 | 0b001<<18 | 0b111<<15 | 0b10000<<10 | (Rn)<<5 | (Rd))
+#define FRINTIS(Sd, Sn)             EMIT(FRINTI_scalar(0b00, Sn, Sd))
+#define FRINTID(Dd, Dn)             EMIT(FRINTI_scalar(0b01, Dn, Dd))
+
 
 #define FRINTxx_scalar(type, op, Rn, Rd)  (0b11110<<24 | (type)<<22 | 1<<21 | 0b0100<<17 | (op)<<15 | 0b10000<<10 | (Rn)<<5 | (Rd))
 #define FRINT32ZS(Sd, Sn)           EMIT(FRINTxx_scalar(0b00, 0b00, Sn, Sd))
@@ -1173,10 +1377,18 @@
 #define FRINT64XD(Dd, Dn)           EMIT(FRINTxx_scalar(0b01, 0b11, Dn, Dd))
 
 #define FRINT_scalar(type, rmode, Rn, Rd)   (0b11110<<24 | (type)<<22 | 1<<21 | 0b001<<18 | (rmode)<<15 | 0b10000<<10 | (Rn)<<5 | (Rd))
+// round toward 0 (truncate)
 #define FRINTZS(Sd, Sn)             EMIT(FRINT_scalar(0b00, 0b011, Sn, Sd))
+// round toward 0 (truncate)
 #define FRINTZD(Sd, Sn)             EMIT(FRINT_scalar(0b01, 0b011, Sn, Sd))
+// round with current FPCR mode
 #define FRINTXS(Sd, Sn)             EMIT(FRINT_scalar(0b00, 0b110, Sn, Sd))
+// round with current FPCR mode
 #define FRINTXD(Sd, Sn)             EMIT(FRINT_scalar(0b01, 0b110, Sn, Sd))
+// round with mode, mode is 0 = TieEven, 1=+inf, 2=-inf, 3=zero
+#define FRINTRRS(Sd, Sn, mode)      EMIT(FRINT_scalar(0b00, ((mode)&3), Sn, Sd))
+// round with mode, mode is 0 = TieEven, 1=+inf, 2=-inf, 3=zero
+#define FRINTRRD(Dd, Dn, mode)      EMIT(FRINT_scalar(0b01, ((mode)&3), Dn, Dd))
 
 // FMAX / FMIN
 #define FMINMAX_vector(Q, U, o1, sz, Rm, Rn, Rd)    ((Q)<<30 | (U)<<29 | 0b01110<<24 | (o1)<<23 | (sz)<<22 | 0b1<<21 | (Rm)<<16 | 0b11110<<11 | 1<<10 | (Rn)<<5 | (Rd))
@@ -1234,6 +1446,24 @@
 #define VUZP1Q_64(Rt, Rn, Rm)       EMIT(UZP_gen(1, 0b11, Rm, 0, Rn, Rt))
 #define VUZP2Q_64(Rt, Rn, Rm)       EMIT(UZP_gen(1, 0b11, Rm, 1, Rn, Rt))
 
+#define DUP_element(Q, imm5, Rn, Rd)    ((Q)<<30 | 0b01110000<<21 | (imm5)<<16 | 1<<10 | (Rn)<<5 | (Rd))
+#define VDUP_8(Vd, Vn, idx)         EMIT(DUP_element(0, ((idx)<<1|1), Vn, Vd))
+#define VDUPQ_8(Vd, Vn, idx)        EMIT(DUP_element(1, ((idx)<<1|1), Vn, Vd))
+#define VDUP_16(Vd, Vn, idx)        EMIT(DUP_element(0, ((idx)<<2|0b10), Vn, Vd))
+#define VDUPQ_16(Vd, Vn, idx)       EMIT(DUP_element(1, ((idx)<<2|0b10), Vn, Vd))
+#define VDUP_32(Vd, Vn, idx)        EMIT(DUP_element(0, ((idx)<<3|0b100), Vn, Vd))
+#define VDUPQ_32(Vd, Vn, idx)       EMIT(DUP_element(1, ((idx)<<3|0b100), Vn, Vd))
+#define VDUPQ_64(Vd, Vn, idx)       EMIT(DUP_element(1, ((idx)<<4|0b1000), Vn, Vd))
+
+#define DUP_general(Q, imm5, Rn, Rd)    ((Q)<<30 | 0b01110000<<21 | (imm5)<<16 | 0b11<<10 | (Rn)<<5 | (Rd))
+#define VDUPB(Vd, Wn)         EMIT(DUP_general(0, 0b1, Wn, Vd))
+#define VDUPQB(Vd, Wn)        EMIT(DUP_general(1, 0b1, Wn, Vd))
+#define VDUPH(Vd, Wn)        EMIT(DUP_general(0, 0b10, Wn, Vd))
+#define VDUPQH(Vd, Wn)       EMIT(DUP_general(1, 0b10, Wn, Vd))
+#define VDUPS(Vd, Wn)        EMIT(DUP_general(0, 0b100, Wn, Vd))
+#define VDUPQS(Vd, Wn)       EMIT(DUP_general(1, 0b100, Wn, Vd))
+#define VDUPQD(Vd, Xn)       EMIT(DUP_general(1, 0b1000, Xn, Vd))
+
 // TBL
 #define TBL_gen(Q, Rm, len, op, Rn, Rd) ((Q)<<30 | 0b001110<<24 | (Rm)<<16 | (len)<<13 | (op)<<12 | (Rn)<<5 | (Rd))
 //Use Rm[] to pick from Rn element and store in Rd. Out-of-range element gets 0
@@ -1246,13 +1476,13 @@
 //Use Rm[] to pick from Rn, Rn+1, Rn+2, Rn+3 element and store in Rd. Out-of-range element gets 0
 #define VTBLQ4_8(Rd, Rn, Rm)        EMIT(TBL_gen(1, Rm, 0b11, 0, Rn, Rd))
 //Use Rm[] to pick from Rn element and store in Rd. Out-of-range element stay untouched
-#define VTBXQ1_8(Rd, Rn, Rm)        EMIT(TBL_gen(1, Rm, 0b00, 0, Rn, Rd))
+#define VTBXQ1_8(Rd, Rn, Rm)        EMIT(TBL_gen(1, Rm, 0b00, 1, Rn, Rd))
 //Use Rm[] to pick from Rn, Rn+1 element and store in Rd. Out-of-range element stay untouched
-#define VTBXQ2_8(Rd, Rn, Rm)        EMIT(TBL_gen(1, Rm, 0b01, 0, Rn, Rd))
+#define VTBXQ2_8(Rd, Rn, Rm)        EMIT(TBL_gen(1, Rm, 0b01, 1, Rn, Rd))
 //Use Rm[] to pick from Rn, Rn+1, Rn+2 element and store in Rd. Out-of-range element stay untouched
-#define VTBXQ3_8(Rd, Rn, Rm)        EMIT(TBL_gen(1, Rm, 0b10, 0, Rn, Rd))
+#define VTBXQ3_8(Rd, Rn, Rm)        EMIT(TBL_gen(1, Rm, 0b10, 1, Rn, Rd))
 //Use Rm[] to pick from Rn, Rn+1, Rn+2, Rn+3 element and store in Rd. Out-of-range element stay untouched
-#define VTBXQ4_8(Rd, Rn, Rm)        EMIT(TBL_gen(1, Rm, 0b11, 0, Rn, Rd))
+#define VTBXQ4_8(Rd, Rn, Rm)        EMIT(TBL_gen(1, Rm, 0b11, 1, Rn, Rd))
 
 // TRN
 #define TRN_gen(Q, size, Rm, op, Rn, Rd)    ((Q)<<30 | 0b001110<<24 | (size)<<22 | (Rm)<<16 | (op)<<14 | 0b10<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
@@ -1342,27 +1572,66 @@
 #define VCMGTQ_16(Rd, Rn, Rm)       EMIT(CMG_vector(1, 0, 0b01, 0, Rm, Rn, Rd))
 #define VCMGTQ_32(Rd, Rn, Rm)       EMIT(CMG_vector(1, 0, 0b10, 0, Rm, Rn, Rd))
 #define VCMGTQ_64(Rd, Rn, Rm)       EMIT(CMG_vector(1, 0, 0b11, 0, Rm, Rn, Rd))
+#define VCMGT_8(Rd, Rn, Rm)         EMIT(CMG_vector(0, 0, 0b00, 0, Rm, Rn, Rd))
+#define VCMGT_16(Rd, Rn, Rm)        EMIT(CMG_vector(0, 0, 0b01, 0, Rm, Rn, Rd))
+#define VCMGT_32(Rd, Rn, Rm)        EMIT(CMG_vector(0, 0, 0b10, 0, Rm, Rn, Rd))
 // Unsigned Higher
 #define VCHIQQ_8(Rd, Rn, Rm)        EMIT(CMG_vector(1, 1, 0b00, 0, Rm, Rn, Rd))
 #define VCHIQQ_16(Rd, Rn, Rm)       EMIT(CMG_vector(1, 1, 0b01, 0, Rm, Rn, Rd))
 #define VCHIQQ_32(Rd, Rn, Rm)       EMIT(CMG_vector(1, 1, 0b10, 0, Rm, Rn, Rd))
 #define VCHIQQ_64(Rd, Rn, Rm)       EMIT(CMG_vector(1, 1, 0b11, 0, Rm, Rn, Rd))
 
+// Less Than 0
+#define CMLT_0_vector(Q, size, Rn, Rd)		((Q)<<30 | 0b01110<<24 | (size)<<22 | 0b10000<<17 | 0b01010<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define CMLT_0_8(Rd, Rn)		    EMIT(CMLT_0_vector(0, 0b00, Rn, Rd))
+#define CMLT_0_16(Rd, Rn)           EMIT(CMLT_0_vector(0, 0b01, Rn, Rd))
+#define CMLT_0_32(Rd, Rn)           EMIT(CMLT_0_vector(0, 0b10, Rn, Rd))
+#define CMLTQ_0_8(Rd, Rn)           EMIT(CMLT_0_vector(1, 0b00, Rn, Rd))
+#define CMLTQ_0_16(Rd, Rn)          EMIT(CMLT_0_vector(1, 0b01, Rn, Rd))
+#define CMLTQ_0_32(Rd, Rn)          EMIT(CMLT_0_vector(1, 0b10, Rn, Rd))
+#define CMLTQ_0_64(Rd, Rn)          EMIT(CMLT_0_vector(1, 0b11, Rn, Rd))
+// Equal 0
+#define CMEQ_0_vector(Q, size, Rn, Rd)          ((Q)<<30 | 0b01110<<24 | (size)<<22 | 0b10000<<17 | 0b0100<<13 | 1<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define CMEQ_0_8(Rd, Rn)            EMIT(CMEQ_0_vector(0, 0b00, Rn, Rd))
+#define CMEQ_0_16(Rd, Rn)           EMIT(CMEQ_0_vector(0, 0b01, Rn, Rd))
+#define CMEQ_0_32(Rd, Rn)           EMIT(CMEQ_0_vector(0, 0b10, Rn, Rd))
+#define CMEQQ_0_8(Rd, Rn)           EMIT(CMEQ_0_vector(1, 0b00, Rn, Rd))
+#define CMEQQ_0_16(Rd, Rn)          EMIT(CMEQ_0_vector(1, 0b01, Rn, Rd))
+#define CMEQQ_0_32(Rd, Rn)          EMIT(CMEQ_0_vector(1, 0b10, Rn, Rd))
+#define CMEQQ_0_64(Rd, Rn)          EMIT(CMEQ_0_vector(1, 0b11, Rn, Rd))
+
 // Vector Float CMP
 // EQual
 #define FCMP_vector(Q, U, E, sz, Rm, ac, Rn, Rd)    ((Q)<<30 | (U)<<29 | 0b01110<<24 | (E)<<23 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b1110<<12 | (ac)<<11 | 1<<10 | (Rn)<<5 | (Rd))
-#define FCMEQQD(Rd, Rn, Rm)          EMIT(FCMP_vector(1, 0, 0, 1, Rm, 0, Rn, Rd))
-#define FCMEQQS(Rd, Rn, Rm)          EMIT(FCMP_vector(1, 0, 0, 0, Rm, 0, Rn, Rd))
+#define VFCMEQQD(Rd, Rn, Rm)         EMIT(FCMP_vector(1, 0, 0, 1, Rm, 0, Rn, Rd))
+#define VFCMEQQS(Rd, Rn, Rm)         EMIT(FCMP_vector(1, 0, 0, 0, Rm, 0, Rn, Rd))
 // Greater or Equal
-#define FCMGEQD(Rd, Rn, Rm)          EMIT(FCMP_vector(1, 1, 0, 1, Rm, 0, Rn, Rd))
-#define FCMGEQS(Rd, Rn, Rm)          EMIT(FCMP_vector(1, 1, 0, 0, Rm, 0, Rn, Rd))
-#define FCMGEQD_ABS(Rd, Rn, Rm)      EMIT(FCMP_vector(1, 1, 0, 1, Rm, 1, Rn, Rd))
-#define FCMGEQS_ABS(Rd, Rn, Rm)      EMIT(FCMP_vector(1, 1, 0, 0, Rm, 1, Rn, Rd))
+#define VFCMGEQD(Rd, Rn, Rm)         EMIT(FCMP_vector(1, 1, 0, 1, Rm, 0, Rn, Rd))
+#define VFCMGEQS(Rd, Rn, Rm)         EMIT(FCMP_vector(1, 1, 0, 0, Rm, 0, Rn, Rd))
+#define VFCMGEQD_ABS(Rd, Rn, Rm)     EMIT(FCMP_vector(1, 1, 0, 1, Rm, 1, Rn, Rd))
+#define VFCMGEQS_ABS(Rd, Rn, Rm)     EMIT(FCMP_vector(1, 1, 0, 0, Rm, 1, Rn, Rd))
 // Greater Than
-#define FCMGTQD(Rd, Rn, Rm)          EMIT(FCMP_vector(1, 1, 1, 1, Rm, 0, Rn, Rd))
-#define FCMGTQS(Rd, Rn, Rm)          EMIT(FCMP_vector(1, 1, 1, 0, Rm, 0, Rn, Rd))
-#define FCMGTQD_ABS(Rd, Rn, Rm)      EMIT(FCMP_vector(1, 1, 1, 1, Rm, 1, Rn, Rd))
-#define FCMGTQS_ABS(Rd, Rn, Rm)      EMIT(FCMP_vector(1, 1, 1, 0, Rm, 1, Rn, Rd))
+#define VFCMGTQD(Rd, Rn, Rm)         EMIT(FCMP_vector(1, 1, 1, 1, Rm, 0, Rn, Rd))
+#define VFCMGTQS(Rd, Rn, Rm)         EMIT(FCMP_vector(1, 1, 1, 0, Rm, 0, Rn, Rd))
+#define VFCMGTQD_ABS(Rd, Rn, Rm)     EMIT(FCMP_vector(1, 1, 1, 1, Rm, 1, Rn, Rd))
+#define VFCMGTQS_ABS(Rd, Rn, Rm)     EMIT(FCMP_vector(1, 1, 1, 0, Rm, 1, Rn, Rd))
+
+// Scalar Float CMP to 0
+#define FCMP_0_scalar(U, sz, op, Rn, Rd) (0b01<<30 | (U)<<29| 0b11110<<24 | 1<<23 | (sz)<<22 | 0b10000<<17 | 0b011<<14 | (op)<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+// Less or equal to 0
+#define FCMLES_0(Rd, Rn)             EMIT(FCMP_0_scalar(1, 0, 0b01, (Rn), (Rd)))
+#define FCMLED_0(Rd, Rn)             EMIT(FCMP_0_scalar(1, 1, 0b01, (Rn), (Rd)))
+// Greater than 0
+#define FCMGTS_0(Rd, Rn)             EMIT(FCMP_0_scalar(0, 0, 0b00, (Rn), (Rd)))
+#define FCMGTD_0(Rd, Rn)             EMIT(FCMP_0_scalar(0, 1, 0b00, (Rn), (Rd)))
+// Less than 0
+#define FCMLTS_0(Rd, Rn)             EMIT(FCMP_0_scalar(0, 0, 0b10, (Rn), (Rd)))
+#define FCMLTD_0(Rd, Rn)             EMIT(FCMP_0_scalar(0, 1, 0b10, (Rn), (Rd)))
+
+// Scalar Float CMP
+#define FCMP_op_scalar(U, E, sz, Rm, ac, Rn, Rd)    (0b01<<30 | (U)<<29 | 0b11110<<24 | (E)<<23 | (sz)<<22 | 1<<21 | (Rm)<<16 | 0b1110<<12 | (ac)<<11 | 1<<10 | (Rn)<<5 | (Rd))
+#define FCMEQS(Rd, Rn, Rm)          EMIT(FCMP_op_scalar(0, 0, 0, (Rm), 0, (Rn), (Rd)))
+#define FCMEQD(Rd, Rn, Rm)          EMIT(FCMP_op_scalar(0, 0, 1, (Rm), 0, (Rn), (Rd)))
 
 // UMULL / SMULL
 #define MULL_vector(Q, U, size, Rm, Rn, Rd) ((Q)<<30 | (U)<<29 | 0b01110<<24 | (size)<<22 | 1<<21 | (Rm)<<16 | 0b1100<<12 |(Rn)<<5 |(Rd))
@@ -1480,10 +1749,17 @@
 #define UADDLV_16(Rd, Rn)           EMIT(ADDLV_vector(0, 1, 0b01, Rn, Rd))
 #define UADDLV_32(Rd, Rn)           EMIT(ADDLV_vector(0, 1, 0b10, Rn, Rd))
 
+// Population Count per byte
+#define CNT_vector(Q, size, Rn, Rd)     ((Q)<<30 | 0b01110<<24 | (size)<<22 | 0b10000<<17 | 0b00101<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define CNT_8(Rd, Rn)               EMIT(CNT_vector(0, 0b00, Rn, Rd))
+#define CNTQ_8(Rd, Rn)              EMIT(CNT_vector(1, 0b00, Rn, Rd))
+
 // MOV Immediate
 #define MOVI_vector(Q, op, abc, cmode, defgh, Rd)   ((Q)<<30 | (op)<<29 | 0b0111100000<<19 | (abc)<<16 | (cmode)<<12 | 1<<10 | (defgh)<<5 | (Rd))
 #define MOVIQ_8(Rd, imm8)           EMIT(MOVI_vector(1, 0, (((imm8)>>5)&0b111), 0b1110, ((imm8)&0b11111), Rd))
 #define MOVI_8(Rd, imm8)            EMIT(MOVI_vector(0, 0, (((imm8)>>5)&0b111), 0b1110, ((imm8)&0b11111), Rd))
+#define MOVI_16(Rd, imm8)           EMIT(MOVI_vector(0, 0, (((imm8)>>5)&0b111), 0b1000, ((imm8)&0b11111), Rd))
+#define MOVI_32(Rd, imm8)           EMIT(MOVI_vector(0, 0, (((imm8)>>5)&0b111), 0b0000, ((imm8)&0b11111), Rd))
 
 // SHLL and eXtend Long
 #define SHLL_vector(Q, U, immh, immb, Rn, Rd)  ((Q)<<30 | (U)<<29 | 0b011110<<23 | (immh)<<19 | (immb)<<16 | 0b10100<<11 | 1<<10 | (Rn)<<5 | (Rd))
@@ -1553,35 +1829,35 @@
 #define SMAX_8(Vd, Vn, Vm)          EMIT(MINMAX_vector(0, 0, 0b00, Vm, 0, Vn, Vd))
 #define SMAX_16(Vd, Vn, Vm)         EMIT(MINMAX_vector(0, 0, 0b01, Vm, 0, Vn, Vd))
 #define SMAX_32(Vd, Vn, Vm)         EMIT(MINMAX_vector(0, 0, 0b10, Vm, 0, Vn, Vd))
-#define SMAX_64(Vd, Vn, Vm)         EMIT(MINMAX_vector(0, 0, 0b11, Vm, 0, Vn, Vd))
+//#define SMAX_64(Vd, Vn, Vm)         EMIT(MINMAX_vector(0, 0, 0b11, Vm, 0, Vn, Vd))
 #define UMAX_8(Vd, Vn, Vm)          EMIT(MINMAX_vector(0, 1, 0b00, Vm, 0, Vn, Vd))
 #define UMAX_16(Vd, Vn, Vm)         EMIT(MINMAX_vector(0, 1, 0b01, Vm, 0, Vn, Vd))
 #define UMAX_32(Vd, Vn, Vm)         EMIT(MINMAX_vector(0, 1, 0b10, Vm, 0, Vn, Vd))
-#define UMAX_64(Vd, Vn, Vm)         EMIT(MINMAX_vector(0, 1, 0b11, Vm, 0, Vn, Vd))
+//#define UMAX_64(Vd, Vn, Vm)         EMIT(MINMAX_vector(0, 1, 0b11, Vm, 0, Vn, Vd))
 #define SMIN_8(Vd, Vn, Vm)          EMIT(MINMAX_vector(0, 0, 0b00, Vm, 1, Vn, Vd))
 #define SMIN_16(Vd, Vn, Vm)         EMIT(MINMAX_vector(0, 0, 0b01, Vm, 1, Vn, Vd))
 #define SMIN_32(Vd, Vn, Vm)         EMIT(MINMAX_vector(0, 0, 0b10, Vm, 1, Vn, Vd))
-#define SMIN_64(Vd, Vn, Vm)         EMIT(MINMAX_vector(0, 0, 0b11, Vm, 1, Vn, Vd))
+//#define SMIN_64(Vd, Vn, Vm)         EMIT(MINMAX_vector(0, 0, 0b11, Vm, 1, Vn, Vd))
 #define UMIN_8(Vd, Vn, Vm)          EMIT(MINMAX_vector(0, 1, 0b00, Vm, 1, Vn, Vd))
 #define UMIN_16(Vd, Vn, Vm)         EMIT(MINMAX_vector(0, 1, 0b01, Vm, 1, Vn, Vd))
 #define UMIN_32(Vd, Vn, Vm)         EMIT(MINMAX_vector(0, 1, 0b10, Vm, 1, Vn, Vd))
-#define UMIN_64(Vd, Vn, Vm)         EMIT(MINMAX_vector(0, 1, 0b11, Vm, 1, Vn, Vd))
+//#define UMIN_64(Vd, Vn, Vm)         EMIT(MINMAX_vector(0, 1, 0b11, Vm, 1, Vn, Vd))
 #define SMAXQ_8(Vd, Vn, Vm)         EMIT(MINMAX_vector(1, 0, 0b00, Vm, 0, Vn, Vd))
 #define SMAXQ_16(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 0, 0b01, Vm, 0, Vn, Vd))
 #define SMAXQ_32(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 0, 0b10, Vm, 0, Vn, Vd))
-#define SMAXQ_64(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 0, 0b11, Vm, 0, Vn, Vd))
+//#define SMAXQ_64(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 0, 0b11, Vm, 0, Vn, Vd))
 #define UMAXQ_8(Vd, Vn, Vm)         EMIT(MINMAX_vector(1, 1, 0b00, Vm, 0, Vn, Vd))
 #define UMAXQ_16(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 1, 0b01, Vm, 0, Vn, Vd))
 #define UMAXQ_32(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 1, 0b10, Vm, 0, Vn, Vd))
-#define UMAXQ_64(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 1, 0b11, Vm, 0, Vn, Vd))
+//#define UMAXQ_64(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 1, 0b11, Vm, 0, Vn, Vd))
 #define SMINQ_8(Vd, Vn, Vm)         EMIT(MINMAX_vector(1, 0, 0b00, Vm, 1, Vn, Vd))
 #define SMINQ_16(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 0, 0b01, Vm, 1, Vn, Vd))
 #define SMINQ_32(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 0, 0b10, Vm, 1, Vn, Vd))
-#define SMINQ_64(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 0, 0b11, Vm, 1, Vn, Vd))
+//#define SMINQ_64(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 0, 0b11, Vm, 1, Vn, Vd))
 #define UMINQ_8(Vd, Vn, Vm)         EMIT(MINMAX_vector(1, 1, 0b00, Vm, 1, Vn, Vd))
 #define UMINQ_16(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 1, 0b01, Vm, 1, Vn, Vd))
 #define UMINQ_32(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 1, 0b10, Vm, 1, Vn, Vd))
-#define UMINQ_64(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 1, 0b11, Vm, 1, Vn, Vd))
+//#define UMINQ_64(Vd, Vn, Vm)        EMIT(MINMAX_vector(1, 1, 0b11, Vm, 1, Vn, Vd))
 
 // HADD vector
 #define HADD_vector(Q, U, size, Rm, Rn, Rd)     ((Q)<<30 | (U)<<29 | 0b01110<<24 | (size)<<22 | 1<<21 | (Rm)<<16 | 1<<10 | (Rn)<<5 | (Rd))
@@ -1627,4 +1903,20 @@
 #define SQDMULHQ_16(Vd, Vn, Vm)     EMIT(QDMULH_vector(1, 0, 0b01, Vm, Vn, Vd))
 #define SQDMULHQ_32(Vd, Vn, Vm)     EMIT(QDMULH_vector(1, 0, 0b10, Vm, Vn, Vd))
 
+// AES extension
+#define AES_gen(D, Rn, Rd)      (0b01001110<<24 | 0b00<<22 | 0b10100<<17 | 0b0010<<13 | (D)<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define AESD(Vd, Vn)    EMIT(AES_gen(1, Vn, Vd))
+#define AESE(Vd, Vn)    EMIT(AES_gen(0, Vn, Vd))
+
+#define AESMC_gen(D, Rn, Rd)    (0b01001110<<24 | 0b00<<22 | 0b10100<<17 | 0b0011<<13 | (D)<<12 | 0b10<<10 | (Rn)<<5 | (Rd))
+#define AESIMC(Vd, Vn)  EMIT(AESMC_gen(1, Vn, Vd))
+#define AESMC(Vd, Vn)   EMIT(AESMC_gen(0, Vn, Vd))
+
+// PMULL extension is PMULL_128
+#define PMULL_gen(Q, size, Rm, Rn, Rd)  (0<<31 | (Q)<<30 | 0b001110<<24 | (size)<<22 | 1<<21 | (Rm)<<16 | 0b1110<<12 | (Rn)<<5 | (Rd))
+#define PMULL(Rd, Rn, Rm)   EMIT(PMULL_gen(0, 0b00, Rm, Rn, Rd))
+#define PMULL2(Rd, Rn, Rm)  EMIT(PMULL_gen(1, 0b00, Rm, Rn, Rd))
+#define PMULL_128(Rd, Rn, Rm)   EMIT(PMULL_gen(0, 0b11, Rm, Rn, Rd))
+#define PMULL2_128(Rd, Rn, Rm)  EMIT(PMULL_gen(1, 0b11, Rm, Rn, Rd))
+
 #endif  //__ARM64_EMITTER_H__

src/dynarec/arm64/arm64_epilog.S

@@ -19,18 +19,19 @@ arm64_epilog:
     stp     x24, x25, [x0, (8 * 14)]
     stp     x26, x27, [x0, (8 * 16)] // put back reg value in emu, including EIP (so x27 must be EIP now)
     //restore all used register
+    add     sp, x28, 0
     //vpop     {d8-d15}
     ldp     x19, x20, [sp, (8 * 0)]
     ldp     x21, x22, [sp, (8 * 2)]
     ldp     x23, x24, [sp, (8 * 4)]
     ldp     x25, x26, [sp, (8 * 6)]
-    ldr     x27, [sp, (8 * 8)]
+    ldp     x27, x28, [sp, (8 * 8)]
     ldp     d8, d9,   [sp, (8 *10)]
     ldp     d10, d11, [sp, (8 *12)]
     ldp     d12, d13, [sp, (8 *14)]
     ldp     d14, d15, [sp, (8 *16)]
     add     sp,  sp, (8 * 18)
-    ldp     lr, fp, [sp], 16  // saved lr
+    ldp     x30, x29, [sp], 16  // saved lr
     //end, return...
     ret
 
@@ -38,17 +39,18 @@ arm64_epilog:
 .global arm64_epilog_fast
 arm64_epilog_fast:
     //restore all used register
+    add     sp, x28, 0
     //vpop     {d8-d15}
     ldp     x19, x20, [sp, (8 * 0)]
     ldp     x21, x22, [sp, (8 * 2)]
     ldp     x23, x24, [sp, (8 * 4)]
     ldp     x25, x26, [sp, (8 * 6)]
-    ldr     x27, [sp, (8 * 8)]
+    ldp     x27, x28, [sp, (8 * 8)]
     ldp     d8, d9,   [sp, (8 *10)]
     ldp     d10, d11, [sp, (8 *12)]
     ldp     d12, d13, [sp, (8 *14)]
     ldp     d14, d15, [sp, (8 *16)]
     add     sp,  sp, (8 * 18)
-    ldp     lr, fp, [sp], 16  // saved lr
+    ldp     x30, x29, [sp], 16  // saved lr
     //end, return...
     ret

src/dynarec/arm64/arm64_lock.S

@@ -0,0 +1,256 @@
+//arm lock helper
+//there is 2 part: read and write
+// write return 0 on success, 1 on fail (value has been changed)
+
+.text
+.align 4
+
+.global arm64_lock_read_b
+.global arm64_lock_write_b
+.global arm64_lock_read_h
+.global arm64_lock_write_h
+.global arm64_lock_read_d
+.global arm64_lock_write_d
+.global arm64_lock_read_dd
+.global arm64_lock_write_dd
+.global arm64_lock_read_dq
+.global arm64_lock_write_dq
+.global arm64_lock_xchg_dd
+.global arm64_lock_xchg_d
+.global arm64_lock_xchg_h
+.global arm64_lock_xchg_b
+.global arm64_lock_storeifnull
+.global arm64_lock_storeifnull_d
+.global arm64_lock_storeifref
+.global arm64_lock_storeifref_d
+.global arm64_lock_storeifref2_d
+.global arm64_lock_decifnot0b
+.global arm64_lock_storeb
+.global arm64_lock_incif0
+.global arm64_lock_decifnot0
+.global arm64_lock_store
+
+arm64_lock_read_b:
+    dmb     ish
+    // address is x0, return is x0
+    ldaxrb  w0, [x0]
+    ret
+
+arm64_lock_write_b:
+    // address is x0, value is x1, return is x0
+    mov     x2, x0
+    stlxrb  w0, w1, [x2]
+    dmb     ish
+    ret
+
+arm64_lock_read_h:
+    dmb     ish
+    // address is x0, return is x0
+    ldaxrh  w0, [x0]
+    ret
+
+arm64_lock_write_h:
+    // address is x0, value is x1, return is x0
+    mov     x2, x0
+    stlxrh  w0, w1, [x2]
+    dmb     ish
+    ret
+
+arm64_lock_read_d:
+    dmb     ish
+    // address is x0, return is x0
+    ldaxr    w0, [x0]
+    ret
+
+arm64_lock_write_d:
+    // address is x0, value is w1, return is x0
+    mov     x2, x0
+    stlxr   w0, w1, [x2]
+    dmb     ish
+    ret
+
+arm64_lock_read_dd:
+    dmb     ish
+    // address is x0, return is x0
+    ldaxr   x0, [x0]
+    ret
+
+arm64_lock_write_dd:
+    // address is x0, value is x1, return is x0
+    mov     x2, x0
+    stlxr   w0, x1, [x2]
+    dmb     ish
+    ret
+
+arm64_lock_read_dq:
+    dmb     ish
+    // address is r2, return is r0, r1
+    ldaxp   x4, x3, [x2]
+    str     x4, [x0]
+    str     x3, [x1]
+    ret
+
+arm64_lock_write_dq:
+    // address is r2, value is r0, r1, return is r0
+    // r0 needs to be aligned
+    stlxp   w3, x0, x1, [x2]
+    mov     w0, w3
+    dmb     ish
+    ret
+
+
+arm64_lock_xchg_dd:
+    dmb     ish
+arm64_lock_xchg_dd_0:
+    // address is x0, value is x1, return old value in x0
+    ldaxr   x2, [x0]
+    stlxr   w3, x1, [x0]
+    cbnz    w3, arm64_lock_xchg_dd_0
+    mov     x0, x2
+    ret
+
+arm64_lock_xchg_d:
+    dmb     ish
+arm64_lock_xchg_d_0:
+    // address is x0, value is x1, return old value in x0
+    ldaxr   w2, [x0]
+    stlxr   w3, w1, [x0]
+    cbnz    w3, arm64_lock_xchg_d_0
+    mov     w0, w2
+    ret
+
+arm64_lock_xchg_h:
+    dmb     ish
+arm64_lock_xchg_h_0:
+    // address is x0, value is x1, return old value in x0
+    ldaxrh  w2, [x0]
+    stlxrh  w3, w1, [x0]
+    cbnz    w3, arm64_lock_xchg_h_0
+    mov     w0, w2
+    ret
+
+arm64_lock_xchg_b:
+    dmb     ish
+arm64_lock_xchg_b_0:
+    // address is x0, value is x1, return old value in x0
+    ldaxrb   w2, [x0]
+    stlxrb   w3, w1, [x0]
+    cbnz    w3, arm64_lock_xchg_b_0
+    mov     w0, w2
+    ret
+
+arm64_lock_storeifnull:
+    dmb     ish
+1:
+    // address is x0, value is x1, x1 store to x0 only if [x0] is 0. return old [x0] value
+    ldaxr   x2, [x0]
+    cbnz    x2, 2f
+    stlxr   w3, x1, [x0]
+    cbnz    w3, 1b
+2:
+    mov     x0, x2
+    ret
+
+arm64_lock_storeifnull_d:
+    dmb     ish
+1:
+    // address is x0, value is w1, w1 store to x0 only if [x0] is 0. return old [x0] value
+    ldaxr   w2, [x0]
+    cbnz    w2, 2f
+    stlxr   w3, w1, [x0]
+    cbnz    w3, 1b
+2:
+    dmb     ish
+    mov     w0, w2
+    ret
+
+arm64_lock_storeifref:
+    dmb     ish
+1:
+    // address is x0, value is x1, x1 store to x0 only if [x0] is x2. return new [x0] value (so x1 or old value)
+    ldaxr   x3, [x0]
+    cmp     x2, x3
+    bne     2f
+    stlxr   w4, x1, [x0]
+    cbnz    w4, 1b
+    mov     x0, x1
+    ret
+2:
+    mov     x0, x3
+    ret
+
+arm64_lock_storeifref_d:
+    dmb     ish
+1:
+    // address is x0, value is w1, w1 store to x0 only if [x0] is w2. return new [x0] value (so x1 or old value)
+    ldaxr   w3, [x0]
+    cmp     w2, w3
+    bne     2f
+    stlxr   w4, w1, [x0]
+    cbnz    w4, 1b
+    mov     w0, w1
+    ret
+2:
+    mov     w0, w3
+    ret
+
+arm64_lock_storeifref2_d:
+    dmb     ish
+1:
+    // address is x0, value is w1, w1 store to x0 only if [x0] is w2. return old [x0] value
+    ldaxr   w3, [x0]
+    cmp     w2, w3
+    bne     2f
+    stlxr   w4, w1, [x0]
+    cbnz    w4, 1b
+2:
+    mov     w0, w3
+    ret
+
+arm64_lock_decifnot0b:
+    dmb     ish
+1:
+    ldaxrb  w1, [x0]
+    cmp     w1, #0
+    beq     2f
+    sub     w1, w1, #1
+    stlxrb  w2, w1, [x0]
+    cbnz    w2, 1b
+2:
+    ret
+
+arm64_lock_storeb:
+    strb    w1, [x0]
+    dmb     ish
+    ret
+
+arm64_lock_decifnot0:
+    dmb     ish
+1:
+    ldaxr   w1, [x0]
+    cmp     w1, #0
+    beq     2f
+    sub     w3, w1, #1
+    stlxr   w2, w3, [x0]
+    cbnz    w2, 1b
+2:
+    mov     w0, w1
+    ret
+
+arm64_lock_incif0:
+    dmb     ish
+1:
+    ldaxr   w1, [x0]
+    cmp     w1, #0
+    bne     2f
+    add     w3, w1, #1
+    stlxr   w2, w3, [x0]
+    cbnz    w2, 1b
+2:
+    mov     w0, w1
+    ret
+
+arm64_lock_store:
+    str     w1, [x0]
+    dmb     ish
+    ret

src/dynarec/arm64/arm64_lock.h

@@ -0,0 +1,72 @@
+#ifndef __ARM64_LOCK__H__
+#define __ARM64_LOCK__H__
+#include <stdint.h>
+
+// LDAXRB of ADDR
+extern uint8_t arm64_lock_read_b(void* addr);
+// STLXRB of ADDR, return 0 if ok, 1 if not
+extern int arm64_lock_write_b(void* addr, uint8_t val);
+
+// LDAXRH of ADDR
+extern uint16_t arm64_lock_read_h(void* addr);
+// STLXRH of ADDR, return 0 if ok, 1 if not
+extern int arm64_lock_write_h(void* addr, uint16_t val);
+
+// LDAXR of ADDR
+extern uint32_t arm64_lock_read_d(void* addr);
+// STLXR of ADDR, return 0 if ok, 1 if not
+extern int arm64_lock_write_d(void* addr, uint32_t val);
+
+// LDAXR of ADDR
+extern uint64_t arm64_lock_read_dd(void* addr);
+// STLXR of ADDR, return 0 if ok, 1 if not
+extern int arm64_lock_write_dd(void* addr, uint64_t val);
+
+// LDAXRD of ADDR
+extern void arm64_lock_read_dq(uint64_t * a, uint64_t* b, void* addr);
+// STLXRD of ADDR, return 0 if ok, 1 if not
+extern int arm64_lock_write_dq(uint64_t a, uint64_t b, void* addr);
+
+// Atomically exchange value at [p] with val, return old p
+extern uintptr_t arm64_lock_xchg_dd(void* p, uintptr_t val);
+
+// Atomically exchange value at [p] with val, return old p
+extern uint32_t arm64_lock_xchg_d(void* p, uint32_t val);
+
+// Atomically exchange value at [p] with val, return old p
+extern uint32_t arm64_lock_xchg_h(void* p, uint32_t val);
+
+// Atomically exchange value at [p] with val, return old p
+extern uint32_t arm64_lock_xchg_b(void* p, uint32_t val);
+
+// Atomically store value to [p] only if [p] is NULL. Return old [p] value
+extern uint32_t arm64_lock_storeifnull_d(void*p, uint32_t val);
+
+// Atomically store value to [p] only if [p] is NULL. Return old [p] value
+extern void* arm64_lock_storeifnull(void*p, void* val);
+
+// Atomically store value to [p] only if [p] is ref. Return new [p] value (so val or old)
+extern void* arm64_lock_storeifref(void*p, void* val, void* ref);
+
+// Atomically store value to [p] only if [p] is ref. Return new [p] value (so val or old)
+extern uint32_t arm64_lock_storeifref_d(void*p, uint32_t val, uint32_t ref);
+
+// Atomically store value to [p] only if [p] is ref. Return new [p] value (so val or old)
+extern uint32_t arm64_lock_storeifref2_d(void*p, uint32_t val, uint32_t ref);
+
+// decrement atomically the byte at [p] (but only if p not 0)
+extern void arm64_lock_decifnot0b(void*p);
+
+// atomic store (with memory barrier)
+extern void arm64_lock_storeb(void*p, uint8_t b);
+
+// increment atomically the int at [p] only if it was 0. Return the old value of [p]
+extern int arm64_lock_incif0(void*p);
+
+// decrement atomically the int at [p] (but only if p not 0)
+extern int arm64_lock_decifnot0(void*p);
+
+// atomic store (with memory barrier)
+extern void arm64_lock_store(void*p, uint32_t v);
+
+#endif  //__ARM64_LOCK__H__

src/dynarec/arm64/arm64_next.S

@@ -9,6 +9,8 @@
 .extern LinkNext
 
 .global arm64_next
+
+    .8byte  0   // NULL pointer before arm64_next, for getDB
 arm64_next:
     // emu is r0
     // IP address is r1
@@ -18,8 +20,10 @@ arm64_next:
     stp     x12, x13, [sp, (8 *  4)]
     stp     x14, x15, [sp, (8 *  6)]
     stp     x16, x17, [sp, (8 *  8)]
-    str     x18, [sp, (8 * 10)]
-    mov     x2, lr      // "from" is in lr, so put in x2
+    stp     x18, x27, [sp, (8 * 10)]    // also save x27(rip) to allow change in LinkNext
+
+    mov     x2, x30      // "from" is in lr, so put in x2
+    add     x3, sp, 8*11    // x3 is address to change rip
     // call the function
     bl      LinkNext
     // preserve return value
@@ -30,7 +34,7 @@ arm64_next:
     ldp     x12, x13, [sp, (8 *  4)]
     ldp     x14, x15, [sp, (8 *  6)]
     ldp     x16, x17, [sp, (8 *  8)]
-    ldr     x18, [sp, (8 * 10)]
+    ldp     x18, x27, [sp, (8 * 10)]
     add     sp,  sp, (8 * 12)
     // return offset is jump address
     br      x3

src/dynarec/arm64/arm64_printer.c

@@ -25,7 +25,7 @@ typedef struct arm64_print_s {
 
 uint64_t DecodeBitMasks(int N, int imms, int immr)
 {
-    int len = 31-__builtin_clz(N<<6 | ((~imms)&0b111111));
+    int len = 31-__builtin_clz((N<<6) | ((~imms)&0b111111));
     if(len<1) return 0;
     int levels = (1<<len) - 1;
     int s = imms & levels;
@@ -160,13 +160,60 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
     if(isMask(opcode, "1x111000010iiiiiiiii01nnnnnttttt", &a)) {
         int size = (opcode>>30)&3;
         int offset = signExtend(imm, 9);
-        snprintf(buff, sizeof(buff), "LDR %s, [%s], %s0x%x", (size==0b10)?Wt[Rt]:Xt[Rt], XtSp[Rn], (offset<0)?"-":"", abs(offset));
+        snprintf(buff, sizeof(buff), "LDUR %s, [%s], %s0x%x", (size==0b10)?Wt[Rt]:Xt[Rt], XtSp[Rn], (offset<0)?"-":"", abs(offset));
         return buff;
     }
     if(isMask(opcode, "1x111000010iiiiiiiii11nnnnnttttt", &a)) {
         int size = (opcode>>30)&3;
         int offset = signExtend(imm, 9);
-        snprintf(buff, sizeof(buff), "LDR %s, [%s, %s0x%x]!", (size==0b10)?Wt[Rt]:Xt[Rt], XtSp[Rn], (offset<0)?"-":"", abs(offset));
+        snprintf(buff, sizeof(buff), "LDUR %s, [%s, %s0x%x]!", (size==0b10)?Wt[Rt]:Xt[Rt], XtSp[Rn], (offset<0)?"-":"", abs(offset));
+        return buff;
+    }
+    if(isMask(opcode, "1x111000010iiiiiiiii00nnnnnttttt", &a)) {
+        int size = (opcode>>30)&3;
+        int offset = signExtend(imm, 9);
+        snprintf(buff, sizeof(buff), "LDUR %s, [%s, %s0x%x]", (size==0b10)?Wt[Rt]:Xt[Rt], XtSp[Rn], (offset<0)?"-":"", abs(offset));
+        return buff;
+    }
+    if(isMask(opcode, "00111000010iiiiiiiii00nnnnnttttt", &a)) {
+        int offset = signExtend(imm, 9);
+        snprintf(buff, sizeof(buff), "LDURB %s, [%s, %s0x%x]", Wt[Rt], XtSp[Rn], (offset<0)?"-":"", abs(offset));
+        return buff;
+    }
+    if(isMask(opcode, "01111000010iiiiiiiii00nnnnnttttt", &a)) {
+        int offset = signExtend(imm, 9);
+        snprintf(buff, sizeof(buff), "LDRUH %s, [%s, %s0x%x]", Wt[Rt], XtSp[Rn], (offset<0)?"-":"", abs(offset));
+        return buff;
+    }
+    if(isMask(opcode, "001110001x0iiiiiiiii00nnnnnttttt", &a)) {
+        int offset = signExtend(imm, 9);
+        snprintf(buff, sizeof(buff), "LDRUSB %s, [%s, %s0x%x]", a.x?Xt[Rt]:Wt[Rt], XtSp[Rn], (offset<0)?"-":"", abs(offset));
+        return buff;
+    }
+    if(isMask(opcode, "011110001x0iiiiiiiii00nnnnnttttt", &a)) {
+        int offset = signExtend(imm, 9);
+        snprintf(buff, sizeof(buff), "LDRUSH %s, [%s, %s0x%x]", a.x?Xt[Rt]:Wt[Rt], XtSp[Rn], (offset<0)?"-":"", abs(offset));
+        return buff;
+    }
+    if(isMask(opcode, "10111000100iiiiiiiii00nnnnnttttt", &a)) {
+        int offset = signExtend(imm, 9);
+        snprintf(buff, sizeof(buff), "LDRUSW %s, [%s, %s0x%x]", Xt[Rt], XtSp[Rn], (offset<0)?"-":"", abs(offset));
+        return buff;
+    }
+    if(isMask(opcode, "1x111000000iiiiiiiii00nnnnnttttt", &a)) {
+        int size = (opcode>>30)&3;
+        int offset = signExtend(imm, 9);
+        snprintf(buff, sizeof(buff), "STUR %s, [%s, %s0x%x]", (size==0b10)?Wt[Rt]:Xt[Rt], XtSp[Rn], (offset<0)?"-":"", abs(offset));
+        return buff;
+    }
+    if(isMask(opcode, "00111000000iiiiiiiii00nnnnnttttt", &a)) {
+        int offset = signExtend(imm, 9);
+        snprintf(buff, sizeof(buff), "STURB %s, [%s, %s0x%x]", Wt[Rt], XtSp[Rn], (offset<0)?"-":"", abs(offset));
+        return buff;
+    }
+    if(isMask(opcode, "01111000000iiiiiiiii00nnnnnttttt", &a)) {
+        int offset = signExtend(imm, 9);
+        snprintf(buff, sizeof(buff), "STRUH %s, [%s, %s0x%x]", Wt[Rt], XtSp[Rn], (offset<0)?"-":"", abs(offset));
         return buff;
     }
     if(isMask(opcode, "1x11100101iiiiiiiiiiiinnnnnttttt", &a)) {
@@ -236,6 +283,15 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
             snprintf(buff, sizeof(buff), "STR %s, [%s, %s, %s %d]", (size==2)?Wt[Rt]:Xt[Rt], XtSp[Rn], ((option&1)==0)?Wt[Rm]:Xt[Rm], extend[option], amount);
         return buff;
     }
+    if(isMask(opcode, "00111000001mmmmmoooS10nnnnnttttt", &a)) {
+        const char* extend[] = {"?0", "?1", "UXTW", "LSL", "?4", "?5", "SXTW", "SXTX"};
+        int amount = a.S;
+        if(option==3 && !amount)
+            snprintf(buff, sizeof(buff), "STRB %s, [%s, %s]", Wt[Rt], XtSp[Rn], ((option&1)==0)?Wt[Rm]:Xt[Rm]);
+        else
+            snprintf(buff, sizeof(buff), "STRB %s, [%s, %s, %s %d]", Wt[Rt], XtSp[Rn], ((option&1)==0)?Wt[Rm]:Xt[Rm], extend[option], amount);
+        return buff;
+    }
     if(isMask(opcode, "0x111000010iiiiiiiii01nnnnnttttt", &a)) {
         int size = a.x;
         int offset = signExtend(imm, 9);
@@ -278,12 +334,12 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
             snprintf(buff, sizeof(buff), "STR%c %s, [%s]", size?'H':'B', Xt[Rt], XtSp[Rn]);
         return buff;
     }    
-    if(isMask(opcode, "101110011xiiiiiiiiiiiinnnnnttttt", &a)) {
+    if(isMask(opcode, "1011100110iiiiiiiiiiiinnnnnttttt", &a)) {
         int offset = imm<<2;
         if(!offset)
-            snprintf(buff, sizeof(buff), "LDRSW %s, [%s]", a.x?Xt[Rt]:Wt[Rt], XtSp[Rn]);
+            snprintf(buff, sizeof(buff), "LDRSW %s, [%s]", Xt[Rt], XtSp[Rn]);
         else
-            snprintf(buff, sizeof(buff), "LDRSW %s, [%s, #%d]", a.x?Xt[Rt]:Wt[Rt], XtSp[Rn], offset);
+            snprintf(buff, sizeof(buff), "LDRSW %s, [%s, #%d]", Xt[Rt], XtSp[Rn], offset);
         return buff;
     }
     if(isMask(opcode, "011110011xiiiiiiiiiiiinnnnnttttt", &a)) {
@@ -620,7 +676,7 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
         else if(immr==0 && imms==0b001111)
             snprintf(buff, sizeof(buff), "SXTH %s, %s", sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn]);
         else if(sf && immr==0 && imms==0b011111)
-            snprintf(buff, sizeof(buff), "SXTW %s, %s", Xt[Rd], Xt[Rn]);
+            snprintf(buff, sizeof(buff), "SXTW %s, %s", Xt[Rd], Wt[Rn]);
         else if(imms>=immr)
             snprintf(buff, sizeof(buff), "SBFX %s, %s, %d, %d", sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn], immr, imms-immr+1);
         else
@@ -767,7 +823,7 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
         return buff;
     }
     if(isMask(opcode, "10011011U10mmmmm011111nnnnnddddd", &a)) {
-        snprintf(buff, sizeof(buff), "%cMULH %s, %s, %s", a.U?'U':'S', Xt[Rd], Wt[Rn], Wt[Rm]);
+        snprintf(buff, sizeof(buff), "%cMULH %s, %s, %s", a.U?'U':'S', Xt[Rd], Xt[Rn], Xt[Rm]);
         return buff;
     }
     if(isMask(opcode, "f0011011000mmmmm0aaaaannnnnddddd", &a)) {
@@ -777,6 +833,19 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
             snprintf(buff, sizeof(buff), "MADD %s, %s, %s, %s", sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn], sf?Xt[Rm]:Wt[Rm], sf?Xt[Ra]:Wt[Ra]);
         return buff;
     }
+    if(isMask(opcode, "f0011011000mmmmm1aaaaannnnnddddd", &a)) {
+        if(Ra==31)
+            snprintf(buff, sizeof(buff), "MNEG %s, %s, %s", sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn], sf?Xt[Rm]:Wt[Rm]);
+        else
+            snprintf(buff, sizeof(buff), "MSUB %s, %s, %s, %s", sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn], sf?Xt[Rm]:Wt[Rm], sf?Xt[Ra]:Wt[Ra]);
+        return buff;
+    }
+
+    // DIV
+    if(isMask(opcode, "f0011010110mmmmm00001onnnnnddddd", &a)) {
+        snprintf(buff, sizeof(buff), "%cDIV %s, %s, %s", option?'S':'U', sf?Xt[Rd]:Wt[Rd], sf?Xt[Rn]:Wt[Rn], sf?Xt[Rm]:Wt[Rm]);
+        return buff;
+    }
 
     // MRS / MSR
     if(isMask(opcode, "110101010001opppnnnnmmmm222ttttt", &a)) {
@@ -881,6 +950,28 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
         snprintf(buff, sizeof(buff), "VCMEQ V%d.%s, V%d.%s, V%d.%s", Rd, Vd, Rn, Vd, Rm, Vd);
         return buff;
     }
+    // MIN/MAX
+    if(isMask(opcode, "0QU01110ff1mmmmm0110o1nnnnnddddd", &a)) {
+        const char* Y[] = {"8B", "16B", "4H", "8H", "2S", "4S", "??", "2D"};
+        const char* Vd = Y[((sf)<<1) | a.Q];
+        snprintf(buff, sizeof(buff), "%c%s V%d.%s, V%d.%s, V%d.%s", a.U?'U':'S', a.o?"MIN":"MAX", Rd, Vd, Rn, Vd, Rm, Vd);
+        return buff;
+    }
+
+    // MOV immediate (not)shifted 8bits
+    if(isMask(opcode, "0Q00111100000iii111001iiiiiddddd", &a)) {
+        const char* Y[] = {"8B", "16B"};
+        const char* Vd = Y[a.Q];
+        snprintf(buff, sizeof(buff), "MOVI V%d.%s, #0x%x", Rd, Vd, imm);
+        return buff;
+    }
+    // MOV immediate (not)shifted 16bits & 32bits
+    if(isMask(opcode, "0Q00111100000iiif00001iiiiiddddd", &a)) {
+        const char* Y[] = {"2S", "4S", "4H", "8H"};
+        const char* Vd = Y[(sf<<1)| a.Q];
+        snprintf(buff, sizeof(buff), "MOVI V%d.%s, #0x%x", Rd, Vd, imm);
+        return buff;
+    }
 
     // Shift
     if(isMask(opcode, "0QU011110hhhhrrr000001nnnnnddddd", &a)) {
@@ -917,6 +1008,12 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
         return buff;
     }
 
+    // ADR
+    if(isMask(opcode, "0ss10000iiiiiiiiiiiiiiiiiiiddddd", &a)) {
+      snprintf(buff, sizeof(buff), "ADR, %s, %ld", Xt[Rd], signExtend((imm)<<2|(imms), 20));
+      return buff;
+    }
+
     // LDR / STR
     if(isMask(opcode, "ss111101cciiiiiiiiiiiinnnnnttttt", &a)) {
         char s = '?';
@@ -1010,6 +1107,84 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
         snprintf(buff, sizeof(buff), "FSQRT %c%d, %c%d", s, Rd, s, Rn);
         return buff;
     }
+    // FPRINTX
+    if(isMask(opcode, "0Q1011100f100001100110nnnnnddddd", &a)) {
+        char s = a.Q?'V':'D';
+        char d = sf?'D':'S';
+        int n = (a.Q && !sf)?4:2;
+        snprintf(buff, sizeof(buff), "VFRINTX %c%d.%d%c, %c%d.%d%c", s, Rd, n, d, s, Rn, n, d);
+        return buff;
+    }
+    if (isMask(opcode, "00011110ff100111010000nnnnnddddd", &a)) {
+        char s = (sf==0)?'S':((sf==1)?'D':'?');
+        snprintf(buff, sizeof(buff), "FRINTX %c%d, %c%d", s, Rd, s, Rn);
+        return buff;
+    }
+    // FRINTI
+    if(isMask(opcode, "0Q1011101f100001100110nnnnnddddd", &a)) {
+        char s = a.Q?'V':'D';
+        char d = sf?'D':'S';
+        int n = (a.Q && !sf)?4:2;
+        snprintf(buff, sizeof(buff), "VFRINTI %c%d.%d%c, %c%d.%d%c", s, Rd, n, d, s, Rn, n, d);
+        return buff;
+    }
+    if(isMask(opcode, "00011110ff100111110000nnnnnddddd", &a)) {
+        char s = (sf==0)?'S':((sf==1)?'D':'?');
+        snprintf(buff, sizeof(buff), "FRINTI %c%d, %c%d", s, Rd, s, Rn);
+        return buff;
+    }
+    // FRINTN
+    if(isMask(opcode, "0Q0011100f100001100010nnnnnddddd", &a)) {
+        char s = a.Q?'V':'D';
+        char d = sf?'D':'S';
+        int n = (a.Q && !sf)?4:2;
+        snprintf(buff, sizeof(buff), "VFRINTN %c%d.%d%c, %c%d.%d%c", s, Rd, n, d, s, Rn, n, d);
+        return buff;
+    }
+    if(isMask(opcode, "000111100f100100010000nnnnnddddd", &a)) {
+        char s = (sf==0)?'S':((sf==1)?'D':'?');
+        snprintf(buff, sizeof(buff), "FRINTN %c%d, %c%d", s, Rd, s, Rn);
+        return buff;
+    }
+    // FRINTM
+    if(isMask(opcode, "0Q0011100f100001100110nnnnnddddd", &a)) {
+        char s = a.Q?'V':'D';
+        char d = sf?'D':'S';
+        int n = (a.Q && !sf)?4:2;
+        snprintf(buff, sizeof(buff), "VFRINTM %c%d.%d%c, %c%d.%d%c", s, Rd, n, d, s, Rn, n, d);
+        return buff;
+    }
+    if(isMask(opcode, "000111100f100101010000nnnnnddddd", &a)) {
+        char s = (sf==0)?'S':((sf==1)?'D':'?');
+        snprintf(buff, sizeof(buff), "FRINTM %c%d, %c%d", s, Rd, s, Rn);
+        return buff;
+    }
+    // FRINTP
+    if(isMask(opcode, "0Q0011101f100001100010nnnnnddddd", &a)) {
+        char s = a.Q?'V':'D';
+        char d = sf?'D':'S';
+        int n = (a.Q && !sf)?4:2;
+        snprintf(buff, sizeof(buff), "VFRINTP %c%d.%d%c, %c%d.%d%c", s, Rd, n, d, s, Rn, n, d);
+        return buff;
+    }
+    if(isMask(opcode, "000111100f100100110000nnnnnddddd", &a)) {
+        char s = (sf==0)?'S':((sf==1)?'D':'?');
+        snprintf(buff, sizeof(buff), "FRINTP %c%d, %c%d", s, Rd, s, Rn);
+        return buff;
+    }
+    // FRINTZ
+    if(isMask(opcode, "0Q0011101f100001100110nnnnnddddd", &a)) {
+        char s = a.Q?'V':'D';
+        char d = sf?'D':'S';
+        int n = (a.Q && !sf)?4:2;
+        snprintf(buff, sizeof(buff), "VFRINTZ %c%d.%d%c, %c%d.%d%c", s, Rd, n, d, s, Rn, n, d);
+        return buff;
+    }
+    if(isMask(opcode, "000111100f100101110000nnnnnddddd", &a)) {
+        char s = (sf==0)?'S':((sf==1)?'D':'?');
+        snprintf(buff, sizeof(buff), "FRINTZ %c%d, %c%d", s, Rd, s, Rn);
+        return buff;
+    }
 
     //CMP
     if(isMask(opcode, "00011110ff1mmmmm001000nnnnn0c000", &a)) {
@@ -1020,10 +1195,20 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
             snprintf(buff, sizeof(buff), "FCMP %c%d, %c%d", s, Rn, s, Rm);
         return buff;
     }
+    //FCMP vector
+    if(isMask(opcode, "0QU01110cf1mmmmm111001nnnnnddddd", &a)) {
+        char s = (sf==0)?'S':((sf==1)?'D':'?');
+        int n = (sf==0)?2:1;
+        n *= a.Q?2:1;
+        int op = (a.c<<1) | (a.U);
+        const char* OP[] = {"EQ", "GE", "??", "GT"};
+        snprintf(buff, sizeof(buff), "FCMP%s%s V%d.%d%c, V%d.%d%c, V%d.%d%c", OP[op], a.Q?"Q":"", Rd, n, s, Rn, n, s, Rm, n, s);
+        return buff;
+    }
     //FMIN/FMAX
     if(isMask(opcode, "00011110ff1mmmmm01oo10nnnnnddddd", &a)) {
         char s = (sf==0)?'S':((sf==1)?'D':'?');
-        snprintf(buff, sizeof(buff), "F%s %c%d, %c%d, %c%d", (option==3)?"MINNM":((option==2)?"MINNMP":((!option)?"MAXNM":"MAXNMP")), s, Rd, s, Rn, s, Rm);
+        snprintf(buff, sizeof(buff), "F%s %c%d, %c%d, %c%d", (option==3)?"MINNM":((option==2)?"MAXNM":((!option)?"MAX":"MIN")), s, Rd, s, Rn, s, Rm);
         return buff;
     }
     if(isMask(opcode, "0Q001110of1mmmmm110001nnnnnddddd", &a)) {
@@ -1033,6 +1218,27 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
         snprintf(buff, sizeof(buff), "F%sNM%s V%d.%d%c, V%d.%d%c, V%d.%d%c", option?"MIN":"MAX", a.Q?"Q":"", Rd, n, s, Rn, n, s, Rm, n, s);
         return buff;
     }
+    if(isMask(opcode, "0Q001110of1mmmmm111101nnnnnddddd", &a)) {
+        char s = (sf==0)?'S':((sf==1)?'D':'?');
+        int n = (sf==0)?2:1;
+        n *= a.Q?2:1;
+        snprintf(buff, sizeof(buff), "F%s%s V%d.%d%c, V%d.%d%c, V%d.%d%c", option?"MIN":"MAX", a.Q?"Q":"", Rd, n, s, Rn, n, s, Rm, n, s);
+        return buff;
+    }
+    // NEG
+    if(isMask(opcode, "0Q101110ff100000101110nnnnnddddd", &a)) {
+        const char* Y[] = {"8B", "16B", "4H", "8H", "2S", "4S", "??", "2D"};
+        const char* Vd = Y[(sf<<1) | a.Q];
+        snprintf(buff, sizeof(buff), "NEG%s V%d.%s, V%d.%s", a.Q?"Q":"", Rd, Vd, Rn, Vd);
+        return buff;
+    }
+    // SSHL vector
+    if(isMask(opcode, "0QU01110ff1mmmmm010rS1nnnnnddddd", &a)) {
+        const char* Y[] = {"8B", "16B", "4H", "8H", "2S", "4S", "??", "2D"};
+        const char* Vd = Y[(sf<<1) | a.Q];
+        snprintf(buff, sizeof(buff), "%c%s%sSHL%s V%d.%s, V%d.%s, V%d.%s", a.U?'U':'S', a.r?"R":"", a.S?"Q":"", a.Q?"Q":"", Rd, Vd, Rn, Vd, Rm, Vd);
+        return buff;
+    }
 
     // FCVT
     if(isMask(opcode, "f0011110pp10010U000000nnnnnddddd", &a)) {
@@ -1112,8 +1318,8 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
         else if(sf==0 && type==0 && rmode==0 && opcd==6) {snprintf(buff, sizeof(buff), "FMOV %s, S%d", Wt[Rn], Rd);}
         else if(sf==1 && type==1 && rmode==0 && opcd==7) {snprintf(buff, sizeof(buff), "FMOV D%d, %s", Rd, Xt[Rn]);}
         else if(sf==1 && type==2 && rmode==1 && opcd==7) {snprintf(buff, sizeof(buff), "FMOV V%d.D[1], %s", Rd, Xt[Rn]);}
-        else if(sf==1 && type==1 && rmode==0 && opcd==6) {snprintf(buff, sizeof(buff), "FMOV %s, S%d", Xt[Rn], Rd);}
-        else if(sf==1 && type==2 && rmode==1 && opcd==6) {snprintf(buff, sizeof(buff), "FMOV %s, V%d.D[1]", Xt[Rn], Rd);}
+        else if(sf==1 && type==1 && rmode==0 && opcd==6) {snprintf(buff, sizeof(buff), "FMOV %s, D%d", Xt[Rd], Rn);}
+        else if(sf==1 && type==2 && rmode==1 && opcd==6) {snprintf(buff, sizeof(buff), "FMOV %s, V%d.D[1]", Xt[Rd], Rn);}
         else snprintf(buff, sizeof(buff), "FMOV ????");
         return buff;
     }
@@ -1208,14 +1414,6 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
         return buff;
     }
     
-    // MOV immediate
-    if(isMask(opcode, "0Q00111100000iii111001iiiiiddddd", &a)) {
-        const char* Y[] = {"8B", "16B"};
-        const char* Vd = Y[a.Q];
-        snprintf(buff, sizeof(buff), "MOVI V%d.%s, #0x%x", Rd, Vd, imm);
-        return buff;
-    }
-
     // LD1/ST1 single structure
     if(isMask(opcode, "0Q0011010L000000cc0Sffnnnnnttttt", &a)) {
         int scale = a.c;
@@ -1244,9 +1442,9 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
             sz = 4;
         int offset = signExtend(imm, 9);
         if(!offset)
-            snprintf(buff, sizeof(buff), "%sUR %s%d, [%s]", a.L?"LD":"ST", Y[sz], Rd, XtSp[Rn]);
+            snprintf(buff, sizeof(buff), "%sUR %s%d, [%s]", a.L?"LD":"ST", Y[sz], Rt, XtSp[Rn]);
         else
-            snprintf(buff, sizeof(buff), "%sUR %s%d, [%s, %+d]", a.L?"LD":"ST", Y[sz], Rd, XtSp[Rn], imm);
+            snprintf(buff, sizeof(buff), "%sUR %s%d, [%s, %s0x%x]", a.L?"LD":"ST", Y[sz], Rt, XtSp[Rn], (offset<0)?"-":"", abs(offset));
         return buff;
     }
     // LDR/STR vector immediate
@@ -1257,9 +1455,9 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
             sz = 4;
         int offset = imm<<sz;
         if(!offset)
-            snprintf(buff, sizeof(buff), "%sR %s%d, [%s]", a.L?"LD":"ST", Y[sz], Rd, XtSp[Rn]);
+            snprintf(buff, sizeof(buff), "%sR %s%d, [%s]", a.L?"LD":"ST", Y[sz], Rt, XtSp[Rn]);
         else
-            snprintf(buff, sizeof(buff), "%sR %s%d, [%s, %+d]", a.L?"LD":"ST", Y[sz], Rd, XtSp[Rn], imm);
+            snprintf(buff, sizeof(buff), "%sR %s%d, [%s, %+d]", a.L?"LD":"ST", Y[sz], Rt, XtSp[Rn], imm);
         return buff;
     }
 
@@ -1298,9 +1496,60 @@ const char* arm64_print(uint32_t opcode, uintptr_t addr)
             snprintf(buff, sizeof(buff), "%cSHLL%s V%d.%s, V%d.%s, #%d", a.U?'U':'S', a.Q?"2":"", Rd, Va, Rn, Vd, sh);
         return buff;
     }
-    
+
+    // DUP
+    if(isMask(opcode, "0Q001110000iiiii000001nnnnnddddd", &a)) {
+        const char* Y[] = {"8B", "16B", "4H", "8H", "2S", "4S", "??", "2D"};
+        const char* Z[] = {"B", "H", "S", "D"};
+        int sz = 3;
+        if((imm&0b0001)==0b0001) sz=0;
+        else if((imm&0b0011)==0b0010) sz=1;
+        else if((imm&0b0111)==0b0100) sz=2;
+        int sh=imm - (1<<sz);
+        const char* Vd = Y[(sz<<1)|a.Q];
+        const char* Vn = Z[sz];
+        snprintf(buff, sizeof(buff), "DUP V%d.%s, V%d.%s[%d]", Rd, Vd, Rn, Vn, sh);
+        return buff;
+    }
+
+    if(isMask(opcode, "0Q001110000iiiii000011nnnnnddddd", &a)) {
+        const char* Y[] = {"8B", "16B", "4H", "8H", "2S", "4S", "??", "2D"};
+        int sz = 3;
+        if((imm&0b0001)==0b0001) sz=0;
+        else if((imm&0b0011)==0b0010) sz=1;
+        else if((imm&0b0111)==0b0100) sz=2;
+        const char* Vd = Y[(sz<<1)|a.Q];
+        snprintf(buff, sizeof(buff), "DUP V%d.%s, X%d", Rd, Vd, Rn);
+        return buff;
+    }
+
+    // AES
+    if(isMask(opcode, "0100111000101000010f10nnnnnddddd", &a)) {
+        snprintf(buff, sizeof(buff), "AES%c V%d.16B, V%d.16B", sf?'D':'E', Rd, Rn);
+        return buff;
+    }
+    if(isMask(opcode, "0100111000101000011f10nnnnnddddd", &a)) {
+        snprintf(buff, sizeof(buff), "AES%sMC V%d.16B, V%d.16B", sf?"I":"", Rd, Rn);
+        return buff;
+    }
+    // PMULL
+    if(isMask(opcode, "0Q001110ff1mmmmm111000nnnnnddddd", &a)) {
+        const char* Y[] = {"8B", "16B", "??", "??", "??", "??", "1D", "2D"};
+        const char* Z[] = {"8H", "??", "??", "1Q"};
+        int sz = sf;
+        const char* Vn = Y[(sz<<1)|a.Q];
+        const char* Vd = Z[sz];
+        snprintf(buff, sizeof(buff), "PMULL%s V%d.%s, V%d.%s, V%d.%s", a.Q?"2":"", Rd, Vd, Rn, Vn, Rm, Vn);   
+        return buff;
+    }
+
+    // DMB ISH
+    if(isMask(opcode, "11010101000000110011nnnn10111111", &a)) {
+        snprintf(buff, sizeof(buff), "DMB %s", (Rn==0b1011)?"ISH":"???");
+        return buff;
+    }
 
 
     snprintf(buff, sizeof(buff), "%08X ???", __builtin_bswap32(opcode));
     return buff;
-}
+}

src/dynarec/arm64/arm64_prolog.S

@@ -6,16 +6,18 @@
 .text
 .align 4
 
+.extern arm64_next
+
 .global arm64_prolog
 arm64_prolog:
     //save all 18 used register
-    stp     lr, fp, [sp, -16]!  // save lr
+    stp     x30, x29, [sp, -16]!  // save lr
     sub     sp,  sp, (8 * 18)
     stp     x19, x20, [sp, (8 * 0)]
     stp     x21, x22, [sp, (8 * 2)]
     stp     x23, x24, [sp, (8 * 4)]
     stp     x25, x26, [sp, (8 * 6)]
-    str     x27, [sp, (8 * 8)]
+    stp     x27, X28, [sp, (8 * 8)]
     stp     d8, d9,   [sp, (8 *10)]
     stp     d10, d11, [sp, (8 *12)]
     stp     d12, d13, [sp, (8 *14)]
@@ -31,5 +33,10 @@ arm64_prolog:
     ldp     x22, x23, [x0, (8 * 12)]
     ldp     x24, x25, [x0, (8 * 14)]
     ldp     x26, x27, [x0, (8 * 16)]
+    // Push a jump next on the stack
+    adr     x28, arm64_next
+    stp     x28, xzr, [sp, -16]!
+    // Save old xSP in x28
+    add     x28, sp, 16
     //jump to function
     br       x1

src/dynarec/arm64/dynarec_arm64_6664.c

@@ -0,0 +1,146 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_helper.h"
+#include "dynarec_arm64_functions.h"
+
+uintptr_t dynarec64_6664(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int seg, int* ok, int* need_epilog)
+{
+    (void)ip; (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop;
+    uint8_t gd, ed;
+    int64_t j64;
+    int v0, v1;
+    int64_t fixedaddress;
+    int unscaled;
+    MAYUSE(j64);
+
+    GETREX();
+
+    /*if(rex.w && opcode!=0x0f) {   // rex.w cancels "66", but not for 66 0f type of prefix
+        MESSAGE(LOG_DUMP, "Here!\n");
+        return dynarec64_64(dyn, addr-2, ip, ninst, rex, rep, ok, need_epilog);
+    }*/
+
+    switch(opcode) {
+
+        case 0x0F:
+            opcode = F8;
+            switch(opcode) {
+                case 0x2E:
+                    // no special check...
+                case 0x2F:
+                    if(opcode==0x2F) {INST_NAME("COMISD Gx, Ex");} else {INST_NAME("UCOMISD Gx, Ex");}
+                    SETFLAGS(X_ALL, SF_SET);
+                    nextop = F8;
+                    GETG;
+                    v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
+                    if(MODREG) {
+                        v1 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3), 0);
+                    } else {
+                        grab_segdata(dyn, addr, ninst, x4, seg);
+                        SMREAD();
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                        v1 = fpu_get_scratch(dyn);
+                        VLDR64_REG(v1, ed, x4);
+                    }
+                    FCMPD(v0, v1);
+                    FCOMI(x1, x2);
+                    break;
+            case 0xD6:
+                INST_NAME("MOVQ Ex, Gx");
+                nextop = F8;
+                GETG;
+                v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
+                if(MODREG) {
+                    v1 = sse_get_reg_empty(dyn, ninst, x1, (nextop&7) + (rex.b<<3));
+                    FMOVD(v1, v0);
+                } else {
+                    grab_segdata(dyn, addr, ninst, x4, seg);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                    VSTR64_REG(v0, ed, x4);
+                    SMWRITE();
+                }
+                break;
+
+                default:
+                    DEFAULT;
+            }
+            break;
+
+        case 0x89:
+            INST_NAME("MOV FS:Ew, Gw");
+            nextop = F8;
+            GETGD;  // don't need GETGW here
+            if(MODREG) {
+                ed = xRAX+(nextop&7)+(rex.b<<3);
+                if(rex.w) {
+                    MOVx_REG(ed, gd);
+                } else {
+                    if(ed!=gd) {
+                        BFIx(ed, gd, 0, 16);
+                    }
+                }
+            } else {
+                grab_segdata(dyn, addr, ninst, x4, seg);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                if(rex.w) {
+                    STRx_REG(gd, ed, x4);
+                } else {
+                    STRH_REG(gd, ed, x4);
+                }
+                SMWRITE();
+            }
+            break;
+
+        case 0x8B:
+            INST_NAME("MOV Gd, FS:Ed");
+            nextop=F8;
+            GETGD;
+            if(MODREG) {   // reg <= reg
+                ed = xRAX+(nextop&7)+(rex.b<<3);
+                if(rex.w) {
+                    MOVx_REG(gd, ed);
+                } else {
+                    if(ed!=gd) {
+                        BFIx(gd, ed, 0, 16);
+                    }
+                }
+            } else {                    // mem <= reg
+                grab_segdata(dyn, addr, ninst, x4, seg);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                if(rex.w) {
+                    LDRx_REG(gd, ed, x4);
+                } else {
+                    LDRH_REG(x1, ed, x4);
+                    BFIx(gd, x1, 0, 16);
+                }
+            }
+            break;
+
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}

src/dynarec/arm64/dynarec_arm64_66f0.c

@@ -0,0 +1,426 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_helper.h"
+#include "dynarec_arm64_functions.h"
+
+
+uintptr_t dynarec64_66F0(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
+{
+    (void)ip; (void)rep; (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop;
+    uint8_t gd, ed, u8;
+    uint8_t wback, wb1, wb2, gb1, gb2;
+    int32_t i32;
+    int64_t i64, j64;
+    int64_t fixedaddress;
+    int unscaled;
+    MAYUSE(gb1);
+    MAYUSE(gb2);
+    MAYUSE(wb1);
+    MAYUSE(wb2);
+    MAYUSE(j64);
+
+    while((opcode==0xF2) || (opcode==0xF3)) {
+        rep = opcode-0xF1;
+        opcode = F8;
+    }
+
+    GETREX();
+
+    switch(opcode) {
+        case 0x09:
+            INST_NAME("LOCK OR Ew, Gw");
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x5);
+            SMDMB();
+            if(MODREG) {
+                ed = xRAX+(nextop&7)+(rex.b<<3);
+                UXTHw(x6, ed);
+                emit_or16(dyn, ninst, x6, x5, x3, x4);
+                BFIx(ed, x6, 0, 16);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
+                MARKLOCK;
+                LDAXRH(x1, wback);
+                emit_or16(dyn, ninst, x1, x5, x3, x4);
+                STLXRH(x3, x1, wback);
+                CBNZx_MARKLOCK(x3);
+            }
+            SMDMB();
+            break;
+
+        case 0x0F:
+            opcode = F8;
+            switch(opcode) {
+
+                case 0xB1:
+                    INST_NAME("LOCK CMPXCHG Ew, Gw");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    nextop = F8;
+                    GETGD;
+                    SMDMB();
+                    UXTHw(x6, xRAX);
+                    if(MODREG) {
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        wback = 0;
+                        UXTHw(x1, ed);
+                        CMPSxw_REG(x6, x1);
+                        B_MARK(cNE);
+                        BFIx(ed, gd, 0, 16);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
+                        TSTx_mask(wback, 1, 0, 0);    // mask=1
+                        B_MARK3(cNE);
+                        // Aligned version
+                        MARKLOCK;
+                        LDAXRH(x1, wback);
+                        CMPSw_REG(x6, x1);
+                        B_MARK(cNE);
+                        // EAX == Ed
+                        STLXRH(x4, gd, wback);
+                        CBNZx_MARKLOCK(x4);
+                        // done
+                        B_MARK_nocond;
+                        // Unaligned version
+                        MARK3;
+                        LDRH_U12(x1, wback, 0);
+                        LDAXRB(x3, wback); // dummy read, to arm the write...
+                        CMPSw_REG(x6, x1);
+                        B_MARK(cNE);
+                        // EAX == Ed
+                        STLXRB(x4, gd, wback);
+                        CBNZx_MARK3(x4);
+                        STRH_U12(gd, wback, 0);
+                    }
+                    MARK;
+                    // Common part (and fallback for EAX != Ed)
+                    UFLAG_IF {emit_cmp16(dyn, ninst, x6, x1, x3, x4, x5);}
+                    BFIx(xRAX, x1, 0, 16);
+                    SMDMB();
+                    break;
+
+                case 0xC1:
+                    INST_NAME("LOCK XADD Gw, Ew");
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    nextop = F8;
+                    gd = xRAX+((nextop&0x38)>>3)+(rex.r<<3);
+                    UXTHx(x5, gd);
+                    SMDMB();
+                    if(MODREG) {
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        BFIx(gd, ed, 0, 16);
+                        emit_add16(dyn, ninst, x5, gd, x3, x4);
+                        BFIx(ed, x5, 0, 16);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
+                        MARKLOCK;
+                        LDAXRH(x1, wback);
+                        ADDxw_REG(x4, x1, x5);
+                        STLXRH(x3, x4, wback);
+                        CBNZx_MARKLOCK(x3);
+                        IFX(X_ALL|X_PEND) {
+                            MOVxw_REG(x2, x1);
+                            emit_add16(dyn, ninst, x2, x5, x3, x4);
+                        }
+                        BFIx(gd, x1, 0, 16);
+                    }
+                    SMDMB();
+                    break;
+
+                default:
+                    DEFAULT;
+            }
+            break;
+        case 0x11:
+            INST_NAME("LOCK ADC Ew, Gw");
+            READFLAGS(X_CF);
+            SETFLAGS(X_ALL, SF_SET_PENDING);
+            nextop = F8;
+            GETGW(x5);
+            SMDMB();
+            if(MODREG) {
+                ed = xRAX+(nextop&7)+(rex.b<<3);
+                UXTHw(x6, ed);
+                emit_adc16(dyn, ninst, x6, x5, x3, x4);
+                BFIx(ed, x6, 0, 16);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
+                MARKLOCK;
+                LDAXRH(x1, wback);
+                emit_adc16(dyn, ninst, x1, x5, x3, x4);
+                STLXRH(x3, x1, wback);
+                CBNZx_MARKLOCK(x3);
+            }
+            SMDMB();
+            break;
+        case 0x81:
+        case 0x83:
+            nextop = F8;
+            SMDMB();
+            switch((nextop>>3)&7) {
+                case 0: //ADD
+                    if(opcode==0x81) {
+                        INST_NAME("LOCK ADD Ew, Iw");
+                    } else {
+                        INST_NAME("LOCK ADD Ew, Ib");
+                    }
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        MOV32w(x5, i32);
+                        UXTHw(x6, ed);
+                        emit_add16(dyn, ninst, x6, x5, x3, x4);
+                        BFIx(ed, x6, 0, 16);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, (opcode==0x81)?2:1);
+                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                        MOV32w(x5, i32);
+                        TSTx_mask(wback, 1, 0, 0);    // mask=1
+                        B_MARK(cNE);
+                        MARKLOCK;
+                        LDAXRH(x1, wback);
+                        emit_add16(dyn, ninst, x1, x5, x3, x4);
+                        STLXRH(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                        B_NEXT_nocond;
+                        MARK;   // unaligned! also, not enough
+                        LDRH_U12(x1, wback, 0);
+                        LDAXRB(x4, wback);
+                        BFIw(x1, x4, 0, 8); // re-inject
+                        emit_add16(dyn, ninst, x1, x5, x3, x4);
+                        STLXRB(x3, x1, wback);
+                        CBNZx_MARK(x3);
+                        STRH_U12(x1, wback, 0);    // put the whole value
+                    }
+                    break;
+                case 1: //OR
+                    if(opcode==0x81) {INST_NAME("LOCK OR Ew, Iw");} else {INST_NAME("LOCK OR Ew, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        MOV32w(x5, i32);
+                        UXTHw(x6, ed);
+                        emit_or16(dyn, ninst, x6, x5, x3, x4);
+                        BFIx(ed, x6, 0, 16);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, (opcode==0x81)?2:1);
+                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                        MOV32w(x5, i32);
+                        MARKLOCK;
+                        LDAXRH(x1, wback);
+                        emit_or16(dyn, ninst, x1, x5, x3, x4);
+                        STLXRH(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    break;
+                case 2: //ADC
+                    if(opcode==0x81) {INST_NAME("LOCK ADC Ew, Iw");} else {INST_NAME("LOCK ADC Ew, Ib");}
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        MOV32w(x5, i32);
+                        UXTHw(x6, ed);
+                        emit_adc16(dyn, ninst, x6, x5, x3, x4);
+                        BFIx(ed, x6, 0, 16);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, (opcode==0x81)?2:1);
+                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                        MOV32w(x5, i32);
+                        MARKLOCK;
+                        LDAXRH(x1, wback);
+                        emit_adc16(dyn, ninst, x1, x5, x3, x4);
+                        STLXRH(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    break;
+                case 3: //SBB
+                    if(opcode==0x81) {INST_NAME("LOCK SBB Ew, Iw");} else {INST_NAME("LOCK SBB Ew, Ib");}
+                    READFLAGS(X_CF);
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        MOV32w(x5, i32);
+                        UXTHw(x6, ed);
+                        emit_sbb16(dyn, ninst, x6, x5, x3, x4);
+                        BFIx(ed, x6, 0, 16);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, (opcode==0x81)?2:1);
+                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                        MOV32w(x5, i32);
+                        MARKLOCK;
+                        LDAXRH(x1, wback);
+                        emit_sbb16(dyn, ninst, x1, x5, x3, x4);
+                        STLXRH(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    break;
+                case 4: //AND
+                    if(opcode==0x81) {INST_NAME("LOCK AND Ew, Iw");} else {INST_NAME("LOCK AND Ew, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        MOV32w(x5, i32);
+                        UXTHw(x6, ed);
+                        emit_and16(dyn, ninst, x6, x5, x3, x4);
+                        BFIx(ed, x6, 0, 16);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, (opcode==0x81)?2:1);
+                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                        MOV32w(x5, i32);
+                        MARKLOCK;
+                        LDAXRH(x1, wback);
+                        emit_and16(dyn, ninst, x1, x5, x3, x4);
+                        STLXRH(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    break;
+                case 5: //SUB
+                    if(opcode==0x81) {INST_NAME("LOCK SUB Ew, Iw");} else {INST_NAME("LOCK SUB Ew, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        MOV32w(x5, i32);
+                        UXTHw(x6, ed);
+                        emit_sub16(dyn, ninst, x6, x5, x3, x4);
+                        BFIx(ed, x6, 0, 16);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, (opcode==0x81)?2:1);
+                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                        MOV32w(x5, i32);
+                        TSTx_mask(wback, 1, 0, 0);    // mask=1
+                        B_MARK(cNE);
+                        MARKLOCK;
+                        LDAXRH(x1, wback);
+                        emit_sub16(dyn, ninst, x1, x5, x3, x4);
+                        STLXRH(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                        B_NEXT_nocond;
+                        MARK;   // unaligned! also, not enough
+                        LDRH_U12(x1, wback, 0);
+                        LDAXRB(x4, wback);
+                        BFIw(x1, x4, 0, 8); // re-inject
+                        emit_sub16(dyn, ninst, x1, x5, x3, x4);
+                        STLXRB(x3, x1, wback);
+                        CBNZx_MARK(x3);
+                        STRH_U12(x1, wback, 0);    // put the whole value
+                    }
+                    break;
+                case 6: //XOR
+                    if(opcode==0x81) {INST_NAME("LOCK XOR Ew, Iw");} else {INST_NAME("LOCK XOR Ew, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    if(MODREG) {
+                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                        ed = xRAX+(nextop&7)+(rex.b<<3);
+                        MOV32w(x5, i32);
+                        UXTHw(x6, ed);
+                        emit_xor16(dyn, ninst, x6, x5, x3, x4);
+                        BFIx(ed, x6, 0, 16);
+                    } else {
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, (opcode==0x81)?2:1);
+                        if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                        MOV32w(x5, i32);
+                        MARKLOCK;
+                        LDAXRH(x1, wback);
+                        emit_xor16(dyn, ninst, x1, x5, x3, x4);
+                        STLXRH(x3, x1, wback);
+                        CBNZx_MARKLOCK(x3);
+                    }
+                    break;
+                case 7: //CMP
+                    if(opcode==0x81) {INST_NAME("(LOCK) CMP Ew, Iw");} else {INST_NAME("(LOCK) CMP Ew, Ib");}
+                    SETFLAGS(X_ALL, SF_SET_PENDING);
+                    GETEW(x6, (opcode==0x81)?2:1);
+                    (void)wb1;
+                    // No need to LOCK, this is readonly
+                    if(opcode==0x81) i32 = F16S; else i32 = F8S;
+                    if(i32) {
+                        MOV32w(x5, i32);
+                        emit_cmp16(dyn, ninst, x6, x5, x3, x4, x6);
+                    } else {
+                        emit_cmp16_0(dyn, ninst, ed, x3, x4);
+                    }
+                    break;
+            }
+            SMDMB();
+            break;
+
+            case 0xFF:
+                nextop = F8;
+                switch((nextop>>3)&7)
+                {
+                    case 0: // INC Ew
+                        INST_NAME("LOCK INC Ew");
+                        SETFLAGS(X_ALL&~X_CF, SF_SUBSET_PENDING);
+                        SMDMB();
+                        if(MODREG) {
+                            ed = xRAX+(nextop&7)+(rex.b<<3);
+                            UXTHw(x6, ed);
+                            emit_inc16(dyn, ninst, x6, x5, x3);
+                            BFIx(ed, x6, 0, 16);
+                        } else {
+                            addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
+                            MARKLOCK;
+                            LDAXRH(x1, wback);
+                            emit_inc16(dyn, ninst, x1, x3, x4);
+                            STLXRH(x3, x1, wback);
+                            CBNZx_MARKLOCK(x3);
+                        }
+                        SMDMB();
+                        break;
+                    case 1: //DEC Ew
+                        INST_NAME("LOCK DEC Ew");
+                        SETFLAGS(X_ALL&~X_CF, SF_SUBSET_PENDING);
+                        SMDMB();
+                        if(MODREG) {
+                            ed = xRAX+(nextop&7)+(rex.b<<3);
+                            UXTHw(x6, ed);
+                            emit_dec16(dyn, ninst, x6, x5, x3);
+                            BFIx(ed, x6, 0, 16);
+                        } else {
+                            addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, LOCK_LOCK, 0, 0);
+                            MARKLOCK;
+                            LDAXRH(x1, wback);
+                            emit_dec16(dyn, ninst, x1, x3, x4);
+                            STLXRH(x3, x1, wback);
+                            CBNZx_MARKLOCK(x3);
+                        }
+                        SMDMB();
+                        break;
+                    default:
+                        DEFAULT;
+                }
+                break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}

src/dynarec/arm64/dynarec_arm64_d8.c

@@ -0,0 +1,296 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "emu/x87emu_private.h"
+#include "dynarec_native.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_helper.h"
+#include "dynarec_arm64_functions.h"
+
+
+uintptr_t dynarec64_D8(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
+{
+    (void)ip; (void)rep; (void)need_epilog;
+
+    uint8_t nextop = F8;
+    uint8_t ed;
+    int64_t fixedaddress;
+    int unscaled;
+    int v1, v2;
+    int s0;
+
+    MAYUSE(s0);
+    MAYUSE(v2);
+    MAYUSE(v1);
+
+    switch(nextop) {
+        case 0xC0:
+        case 0xC1:
+        case 0xC2:
+        case 0xC3:
+        case 0xC4:
+        case 0xC5:
+        case 0xC6:
+        case 0xC7:
+            INST_NAME("FADD ST0, STx");
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FADDS(v1, v1, v2);
+            } else {
+                FADDD(v1, v1, v2);
+            }
+            break;
+        case 0xC8:
+        case 0xC9:
+        case 0xCA:
+        case 0xCB:
+        case 0xCC:
+        case 0xCD:
+        case 0xCE:
+        case 0xCF:
+            INST_NAME("FMUL ST0, STx");
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FMULS(v1, v1, v2);
+            } else {
+                FMULD(v1, v1, v2);
+            }
+            break;
+        case 0xD0:
+        case 0xD1:
+        case 0xD2:
+        case 0xD3:
+        case 0xD4:
+        case 0xD5:
+        case 0xD6:
+        case 0xD7:
+            INST_NAME("FCOM ST0, STx");
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
+            FCOM(x1, x2, x3);
+            break;
+        case 0xD8:
+        case 0xD9:
+        case 0xDA:
+        case 0xDB:
+        case 0xDC:
+        case 0xDD:
+        case 0xDE:
+        case 0xDF:
+            INST_NAME("FCOMP ST0, STx");
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
+            FCOM(x1, x2, x3);
+            x87_do_pop(dyn, ninst, x3);
+            break;
+        case 0xE0:
+        case 0xE1:
+        case 0xE2:
+        case 0xE3:
+        case 0xE4:
+        case 0xE5:
+        case 0xE6:
+        case 0xE7:
+            INST_NAME("FSUB ST0, STx");
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FSUBS(v1, v1, v2);
+            } else {
+                FSUBD(v1, v1, v2);
+            }
+            break;
+        case 0xE8:
+        case 0xE9:
+        case 0xEA:
+        case 0xEB:
+        case 0xEC:
+        case 0xED:
+        case 0xEE:
+        case 0xEF:
+            INST_NAME("FSUBR ST0, STx");
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FSUBS(v1, v2, v1);
+            } else {
+                FSUBD(v1, v2, v1);
+            }
+            break;
+        case 0xF0:
+        case 0xF1:
+        case 0xF2:
+        case 0xF3:
+        case 0xF4:
+        case 0xF5:
+        case 0xF6:
+        case 0xF7:
+            INST_NAME("FDIV ST0, STx");
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FDIVS(v1, v1, v2);
+            } else {
+                FDIVD(v1, v1, v2);
+            }
+            break;
+        case 0xF8:
+        case 0xF9:
+        case 0xFA:
+        case 0xFB:
+        case 0xFC:
+        case 0xFD:
+        case 0xFE:
+        case 0xFF:
+            INST_NAME("FDIVR ST0, STx");
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FDIVS(v1, v2, v1);
+            } else {
+                FDIVD(v1, v2, v1);
+            }
+            break;
+      
+        default:
+            switch((nextop>>3)&7) {
+                case 0:
+                    INST_NAME("FADD ST0, float[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                    s0 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                    VLD32(s0, ed, fixedaddress);
+                    if(ST_IS_F(0)) {
+                        FADDS(v1, v1, s0);
+                    } else {
+                        FCVT_D_S(s0, s0);
+                        FADDD(v1, v1, s0);
+                    }
+                    break;
+                case 1:
+                    INST_NAME("FMUL ST0, float[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                    s0 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                    VLD32(s0, ed, fixedaddress);
+                    if(ST_IS_F(0)) {
+                        FMULS(v1, v1, s0);
+                    } else {
+                        FCVT_D_S(s0, s0);
+                        FMULD(v1, v1, s0);
+                    }
+                    break;
+                case 2:
+                    INST_NAME("FCOM ST0, float[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                    s0 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                    VLD32(s0, ed, fixedaddress);
+                    if(ST_IS_F(0)) {
+                        FCMPS(v1, s0);
+                    } else {
+                        FCVT_D_S(s0, s0);
+                        FCMPD(v1, s0);
+                    }
+                    FCOM(x1, x2, x3);
+                    break;
+                case 3:
+                    INST_NAME("FCOMP ST0, float[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                    s0 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                    VLD32(s0, ed, fixedaddress);
+                    if(ST_IS_F(0)) {
+                        FCMPS(v1, s0);
+                    } else {
+                        FCVT_D_S(s0, s0);
+                        FCMPD(v1, s0);
+                    }
+                    FCOM(x1, x2, x3);
+                    x87_do_pop(dyn, ninst, x3);
+                    break;
+                case 4:
+                    INST_NAME("FSUB ST0, float[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                    s0 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                    VLD32(s0, ed, fixedaddress);
+                    if(ST_IS_F(0)) {
+                        FSUBS(v1, v1, s0);
+                    } else {
+                        FCVT_D_S(s0, s0);
+                        FSUBD(v1, v1, s0);
+                    }
+                    break;
+                case 5:
+                    INST_NAME("FSUBR ST0, float[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                    s0 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                    VLD32(s0, ed, fixedaddress);
+                    if(ST_IS_F(0)) {
+                        FSUBS(v1, s0, v1);
+                    } else {
+                        FCVT_D_S(s0, s0);
+                        FSUBD(v1, s0, v1);
+                    }
+                    break;
+                case 6:
+                    INST_NAME("FDIV ST0, float[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                    s0 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                    VLD32(s0, ed, fixedaddress);
+                    if(ST_IS_F(0)) {
+                        FDIVS(v1, v1, s0);
+                    } else {
+                        FCVT_D_S(s0, s0);
+                        FDIVD(v1, v1, s0);
+                    }
+                    break;
+                case 7:
+                    INST_NAME("FDIVR ST0, float[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+                    s0 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                    VLD32(s0, ed, fixedaddress);
+                    if(ST_IS_F(0)) {
+                        FDIVS(v1, s0, v1);
+                    } else {
+                        FCVT_D_S(s0, s0);
+                        FDIVD(v1, s0, v1);
+                    }
+                    break;
+                default:
+                    DEFAULT;
+            }
+    }
+    return addr;
+}

src/dynarec/arm64/dynarec_arm64_d9.c

@@ -1,7 +1,6 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <stddef.h>
-#include <pthread.h>
 #include <errno.h>
 
 #include "debug.h"
@@ -15,21 +14,25 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
 #include "emu/x87emu_private.h"
+#include "dynarec_native.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_helper.h"
 #include "dynarec_arm64_functions.h"
 
 
 uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
 {
+    (void)ip; (void)rep; (void)need_epilog;
+
     uint8_t nextop = F8;
     uint8_t ed;
     uint8_t wback, wb1;
-    int fixedaddress;
+    uint8_t u8;
+    int64_t fixedaddress;
+    int unscaled;
     int v1, v2;
     int s0;
     int i1, i2, i3;
@@ -48,12 +51,18 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xC6:
         case 0xC7:
             INST_NAME("FLD STx");
-            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7);
-            v2 = x87_do_push(dyn, ninst);
-            FMOVD(v2, v1);
+            v2 = x87_do_push(dyn, ninst, x1, X87_ST(nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, (nextop&7)+1, X87_COMBINE(0, (nextop&7)+1));
+            if(ST_IS_F(0)) {
+                FMOVS(v2, v1);
+            } else {
+                FMOVD(v2, v1);
+            }
             break;
 
         case 0xC8:
+            INST_NAME("FXCH ST0");
+            break;
         case 0xC9:
         case 0xCA:
         case 0xCB:
@@ -63,140 +72,161 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xCF:
             INST_NAME("FXCH STx");
             // swap the cache value, not the double value itself :p
-            i1 = x87_get_cache(dyn, ninst, x1, x2, nextop&7);
-            i2 = x87_get_cache(dyn, ninst, x1, x2, 0);
-            i3 = dyn->x87cache[i1];
-            dyn->x87cache[i1] = dyn->x87cache[i2];
-            dyn->x87cache[i2] = i3;
+            x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_ST(nextop&7));
+            x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+            x87_swapreg(dyn, ninst, x1, x2, 0, nextop&7);
+            // should set C1 to 0
             break;
 
         case 0xD0:
             INST_NAME("FNOP");
             break;
 
+        case 0xD8:
+            INST_NAME("FSTPNCE ST0, ST0");
+            x87_do_pop(dyn, ninst, x3);
+            break;
+        case 0xD9:
+        case 0xDA:
+        case 0xDB:
+        case 0xDC:
+        case 0xDD:
+        case 0xDE:
+        case 0xDF:
+            INST_NAME("FSTPNCE ST0, STx");
+            // copy the cache value for st0 to stx
+            x87_get_st_empty(dyn, ninst, x1, x2, nextop&7, X87_ST(nextop&7));
+            x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+            x87_swapreg(dyn, ninst, x1, x2, 0, nextop&7);
+            x87_do_pop(dyn, ninst, x3);
+            break;
         case 0xE0:
             INST_NAME("FCHS");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            FNEGD(v1, v1);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+            if(ST_IS_F(0)) {
+                FNEGS(v1, v1);
+            } else {
+                FNEGD(v1, v1);
+            }
             break;
         case 0xE1:
             INST_NAME("FABS");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            FABSD(v1, v1);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+            if(ST_IS_F(0)) {
+                FABSS(v1, v1);
+            } else {
+                FABSD(v1, v1);
+            }
             break;
 
         case 0xE4:
             INST_NAME("FTST");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            FCMPD_0(v1);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+            if(ST_IS_F(0)) {
+                FCMPS_0(v1);
+            } else {
+                FCMPD_0(v1);
+            }
             FCOM(x1, x2, x3);   // same flags...
             break;
         case 0xE5:
             INST_NAME("FXAM");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             x87_refresh(dyn, ninst, x1, x2, 0);
             CALL(fpu_fxam, -1);  // should be possible inline, but is it worth it?
             break;
 
         case 0xE8:
             INST_NAME("FLD1");
-            v1 = x87_do_push(dyn, ninst);
-            FTABLE64(v1, 1.0);
+            v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_F);
+            if(ST_IS_F(0)) {
+                FMOVS_8(v1, 0b01110000);
+            } else {
+                FMOVD_8(v1, 0b01110000);
+            }
             break;
         case 0xE9:
             INST_NAME("FLDL2T");
-            v1 = x87_do_push(dyn, ninst);
+            v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_D);
             FTABLE64(v1, L2T);
             break;
         case 0xEA:     
             INST_NAME("FLDL2E");
-            v1 = x87_do_push(dyn, ninst);
+            v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_D);
             FTABLE64(v1, L2E);
             break;
         case 0xEB:
             INST_NAME("FLDPI");
-            v1 = x87_do_push(dyn, ninst);
+            v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_D);
             FTABLE64(v1, PI);
             break;
         case 0xEC:
             INST_NAME("FLDLG2");
-            v1 = x87_do_push(dyn, ninst);
+            v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_D);
             FTABLE64(v1, LG2);
             break;
         case 0xED:
             INST_NAME("FLDLN2");
-            v1 = x87_do_push(dyn, ninst);
+            v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_D);
             FTABLE64(v1, LN2);
             break;
         case 0xEE:
             INST_NAME("FLDZ");
-            v1 = x87_do_push(dyn, ninst);
-            FTABLE64(v1, 0.0);
+            v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_F);
+            VEOR(v1, v1, v1);
             break;
 
-        case 0xFA:
-            INST_NAME("FSQRT");
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            FSQRTD(v1, v1);
-            break;
-
-        case 0xFC:
-            INST_NAME("FRNDINT");
-            // use C helper for now, nothing staightforward is available
-            x87_forget(dyn, ninst, x1, x2, 0);
-            CALL(arm_frndint, -1);
-            /*
-            v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-            VCMP_F64_0(v1);
-            VMRS_APSR();
-            B_NEXT(cVS);    // Unordered, skip
-            B_NEXT(cEQ);    // Zero, skip
-            u8 = x87_setround(dyn, ninst, x1, x2, x3);
-            VCVT_S32_F64(x1, v1);   // limit to 32bits....
-            VCVT_F64_S32(v1, x1);
-            x87_restoreround(dyn, ninst, u8);
-            */
-            break;
         case 0xF0:
             INST_NAME("F2XM1");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             x87_forget(dyn, ninst, x1, x2, 0);
-            CALL(arm_f2xm1, -1);
+            CALL(native_f2xm1, -1);
             break;
         case 0xF1:
             INST_NAME("FYL2X");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             x87_forget(dyn, ninst, x1, x2, 0);
             x87_forget(dyn, ninst, x1, x2, 1);
-            CALL(arm_fyl2x, -1);
-            x87_do_pop(dyn, ninst);
+            CALL(native_fyl2x, -1);
+            x87_do_pop(dyn, ninst, x3);
             break;
         case 0xF2:
-            INST_NAME("FTAN");
+            INST_NAME("FPTAN");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             x87_forget(dyn, ninst, x1, x2, 0);
-            CALL(arm_ftan, -1);
-            v1 = x87_do_push(dyn, ninst);
-            FTABLE64(v1, 1.0);
+            CALL(native_ftan, -1);
+            v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_F);
+            if(ST_IS_F(0)) {
+                FMOVS_8(v1, 0b01110000);
+            } else {
+                FMOVD_8(v1, 0b01110000);
+            }
             break;
         case 0xF3:
             INST_NAME("FPATAN");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             x87_forget(dyn, ninst, x1, x2, 0);
             x87_forget(dyn, ninst, x1, x2, 1);
-            CALL(arm_fpatan, -1);
-            x87_do_pop(dyn, ninst);
+            CALL(native_fpatan, -1);
+            x87_do_pop(dyn, ninst, x3);
             break;
         case 0xF4:
             INST_NAME("FXTRACT");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             x87_do_push_empty(dyn, ninst, 0);
             x87_forget(dyn, ninst, x1, x2, 1);
-            CALL(arm_fxtract, -1);
+            CALL(native_fxtract, -1);
             break;
         case 0xF5:
             INST_NAME("FPREM1");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             x87_forget(dyn, ninst, x1, x2, 0);
             x87_forget(dyn, ninst, x1, x2, 1);
-            CALL(arm_fprem1, -1);
+            CALL(native_fprem1, -1);
             break;
         case 0xF6:
             INST_NAME("FDECSTP");
-            fpu_purgecache(dyn, ninst, x1, x2, x3);
+            fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
             LDRw_U12(x2, xEmu, offsetof(x64emu_t, top));
             SUBw_U12(x2, x2, 1);
             ANDw_mask(x2, x2, 0, 2);    //mask=7
@@ -204,7 +234,7 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             break;
         case 0xF7:
             INST_NAME("FINCSTP");
-            fpu_purgecache(dyn, ninst, x1, x2, x3);
+            fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
             LDRw_U12(x2, xEmu, offsetof(x64emu_t, top));
             ADDw_U12(x2, x2, 1);
             ANDw_mask(x2, x2, 0, 2);    //mask=7
@@ -212,38 +242,71 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             break;
         case 0xF8:
             INST_NAME("FPREM");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             x87_forget(dyn, ninst, x1, x2, 0);
             x87_forget(dyn, ninst, x1, x2, 1);
-            CALL(arm_fprem, -1);
+            CALL(native_fprem, -1);
             break;
         case 0xF9:
             INST_NAME("FYL2XP1");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             x87_forget(dyn, ninst, x1, x2, 0);
             x87_forget(dyn, ninst, x1, x2, 1);
-            CALL(arm_fyl2xp1, -1);
-            x87_do_pop(dyn, ninst);
+            CALL(native_fyl2xp1, -1);
+            x87_do_pop(dyn, ninst, x3);
+            break;
+        case 0xFA:
+            INST_NAME("FSQRT");
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+            if(ST_IS_F(0)) {
+                FSQRTS(v1, v1);
+            } else {
+                FSQRTD(v1, v1);
+            }
             break;
         case 0xFB:
             INST_NAME("FSINCOS");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             x87_do_push_empty(dyn, ninst, 0);
             x87_forget(dyn, ninst, x1, x2, 1);
-            CALL(arm_fsincos, -1);
+            CALL(native_fsincos, -1);
+            break;
+        case 0xFC:
+            INST_NAME("FRNDINT");
+            #if 0
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
+            // use C helper for now, nothing staightforward is available
+            x87_forget(dyn, ninst, x1, x2, 0);
+            CALL(native_frndint, -1);
+            #else
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+            u8 = x87_setround(dyn, ninst, x1, x2, x3);
+            if(ST_IS_F(0)) {
+                FRINTIS(v1, v1);
+            } else {
+                FRINTID(v1, v1);
+            }
+            x87_restoreround(dyn, ninst, u8);
+            #endif
             break;
         case 0xFD:
             INST_NAME("FSCALE");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             x87_forget(dyn, ninst, x1, x2, 0);
             x87_forget(dyn, ninst, x1, x2, 1);
-            CALL(arm_fscale, -1);
+            CALL(native_fscale, -1);
             break;
         case 0xFE:
             INST_NAME("FSIN");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             x87_forget(dyn, ninst, x1, x2, 0);
-            CALL(arm_fsin, -1);
+            CALL(native_fsin, -1);
             break;
         case 0xFF:
             INST_NAME("FCOS");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
             x87_forget(dyn, ninst, x1, x2, 0);
-            CALL(arm_fcos, -1);
+            CALL(native_fcos, -1);
             break;
 
 
@@ -252,14 +315,6 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
         case 0xD5:
         case 0xD6:
         case 0xD7:
-        case 0xD8:
-        case 0xD9:
-        case 0xDA:
-        case 0xDB:
-        case 0xDC:
-        case 0xDD:
-        case 0xDE:
-        case 0xDF:
         case 0xE2:
         case 0xE3:
         case 0xE6:
@@ -272,33 +327,40 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             switch((nextop>>3)&7) {
                 case 0:
                     INST_NAME("FLD ST0, float[ED]");
-                    v1 = x87_do_push(dyn, ninst);
-                    s0 = fpu_get_scratch(dyn);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
-                    VLDR32_U12(s0, ed, fixedaddress);
-                    FCVT_D_S(v1, s0);
+                    v1 = x87_do_push(dyn, ninst, x1, box64_dynarec_x87double?NEON_CACHE_ST_D:NEON_CACHE_ST_F);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                    VLD32(v1, ed, fixedaddress);
+                    if(!ST_IS_F(0)) {
+                        FCVT_D_S(v1, v1);
+                    }
                     break;
                 case 2:
                     INST_NAME("FST float[ED], ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    s0 = fpu_get_scratch(dyn);
-                    FCVT_S_D(s0, v1);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
-                    VSTR32_U12(s0, ed, fixedaddress);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
+                    if(ST_IS_F(0))
+                        s0 = v1;
+                    else {
+                        s0 = fpu_get_scratch(dyn);
+                        FCVT_S_D(s0, v1);
+                    }
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                    VST32(s0, ed, fixedaddress);
                     break;
                 case 3:
                     INST_NAME("FSTP float[ED], ST0");
-                    v1 = x87_get_st(dyn, ninst, x1, x2, 0);
-                    s0 = fpu_get_scratch(dyn);
-                    FCVT_S_D(s0, v1);
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
-                    VSTR32_U12(s0, ed, fixedaddress);
-                    x87_do_pop(dyn, ninst);
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                    if(!ST_IS_F(0)) {
+                        FCVT_S_D(v1, v1);
+                    }
+                    VST32(v1, ed, fixedaddress);
+                    x87_do_pop(dyn, ninst, x3);
                     break;
                 case 4:
                     INST_NAME("FLDENV Ed");
-                    fpu_purgecache(dyn, ninst, x1, x2, x3); // maybe only x87, not SSE?
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 0);
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    fpu_purgecache(dyn, ninst, 0, x1, x2, x3); // maybe only x87, not SSE?
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
                     if(ed!=x1) {
                         MOVx_REG(x1, ed);
                     }
@@ -309,13 +371,12 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     INST_NAME("FLDCW Ew");
                     GETEW(x1, 0);
                     STRH_U12(x1, xEmu, offsetof(x64emu_t, cw));    // hopefully cw is not too far for an imm8
-                    UBFXw(x1, x1, 10, 2);    // extract round
-                    STRw_U12(x1, xEmu, offsetof(x64emu_t, round));
                     break;
                 case 6:
                     INST_NAME("FNSTENV Ed");
-                    fpu_purgecache(dyn, ninst, x1, x2, x3); // maybe only x87, not SSE?
-                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 0);
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    fpu_purgecache(dyn, ninst, 0, x1, x2, x3); // maybe only x87, not SSE?
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
                     if(ed!=x1) {
                         MOVx_REG(x1, ed);
                     }
@@ -324,7 +385,7 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
                     break;
                 case 7:
                     INST_NAME("FNSTCW Ew");
-                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, 0xfff<<1, 1, rex, 0, 0);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
                     ed = x1;
                     wb1 = 1;
                     LDRH_U12(x1, xEmu, offsetof(x64emu_t, cw));
@@ -336,4 +397,3 @@ uintptr_t dynarec64_D9(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
     }
     return addr;
 }
-

src/dynarec/arm64/dynarec_arm64_db.c

@@ -0,0 +1,382 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "emu/x87emu_private.h"
+#include "dynarec_native.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_helper.h"
+#include "dynarec_arm64_functions.h"
+
+
+uintptr_t dynarec64_DB(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
+{
+    (void)ip; (void)rep; (void)need_epilog;
+
+    uint8_t nextop = F8;
+    uint8_t ed;
+    uint8_t wback;
+    uint8_t u8;
+    int64_t fixedaddress;
+    int unscaled;
+    int v1, v2;
+    int s0;
+    int64_t j64;
+
+    MAYUSE(s0);
+    MAYUSE(v2);
+    MAYUSE(v1);
+    MAYUSE(j64);
+
+    switch(nextop) {
+        case 0xC0:
+        case 0xC1:
+        case 0xC2:
+        case 0xC3:
+        case 0xC4:
+        case 0xC5:
+        case 0xC6:
+        case 0xC7:
+            INST_NAME("FCMOVNB ST0, STx");
+            READFLAGS(X_CF);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            TSTw_mask(xFlags, 0, 0);    //mask=1<<F_CF
+            if(ST_IS_F(0)) {
+                FCSELS(v1, v2, v1, cEQ);
+            } else {
+                FCSELD(v1, v2, v1, cEQ);    // F_CF==0
+            }
+            break;
+        case 0xC8:
+        case 0xC9:
+        case 0xCA:
+        case 0xCB:
+        case 0xCC:
+        case 0xCD:
+        case 0xCE:
+        case 0xCF:
+            INST_NAME("FCMOVNE ST0, STx");
+            READFLAGS(X_ZF);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            TSTw_mask(xFlags, 0b011010, 0); //mask=1<<F_ZF
+            if(ST_IS_F(0)) {
+                FCSELS(v1, v2, v1, cEQ);
+            } else {
+                FCSELD(v1, v2, v1, cEQ);        // F_ZF==0
+            }
+            break;
+        case 0xD0:
+        case 0xD1:
+        case 0xD2:
+        case 0xD3:
+        case 0xD4:
+        case 0xD5:
+        case 0xD6:
+        case 0xD7:
+            INST_NAME("FCMOVNBE ST0, STx");
+            READFLAGS(X_CF|X_ZF);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            MOV32w(x1, (1<<F_CF)|(1<<F_ZF));
+            TSTw_REG(xFlags, x1);
+            if(ST_IS_F(0)) {
+                FCSELS(v1, v2, v1, cEQ);
+            } else {
+                FCSELD(v1, v2, v1, cEQ);   // F_CF==0 & F_ZF==0
+            }
+            break;
+        case 0xD8:
+        case 0xD9:
+        case 0xDA:
+        case 0xDB:
+        case 0xDC:
+        case 0xDD:
+        case 0xDE:
+        case 0xDF:
+            INST_NAME("FCMOVNU ST0, STx");
+            READFLAGS(X_PF);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            TSTw_mask(xFlags, 0b011110, 0); //mask=1<<F_PF
+            if(ST_IS_F(0)) {
+                FCSELS(v1, v2, v1, cEQ);
+            } else {
+                FCSELD(v1, v2, v1, cEQ);        // F_PF==0
+            }
+            break;
+        case 0xE1:
+            INST_NAME("FDISI8087_NOP"); // so.. NOP?
+            break;
+        case 0xE2:
+            INST_NAME("FNCLEX");
+            LDRH_U12(x2, xEmu, offsetof(x64emu_t, sw));
+            MOV32w(x1, 0);
+            BFIw(x2, x1, 0, 8);  // IE .. PE, SF, ES
+            BFIw(x2, x1, 15, 1); // B
+            STRH_U12(x2, xEmu, offsetof(x64emu_t, sw));
+            break;
+        case 0xE3:
+            INST_NAME("FNINIT");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
+            x87_purgecache(dyn, ninst, 0, x1, x2, x3);
+            CALL(reset_fpu, -1);
+            break;
+        case 0xE8:
+        case 0xE9:
+        case 0xEA:
+        case 0xEB:
+        case 0xEC:
+        case 0xED:
+        case 0xEE:
+        case 0xEF:
+            INST_NAME("FUCOMI ST0, STx");
+            SETFLAGS(X_ALL, SF_SET);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
+            FCOMI(x1, x2);
+            break;
+        case 0xF0:  
+        case 0xF1:
+        case 0xF2:
+        case 0xF3:
+        case 0xF4:
+        case 0xF5:
+        case 0xF6:
+        case 0xF7:
+            INST_NAME("FCOMI ST0, STx");
+            SETFLAGS(X_ALL, SF_SET);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
+            FCOMI(x1, x2);
+            break;
+
+        case 0xE0:
+        case 0xE4:
+        case 0xE5:
+        case 0xE6:
+        case 0xE7:
+            DEFAULT;
+            break;
+
+        default:
+            switch((nextop>>3)&7) {
+                case 0:
+                    INST_NAME("FILD ST0, Ed");
+                    v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_D);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                    VLD32(v1, ed, fixedaddress);
+                    SXTL_32(v1, v1);    // i32 -> i64
+                    SCVTFDD(v1, v1);    // i64 -> double
+                    break;
+                case 1:
+                    INST_NAME("FISTTP Ed, ST0");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                    s0 = fpu_get_scratch(dyn);
+                    #if 0
+                    ed = x1;
+                    FRINT32ZD(s0, v1);
+                    FCVTZSwD(ed, s0);
+                    WBACK;
+                    #else
+                    MRS_fpsr(x5);
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    MSR_fpsr(x5);
+                    FRINTZD(s0, v1);
+                    VFCVTZSd(s0, s0);
+                    SQXTN_S_D(s0, s0);
+                    VST32(s0, wback, fixedaddress);
+                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                    TBZ_MARK3(x5, FPSR_IOC);
+                    MOV32w(x5, 0x80000000);
+                    STW(x5, wback, fixedaddress);
+                    MARK3;
+                    #endif
+                    x87_do_pop(dyn, ninst, x3);
+                    break;
+                case 2:
+                    INST_NAME("FIST Ed, ST0");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    u8 = x87_setround(dyn, ninst, x1, x2, x4); // x1 have the modified RPSCR reg
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                    s0 = fpu_get_scratch(dyn);
+                    #if 0
+                    ed = x1;
+                    FRINT32XD(s0, v1);
+                    FCVTZSwD(ed, s0);
+                    WBACK;
+                    #else
+                    MRS_fpsr(x5);
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    MSR_fpsr(x5);
+                    FRINTXD(s0, v1);
+                    VFCVTZSd(s0, s0);
+                    SQXTN_S_D(s0, s0);
+                    VST32(s0, wback, fixedaddress);
+                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                    TBZ_MARK3(x5, FPSR_IOC);
+                    MOV32w(x5, 0x80000000);
+                    STW(x5, wback, fixedaddress);
+                    MARK3;
+                    #endif
+                    x87_restoreround(dyn, ninst, u8);
+                    break;
+                case 3:
+                    INST_NAME("FISTP Ed, ST0");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    u8 = x87_setround(dyn, ninst, x1, x2, x4); // x1 have the modified RPSCR reg
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                    s0 = fpu_get_scratch(dyn);
+                    #if 0
+                    ed = x1;
+                    FRINT32XD(s0, v1);
+                    FCVTZSwD(ed, s0);
+                    WBACK;
+                    #else
+                    MRS_fpsr(x5);
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    MSR_fpsr(x5);
+                    FRINTXD(s0, v1);
+                    VFCVTZSd(s0, s0);
+                    SQXTN_S_D(s0, s0);
+                    VST32(s0, wback, fixedaddress);
+                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                    TBZ_MARK3(x5, FPSR_IOC);
+                    MOV32w(x5, 0x80000000);
+                    STW(x5, wback, fixedaddress);
+                    MARK3;
+                    #endif
+                    x87_restoreround(dyn, ninst, u8);
+                    x87_do_pop(dyn, ninst, x3);
+                    break;
+                case 5:
+                    INST_NAME("FLD tbyte");
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                    if((PK(0)==0xDB && ((PK(1)>>3)&7)==7) || (PK(0)>=0x40 && PK(0)<=0x4f && PK(1)==0xDB && ((PK(2)>>3)&7)==7)) {
+                        // the FLD is immediatly followed by an FSTP
+                        LDRx_U12(x5, ed, 0);
+                        LDRH_U12(x6, ed, 8);
+                        // no persistant scratch register, so unrool both instruction here...
+                        MESSAGE(LOG_DUMP, "\tHack: FSTP tbyte\n");
+                        nextop = F8;    // 0xDB or rex
+                        if(nextop>=0x40 && nextop<=0x4f) {
+                            rex.rex = nextop;
+                            nextop = F8;    //0xDB
+                        } else
+                            rex.rex = 0;
+                        nextop = F8;    //modrm
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                        STRx_U12(x5, ed, 0);
+                        STRH_U12(x6, ed, 8);
+                    } else {
+                        if(box64_x87_no80bits) {
+                            v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_D);
+                            VLDR64_U12(v1, ed, fixedaddress);
+                        } else {
+                            if(ed!=x1) {
+                                MOVx_REG(x1, ed);
+                            }
+                            x87_do_push_empty(dyn, ninst, x3);
+                            CALL(native_fld, -1);
+                        }
+                    }
+                    break;
+                case 7:
+                    INST_NAME("FSTP tbyte");
+                    if(box64_x87_no80bits) {
+                        v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                        VST64(v1, wback, fixedaddress);
+                    } else {
+                        #if 0
+                        x87_forget(dyn, ninst, x1, x3, 0);
+                        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                        if(ed!=x1) {
+                            MOVx_REG(x1, ed);
+                        }
+                        CALL(native_fstp, -1);
+                        #else
+                        // Painfully long, straight conversion from the C code, shoud be optimized
+                        v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                        addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                        FMOVxD(x1, v1);
+                        // do special value first
+                        TSTx_mask(x1, 1, 0b00000, 0b111110);    //0x7fffffffffffffffL
+                        B_MARK(cNE);
+                        // Zero
+                        LSRx(x3, x1, 63-15);    //x3 = sign+exp
+                        MOVZw(x5, 0);           // x5 = mantisse
+                        B_MARK3_nocond;
+                        MARK;
+                        // get sign, in main ouput x5 for sign+exp
+                        ANDx_mask(x5, x1, 1, 1, 0); //0x8000000000000000
+                        LSRx(x5, x5, 63-15);    // x5 = sign
+                        // get exp
+                        LSRx(x3, x1, 52);       // x3 = exp11
+                        ANDw_mask(x3, x3, 0, 0b1010);    //0x7ff
+                        MOV32w(x4, 0x7ff);
+                        CMPSw_REG(x3, x4);
+                        B_MARK2(cNE);
+                        // NaN and Infinite
+                        ORRw_mask(x3, x5, 0, 0b1110);    //x3 = sign | 0x7fff 
+                        TSTx_mask(x1, 1, 0, 0b110011); //0x000fffffffffffffL
+                        ORRx_mask(x5, xZR, 1, 1, 0);    //0x8000000000000000
+                        ORRx_mask(x4, xZR, 1, 0b10, 0b01); //0xc000000000000000
+                        CSELx(x5, x5, x4, cEQ);     // x5 = mantisse
+                        B_MARK3_nocond;
+                        MARK2;
+                        // regular / denormals
+                        ANDx_mask(x1, x1, 1, 0, 0b110011); //0x000fffffffffffffL
+                        LSLx_IMM(x1, x1, 11);   //x1 = mantisse missing "1"
+                        MOVZw(x4, 16383-1023);  //BIAS80 - BIAS64
+                        CBZw(x3, 4+3*4);        // exp11 == 0?
+                        // normals
+                        ADDw_REG(x3, x3, x4);   // x3 = exp16
+                        ORRw_REG(x3, x3, x5);   // x3 = sign | exp
+                        ORRx_mask(x5, x1, 1, 1, 0);    //0x8000000000000000 x5 = mantisse
+                        B_MARK3_nocond;
+                        // denormals
+                        CLZx(x6, x1);
+                        ADDw_U12(x6, x6, 1);    // "one"
+                        SUBw_REG(x3, x4, x6);   // x3 = exp16
+                        ORRw_REG(x3, x3, x5);   // x3 = sign | exp16
+                        LSLx_REG(x5, x1, x6);   // x5 = mantisse
+                        MARK3;
+                        STRx_U12(x5, wback, 0);
+                        STRH_U12(x3, wback, 8);
+                        #endif
+                    }
+                    x87_do_pop(dyn, ninst, x3);
+                    break;
+                default:
+                    DEFAULT;
+            }
+    }
+    return addr;
+}

src/dynarec/arm64/dynarec_arm64_dc.c

@@ -0,0 +1,251 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "emu/x87emu_private.h"
+#include "dynarec_native.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_helper.h"
+#include "dynarec_arm64_functions.h"
+
+
+uintptr_t dynarec64_DC(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
+{
+    (void)ip; (void)rep; (void)need_epilog;
+
+    uint8_t nextop = F8;
+    uint8_t wback;
+    int64_t fixedaddress;
+    int unscaled;
+    int v1, v2;
+
+    MAYUSE(v2);
+    MAYUSE(v1);
+
+    switch(nextop) {
+        case 0xC0:
+        case 0xC1:
+        case 0xC2:
+        case 0xC3:
+        case 0xC4:
+        case 0xC5:
+        case 0xC6:
+        case 0xC7:
+            INST_NAME("FADD STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FADDS(v1, v1, v2);
+            } else {
+                FADDD(v1, v1, v2);
+            }
+            break;
+        case 0xC8:
+        case 0xC9:
+        case 0xCA:
+        case 0xCB:
+        case 0xCC:
+        case 0xCD:
+        case 0xCE:
+        case 0xCF:
+            INST_NAME("FMUL STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FMULS(v1, v1, v2);
+            } else {
+                FMULD(v1, v1, v2);
+            }
+            break;
+        case 0xD0:
+        case 0xD1:
+        case 0xD2:
+        case 0xD3:
+        case 0xD4:
+        case 0xD5:
+        case 0xD6:
+        case 0xD7:
+            INST_NAME("FCOM ST0, STx"); //yep
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
+            FCOM(x1, x2, x3);
+            break;
+        case 0xD8:
+        case 0xD9:
+        case 0xDA:
+        case 0xDB:
+        case 0xDC:
+        case 0xDD:
+        case 0xDE:
+        case 0xDF:
+            INST_NAME("FCOMP ST0, STx");
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
+            FCOM(x1, x2, x3);
+            x87_do_pop(dyn, ninst, x3);
+            break;
+        case 0xE0:
+        case 0xE1:
+        case 0xE2:
+        case 0xE3:
+        case 0xE4:
+        case 0xE5:
+        case 0xE6:
+        case 0xE7:
+            INST_NAME("FSUBR STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FSUBS(v1, v2, v1);
+            } else {
+                FSUBD(v1, v2, v1);
+            }
+            break;
+        case 0xE8:
+        case 0xE9:
+        case 0xEA:
+        case 0xEB:
+        case 0xEC:
+        case 0xED:
+        case 0xEE:
+        case 0xEF:
+            INST_NAME("FSUB STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FSUBS(v1, v1, v2);
+            } else {
+                FSUBD(v1, v1, v2);
+            }
+            break;
+        case 0xF0:
+        case 0xF1:
+        case 0xF2:
+        case 0xF3:
+        case 0xF4:
+        case 0xF5:
+        case 0xF6:
+        case 0xF7:
+            INST_NAME("FDIVR STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FDIVS(v1, v2, v1);
+            } else {
+                FDIVD(v1, v2, v1);
+            }
+            break;       
+        case 0xF8:
+        case 0xF9:
+        case 0xFA:
+        case 0xFB:
+        case 0xFC:
+        case 0xFD:
+        case 0xFE:
+        case 0xFF:
+            INST_NAME("FDIV STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FDIVS(v1, v1, v2);
+            } else {
+                FDIVD(v1, v1, v2);
+            }
+            break;
+        default:
+            switch((nextop>>3)&7) {
+                case 0:
+                    INST_NAME("FADD ST0, double[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                    VLD64(v2, wback, fixedaddress);
+                    FADDD(v1, v1, v2);
+                    break;
+                case 1:
+                    INST_NAME("FMUL ST0, double[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                    VLD64(v2, wback, fixedaddress);
+                    FMULD(v1, v1, v2);
+                    break;
+                case 2:
+                    INST_NAME("FCOM ST0, double[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                    VLD64(v2, wback, fixedaddress);
+                    FCMPD(v1, v2);
+                    FCOM(x1, x2, x3);
+                    break;
+                case 3:
+                    INST_NAME("FCOMP ST0, double[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                    VLD64(v2, wback, fixedaddress);
+                    FCMPD(v1, v2);
+                    FCOM(x1, x2, x3);
+                    x87_do_pop(dyn, ninst, x3);
+                    break;
+                case 4:
+                    INST_NAME("FSUB ST0, double[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                    VLD64(v2, wback, fixedaddress);
+                    FSUBD(v1, v1, v2);
+                    break;
+                case 5:
+                    INST_NAME("FSUBR ST0, double[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                    VLD64(v2, wback, fixedaddress);
+                    FSUBD(v1, v2, v1);
+                    break;
+                case 6:
+                    INST_NAME("FDIV ST0, double[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                    VLD64(v2, wback, fixedaddress);
+                    FDIVD(v1, v1, v2);
+                    break;
+                case 7:
+                    INST_NAME("FDIVR ST0, double[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                    VLD64(v2, wback, fixedaddress);
+                    FDIVD(v1, v2, v1);
+                    break;
+            }
+    }
+    return addr;
+}

src/dynarec/arm64/dynarec_arm64_dd.c

@@ -0,0 +1,244 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "emu/x87emu_private.h"
+#include "dynarec_native.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_helper.h"
+#include "dynarec_arm64_functions.h"
+
+
+uintptr_t dynarec64_DD(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
+{
+    (void)ip; (void)rep; (void)need_epilog;
+
+    uint8_t nextop = F8;
+    uint8_t ed;
+    int64_t fixedaddress;
+    int unscaled;
+    int v1, v2;
+    int s0;
+    int64_t j64;
+
+    MAYUSE(s0);
+    MAYUSE(v2);
+    MAYUSE(v1);
+    MAYUSE(j64);
+
+    switch(nextop) {
+        case 0xC0:
+        case 0xC1:
+        case 0xC2:
+        case 0xC3:
+        case 0xC4:
+        case 0xC5:
+        case 0xC6:
+        case 0xC7:
+            INST_NAME("FFREE STx");
+            MESSAGE(LOG_DUMP, "Need Optimization\n");
+            x87_purgecache(dyn, ninst, 0, x1, x2, x3);
+            MOV32w(x1, nextop&7);
+            CALL(fpu_do_free, -1);
+            break;
+        case 0xD0:
+        case 0xD1:
+        case 0xD2:
+        case 0xD3:
+        case 0xD4:
+        case 0xD5:
+        case 0xD6:
+        case 0xD7:
+            INST_NAME("FST ST0, STx");
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FMOVS(v2, v1);
+            } else {
+                FMOVD(v2, v1);
+            }
+            break;
+        case 0xD8:
+            INST_NAME("FSTP ST0, ST0");
+            x87_do_pop(dyn, ninst, x3);
+            break;
+        case 0xD9:
+        case 0xDA:
+        case 0xDB:
+        case 0xDC:
+        case 0xDD:
+        case 0xDE:
+        case 0xDF:
+            INST_NAME("FSTP ST0, STx");
+            // copy the cache value for st0 to stx
+            x87_get_st_empty(dyn, ninst, x1, x2, nextop&7, X87_ST(nextop&7));
+            x87_get_st(dyn, ninst, x1, x2, 0, X87_ST0);
+            x87_swapreg(dyn, ninst, x1, x2, 0, nextop&7);
+            x87_do_pop(dyn, ninst, x3);
+            break;
+
+        case 0xE0:
+        case 0xE1:
+        case 0xE2:
+        case 0xE3:
+        case 0xE4:
+        case 0xE5:
+        case 0xE6:
+        case 0xE7:
+            INST_NAME("FUCOM ST0, STx");
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
+            FCOM(x1, x2, x3);
+            break;
+        case 0xE8:
+        case 0xE9:
+        case 0xEA:
+        case 0xEB:
+        case 0xEC:
+        case 0xED:
+        case 0xEE:
+        case 0xEF:
+            INST_NAME("FUCOMP ST0, STx");
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
+            FCOM(x1, x2, x3);
+            x87_do_pop(dyn, ninst, x3);
+            break;
+
+        case 0xC8:
+        case 0xC9:
+        case 0xCA:
+        case 0xCB:
+        case 0xCC:
+        case 0xCD:
+        case 0xCE:
+        case 0xCF:
+        case 0xF0:
+        case 0xF1:
+        case 0xF2:
+        case 0xF3:
+        case 0xF4:
+        case 0xF5:
+        case 0xF6:
+        case 0xF7:
+        case 0xF8:
+        case 0xF9:
+        case 0xFA:
+        case 0xFB:
+        case 0xFC:
+        case 0xFD:
+        case 0xFE:
+        case 0xFF:
+            DEFAULT;
+            break;
+
+        default:
+            switch((nextop>>3)&7) {
+                case 0:
+                    INST_NAME("FLD double");
+                    v1 = x87_do_push(dyn, ninst, x3, NEON_CACHE_ST_D);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                    VLD64(v1, ed, fixedaddress);
+                    break;
+                case 1:
+                    INST_NAME("FISTTP i64, ST0");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                    s0 = fpu_get_scratch(dyn);
+                    #if 0
+                    // those are ARM 8.5 opcode!
+                    FRINT64ZD(s0, v1);
+                    FCVTZSxD(x2, s0);
+                    STRx_U12(x2, ed, fixedaddress);
+                    #else
+                    MRS_fpsr(x5);
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    MSR_fpsr(x5);
+                    FRINTRRD(s0, v1, 3);
+                    FCVTZSxD(x2, s0);
+                    STx(x2, ed, fixedaddress);
+                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                    TBZ_MARK3(x5, FPSR_IOC);
+                    ORRx_mask(x5, xZR, 1, 1, 0);    //0x8000000000000000
+                    STx(x5, ed, fixedaddress);
+                    MARK3;
+                    #endif
+                    x87_do_pop(dyn, ninst, x3);
+                    break;
+                case 2:
+                    INST_NAME("FST double");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                    VST64(v1, ed, fixedaddress);
+                    break;
+                case 3:
+                    INST_NAME("FSTP double");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                    VST64(v1, ed, fixedaddress);
+                    x87_do_pop(dyn, ninst, x3);
+                    break;
+                case 4: 
+                    INST_NAME("FRSTOR m108byte");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                    if(ed!=x1) {MOVx_REG(x1, ed);}
+                    CALL(native_frstor, -1);
+                    break;
+                case 6: 
+                    INST_NAME("FSAVE m108byte");
+                    MESSAGE(LOG_DUMP, "Need Optimization\n");
+                    fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                    if(ed!=x1) {MOVx_REG(x1, ed);}
+                    CALL(native_fsave, -1);
+                    break;
+                case 7:
+                    INST_NAME("FNSTSW m2byte");
+                    fpu_purgecache(dyn, ninst, 0, x1, x2, x3);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x4, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                    LDRw_U12(x2, xEmu, offsetof(x64emu_t, top));
+                    LDRH_U12(x3, xEmu, offsetof(x64emu_t, sw));
+                    if(dyn->n.x87stack) {
+                        // update top
+                        if(dyn->n.x87stack>0) {
+                            SUBw_U12(x2, x2, dyn->n.x87stack);
+                        } else {
+                            ADDw_U12(x2, x2, -dyn->n.x87stack);
+                        }
+                        ANDw_mask(x2, x2, 0, 2);
+                    }
+                    BFIw(x3, x2, 11, 3); // inject TOP at bit 11 (3 bits)
+                    STH(x3, ed, fixedaddress);   // store whole sw flags
+                    break;
+                default:
+                    DEFAULT;
+            }
+    }
+    return addr;
+}

src/dynarec/arm64/dynarec_arm64_de.c

@@ -0,0 +1,285 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "emu/x87emu_private.h"
+#include "dynarec_native.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_helper.h"
+#include "dynarec_arm64_functions.h"
+
+
+uintptr_t dynarec64_DE(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
+{
+    (void)ip; (void)rep; (void)need_epilog;
+
+    uint8_t nextop = F8;
+    uint8_t wback;
+    int64_t fixedaddress;
+    int unscaled;
+    int v1, v2;
+
+    MAYUSE(v2);
+    MAYUSE(v1);
+
+    switch(nextop) {
+        case 0xC0:
+        case 0xC1:
+        case 0xC2:
+        case 0xC3:
+        case 0xC4:
+        case 0xC5:
+        case 0xC6:
+        case 0xC7:
+            INST_NAME("FADDP STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FADDS(v1, v1, v2);
+            } else {
+                FADDD(v1, v1, v2);
+            }
+            x87_do_pop(dyn, ninst, x3);
+            break;
+        case 0xC8:
+        case 0xC9:
+        case 0xCA:
+        case 0xCB:
+        case 0xCC:
+        case 0xCD:
+        case 0xCE:
+        case 0xCF:
+            INST_NAME("FMULP STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FMULS(v1, v1, v2);
+            } else {
+                FMULD(v1, v1, v2);
+            }
+            x87_do_pop(dyn, ninst, x3);
+            break;
+        case 0xD0:
+        case 0xD1:
+        case 0xD2:
+        case 0xD3:
+        case 0xD4:
+        case 0xD5:
+        case 0xD6:
+        case 0xD7:
+            INST_NAME("FCOMP ST0, STx"); //yep
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
+            FCOM(x1, x2, x3);
+            x87_do_pop(dyn, ninst, x3);
+            break;
+        case 0xD9:
+            INST_NAME("FCOMPP ST0, STx");
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
+            FCOM(x1, x2, x3);
+            x87_do_pop(dyn, ninst, x3);
+            x87_do_pop(dyn, ninst, x3);
+            break;
+        case 0xE0:
+        case 0xE1:
+        case 0xE2:
+        case 0xE3:
+        case 0xE4:
+        case 0xE5:
+        case 0xE6:
+        case 0xE7:
+            INST_NAME("FSUBRP STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FSUBS(v1, v2, v1);
+            } else {
+                FSUBD(v1, v2, v1);
+            }
+            x87_do_pop(dyn, ninst, x3);
+            break;
+        case 0xE8:
+        case 0xE9:
+        case 0xEA:
+        case 0xEB:
+        case 0xEC:
+        case 0xED:
+        case 0xEE:
+        case 0xEF:
+            INST_NAME("FSUBP STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FSUBS(v1, v1, v2);
+            } else {
+                FSUBD(v1, v1, v2);
+            }
+            x87_do_pop(dyn, ninst, x3);
+            break;
+        case 0xF0:
+        case 0xF1:
+        case 0xF2:
+        case 0xF3:
+        case 0xF4:
+        case 0xF5:
+        case 0xF6:
+        case 0xF7:
+            INST_NAME("FDIVRP STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FDIVS(v1, v2, v1);
+            } else {
+                FDIVD(v1, v2, v1);
+            }
+            x87_do_pop(dyn, ninst, x3);
+            break;       
+        case 0xF8:
+        case 0xF9:
+        case 0xFA:
+        case 0xFB:
+        case 0xFC:
+        case 0xFD:
+        case 0xFE:
+        case 0xFF:
+            INST_NAME("FDIVP STx, ST0");
+            v2 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v1 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0)) {
+                FDIVS(v1, v1, v2);
+            } else {
+                FDIVD(v1, v1, v2);
+            }
+            x87_do_pop(dyn, ninst, x3);
+            break;
+        case 0xD8:
+        case 0xDA:
+        case 0xDB:
+        case 0xDC:
+        case 0xDD:
+        case 0xDE:
+        case 0xDF:
+            DEFAULT;
+            break;
+        default:
+            switch((nextop>>3)&7) {
+                case 0:
+                    INST_NAME("FIADD ST0, word[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                    VLD16(v2, wback, fixedaddress);
+                    SXTL_16(v2, v2);
+                    SXTL_32(v2, v2);
+                    SCVTFDD(v2, v2);
+                    FADDD(v1, v1, v2);
+                    break;
+                case 1:
+                    INST_NAME("FIMUL ST0, word[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                    VLD16(v2, wback, fixedaddress);
+                    SXTL_16(v2, v2);
+                    SXTL_32(v2, v2);
+                    SCVTFDD(v2, v2);
+                    FMULD(v1, v1, v2);
+                    break;
+                case 2:
+                    INST_NAME("FICOM ST0, word[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                    VLD16(v2, wback, fixedaddress);
+                    SXTL_16(v2, v2);
+                    SXTL_32(v2, v2);
+                    SCVTFDD(v2, v2);
+                    FCMPD(v1, v2);
+                    FCOM(x1, x2, x3);
+                    break;
+                case 3:
+                    INST_NAME("FICOMP ST0, word[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                    VLD16(v2, wback, fixedaddress);
+                    SXTL_16(v2, v2);
+                    SXTL_32(v2, v2);
+                    SCVTFDD(v2, v2);
+                    FCMPD(v1, v2);
+                    FCOM(x1, x2, x3);
+                    x87_do_pop(dyn, ninst, x3);
+                    break;
+                case 4:
+                    INST_NAME("FISUB ST0, word[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                    VLD16(v2, wback, fixedaddress);
+                    SXTL_16(v2, v2);
+                    SXTL_32(v2, v2);
+                    SCVTFDD(v2, v2);
+                    FSUBD(v1, v1, v2);
+                    break;
+                case 5:
+                    INST_NAME("FISUBR ST0, word[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                    VLD16(v2, wback, fixedaddress);
+                    SXTL_16(v2, v2);
+                    SXTL_32(v2, v2);
+                    SCVTFDD(v2, v2);
+                    FSUBD(v1, v2, v1);
+                    break;
+                case 6:
+                    INST_NAME("FIDIV ST0, word[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                    VLD16(v2, wback, fixedaddress);
+                    SXTL_16(v2, v2);
+                    SXTL_32(v2, v2);
+                    SCVTFDD(v2, v2);
+                    FDIVD(v1, v1, v2);
+                    break;
+                case 7:
+                    INST_NAME("FIDIVR ST0, word[ED]");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_D);
+                    v2 = fpu_get_scratch(dyn);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                    VLD16(v2, wback, fixedaddress);
+                    SXTL_16(v2, v2);
+                    SXTL_32(v2, v2);
+                    SCVTFDD(v2, v2);
+                    FDIVD(v1, v2, v1);
+                    break;
+            }
+    }
+    return addr;
+}

src/dynarec/arm64/dynarec_arm64_df.c

@@ -0,0 +1,385 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "emu/x87emu_private.h"
+#include "dynarec_native.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_helper.h"
+#include "dynarec_arm64_functions.h"
+
+
+uintptr_t dynarec64_DF(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
+{
+    (void)ip; (void)rep; (void)need_epilog;
+
+    uint8_t nextop = F8;
+    uint8_t ed, wback, u8;
+    int v1, v2;
+    int s0;
+    int64_t j64;
+    int64_t fixedaddress;
+    int unscaled;
+
+    MAYUSE(s0);
+    MAYUSE(v2);
+    MAYUSE(v1);
+    MAYUSE(j64);
+
+    switch(nextop) {
+        case 0xC0:
+        case 0xC1:
+        case 0xC2:
+        case 0xC3:
+        case 0xC4:
+        case 0xC5:
+        case 0xC6:
+        case 0xC7:
+            INST_NAME("FFREEP STx");
+            // not handling Tag...
+            x87_do_pop(dyn, ninst, x3);
+            break;
+
+        case 0xE0:
+            INST_NAME("FNSTSW AX");
+            LDRw_U12(x2, xEmu, offsetof(x64emu_t, top));
+            LDRH_U12(x1, xEmu, offsetof(x64emu_t, sw));
+            BFIw(x1, x2, 11, 3); // inject top
+            STRH_U12(x1, xEmu, offsetof(x64emu_t, sw));
+            BFIx(xRAX, x1, 0, 16);
+            break;
+        case 0xE8:
+        case 0xE9:
+        case 0xEA:
+        case 0xEB:
+        case 0xEC:
+        case 0xED:
+        case 0xEE:
+        case 0xEF:
+            INST_NAME("FUCOMIP ST0, STx");
+            SETFLAGS(X_ALL, SF_SET);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0))
+            {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
+            FCOMI(x1, x2);
+            x87_do_pop(dyn, ninst, x3);
+            break;
+        case 0xF0:
+        case 0xF1:
+        case 0xF2:
+        case 0xF3:
+        case 0xF4:
+        case 0xF5:
+        case 0xF6:
+        case 0xF7:
+            INST_NAME("FCOMIP ST0, STx");
+            SETFLAGS(X_ALL, SF_SET);
+            v1 = x87_get_st(dyn, ninst, x1, x2, 0, X87_COMBINE(0, nextop&7));
+            v2 = x87_get_st(dyn, ninst, x1, x2, nextop&7, X87_COMBINE(0, nextop&7));
+            if(ST_IS_F(0))
+            {
+                FCMPS(v1, v2);
+            } else {
+                FCMPD(v1, v2);
+            }
+            FCOMI(x1, x2);
+            x87_do_pop(dyn, ninst, x3);
+            break;
+
+        case 0xC8:
+        case 0xC9:
+        case 0xCA:
+        case 0xCB:
+        case 0xCC:
+        case 0xCD:
+        case 0xCE:
+        case 0xCF:
+        case 0xD0:
+        case 0xD1:
+        case 0xD2:
+        case 0xD3:
+        case 0xD4:
+        case 0xD5:
+        case 0xD6:
+        case 0xD7:
+        case 0xD8:
+        case 0xD9:
+        case 0xDA:
+        case 0xDB:
+        case 0xDC:
+        case 0xDD:
+        case 0xDE:
+        case 0xDF:
+        case 0xE1:
+        case 0xE2:
+        case 0xE3:
+        case 0xE4:
+        case 0xE5:
+        case 0xE6:
+        case 0xE7:
+        case 0xF8:
+        case 0xF9:
+        case 0xFA:
+        case 0xFB:
+        case 0xFC:
+        case 0xFD:
+        case 0xFE:
+        case 0xFF:
+            DEFAULT;
+            break;
+
+        default:
+            switch((nextop>>3)&7) {
+                case 0:
+                    INST_NAME("FILD ST0, Ew");
+                    v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_F);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                    LDSHw(x1, wback, fixedaddress);
+                    if(ST_IS_F(0)) {
+                        SCVTFSw(v1, x1);
+                    } else {
+                        SCVTFDw(v1, x1);
+                    }
+                    break;
+                case 1:
+                    INST_NAME("FISTTP Ew, ST0");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                    ed = x1;
+                    s0 = fpu_get_scratch(dyn);
+                    #if 0
+                    // this version needs ARM v8.5, //TODO: add detection of this extension to use it
+                    FRINT32ZD(s0, v1);
+                    // no saturation instruction on Arm, so using NEON
+                    VFCVTZSd(s0, s0);
+                    SQXTN_S_D(s0, s0);
+                    SQXTN_H_S(s0, s0);
+                    VST16(s0, wback, fixedaddress);
+                    #else
+                    MRS_fpsr(x5);
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    BFCw(x5, FPSR_QC, 1);   // reset QC bit
+                    MSR_fpsr(x5);
+                    if(ST_IS_F(0)) {
+                        VFCVTZSs(s0, v1);
+                    } else {
+                        VFCVTZSd(s0, v1);
+                        SQXTN_S_D(s0, s0);
+                    }
+                    VMOVSto(x3, s0, 0);
+                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                    TBNZ_MARK2(x5, FPSR_IOC);
+                    SXTHw(x5, x3);  // check if 16bits value is fine
+                    SUBw_REG(x5, x5, x3);
+                    CBZw_MARK3(x5);
+                    MARK2;
+                    MOV32w(x3, 0x8000);
+                    MARK3;
+                    STH(x3, wback, fixedaddress);
+                    #endif
+                    x87_do_pop(dyn, ninst, x3);
+                    break;
+                case 2:
+                    INST_NAME("FIST Ew, ST0");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
+                    u8 = x87_setround(dyn, ninst, x1, x2, x4);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                    ed = x1;
+                    s0 = fpu_get_scratch(dyn);
+                    #if 0
+                    FRINT32XD(s0, v1);
+                    // no saturation instruction on Arm, so using NEON
+                    VFCVTZSd(s0, s0);
+                    SQXTN_S_D(s0, s0);
+                    SQXTN_H_S(s0, s0);
+                    VST16(s0, wback, fixedaddress);
+                    #else
+                    MRS_fpsr(x5);
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    BFCw(x5, FPSR_QC, 1);   // reset QC bit
+                    MSR_fpsr(x5);
+                    if(ST_IS_F(0)) {
+                        FRINTXS(s0, v1);
+                        VFCVTZSs(s0, s0);
+                    } else {
+                        FRINTXD(s0, v1);
+                        VFCVTZSd(s0, s0);
+                        SQXTN_S_D(s0, s0);
+                    }
+                    VMOVSto(x3, s0, 0);
+                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                    TBNZ_MARK2(x5, FPSR_IOC);
+                    SXTHw(x5, x3);  // check if 16bits value is fine
+                    SUBw_REG(x5, x5, x3);
+                    CBZw_MARK3(x5);
+                    MARK2;
+                    MOV32w(x3, 0x8000);
+                    MARK3;
+                    STH(x3, wback, fixedaddress);
+                    #endif
+                    x87_restoreround(dyn, ninst, u8);
+                    break;
+                case 3:
+                    INST_NAME("FISTP Ew, ST0");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_F);
+                    u8 = x87_setround(dyn, ninst, x1, x2, x4);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<1, 1, rex, NULL, 0, 0);
+                    ed = x1;
+                    s0 = fpu_get_scratch(dyn);
+                    #if 0
+                    FRINT32XD(s0, v1);
+                    // no saturation instruction on Arm, so using NEON
+                    VFCVTZSd(s0, s0);
+                    SQXTN_S_D(s0, s0);
+                    SQXTN_H_S(s0, s0);
+                    VST16(s0, wback, fixedaddress);
+                    #else
+                    MRS_fpsr(x5);
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    MSR_fpsr(x5);
+                    if(ST_IS_F(0)) {
+                        FRINTXS(s0, v1);
+                        VFCVTZSs(s0, s0);
+                    } else {
+                        FRINTXD(s0, v1);
+                        VFCVTZSd(s0, s0);
+                        SQXTN_S_D(s0, s0);
+                    }
+                    VMOVSto(x3, s0, 0);
+                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                    TBNZ_MARK2(x5, FPSR_IOC);
+                    SXTHw(x5, x3);  // check if 16bits value is fine
+                    SUBw_REG(x5, x5, x3);
+                    CBZw_MARK3(x5);
+                    MARK2;
+                    MOV32w(x3, 0x8000);
+                    MARK3;
+                    STH(x3, wback, fixedaddress);
+                    #endif
+                    x87_do_pop(dyn, ninst, x3);
+                    x87_restoreround(dyn, ninst, u8);
+                    break;
+                case 4:
+                    INST_NAME("FBLD ST0, tbytes");
+                    x87_do_push_empty(dyn, ninst, x1);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                    if(ed!=x1) {MOVx_REG(x1, ed);}
+                    CALL(fpu_fbld, -1);
+                    break;
+                case 5:
+                    INST_NAME("FILD ST0, i64");
+                    v1 = x87_do_push(dyn, ninst, x1, NEON_CACHE_ST_I64);
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x3, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                    VLD64(v1, wback, fixedaddress);
+                    if(!ST_IS_I64(0)) {
+                        if(rex.is32bits) {
+                            // need to also feed the STll stuff...
+                            ADDx_U12(x4, xEmu, offsetof(x64emu_t, fpu_ll));
+                            LDRw_U12(x1, xEmu, offsetof(x64emu_t, top));
+                            int a = 0 - dyn->n.x87stack;
+                            if(a) {
+                                if(a<0) {
+                                    SUBw_U12(x1, x1, -a);
+                                } else {
+                                    ADDw_U12(x1, x1, a);
+                                }
+                                ANDw_mask(x1, x1, 0, 2); //mask=7
+                            }
+                            ADDx_REG_LSL(x1, x4, x1, 4);    // fpu_ll is 2 i64
+                            VSTR64_U12(v1, x1, 8);  // ll
+                        }
+                        SCVTFDD(v1, v1);
+                        if(rex.is32bits) {
+                            VSTR64_U12(v1, x1, 0);  // ref
+                        }
+                    }
+                    break;
+                case 6:
+                    INST_NAME("FBSTP tbytes, ST0");
+                    x87_forget(dyn, ninst, x1, x2, 0);
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                    if(ed!=x1) {MOVx_REG(x1, ed);}
+                    CALL(fpu_fbst, -1);
+                    x87_do_pop(dyn, ninst, x3);
+                    break;
+                case 7:
+                    INST_NAME("FISTP i64, ST0");
+                    v1 = x87_get_st(dyn, ninst, x1, x2, 0, NEON_CACHE_ST_I64);
+                    if(!ST_IS_I64(0)) {
+                        u8 = x87_setround(dyn, ninst, x1, x2, x4);
+                    }
+                    addr = geted(dyn, addr, ninst, nextop, &wback, x2, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                    ed = x1;
+                    s0 = fpu_get_scratch(dyn);
+                    if(ST_IS_I64(0)) {
+                        VST64(v1, wback, fixedaddress);
+                    } else {
+                        #if 0
+                        FRINT64XD(s0, v1);
+                        VFCVTZSd(s0, s0);
+                        VSTR64_U12(s0, wback, fixedaddress);
+                        #else
+                        if(rex.is32bits) {
+                            // need to check STll first...
+                            ADDx_U12(x5, xEmu, offsetof(x64emu_t, fpu_ll));
+                            LDRw_U12(x1, xEmu, offsetof(x64emu_t, top));
+                            VMOVQDto(x3, v1, 0);
+                            int a = 0 - dyn->n.x87stack;
+                            if(a) {
+                                if(a<0) {
+                                    SUBw_U12(x1, x1, -a);
+                                } else {
+                                    ADDw_U12(x1, x1, a);
+                                }
+                                ANDw_mask(x1, x1, 0, 2); //mask=7
+                            }
+                            ADDx_REG_LSL(x1, x5, x1, 4);    // fpu_ll is 2 i64
+                            LDRx_U12(x5, x1, 0);  // ref
+                            SUBx_REG(x5, x5, x3);
+                            CBNZx_MARK2(x5);
+                            LDRx_U12(x5, x1, 8);  // ll
+                            STx(x5, wback, fixedaddress);
+                            B_MARK3(c__);
+                            MARK2;
+                        }
+                        MRS_fpsr(x5);
+                        BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                        MSR_fpsr(x5);
+                        FRINTXD(s0, v1);
+                        VFCVTZSd(s0, s0);
+                        VST64(s0, wback, fixedaddress);
+                        MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                        TBZ_MARK3(x5, FPSR_IOC);
+                        ORRx_mask(x5, xZR, 1, 1, 0);    //0x8000000000000000
+                        STx(x5, wback, fixedaddress);
+                        MARK3;
+                        #endif
+                        x87_restoreround(dyn, ninst, u8);
+                    }
+                    x87_do_pop(dyn, ninst, x3);
+                    break;
+                default:
+                    DEFAULT;
+            }
+    }
+    return addr;
+}

src/dynarec/arm64/dynarec_arm64_emit_logic.c

@@ -1,7 +1,6 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <stddef.h>
-#include <pthread.h>
 #include <errno.h>
 
 #include "debug.h"
@@ -15,20 +14,18 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
-#include "../tools/bridge_private.h"
+#include "dynarec_native.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_functions.h"
 #include "dynarec_arm64_helper.h"
 
-// emit OR32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+// emit OR32 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_or32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
-        STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_or64:d_or32);
     } else IFX(X_ALL) {
         SET_DFNONE(s4);
@@ -48,7 +45,7 @@ void emit_or32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3,
     }
     IFX(X_SF) {
         LSRxw(s3, s1, (rex.w)?63:31);
-        BFIx(xFlags, s3, F_SF, 1);
+        BFIw(xFlags, s3, F_SF, 1);
     }
     IFX(X_PF) {
         emit_pf(dyn, ninst, s1, s3, s4);
@@ -59,14 +56,11 @@ void emit_or32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3,
 void emit_or32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, int s3, int s4)
 {
     IFX(X_PEND) {
-        MOV64xw(s3, c);
-        STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_or64:d_or32);
     } else IFX(X_ALL) {
         SET_DFNONE(s4);
     }
-    IFX(X_PEND) {} else {MOV64xw(s3, c);}
+    MOV64xw(s3, c);
     ORRxw_REG(s1, s1, s3);
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
@@ -82,19 +76,18 @@ void emit_or32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, int
     }
     IFX(X_SF) {
         LSRxw(s3, s1, (rex.w)?63:31);
-        BFIx(xFlags, s3, F_SF, 1);
+        BFIw(xFlags, s3, F_SF, 1);
     }
     IFX(X_PF) {
         emit_pf(dyn, ninst, s1, s3, s4);
     }
 }
 
-// emit XOR32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+// emit XOR32 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_xor32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
-        STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_xor64:d_xor32);
     } else IFX(X_ALL) {
         SET_DFNONE(s4);
@@ -114,7 +107,7 @@ void emit_xor32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     }
     IFX(X_SF) {
         LSRxw(s3, s1, (rex.w)?63:31);
-        BFIx(xFlags, s3, F_SF, 1);
+        BFIw(xFlags, s3, F_SF, 1);
     }
     IFX(X_PF) {
         emit_pf(dyn, ninst, s1, s3, s4);
@@ -125,14 +118,11 @@ void emit_xor32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
 void emit_xor32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, int s3, int s4)
 {
     IFX(X_PEND) {
-        MOV64xw(s3, c);
-        STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_xor64:d_xor32);
     } else IFX(X_ALL) {
         SET_DFNONE(s4);
     }
-    IFX(X_PEND) {} else {MOV64xw(s3, c);}
+    MOV64xw(s3, c);
     EORxw_REG(s1, s1, s3);
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
@@ -148,19 +138,18 @@ void emit_xor32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
     }
     IFX(X_SF) {
         LSRxw(s3, s1, (rex.w)?63:31);
-        BFIx(xFlags, s3, F_SF, 1);
+        BFIw(xFlags, s3, F_SF, 1);
     }
     IFX(X_PF) {
         emit_pf(dyn, ninst, s1, s3, s4);
     }
 }
 
-// emit AND32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+// emit AND32 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_and32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
-        STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_and64:d_and32);
     } else IFX(X_ALL) {
         SET_DFNONE(s4);
@@ -183,7 +172,7 @@ void emit_and32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     }
     IFX(X_SF) {
         LSRxw(s3, s1, (rex.w)?63:31);
-        BFIx(xFlags, s3, F_SF, 1);
+        BFIw(xFlags, s3, F_SF, 1);
     }
     IFX(X_PF) {
         emit_pf(dyn, ninst, s1, s3, s4);
@@ -194,14 +183,11 @@ void emit_and32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
 void emit_and32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, int s3, int s4)
 {
     IFX(X_PEND) {
-        MOV64xw(s3, c);
-        STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, rex.w?d_and64:d_and32);
     } else IFX(X_ALL) {
         SET_DFNONE(s4);
     }
-    IFX(X_PEND) {} else {MOV64xw(s3, c);}
+    MOV64xw(s3, c);
     IFX(X_ALL) {
         ANDSxw_REG(s1, s1, s3);
     } else {
@@ -220,19 +206,18 @@ void emit_and32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
     }
     IFX(X_SF) {
         LSRxw(s3, s1, (rex.w)?63:31);
-        BFIx(xFlags, s3, F_SF, 1);
+        BFIw(xFlags, s3, F_SF, 1);
     }
     IFX(X_PF) {
         emit_pf(dyn, ninst, s1, s3, s4);
     }
 }
 
-// emit OR8 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
+// emit OR8 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
 void emit_or8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
-        STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_or8);
     } else IFX(X_ALL) {
         SET_DFNONE(s3);
@@ -264,8 +249,6 @@ void emit_or8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
 {
     MOV32w(s3, c&0xff);
     IFX(X_PEND) {
-        STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRB_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_or8);
     } else IFX(X_ALL) {
         SET_DFNONE(s4);
@@ -292,12 +275,11 @@ void emit_or8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
     }
 }
 
-// emit XOR8 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
+// emit XOR8 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
 void emit_xor8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
-        STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_xor8);
     } else IFX(X_ALL) {
         SET_DFNONE(s3);
@@ -329,8 +311,6 @@ void emit_xor8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4
 {
     MOV32w(s3, c&0xff);
     IFX(X_PEND) {
-        STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRB_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_xor8);
     } else IFX(X_ALL) {
         SET_DFNONE(s4);
@@ -357,12 +337,11 @@ void emit_xor8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4
     }
 }
 
-// emit AND8 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
+// emit AND8 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
 void emit_and8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
-        STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_and8);
     } else IFX(X_ALL) {
         SET_DFNONE(s3);
@@ -397,8 +376,6 @@ void emit_and8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4
 {
     MOV32w(s3, c&0xff);
     IFX(X_PEND) {
-        STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRB_U12(s3, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s4, d_and8);
     } else IFX(X_ALL) {
         SET_DFNONE(s4);
@@ -429,12 +406,11 @@ void emit_and8c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4
 }
 
 
-// emit OR16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
+// emit OR16 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
 void emit_or16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
-        STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_or16);
     } else IFX(X_ALL) {
         SET_DFNONE(s3);
@@ -507,12 +483,11 @@ void emit_or16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 //    }
 //}
 
-// emit XOR16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
+// emit XOR16 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
 void emit_xor16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
-        STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_xor16);
     } else IFX(X_ALL) {
         SET_DFNONE(s3);
@@ -585,12 +560,11 @@ void emit_xor16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 //    }
 //}
 
-// emit AND16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
+// emit AND16 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch, s4 can be same as s2 (and so s2 destroyed)
 void emit_and16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
-        STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_and16);
     } else IFX(X_ALL) {
         SET_DFNONE(s3);
@@ -603,9 +577,6 @@ void emit_and16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     IFX(X_PEND) {
         STRH_U12(s1, xEmu, offsetof(x64emu_t, res));
     }
-    IFX(X_PEND) {
-        STRB_U12(s1, xEmu, offsetof(x64emu_t, res));
-    }
     IFX(X_CF | X_AF | X_OF) {
         MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
         BICw_REG(xFlags, xFlags, s3);
@@ -667,4 +638,4 @@ void emit_and16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 //    IFX(X_PF) {
 //        emit_pf(dyn, ninst, s1, s3, s4);
 //    }
-//}
+//}

src/dynarec/arm64/dynarec_arm64_emit_math.c

@@ -1,7 +1,6 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <stddef.h>
-#include <pthread.h>
 #include <errno.h>
 
 #include "debug.h"
@@ -15,17 +14,17 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
-#include "../tools/bridge_private.h"
+#include "dynarec_native.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_functions.h"
 #include "dynarec_arm64_helper.h"
 
-// emit ADD32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+// emit ADD32 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_add32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -51,21 +50,17 @@ void emit_add32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         LSRxw(s4, s3, 3);
         BFIxw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
     }
-    IFX(X_ZF|X_CF|X_OF) {
-        MOV32w(s3, (1<<F_ZF)|(1<<F_CF)|(1<<F_OF));
-        BICx(xFlags, xFlags, s3);
-    }
     IFX(X_ZF) {
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_CF) {
-        Bcond(cCC, +8);
-        ORRw_mask(xFlags, xFlags, 0, 0);    // mask=0x01
+        CSETw(s4, cCS);
+        BFIw(xFlags, s4, F_CF, 1);
     }
     IFX(X_OF) {
-        Bcond(cVC, +8);
-        ORRw_mask(xFlags, xFlags, 0b010101, 0);  // mask=0x800
+        CSETw(s4, cVS);
+        BFIw(xFlags, s4, F_OF, 1);
     }
     IFX(X_SF) {
         LSRxw(s3, s1, (rex.w)?63:31);
@@ -76,10 +71,11 @@ void emit_add32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     }
 }
 
-// emit ADD32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+// emit ADD32 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
 void emit_add32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, int s3, int s4, int s5)
 {
-    if(s1==xRSP && (!dyn->insts || dyn->insts[ninst].x64.need_flags==X_PEND))
+    MAYUSE(s5);
+    if(s1==xRSP && (!dyn->insts || dyn->insts[ninst].x64.gen_flags==X_PEND))
     {
         // special case when doing math on ESP and only PEND is needed: ignoring it!
         if(c>=0 && c<0x1000) {
@@ -126,21 +122,17 @@ void emit_add32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
         LSRxw(s4, s3, 3);
         BFIxw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
     }
-    IFX(X_ZF|X_CF|X_OF) {
-        MOV32w(s3, (1<<F_ZF)|(1<<F_CF)|(1<<F_OF));
-        BICx(xFlags, xFlags, s3);
-    }
     IFX(X_ZF) {
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_CF) {
-        Bcond(cCC, +8);
-        ORRw_mask(xFlags, xFlags, 0, 0);    // mask=0x01
+        CSETw(s4, cCS);
+        BFIw(xFlags, s4, F_CF, 1);
     }
     IFX(X_OF) {
-        Bcond(cVC, +8);
-        ORRw_mask(xFlags, xFlags, 0b010101, 0);  // mask=0x800
+        CSETw(s4, cVS);
+        BFIw(xFlags, s4, F_OF, 1);
     }
     IFX(X_SF) {
         LSRxw(s3, s1, (rex.w)?63:31);
@@ -151,9 +143,10 @@ void emit_add32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
     }
 }
 
-// emit SUB32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+// emit SUB32 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_sub32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -162,8 +155,7 @@ void emit_sub32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         SET_DFNONE(s3);
     }
     IFX(X_AF) {
-        MVNxw_REG(s3, s1);
-        ORRxw_REG(s3, s3, s2);  // s3 = ~op1 | op2
+        ORNxw_REG(s3, s2, s1);  // s3 = ~op1 | op2
         BICxw(s4, s2, s1);      // s4 = ~op1 & op2
     }
     IFX(X_ALL) {
@@ -180,22 +172,18 @@ void emit_sub32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         LSRxw(s4, s3, 3);
         BFIx(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
     }
-    IFX(X_ZF|X_CF|X_OF) {
-        MOV32w(s3, (1<<F_ZF)|(1<<F_CF)|(1<<F_OF));
-        BICx(xFlags, xFlags, s3);
-    }
     IFX(X_ZF) {
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_CF) {
         // inverted carry
-        Bcond(cCS, +8);
-        ORRw_mask(xFlags, xFlags, 0, 0);    // mask=0x01
+        CSETw(s4, cCC);
+        BFIw(xFlags, s4, F_CF, 1);
     }
     IFX(X_OF) {
-        Bcond(cVC, +8);
-        ORRw_mask(xFlags, xFlags, 0b010101, 0);  // mask=0x800
+        CSETw(s4, cVS);
+        BFIw(xFlags, s4, F_OF, 1);
     }
     IFX(X_SF) {
         LSRxw(s3, s1, (rex.w)?63:31);
@@ -206,10 +194,11 @@ void emit_sub32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     }
 }
 
-// emit SUB32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+// emit SUB32 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
 void emit_sub32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, int s3, int s4, int s5)
 {
-    if(s1==xRSP && (!dyn->insts || dyn->insts[ninst].x64.need_flags==X_PEND))
+    MAYUSE(s5);
+    if(s1==xRSP && (!dyn->insts || dyn->insts[ninst].x64.gen_flags==X_PEND))
     {
         // special case when doing math on RSP and only PEND is needed: ignoring it!
         if(c>=0 && c<0x1000) {
@@ -256,22 +245,18 @@ void emit_sub32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
         LSRxw(s4, s3, 3);
         BFIw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
     }
-    IFX(X_ZF|X_CF|X_OF) {
-        MOV32w(s3, (1<<F_ZF)|(1<<F_CF)|(1<<F_OF));
-        BICx(xFlags, xFlags, s3);
-    }
     IFX(X_ZF) {
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_CF) {
         // inverted carry
-        Bcond(cCS, +8);
-        ORRw_mask(xFlags, xFlags, 0, 0);    // mask=0x01
+        CSETw(s4, cCC);
+        BFIw(xFlags, s4, F_CF, 1);
     }
     IFX(X_OF) {
-        Bcond(cVC, +8);
-        ORRw_mask(xFlags, xFlags, 0b010101, 0);  // mask=0x800
+        CSETw(s4, cVS);
+        BFIw(xFlags, s4, F_OF, 1);
     }
     IFX(X_SF) {
         LSRxw(s3, s1, (rex.w)?63:31);
@@ -282,9 +267,10 @@ void emit_sub32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int64_t c, in
     }
 }
 
-// emit ADD8 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit ADD8 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_add8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -331,7 +317,7 @@ void emit_add8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     }
 }
 
-// emit ADD8 instruction, from s1 , const c, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit ADD8 instruction, from s1, const c, store result in s1 using s3 and s4 as scratch
 void emit_add8c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
 {
     IFX(X_PEND) {
@@ -383,9 +369,10 @@ void emit_add8c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
     }
 }
 
-// emit SUB8 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit SUB8 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_sub8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -434,15 +421,16 @@ void emit_sub8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     }
 }
 
-// emit SUB8 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+// emit SUB8 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
 void emit_sub8c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4, int s5)
 {
+    MAYUSE(s5);
     IFX(X_ALL|X_PEND) {
         MOV32w(s5, c&0xff);
     }
     IFX(X_PEND) {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRB_U12(s3, xEmu, offsetof(x64emu_t, op2));
+        STRB_U12(s5, xEmu, offsetof(x64emu_t, op2));
         SET_DF(s3, d_sub8);
     } else IFX(X_ALL) {
         SET_DFNONE(s3);
@@ -491,9 +479,10 @@ void emit_sub8c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4, in
     }
 }
 
-// emit ADD16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit ADD16 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_add16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -541,7 +530,7 @@ void emit_add16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     }
 }
 
-// emit ADD16 instruction, from s1 , const c, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit ADD16 instruction, from s1, const c, store result in s1 using s3 and s4 as scratch
 //void emit_add16c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
@@ -608,9 +597,10 @@ void emit_add16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 //    }
 //}
 
-// emit SUB16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit SUB16 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_sub16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -619,8 +609,7 @@ void emit_sub16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
         SET_DFNONE(s3);
     }
     IFX(X_AF|X_OF|X_CF) {
-        MVNw_REG(s3, s1);
-        ORRw_REG(s3, s3, s2);    // s3 = ~op1 | op2
+        ORNw_REG(s3, s2, s1);    // s3 = ~op1 | op2
         BICw_REG(s4, s2, s1);    // s4 = ~op1 & op2
     }
 
@@ -659,7 +648,7 @@ void emit_sub16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     }
 }
 
-// emit SUB16 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+// emit SUB16 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
 //void emit_sub16c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
@@ -756,17 +745,13 @@ void emit_inc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4
         LSRxw(s4, s3, 3);
         BFIxw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
     }
-    IFX(X_ZF|X_OF) {
-        MOV32w(s3, (1<<F_ZF)|(1<<F_OF));
-        BICx(xFlags, xFlags, s3);
-    }
     IFX(X_ZF) {
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_OF) {
-        Bcond(cVC, +8);
-        ORRw_mask(xFlags, xFlags, 0b010101, 0);  // mask=0x800
+        CSETw(s4, cVS);
+        BFIw(xFlags, s4, F_OF, 1);
     }
     IFX(X_SF) {
         LSRxw(s3, s1, rex.w?63:31);
@@ -777,7 +762,7 @@ void emit_inc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4
     }
 }
 
-// emit INC8 instruction, from s1, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit INC8 instruction, from s1, store result in s1 using s3 and s4 as scratch
 void emit_inc8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
 {
     IFX(X_PEND) {
@@ -822,7 +807,7 @@ void emit_inc8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
     }
 }
 
-// emit INC16 instruction, from s1 , store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit INC16 instruction, from s1, store result in s1 using s3 and s4 as scratch
 void emit_inc16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
 {
     IFX(X_PEND) {
@@ -900,17 +885,13 @@ void emit_dec32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int s4
         LSRxw(s4, s3, 3);
         BFIw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
     }
-    IFX(X_ZF|X_OF) {
-        MOV32w(s3, (1<<F_ZF)|(1<<F_OF));
-        BICx(xFlags, xFlags, s3);
-    }
     IFX(X_ZF) {
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_OF) {
-        Bcond(cVC, +8);
-        ORRw_mask(xFlags, xFlags, 0b010101, 0);  // mask=0x800
+        CSETw(s4, cVS);
+        BFIw(xFlags, s4, F_OF, 1);
     }
     IFX(X_SF) {
         LSRxw(s3, s1, rex.w?63:31);
@@ -935,7 +916,11 @@ void emit_dec8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
         ANDw_mask(s4, s3, 0, 0);        // s4 = ~op1 & op2
         ORRw_mask(s3, s3, 0, 0);     // s3 = ~op1 | op2
     }
-    SUBSw_U12(s1, s1, 1);
+    IFX(X_ZF) {
+        SUBSw_U12(s1, s1, 1);
+    } else {
+        SUBw_U12(s1, s1, 1);
+    }
     IFX(X_PEND) {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, res));
     }
@@ -977,7 +962,11 @@ void emit_dec16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
     IFX(X_AF|X_OF) {
         MVNw_REG(s4, s1);
     }
-    SUBSw_U12(s1, s1, 1);
+    IFX(X_ZF) {
+        SUBSw_U12(s1, s1, 1);
+    } else {
+        SUBw_U12(s1, s1, 1);
+    }
     IFX(X_PEND) {
         STRH_U12(s1, xEmu, offsetof(x64emu_t, res));
     }
@@ -1009,9 +998,10 @@ void emit_dec16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
     }
 }
 
-// emit ADC32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+// emit ADC32 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_adc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -1062,7 +1052,7 @@ void emit_adc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     }
 }
 
-// emit ADC32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+// emit ADC32 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
 //void emit_adc32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
@@ -1132,9 +1122,10 @@ void emit_adc32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
 //    }
 //}
 
-// emit ADC8 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit ADC8 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_adc8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -1185,63 +1176,18 @@ void emit_adc8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     }
 }
 
-// emit ADC8 instruction, from s1 , const c, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit ADC8 instruction, from s1, const c, store result in s1 using s3 and s4 as scratch
 void emit_adc8c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4, int s5)
 {
+    MAYUSE(s5);
     MOV32w(s5, c&0xff);
-    IFX(X_PEND) {
-        STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRB_U12(s5, xEmu, offsetof(x64emu_t, op2));
-        SET_DF(s4, d_adc8);
-    } else IFX(X_ALL) {
-        SET_DFNONE(s4);
-    }
-    IFX(X_AF | X_OF) {
-        MOVw_REG(s4, s1);
-    }
-    MRS_nzvc(s3);
-    BFIx(s3, xFlags, 29, 1); // set C
-    MSR_nzvc(s3);      // load CC into ARM CF
-    ADCw_REG(s1, s1, s5);
-    IFX(X_PEND) {
-        STRH_U12(s1, xEmu, offsetof(x64emu_t, res));
-    }
-    IFX(X_AF|X_OF) {
-        ORRw_REG(s3, s4, s5);        // s3 = op1 | op2
-        ANDw_REG(s4, s4, s5);        // s4 = op1 & op2
-        BICw_REG(s3, s3, s1);   // s3 = (op1 | op2) & ~ res
-        ORRw_REG(s3, s3, s4);   // s4 = (op1 & op2) | ((op1 | op2) & ~ res)
-        IFX(X_AF) {
-            LSRw(s4, s3, 3);
-            BFIw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
-        }
-        IFX(X_OF) {
-            LSRw(s4, s3, 6);
-            EORw_REG_LSR(s4, s4, s4, 1);
-            BFIw(xFlags, s4, F_OF, 1);    // OF: ((bc >> 6) ^ ((bc>>6)>>1)) & 1
-        }
-    }
-    IFX(X_CF) {
-        LSRw(s3, s1, 8);
-        BFIw(xFlags, s3, F_CF, 1);
-    }
-    IFX(X_ZF) {
-        ANDSw_mask(s1, s1, 0, 0b000111);    //mask=000000ff
-        CSETw(s3, cEQ);
-        BFIw(xFlags, s3, F_ZF, 1);
-    }
-    IFX(X_SF) {
-        LSRw(s3, s1, 7);
-        BFIw(xFlags, s3, F_SF, 1);
-    }
-    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
-    }
+    emit_adc8(dyn, ninst, s1, s5, s3, s4);
 }
 
-// emit ADC16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit ADC16 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_adc16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -1257,7 +1203,7 @@ void emit_adc16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     MSR_nzvc(s3);      // load CC into ARM CF
     ADCw_REG(s1, s1, s2);
     IFX(X_PEND) {
-        STRH_U12(s1, xEmu, offsetof(x64emu_t, res));
+        STRw_U12(s1, xEmu, offsetof(x64emu_t, res));
     }
     IFX(X_AF|X_OF) {
         ORRw_REG(s3, s4, s2);    // s3 = op1 | op2
@@ -1292,7 +1238,7 @@ void emit_adc16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     }
 }
 
-// emit ADC16 instruction, from s1 , const c, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit ADC16 instruction, from s1, const c, store result in s1 using s3 and s4 as scratch
 //void emit_adc16c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
@@ -1359,9 +1305,10 @@ void emit_adc16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 //    }
 //}
 
-// emit SBB32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch
+// emit SBB32 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_sbb32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -1414,7 +1361,7 @@ void emit_sbb32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     }
 }
 
-// emit SBB32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+// emit SBB32 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
 //void emit_sbb32c(dynarec_arm_t* dyn, int ninst, int s1, int32_t c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
@@ -1486,9 +1433,10 @@ void emit_sbb32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
 //    }
 //}
 
-// emit SBB8 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit SBB8 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_sbb8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -1540,64 +1488,18 @@ void emit_sbb8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     }
 }
 
-// emit SBB8 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+// emit SBB8 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
 void emit_sbb8c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4, int s5)
 {
+    MAYUSE(s5);
     MOV32w(s5, c&0xff);
-    IFX(X_PEND) {
-        STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
-        STRB_U12(s5, xEmu, offsetof(x64emu_t, op2));
-        SET_DF(s3, d_sbb8);
-    } else IFX(X_ALL) {
-        SET_DFNONE(s3);
-    }
-    EORw_mask(s4, xFlags, 0, 0);            // invert CC because it's reverted for SUB on ARM
-    MRS_nzvc(s3);
-    BFIx(s3, s4, 29, 1); // set C, bit 29
-    MSR_nzvc(s3);      // load CC into ARM CF
-    IFX(X_AF|X_OF|X_CF) {
-        MVNw_REG(s4, s1);
-    }
-    SBCw_REG(s1, s1, s5);
-    IFX(X_PEND) {
-        STRB_U12(s1, xEmu, offsetof(x64emu_t, res));
-    }
-    IFX(X_AF|X_OF|X_CF) {
-        ORRw_REG(s3, s4, s5);               // s3 = ~op1 | op2
-        ANDw_REG(s4, s4, s5);               // s4 = ~op1 & op2
-        ANDw_REG(s3, s3, s1);               // s3 = (~op1 | op2) & res
-        ORRw_REG(s3, s3, s4);               // s3 = (~op1 & op2) | ((~op1 | op2) & res)
-        IFX(X_CF) {
-            LSRw(s4, s3, 7);
-            BFIw(xFlags, s4, F_CF, 1);    // CF : bc & 0x80
-        }
-        IFX(X_AF) {
-            LSRw(s4, s3, 3);
-            BFIw(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
-        }
-        IFX(X_OF) {
-            LSRw(s4, s3, 6);
-            EORw_REG_LSR(s4, s4, s4, 1);
-            BFIw(xFlags, s4, F_OF, 1);    // OF: ((bc >> 6) ^ ((bc>>6)>>1)) & 1
-        }
-    }
-    IFX(X_ZF) {
-        ANDSw_mask(s1, s1, 0, 0b000111);    //mask=000000ff
-        CSETw(s3, cEQ);
-        BFIw(xFlags, s3, F_ZF, 1);
-    }
-    IFX(X_SF) {
-        LSRw(s3, s1, 7);
-        BFIw(xFlags, s3, F_SF, 1);
-    }
-    IFX(X_PF) {
-        emit_pf(dyn, ninst, s1, s3, s4);
-    }
+    emit_sbb8(dyn, ninst, s1, s5, s3, s4);
 }
 
-// emit SBB16 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, with save_s4 is s4 need to be saved
+// emit SBB16 instruction, from s1, s2, store result in s1 using s3 and s4 as scratch
 void emit_sbb16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
 {
+    MAYUSE(s2);
     IFX(X_PEND) {
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -1649,7 +1551,7 @@ void emit_sbb16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4)
     }
 }
 
-// emit SBB16 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
+// emit SBB16 instruction, from s1, constant c, store result in s1 using s3 and s4 as scratch
 //void emit_sbb16c(dynarec_arm_t* dyn, int ninst, int s1, int c, int s3, int s4)
 //{
 //    IFX(X_PEND) {
@@ -1780,7 +1682,11 @@ void emit_neg16(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
     IFX(X_AF|X_OF) {
         MOVw_REG(s3, s1);
     }
-    NEGSw_REG(s1, s1);
+    IFX(X_ZF) {
+        NEGSw_REG(s1, s1);
+    } else {
+        NEGw_REG(s1, s1);
+    }
     IFX(X_PEND) {
         STRH_U12(s1, xEmu, offsetof(x64emu_t, res));
     }
@@ -1826,7 +1732,11 @@ void emit_neg8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
     IFX(X_AF|X_OF) {
         MOVw_REG(s3, s1);
     }
-    NEGSw_REG(s1, s1);
+    IFX(X_ZF) {
+        NEGSw_REG(s1, s1);
+    } else {
+        NEGw_REG(s1, s1);
+    }
     IFX(X_PEND) {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, res));
     }
@@ -1853,4 +1763,4 @@ void emit_neg8(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
     IFX(X_PF) {
         emit_pf(dyn, ninst, s1, s3, s4);
     }
-}
+}

src/dynarec/arm64/dynarec_arm64_emit_shift.c

@@ -1,7 +1,6 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <stddef.h>
-#include <pthread.h>
 #include <errno.h>
 
 #include "debug.h"
@@ -15,19 +14,19 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
-#include "../tools/bridge_private.h"
+#include "dynarec_native.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_functions.h"
 #include "dynarec_arm64_helper.h"
 
 // emit SHL32 instruction, from s1 , shift s2, store result in s1 using s3 and s4 as scratch. s3 can be same as s2
 void emit_shl32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
-    int32_t j32;
-    MAYUSE(j32);
+    MAYUSE(s2);
+    int64_t j64;
+    MAYUSE(j64);
 
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
@@ -36,14 +35,11 @@ void emit_shl32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     } else IFX(X_ALL) {
         SET_DFNONE(s4);
     }
-    IFX(F_OF) {
+    IFX(X_OF) {
         CMPSxw_U12(s2, 0);
-        IFX(F_OF) {
-            Bcond(cNE, +8);
-            BFCx(xFlags, F_OF, 1);
-        }
+        Bcond(cNE, +8+((dyn->insts[ninst].x64.gen_flags&X_PEND)?4:0));
+        BFCw(xFlags, F_OF, 1);
         IFX(X_PEND) {
-            Bcond(cNE, +8);
             STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
         }
         B_NEXT(cEQ);
@@ -60,9 +56,8 @@ void emit_shl32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     }
     IFX(X_ZF) {
         TSTxw_REG(s1, s1);
-        BFCx(xFlags, F_ZF, 1);
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_SF) {
         LSRxw(s4, s1, (rex.w)?63:31);
@@ -71,9 +66,8 @@ void emit_shl32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     IFX(X_OF) {
         CMPSxw_U12(s2, 1);   // if s2==1
             IFX(X_SF) {} else {LSRxw(s4, s1, (rex.w)?63:31);}
-            Bcond(cNE, 4+3*4);
-            BFCw(xFlags, F_OF, 1);
             EORxw_REG(s4, s4, xFlags);  // CF is set if OF is asked
+            CSELw(s4, s4, wZR, cEQ);
             BFIw(xFlags, s4, F_OF, 1);
     }
     IFX(X_PF) {
@@ -82,7 +76,7 @@ void emit_shl32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
 }
 
 // emit SHL32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
-void emit_shl32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, int s3, int s4)
+void emit_shl32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, int s3, int s4)
 {
     IFX(X_PEND) {
         MOV32w(s3, c);
@@ -93,15 +87,15 @@ void emit_shl32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
         SET_DFNONE(s4);
     }
     if(c==0) {
-        IFX(F_OF) {
-            BFCx(xFlags, F_OF, 1);
+        IFX(X_OF) {
+            BFCw(xFlags, F_OF, 1);
         }
         IFX(X_PEND) {
             STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
         }
         return;
     }
-    IFX(X_CF) {
+    IFX(X_CF|X_OF) {
         LSRxw(s3, s1, (rex.w?64:32)-c);
         BFIxw(xFlags, s3, F_CF, 1);
     }
@@ -112,9 +106,8 @@ void emit_shl32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
     }
     IFX(X_ZF) {
         TSTxw_REG(s1, s1);
-        BFCx(xFlags, F_ZF, 1);
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_SF) {
         LSRxw(s4, s1, (rex.w)?63:31);
@@ -123,7 +116,6 @@ void emit_shl32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
     IFX(X_OF) {
         if(c==1) {
             IFX(X_SF) {} else {LSRxw(s4, s1, (rex.w)?63:31);}
-            Bcond(cNE, +12);
             EORxw_REG(s4, s4, xFlags);  // CF is set if OF is asked
             BFIw(xFlags, s4, F_OF, 1);
         } else {
@@ -138,8 +130,9 @@ void emit_shl32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
 // emit SHR32 instruction, from s1 , s2, store result in s1 using s3 and s4 as scratch, s2 can be same as s3
 void emit_shr32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
 {
-    int32_t j32;
-    MAYUSE(j32);
+    MAYUSE(s2);
+    int64_t j64;
+    MAYUSE(j64);
 
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
@@ -167,9 +160,8 @@ void emit_shr32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     }
     IFX(X_ZF) {
         TSTxw_REG(s1, s1);
-        BFCx(xFlags, F_ZF, 1);
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_SF) {
         LSRxw(s4, s1, (rex.w)?63:31);
@@ -178,11 +170,7 @@ void emit_shr32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
     IFX(X_OF) {
         CMPSxw_U12(s2, 1);   // if s2==1
             Bcond(cNE, 4+3*4);
-            if(rex.w) {
-                LSRx(s4, s1, 62);
-            } else {
-                LSRw(s4, s1, 30);
-            }
+            LSRxw(s4, s1, rex.w?62:30);
             EORw_REG_LSR(s4, s4, s4, 1);
             BFIw(xFlags, s4, F_OF, 1);
     }
@@ -192,7 +180,7 @@ void emit_shr32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
 }
 
 // emit SHR32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
-void emit_shr32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, int s3, int s4)
+void emit_shr32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, int s3, int s4)
 {
     IFX(X_PEND) {
         MOV32w(s3, c);
@@ -209,7 +197,7 @@ void emit_shr32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
         return;
     }
     IFX(X_CF) {
-        LSRxw_REG(s3, s1, c-1);
+        LSRxw(s3, s1, c-1);
         BFIw(xFlags, s3, 0, 1);
     }
     LSRxw(s1, s1, c);
@@ -218,9 +206,8 @@ void emit_shr32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
     }
     IFX(X_ZF) {
         TSTxw_REG(s1, s1);
-        BFCx(xFlags, F_ZF, 1);
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_SF) {
         LSRxw(s4, s1, (rex.w)?63:31);
@@ -239,7 +226,7 @@ void emit_shr32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
 }
 
 // emit SAR32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
-void emit_sar32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, int s3, int s4)
+void emit_sar32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, int s3, int s4)
 {
     IFX(X_PEND) {
         MOV32w(s3, c);
@@ -255,19 +242,18 @@ void emit_sar32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
         }
         return;
     }
+    IFX(X_CF) {
+        ASRxw(s3, s1, c-1);
+        BFIw(xFlags, s3, 0, 1);
+    }
     ASRxw(s1, s1, c);
     IFX(X_PEND) {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
     }
     IFX(X_ZF) {
         TSTw_REG(s1, s1);
-        BFCx(xFlags, F_ZF, 1);
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
-    }
-    IFX(X_CF) {
-        ASRxw(s3, s1, c-1);
-        BFIw(xFlags, s3, 0, 1);
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_SF) {
         LSRxw(s4, s1, (rex.w)?63:31);
@@ -279,12 +265,13 @@ void emit_sar32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
 }
 
 // emit ROL32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
-void emit_rol32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, int s3, int s4)
+void emit_rol32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, int s3, int s4)
 {
+    MAYUSE(rex); MAYUSE(s1); MAYUSE(s3); MAYUSE(s4);
     IFX(X_PEND) {
         MOV32w(s3, c);
         STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
-        SET_DF(s4, d_rol32);
+        SET_DF(s4, rex.w?d_rol64:d_rol32);
     } else IFX(X_ALL) {
         SET_DFNONE(s4);
     }
@@ -310,8 +297,9 @@ void emit_rol32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
 }
 
 // emit ROR32 instruction, from s1 , constant c, store result in s1 using s3 and s4 as scratch
-void emit_ror32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, int s3, int s4)
+void emit_ror32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, uint32_t c, int s3, int s4)
 {
+    MAYUSE(s1); MAYUSE(s3); MAYUSE(s4);
     IFX(X_PEND) {
         MOV32w(s3, c);
         STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
@@ -337,125 +325,110 @@ void emit_ror32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int32_t c, in
         if(c==1) {
             LSRxw(s3, s1, rex.w?62:30);
             EORxw_REG_LSR(s3, s3, s3, 1);
-            BFIw(xFlags, s4, F_OF, 1);
+            BFIw(xFlags, s3, F_OF, 1);
         }
     }
 }
 
 // emit SHRD32 instruction, from s1, fill s2 , constant c, store result in s1 using s3 and s4 as scratch
-//void emit_shrd32c(dynarec_arm_t* dyn, int ninst, int s1, int s2, int32_t c, int s3, int s4)
-//{
-//    c&=0x1f;
-//    IFX(X_PEND) {
-//        MOVW(s3, c);
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, op1));
-//        STR_IMM9(s3, xEmu, offsetof(x64emu_t, op2));
-//        // same flags calc as shr32
-//        SET_DF(s4, d_shr32);
-//    } else IFX(X_ALL) {
-//        SET_DFNONE(s4);
-//    }
-//    if(!c) {
-//        IFX(X_PEND) {
-//            STR_IMM9(s1, xEmu, offsetof(x64emu_t, res));
-//        }
-//        return;
-//    }
-//    IFX(X_CF) {
-//        MOVS_REG_LSR_IMM5(s1, s1, c);
-//    } else {
-//        MOV_REG_LSR_IMM5(s1, s1, c);
-//    }
-//    IFX(X_ZF|X_CF) {
-//        BIC_IMM8(xFlags, xFlags, (1<<F_ZF)|(1<<F_CF), 0);
-//    }
-//    IFX(X_CF) {
-//        ORR_IMM8_COND(cCS, xFlags, xFlags, 1<<F_CF, 0);
-//    }
-//    IFX(X_ZF) {
-//        ORRS_REG_LSL_IMM5(s1, s1, s2, 32-c);
-//    } else {
-//        ORR_REG_LSL_IMM5(s1, s1, s2, 32-c);
-//    }
-//    IFX(X_PEND) {
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, res));
-//    }
-//    IFX(X_ZF) {
-//        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
-//    }
-//    IFX(X_SF) {
-//        MOV_REG_LSR_IMM5(s3, s1, 31);
-//        BFI(xFlags, s3, F_SF, 1);
-//    }
-//    IFX(X_OF) {
-//        if(c==1) {
-//            MOV_REG_LSR_IMM5(s4, s1, 30);
-//            XOR_REG_LSR_IMM8(s4, s4, s4, 1);
-//            BFI(xFlags, s4, F_OF, 1);
-//        }
-//    }
-//    IFX(X_PF) {
-//        emit_pf(dyn, ninst, s1, s3, s4);
-//    }
-//}
+void emit_shrd32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, uint32_t c, int s3, int s4)
+{
+    c&=(rex.w?0x3f:0x1f);
+    IFX(X_PEND) {
+        MOV32w(s3, c);
+        STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
+        STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
+        // same flags computation as with shl64/shl32
+        SET_DF(s4, rex.w?d_shl64:d_shl32);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    if(!c) {
+        IFX(X_PEND) {
+            STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
+        }
+        return;
+    }
+    IFX(X_CF) {
+        LSRxw(s3, s1, c-1);
+        BFIw(xFlags, s3, 0, 1);
+    }
+    LSRxw(s3, s1, c);
+    ORRxw_REG_LSL(s1, s3, s2, (rex.w?64:32)-c);
+    IFX(X_PEND) {
+        STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
+    }
+    IFX(X_ZF) {
+        TSTxw_REG(s1, s1);
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
+    }
+    IFX(X_SF) {
+        LSRxw(s4, s1, (rex.w)?63:31);
+        BFIx(xFlags, s4, F_SF, 1);
+    }
+    IFX(X_OF) {
+        if(c==1) {
+            LSRxw(s4, s1, rex.w?62:30);
+            EORw_REG_LSR(s4, s4, s4, 1);
+            BFIw(xFlags, s4, F_OF, 1);
+        }
+    }
+    IFX(X_PF) {
+        emit_pf(dyn, ninst, s1, s3, s4);
+    }
+}
 
-//void emit_shld32c(dynarec_arm_t* dyn, int ninst, int s1, int s2, int32_t c, int s3, int s4)
-//{
-//    c&=0x1f;
-//    IFX(X_PEND) {
-//        MOVW(s3, c);
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, op1));
-//        STR_IMM9(s3, xEmu, offsetof(x64emu_t, op2));
-//        // same flags computation as with shl32
-//        SET_DF(s4, d_shl32);
-//    } else IFX(X_ALL) {
-//        SET_DFNONE(s4);
-//    }
-//    if(c==0) {
-//        IFX(F_OF) {
-//            BFC(xFlags, F_OF, 1);
-//        }
-//        IFX(X_PEND) {
-//            STR_IMM9(s1, xEmu, offsetof(x64emu_t, res));
-//        }
-//        return;
-//    }
-//    IFX(X_CF) {
-//        MOV_REG_LSR_IMM5(s3, s1, 32-c);
-//        BFI(xFlags, s3, F_CF, 1);
-//    }
-//    IFX(X_OF) {
-//        MOVS_REG_LSL_IMM5(s1, s1, c);
-//    } else {
-//        MOV_REG_LSL_IMM5(s1, s1, c);
-//    }
-//    IFX(X_OF) {
-//        if(c==1) {
-//            UBFX(s3, s2, 0, 1);
-//            XOR_IMM8_COND(cCS, s3, s3, 1);
-//            BFI(xFlags, s3, F_OF, 1);
-//        } else {
-//            BFC(xFlags, F_OF, 1);
-//        }
-//    }
-//    IFX(X_ZF) {
-//        ORRS_REG_LSR_IMM5(s1, s1, s2, 32-c);
-//    } else {
-//        ORR_REG_LSR_IMM5(s1, s1, s2, 32-c);
-//    }
-//
-//    IFX(X_PEND) {
-//        STR_IMM9(s1, xEmu, offsetof(x64emu_t, res));
-//    }
-//    IFX(X_ZF) {
-//        ORR_IMM8_COND(cEQ, xFlags, xFlags, 1<<F_ZF, 0);
-//        BIC_IMM8_COND(cNE, xFlags, xFlags, 1<<F_ZF, 0);
-//    }
-//    IFX(X_SF) {
-//        MOV_REG_LSR_IMM5(s3, s1, 31);
-//        BFI(xFlags, s3, F_SF, 1);
-//    }
-//    IFX(X_PF) {
-//        emit_pf(dyn, ninst, s1, s3, s4);
-//    }
-//}
+void emit_shld32c(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, uint32_t c, int s3, int s4)
+{
+    c&=(rex.w?0x3f:0x1f);
+    IFX(X_PEND) {
+        MOV32w(s3, c);
+        STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
+        STRxw_U12(s3, xEmu, offsetof(x64emu_t, op2));
+        // same flags computation as with shl64/shl32
+        SET_DF(s4, rex.w?d_shl64:d_shl32);
+    } else IFX(X_ALL) {
+        SET_DFNONE(s4);
+    }
+    if(c==0) {
+        IFX(X_OF) {
+            BFCw(xFlags, F_OF, 1);
+        }
+        IFX(X_PEND) {
+            STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
+        }
+        return;
+    }
+    IFX(X_CF|X_OF) {
+        LSRxw(s3, s1, (rex.w?64:32)-c);
+        BFIxw(xFlags, s3, F_CF, 1);
+    }
+    LSLxw(s3, s1, c);
+    ORRxw_REG_LSR(s1, s3, s2, (rex.w?64:32)-c);
+
+    IFX(X_PEND) {
+        STRxw_U12(s1, xEmu, offsetof(x64emu_t, res));
+    }
+    IFX(X_ZF) {
+        TSTxw_REG(s1, s1);
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
+    }
+    IFX(X_SF) {
+        LSRxw(s4, s1, (rex.w)?63:31);
+        BFIx(xFlags, s4, F_SF, 1);
+    }
+    IFX(X_OF) {
+        if(c==1) {
+            UBFXxw(s3, s1, rex.w?63:31, 1);
+            EORxw_REG(s3, s3, xFlags);  // CF is set if OF is asked
+            BFIw(xFlags, s3, F_OF, 1);
+        } else {
+            BFCw(xFlags, F_OF, 1);
+        }
+    }
+    IFX(X_PF) {
+        emit_pf(dyn, ninst, s1, s3, s4);
+    }
+}

src/dynarec/arm64/dynarec_arm64_emit_tests.c

@@ -1,7 +1,6 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <stddef.h>
-#include <pthread.h>
 #include <errno.h>
 
 #include "debug.h"
@@ -15,17 +14,17 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
-#include "../tools/bridge_private.h"
+#include "dynarec_native.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_functions.h"
 #include "dynarec_arm64_helper.h"
 
-// emit CMP32 instruction, from cmp s1 , s2, using s3 and s4 as scratch
+// emit CMP32 instruction, from cmp s1, s2, using s3 and s4 as scratch
 void emit_cmp32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4, int s5)
 {
+    MAYUSE(s1); MAYUSE(s2);
     IFX_PENDOR0 {
         STRxw_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRxw_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -47,22 +46,18 @@ void emit_cmp32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3
         LSRxw(s4, s3, 3);
         BFIx(xFlags, s4, F_AF, 1);    // AF: bc & 0x08
     }
-    IFX(X_ZF|X_CF|X_OF) {
-        MOV32w(s4, (1<<F_ZF)|(1<<F_CF)|(1<<F_OF));
-        BICx(xFlags, xFlags, s4);
-    }
     IFX(X_ZF) {
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_CF) {
         // inverted carry
-        Bcond(cCS, +8);
-        ORRw_mask(xFlags, xFlags, 0, 0);    // mask=0x01
+        CSETw(s4, cCC);
+        BFIw(xFlags, s4, F_CF, 1);
     }
     IFX(X_OF) {
-        Bcond(cVC, +8);
-        ORRw_mask(xFlags, xFlags, 0b010101, 0);  // mask=0x800
+        CSETw(s4, cVS);
+        BFIw(xFlags, s4, F_OF, 1);
     }
     IFX(X_SF) {
         LSRxw(s3, s5, (rex.w)?63:31);
@@ -88,18 +83,13 @@ void emit_cmp32_0(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int
     SUBSxw_U12(s3, s1, 0);   // res = s1 - 0
     // and now the tricky ones (and mostly unused), PF and AF
     // bc = (res & (~d | s)) | (~d & s) => is 0 here...
-    IFX(X_ZF|X_CF|X_OF|X_AF) {
-        MOV32w(s4, (1<<F_ZF)|(1<<F_CF)|(1<<F_OF)|(1<<F_AF));
+    IFX(X_OF|X_AF|X_CF) {
+        MOV32w(s4, (1<<F_OF)|(1<<F_AF)|(1<<F_CF));
         BICw(xFlags, xFlags, s4);
     }
     IFX(X_ZF) {
-        Bcond(cNE, +8);
-        ORRw_mask(xFlags, xFlags, 0b011010, 0); // mask=0x40
-    }
-    IFX(X_CF) {
-        // inverted carry
-        Bcond(cCS, +8);
-        ORRw_mask(xFlags, xFlags, 0, 0);    // mask=0x01
+        CSETw(s4, cEQ);
+        BFIw(xFlags, s4, F_ZF, 1);
     }
     IFX(X_SF) {
         LSRxw(s3, s1, (rex.w)?63:31);
@@ -110,9 +100,10 @@ void emit_cmp32_0(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s3, int
     }
 }
 
-// emit CMP16 instruction, from cmp s1 , s2, using s3 and s4 as scratch
+// emit CMP16 instruction, from cmp s1, s2, using s3 and s4 as scratch
 void emit_cmp16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int s5)
 {
+    MAYUSE(s1); MAYUSE(s2);
     IFX_PENDOR0 {
         STRH_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRH_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -120,12 +111,15 @@ void emit_cmp16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, i
     } else {
         SET_DFNONE(s3);
     }
-    SUBw_REG(s5, s1, s2);   // res = s1 - s2
+    IFX(X_ZF) {
+        SUBSw_REG(s5, s1, s2);   // res = s1 - s2
+    } else {
+        SUBw_REG(s5, s1, s2);   // res = s1 - s2
+    }
     IFX_PENDOR0 {
         STRH_U12(s5, xEmu, offsetof(x64emu_t, res));
     }
     IFX(X_ZF) {
-        TSTw_mask(s5, 0, 15);   //mask=0xffff
         CSETw(s3, cEQ);
         BFIw(xFlags, s3, F_ZF, 1);
     }
@@ -189,9 +183,10 @@ void emit_cmp16_0(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
         emit_pf(dyn, ninst, s1, s3, s4);
     }
 }
-// emit CMP8 instruction, from cmp s1 , s2, using s3 and s4 as scratch
+// emit CMP8 instruction, from cmp s1, s2, using s3 and s4 as scratch
 void emit_cmp8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int s5)
 {
+    MAYUSE(s1); MAYUSE(s2);
     IFX_PENDOR0 {
         STRB_U12(s1, xEmu, offsetof(x64emu_t, op1));
         STRB_U12(s2, xEmu, offsetof(x64emu_t, op2));
@@ -252,8 +247,8 @@ void emit_cmp8_0(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
         SET_DFNONE(s4);
     }
     // bc = (res & (~d | s)) | (~d & s) = 0
-    IFX(X_CF | X_AF | X_ZF | X_OF) {
-        MOV32w(s3, (1<<F_ZF)|(1<<F_CF)|(1<<F_AF)|(1<<F_OF));
+    IFX(X_CF | X_AF | X_OF) {
+        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
         BICw(xFlags, xFlags, s3);
     }
     IFX(X_ZF) {
@@ -270,9 +265,10 @@ void emit_cmp8_0(dynarec_arm_t* dyn, int ninst, int s1, int s3, int s4)
     }
 }
 
-// emit TEST32 instruction, from test s1 , s2, using s3 and s4 as scratch
-void emit_test32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4)
+// emit TEST32 instruction, from test s1, s2, using s3, s4 and s5 as scratch
+void emit_test32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s3, int s4, int s5)
 {
+    MAYUSE(s1); MAYUSE(s2); MAYUSE(s3); MAYUSE(s4);
     IFX_PENDOR0 {
         SET_DF(s3, rex.w?d_tst64:d_tst32);
     } else {
@@ -296,30 +292,22 @@ void emit_test32(dynarec_arm_t* dyn, int ninst, rex_t rex, int s1, int s2, int s
     }
     // PF: (((emu->x64emu_parity_tab[(res) / 32] >> ((res) % 32)) & 1) == 0)
     IFX(X_PF) {
-        ANDw_mask(s3, s3, 0b011011, 000010); // 0xE0
-        LSRw(s3, s3, 5);
-        MOV64x(s4, (uintptr_t)GetParityTab());
-        LDRw_REG_LSL2(s4, s4, s3);
-        ANDw_mask(s3, s1, 0, 0b000100);   // 0x1f
-        LSRw_REG(s4, s4, s3);
-        MVNx_REG(s4, s4);
-        BFIw(xFlags, s4, F_PF, 1);
+        emit_pf(dyn, ninst, s3, s4, s5);
     }
 }
 
-// emit TEST16 instruction, from test s1 , s2, using s3 and s4 as scratch
+// emit TEST16 instruction, from test s1, s2, using s3, s4 and s5 as scratch
 void emit_test16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int s5)
 {
+    MAYUSE(s1); MAYUSE(s2);
     IFX_PENDOR0 {
         SET_DF(s3, d_tst16);
     } else {
         SET_DFNONE(s4);
     }
-    IFX(X_OF) {
-        BFCw(xFlags, F_OF, 1);
-    }
-    IFX(X_CF) {
-        BFCw(xFlags, F_CF, 1);
+    IFX(X_CF | X_AF | X_OF) {
+        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
+        BICw(xFlags, xFlags, s3);
     }
     ANDSw_REG(s5, s1, s2);   // res = s1 & s2
     IFX_PENDOR0 {
@@ -339,19 +327,18 @@ void emit_test16(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4,
     }
 }
 
-// emit TEST8 instruction, from test s1 , s2, using s3 and s4 as scratch
+// emit TEST8 instruction, from test s1, s2, using s3, s4 and s5 as scratch
 void emit_test8(dynarec_arm_t* dyn, int ninst, int s1, int s2, int s3, int s4, int s5)
 {
+    MAYUSE(s1); MAYUSE(s2);
     IFX_PENDOR0 {
         SET_DF(s3, d_tst8);
     } else {
         SET_DFNONE(s4);
     }
-    IFX(X_OF) {
-        BFCw(xFlags, F_OF, 1);
-    }
-    IFX(X_CF) {
-        BFCw(xFlags, F_CF, 1);
+    IFX(X_CF | X_AF | X_OF) {
+        MOV32w(s3, (1<<F_CF)|(1<<F_AF)|(1<<F_OF));
+        BICw(xFlags, xFlags, s3);
     }
     ANDSw_REG(s5, s1, s2);   // res = s1 & s2
     IFX_PENDOR0 {

src/dynarec/arm64/dynarec_arm64_f20f.c

@@ -0,0 +1,479 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <stddef.h>
+#include <errno.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "emu/x64run_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "x64trace.h"
+#include "dynarec_native.h"
+
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_functions.h"
+#include "dynarec_arm64_helper.h"
+
+uintptr_t dynarec64_F20F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int* ok, int* need_epilog)
+{
+    (void)ip; (void)need_epilog;
+
+    uint8_t opcode = F8;
+    uint8_t nextop;
+    uint8_t gd, ed;
+    uint8_t wback;
+    uint8_t u8;
+    uint64_t u64, j64;
+    int v0, v1;
+    int q0;
+    int d0, d1;
+    int64_t fixedaddress;
+    int unscaled;
+
+    MAYUSE(d0);
+    MAYUSE(d1);
+    MAYUSE(q0);
+    MAYUSE(v0);
+    MAYUSE(v1);
+
+    switch(opcode) {
+
+        case 0x10:
+            INST_NAME("MOVSD Gx, Ex");
+            nextop = F8;
+            GETG;
+            if(MODREG) {
+                ed = (nextop&7)+ (rex.b<<3);
+                v0 = sse_get_reg(dyn, ninst, x1, gd, 1);
+                d0 = sse_get_reg(dyn, ninst, x1, ed, 0);
+                VMOVeD(v0, 0, d0, 0);
+            } else {
+                SMREAD();
+                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VLD64(v0, ed, fixedaddress); // upper part reseted
+            }
+            break;
+        case 0x11:
+            INST_NAME("MOVSD Ex, Gx");
+            nextop = F8;
+            GETG;
+            v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
+            if(MODREG) {
+                ed = (nextop&7)+ (rex.b<<3);
+                d0 = sse_get_reg(dyn, ninst, x1, ed, 1);
+                VMOVeD(d0, 0, v0, 0);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VST64(v0, ed, fixedaddress);
+                SMWRITE2();
+            }
+            break;
+        case 0x12:
+            INST_NAME("MOVDDUP Gx, Ex");
+            nextop = F8;
+            GETG;
+            if(MODREG) {
+                d0 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
+                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                VMOVeD(v0, 0, d0, 0);
+            } else {
+                SMREAD();
+                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VLD64(v0, ed, fixedaddress);
+            }
+            VMOVeD(v0, 1, v0, 0);
+            break;
+
+        case 0x2A:
+            INST_NAME("CVTSI2SD Gx, Ed");
+            nextop = F8;
+            GETGX(v0, 1);
+            GETED(0);
+            d1 = fpu_get_scratch(dyn);
+            if(rex.w) {
+                SCVTFDx(d1, ed);
+            } else {
+                SCVTFDw(d1, ed);
+            }
+            VMOVeD(v0, 0, d1, 0);
+            break;
+
+        case 0x2C:
+            INST_NAME("CVTTSD2SI Gd, Ex");
+            nextop = F8;
+            GETGD;
+            GETEXSD(q0, 0, 0);
+            if(!box64_dynarec_fastround) {
+                MRS_fpsr(x5);
+                BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                MSR_fpsr(x5);
+            }
+            FCVTZSxwD(gd, q0);
+            if(!box64_dynarec_fastround) {
+                MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                TBZ_NEXT(x5, FPSR_IOC);
+                if(rex.w) {
+                    ORRx_mask(gd, xZR, 1, 1, 0);    //0x8000000000000000
+                } else {
+                    MOV32w(gd, 0x80000000);
+                }
+            }
+            break;
+        case 0x2D:
+            INST_NAME("CVTSD2SI Gd, Ex");
+            nextop = F8;
+            GETGD;
+            GETEXSD(q0, 0, 0);
+            if(!box64_dynarec_fastround) {
+                MRS_fpsr(x5);
+                BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                MSR_fpsr(x5);
+            }
+            u8 = sse_setround(dyn, ninst, x1, x2, x3);
+            d1 = fpu_get_scratch(dyn);
+            FRINTID(d1, q0);
+            x87_restoreround(dyn, ninst, u8);
+            FCVTZSxwD(gd, d1);
+            if(!box64_dynarec_fastround) {
+                MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                TBZ_NEXT(x5, FPSR_IOC);
+                if(rex.w) {
+                    ORRx_mask(gd, xZR, 1, 1, 0);    //0x8000000000000000
+                } else {
+                    MOV32w(gd, 0x80000000);
+                }
+            }
+            break;
+
+        case 0x38:  // these are some more SSSE4.2+ opcodes
+            opcode = F8;
+            switch(opcode) {
+
+                case 0xF0:
+                    INST_NAME("(unsupported) CRC32 Gd, Eb)");
+                    nextop = F8;
+                    addr = fakeed(dyn, addr, ninst, nextop);
+                    SETFLAGS(X_ALL, SF_SET);    // Hack to set flags in "don't care" state
+                    GETIP(ip);
+                    STORE_XEMU_CALL(xRIP);
+                    CALL(native_ud, -1);
+                    LOAD_XEMU_CALL(xRIP);
+                    jump_to_epilog(dyn, 0, xRIP, ninst);
+                    *need_epilog = 0;
+                    *ok = 0;
+                    break;
+                case 0xF1:
+                    INST_NAME("(unsupported) CRC32 Gd, Ed)");
+                    nextop = F8;
+                    addr = fakeed(dyn, addr, ninst, nextop);
+                    SETFLAGS(X_ALL, SF_SET);    // Hack to set flags in "don't care" state
+                    GETIP(ip);
+                    STORE_XEMU_CALL(xRIP);
+                    CALL(native_ud, -1);
+                    LOAD_XEMU_CALL(xRIP);
+                    jump_to_epilog(dyn, 0, xRIP, ninst);
+                    *need_epilog = 0;
+                    *ok = 0;
+                    break;
+
+                default:
+                    DEFAULT;
+            }
+            break;
+
+
+        case 0x51:
+            INST_NAME("SQRTSD Gx, Ex");
+            nextop = F8;
+            GETGX(v0, 1);
+            d1 = fpu_get_scratch(dyn);
+            GETEXSD(d0, 0, 0);
+            if(!box64_dynarec_fastnan) {
+                v1 = fpu_get_scratch(dyn);
+                FCMLTD_0(v1, d0);
+                SHL_64(v1, v1, 63);
+                FSQRTD(d1, d0);
+                VORR(d1, d1, v1);
+            } else {
+                FSQRTD(d1, d0);
+            }
+            VMOVeD(v0, 0, d1, 0);
+            break;
+
+        case 0x58:
+            INST_NAME("ADDSD Gx, Ex");
+            nextop = F8;
+            GETGX(d1, 1);
+            v1 = fpu_get_scratch(dyn);
+            GETEXSD(d0, 0, 0);
+            if(!box64_dynarec_fastnan) {
+                v0 = fpu_get_scratch(dyn);
+                q0 = fpu_get_scratch(dyn);
+                // check if any input value was NAN
+                FMAXD(v0, d0, d1);    // propagate NAN
+                FCMEQD(v0, v0, v0);    // 0 if NAN, 1 if not NAN
+                FADDD(v1, d1, d0);  // the high part of the vector is erased...
+                FCMEQD(q0, v1, v1);    // 0 => out is NAN
+                VBIC(q0, v0, q0);      // forget it in any input was a NAN already
+                SHL_64(q0, q0, 63);     // only keep the sign bit
+                VORR(v1, v1, q0);      // NAN -> -NAN
+            } else {
+                FADDD(v1, d1, d0);  // the high part of the vector is erased...
+            }
+            VMOVeD(d1, 0, v1, 0);
+            break;
+        case 0x59:
+            INST_NAME("MULSD Gx, Ex");
+            nextop = F8;
+            GETGX(d1, 1);
+            v1 = fpu_get_scratch(dyn);
+            GETEXSD(d0, 0, 0);
+            if(!box64_dynarec_fastnan) {
+                v0 = fpu_get_scratch(dyn);
+                q0 = fpu_get_scratch(dyn);
+                // check if any input value was NAN
+                FMAXD(v0, d0, d1);    // propagate NAN
+                FCMEQD(v0, v0, v0);    // 0 if NAN, 1 if not NAN
+                FMULD(v1, d1, d0);
+                FCMEQD(q0, v1, v1);    // 0 => out is NAN
+                VBIC(q0, v0, q0);      // forget it in any input was a NAN already
+                SHL_64(q0, q0, 63);     // only keep the sign bit
+                VORR(v1, v1, q0);      // NAN -> -NAN
+            } else {
+                FMULD(v1, d1, d0);
+            }
+            VMOVeD(d1, 0, v1, 0);
+            break;
+        case 0x5A:
+            INST_NAME("CVTSD2SS Gx, Ex");
+            nextop = F8;
+            GETGX(v0, 1);
+            GETEXSD(d0, 0, 0);
+            d1 = fpu_get_scratch(dyn);
+            FCVT_S_D(d1, d0);
+            VMOVeS(v0, 0, d1, 0);
+            break;
+
+        case 0x5C:
+            INST_NAME("SUBSD Gx, Ex");
+            nextop = F8;
+            GETGX(d1, 1);
+            v1 = fpu_get_scratch(dyn);
+            GETEXSD(d0, 0, 0);
+            if(!box64_dynarec_fastnan) {
+                v0 = fpu_get_scratch(dyn);
+                q0 = fpu_get_scratch(dyn);
+                // check if any input value was NAN
+                FMAXD(v0, d0, d1);    // propagate NAN
+                FCMEQD(v0, v0, v0);    // 0 if NAN, 1 if not NAN
+                FSUBD(v1, d1, d0);
+                FCMEQD(q0, v1, v1);    // 0 => out is NAN
+                VBIC(q0, v0, q0);      // forget it in any input was a NAN already
+                SHL_64(q0, q0, 63);     // only keep the sign bit
+                VORR(v1, v1, q0);      // NAN -> -NAN
+            } else {
+                FSUBD(v1, d1, d0);
+            }
+            VMOVeD(d1, 0, v1, 0);
+            break;
+        case 0x5D:
+            INST_NAME("MINSD Gx, Ex");
+            nextop = F8;
+            GETGX(v0, 1);
+            GETEXSD(v1, 0, 0);
+            // MINSD: if any input is NaN, or Ex[0]<Gx[0], copy Ex[0] -> Gx[0]
+            #if 0
+            d0 = fpu_get_scratch(dyn);
+            FMINNMD(d0, v0, v1);    // NaN handling may be slightly different, is that a problem?
+            VMOVeD(v0, 0, d0, 0);   // to not erase uper part
+            #else
+            FCMPD(v0, v1);
+            B_NEXT(cCC);    //Less than
+            VMOVeD(v0, 0, v1, 0);   // to not erase uper part
+            #endif
+            break;
+        case 0x5E:
+            INST_NAME("DIVSD Gx, Ex");
+            nextop = F8;
+            GETGX(v0, 1);
+            d1 = fpu_get_scratch(dyn);
+            GETEXSD(v1, 0, 0);
+            if(!box64_dynarec_fastnan) {
+                d0 = fpu_get_scratch(dyn);
+                q0 = fpu_get_scratch(dyn);
+                // check if any input value was NAN
+                FMAXD(d0, v0, v1);      // propagate NAN
+                FCMEQD(d0, d0, d0);     // 0 if NAN, 1 if not NAN
+                FDIVD(d1, v0, v1);
+                FCMEQD(q0, d1, d1);     // 0 => out is NAN
+                VBIC(q0, d0, q0);       // forget it in any input was a NAN already
+                SHL_64(q0, q0, 63);     // only keep the sign bit
+                VORR(d1, d1, q0);       // NAN -> -NAN
+            } else {
+                FDIVD(d1, v0, v1);
+            }
+            VMOVeD(v0, 0, d1, 0);
+            break;
+        case 0x5F:
+            INST_NAME("MAXSD Gx, Ex");
+            nextop = F8;
+            GETGX(v0, 1);
+            GETEXSD(v1, 0, 0);
+            // MAXSD: if any input is NaN, or Ex[0]>Gx[0], copy Ex[0] -> Gx[0]
+            #if 0
+            d0 = fpu_get_scratch(dyn);
+            FMAXNMD(d0, v0, v1);    // NaN handling may be slightly different, is that a problem?
+            VMOVeD(v0, 0, d0, 0);   // to not erase uper part
+            #else
+            FCMPD(v0, v1);
+            B_NEXT(cGT);    //Greater than
+            VMOVeD(v0, 0, v1, 0);   // to not erase uper part
+            #endif
+            break;
+
+        case 0x70:
+            INST_NAME("PSHUFLW Gx, Ex, Ib");
+            nextop = F8;
+            GETEX(v1, 0, 1);
+            GETGX(v0, 1);
+
+            u8 = F8;
+            // only low part need to be suffled. VTBL only handle 8bits value, so the 16bits suffles need to be changed in 8bits
+            u64 = 0;
+            for (int i=0; i<4; ++i) {
+                u64 |= ((uint64_t)((u8>>(i*2))&3)*2+0)<<(i*16+0);
+                u64 |= ((uint64_t)((u8>>(i*2))&3)*2+1)<<(i*16+8);
+            }
+            MOV64x(x2, u64);
+            d0 = fpu_get_scratch(dyn);
+            VMOVQDfrom(d0, 0, x2);
+            VTBL1_8(d0, v1, d0);
+            VMOVeD(v0, 0, d0, 0);
+            if(v0!=v1) {
+                VMOVeD(v0, 1, v1, 1);
+            }
+            break;
+
+        case 0x7C:
+            INST_NAME("HADDPS Gx, Ex");
+            nextop = F8;
+            GETGX(v0, 1);
+            if(MODREG) {
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
+            } else {
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<4, 15, rex, NULL, 0, 0);
+                v1 = fpu_get_scratch(dyn);
+                VLD128(v1, ed, fixedaddress);
+            }
+            VFADDPQS(v0, v0, v1);
+            break;
+            
+        case 0xC2:
+            INST_NAME("CMPSD Gx, Ex, Ib");
+            nextop = F8;
+            GETGX(v0, 1);
+            GETEXSD(v1, 0, 1);
+            u8 = F8;
+            FCMPD(v0, v1);
+            switch(u8&7) {
+                case 0: CSETMx(x2, cEQ); break;   // Equal
+                case 1: CSETMx(x2, cCC); break;   // Less than
+                case 2: CSETMx(x2, cLS); break;   // Less or equal
+                case 3: CSETMx(x2, cVS); break;   // NaN
+                case 4: CSETMx(x2, cNE); break;   // Not Equal or unordered
+                case 5: CSETMx(x2, cCS); break;   // Greater or equal or unordered
+                case 6: CSETMx(x2, cHI); break;   // Greater or unordered, test inverted, N!=V so unordered or less than (inverted)
+                case 7: CSETMx(x2, cVC); break;   // not NaN
+            }
+            VMOVQDfrom(v0, 0, x2);
+            break;
+
+        case 0xD0:
+            INST_NAME("ADDSUBPS Gx, Ex");
+            nextop = F8;
+            GETGX(v0, 1);
+            GETEX(v1, 0, 0);
+            q0 = fpu_get_scratch(dyn);
+            static float addsubps[4] = {-1.f, 1.f, -1.f, 1.f};
+            MAYUSE(addsubps);
+            TABLE64(x2, (uintptr_t)&addsubps);
+            VLDR128_U12(q0, x2, 0);
+            VFMLAQS(v0, v1, q0);
+            break;
+
+        case 0xD6:
+            INST_NAME("MOVDQ2Q Gm, Ex");
+            nextop = F8;
+            GETGM(v0);
+            GETEXSD(v1, 0, 0);
+            VMOV(v0, v1);
+            break;
+
+        case 0xE6:
+            INST_NAME("CVTPD2DQ Gx, Ex");
+            nextop = F8;
+            GETEX(v1, 0, 0);
+            GETGX_empty(v0);
+            if(box64_dynarec_fastround) {
+                u8 = sse_setround(dyn, ninst, x1, x2, x3);
+                VFRINTIDQ(v0, v1);
+                x87_restoreround(dyn, ninst, u8);
+                VFCVTNSQD(v0, v0);  // convert double -> int64
+                SQXTN_32(v0, v0);   // convert int64 -> int32 with saturation in lower part, RaZ high part
+            } else {
+                u8 = sse_setround(dyn, ninst, x1, x2, x3);
+                MRS_fpsr(x5);
+                BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                MSR_fpsr(x5);
+                ORRw_mask(x4, xZR, 1, 0);    //0x80000000
+                d0 = fpu_get_scratch(dyn);
+                for(int i=0; i<2; ++i) {
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    MSR_fpsr(x5);
+                    if(i) {
+                        VMOVeD(d0, 0, v1, i);
+                        FRINTID(d0, d0);
+                    } else {
+                        FRINTID(d0, v1);
+                    }
+                    FCVTZSwD(x1, d0);
+                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                    TBZ(x5, FPSR_IOC, 4+4);
+                    MOVw_REG(x1, x4);
+                    VMOVQSfrom(v0, i, x1);
+                }
+                x87_restoreround(dyn, ninst, u8);
+                VMOVQDfrom(v0, 1, xZR);
+            }
+            break;
+
+        case 0xF0:
+            INST_NAME("LDDQU Gx,Ex");
+            nextop = F8;
+            GETG;
+            if(MODREG) {
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
+                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                VMOVQ(v0, v1);
+            } else {
+                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<4, 7, rex, NULL, 0, 0);
+                VLD128(v0, ed, fixedaddress);
+            }
+            break;
+
+        default:
+            DEFAULT;
+    }
+    return addr;
+}

src/dynarec/arm64/dynarec_arm64_f30f.c

@@ -1,7 +1,6 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <stddef.h>
-#include <pthread.h>
 #include <errno.h>
 
 #include "debug.h"
@@ -15,33 +14,17 @@
 #include "callback.h"
 #include "emu/x64run_private.h"
 #include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
+#include "dynarec_native.h"
 
+#include "arm64_printer.h"
+#include "dynarec_arm64_private.h"
 #include "dynarec_arm64_functions.h"
 #include "dynarec_arm64_helper.h"
 
-// Get Ex as a single, not a quad (warning, x2 get used)
-#define GETEX(a, D)                                                                                 \
-    if(MODREG) {                                                                                    \
-        a = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3));                                     \
-    } else {                                                                                        \
-        a = fpu_get_scratch(dyn);                                                                   \
-        addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<2, 3, rex, 0, D);     \
-        VLDR32_U12(a, ed, fixedaddress);                                                            \
-    }
-
-#define GETG        gd = ((nextop&0x38)>>3)+(rex.r<<3)
-
-#define GETGX(a)    gd = ((nextop&0x38)>>3)+(rex.r<<3); \
-                    a = sse_get_reg(dyn, ninst, x1, gd)
-
-#define GETGX_empty(a)  gd = ((nextop&0x38)>>3)+(rex.r<<3);         \
-                        a = sse_get_reg_empty(dyn, ninst, x1, gd)
-
 uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int* ok, int* need_epilog)
 {
+    (void)ip; (void)need_epilog;
+
     uint8_t opcode = F8;
     uint8_t nextop, u8;
     uint8_t gd, ed;
@@ -50,8 +33,9 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
     int v0, v1;
     int q0, q1;
     int d0, d1;
-    int fixedaddress;
-    int j32;
+    int64_t fixedaddress;
+    int unscaled;
+    int64_t j64;
 
     MAYUSE(d0);
     MAYUSE(d1);
@@ -59,7 +43,7 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
     MAYUSE(q1);
     MAYUSE(v0);
     MAYUSE(v1);
-    MAYUSE(j32);
+    MAYUSE(j64);
 
     switch(opcode) {
 
@@ -68,37 +52,40 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             nextop = F8;
             GETG;
             if(MODREG) {
-                v0 = sse_get_reg(dyn, ninst, x1, gd);
-                q0 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3));
+                v0 = sse_get_reg(dyn, ninst, x1, gd, 1);
+                q0 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3), 0);
                 VMOVeS(v0, 0, q0, 0);
             } else {
                 v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
-                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
-                VLDR32_U12(v0, ed, fixedaddress);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VLD32(v0, ed, fixedaddress);
             }
             break;
         case 0x11:
             INST_NAME("MOVSS Ex, Gx");
             nextop = F8;
             GETG;
-            v0 = sse_get_reg(dyn, ninst, x1, gd);
+            v0 = sse_get_reg(dyn, ninst, x1, gd, 0);
             if(MODREG) {
-                q0 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3));
+                q0 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3), 1);
                 VMOVeS(q0, 0, v0, 0);
             } else {
-                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<2, 3, rex, 0, 0);
-                VSTR32_U12(v0, ed, fixedaddress);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<2, 3, rex, NULL, 0, 0);
+                VST32(v0, ed, fixedaddress);
+                SMWRITE2();
             }
             break;
         case 0x12:
             INST_NAME("MOVSLDUP Gx, Ex");
             nextop = F8;
             if(MODREG) {
-                q1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3));
+                q1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
             } else {
-                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<4, 15, rex, 0, 0);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<4, 15, rex, NULL, 0, 0);
                 q1 = fpu_get_scratch(dyn);
-                VLDR128_U12(q1, ed, fixedaddress);
+                VLD128(q1, ed, fixedaddress);
             }
             GETGX_empty(q0);
             VTRNQ1_32(q0, q1, q1);
@@ -108,20 +95,27 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             INST_NAME("MOVSHDUP Gx, Ex");
             nextop = F8;
             if(MODREG) {
-                q1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3));
+                q1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
             } else {
-                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<4, 15, rex, 0, 0);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<4, 15, rex, NULL, 0, 0);
                 q1 = fpu_get_scratch(dyn);
-                VLDR128_U12(q1, ed, fixedaddress);
+                VLD128(q1, ed, fixedaddress);
             }
             GETGX_empty(q0);
             VTRNQ2_32(q0, q1, q1);
             break;
 
+        case 0x1E:
+            INST_NAME("NOP / ENDBR32 / ENDBR64");
+            nextop = F8;
+            FAKEED;
+            break;
+
         case 0x2A:
             INST_NAME("CVTSI2SS Gx, Ed");
             nextop = F8;
-            GETGX(v0);
+            GETGX(v0, 1);
             GETED(0);
             d1 = fpu_get_scratch(dyn);
             if(rex.w) {
@@ -136,153 +130,208 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             INST_NAME("CVTTSS2SI Gd, Ex");
             nextop = F8;
             GETGD;
-            GETEX(d0, 0);
+            GETEXSS(d0, 0, 0);
+            if(!box64_dynarec_fastround) {
+                MRS_fpsr(x5);
+                BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                MSR_fpsr(x5);
+            }
             FCVTZSxwS(gd, d0);
+            if(!box64_dynarec_fastround) {
+                MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                TBZ_NEXT(x5, FPSR_IOC);
+                if(rex.w) {
+                    ORRx_mask(gd, xZR, 1, 1, 0);    //0x8000000000000000
+                } else {
+                    ORRw_mask(gd, xZR, 1, 0);    //0x80000000
+                }
+            }
             break;
         case 0x2D:
             INST_NAME("CVTSS2SI Gd, Ex");
             nextop = F8;
             GETGD;
-            GETEX(q0, 0);
-            #ifdef PRECISE_CVT
-            LDRH_U12(x1, xEmu, offsetof(x64emu_t, mxcsr));
-            UBFXx(x1, x1, 13, 2);   // extract round requested
-            LSLx_REG(x1, x1, 3);
-            ADDx_U12(x1, x1, 8);    // add the actual add+jump opcodes
-            // Construct a "switch case", with each case 2 instructions, so 8 bytes
-            BL(+4); // Branch with Link to next, so LR gets next PC address
-            ADDx_REG(xLR, xLR, x1);
-            B(xLR); // could use RET, but it's not really one
-            FCVTNSxwS(gd, q0);  // 0: Nearest (even)
-            B_NEXT_nocond;
-            FCVTMSxwS(gd, q0);  // 1: Toward -inf
-            B_NEXT_nocond;
-            FCVTPSxwS(gd, q0);  // 2: Toward +inf
-            B_NEXT_nocond;
-            FCVTZSxwS(gd, q0);  // 3: Toward 0
-            #else
-            FCVTNSxwS(gd, q0);
-            #endif
+            GETEXSS(q0, 0, 0);
+            if(!box64_dynarec_fastround) {
+                MRS_fpsr(x5);
+                BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                MSR_fpsr(x5);
+            }
+            u8 = sse_setround(dyn, ninst, x1, x2, x3);
+            d1 = fpu_get_scratch(dyn);
+            FRINTIS(d1, q0);
+            x87_restoreround(dyn, ninst, u8);
+            FCVTZSxwS(gd, d1);
+            if(!box64_dynarec_fastround) {
+                MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                TBZ_NEXT(x5, FPSR_IOC);
+                if(rex.w) {
+                    ORRx_mask(gd, xZR, 1, 1, 0);    //0x8000000000000000
+                } else {
+                    ORRw_mask(gd, xZR, 1, 0);    //0x80000000
+                }
+            }
             break;
         case 0x51:
             INST_NAME("SQRTSS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
+            GETGX(v0, 1);
             d1 = fpu_get_scratch(dyn);
-            GETEX(d0, 0);
+            GETEXSS(d0, 0, 0);
             FSQRTS(d1, d0);
             VMOVeS(v0, 0, d1, 0);
             break;
         case 0x52:
             INST_NAME("RSQRTSS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
-            GETEX(v1, 0);
+            GETGX(v0, 1);
+            GETEXSS(v1, 0, 0);
             d0 = fpu_get_scratch(dyn);
+            d1 = fpu_get_scratch(dyn);
             // so here: F32: Imm8 = abcd efgh that gives => aBbbbbbc defgh000 00000000 00000000
             // and want 1.0f = 0x3f800000
             // so 00111111 10000000 00000000 00000000
             // a = 0, b = 1, c = 1, d = 1, efgh=0
             // 0b01110000
             FMOVS_8(d0, 0b01110000);
-            FSQRTS(v0, v1);
-            FDIVS(d0, d0, v0);
+            FSQRTS(d1, v1);
+            FDIVS(d0, d0, d1);
+            VMOVeS(v0, 0, d0, 0);
+            break;
+        case 0x53:
+            INST_NAME("RCPSS Gx, Ex");
+            nextop = F8;
+            GETGX(v0, 1);
+            GETEXSS(v1, 0, 0);
+            d0 = fpu_get_scratch(dyn);
+            FMOVS_8(d0, 0b01110000);    //1.0f
+            FDIVS(d0, d0, v1);
             VMOVeS(v0, 0, d0, 0);
             break;
 
         case 0x58:
             INST_NAME("ADDSS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
+            GETGX(v0, 1);
             d1 = fpu_get_scratch(dyn);
-            GETEX(d0, 0);
+            GETEXSS(d0, 0, 0);
             FADDS(d1, v0, d0);  // the high part of the vector is erased...
             VMOVeS(v0, 0, d1, 0);
             break;
         case 0x59:
             INST_NAME("MULSS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
+            GETGX(v0, 1);
             d1 = fpu_get_scratch(dyn);
-            GETEX(d0, 0);
+            GETEXSS(d0, 0, 0);
             FMULS(d1, v0, d0);
             VMOVeS(v0, 0, d1, 0);
             break;
         case 0x5A:
             INST_NAME("CVTSS2SD Gx, Ex");
             nextop = F8;
-            GETGX(v0);
-            GETEX(v1, 0);
+            GETGX(v0, 1);
+            GETEXSS(v1, 0, 0);
             d0 = fpu_get_scratch(dyn);
             FCVT_D_S(d0, v1);
             VMOVeD(v0, 0, d0, 0);
             break;
         case 0x5B:
-            INST_NAME("CVTPS2DQ Gx, Ex");
+            INST_NAME("CVTTPS2DQ Gx, Ex");
             nextop = F8;
-            GETEX(d0, 0);
+            GETEX(v1, 0, 0) ;
             GETGX_empty(v0);
-            VFCVTZSQS(v0, d0);
+            if(box64_dynarec_fastround) {
+                VFCVTZSQS(v0, v1);
+            } else {
+                MRS_fpsr(x5);
+                BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                MSR_fpsr(x5);
+                ORRw_mask(x4, xZR, 1, 0);    //0x80000000
+                d0 = fpu_get_scratch(dyn);
+                for(int i=0; i<4; ++i) {
+                    BFCw(x5, FPSR_IOC, 1);   // reset IOC bit
+                    MSR_fpsr(x5);
+                    VMOVeS(d0, 0, v1, i);
+                    VFCVTZSs(d0, d0);
+                    MRS_fpsr(x5);   // get back FPSR to check the IOC bit
+                    TBZ(x5, FPSR_IOC, 4+4);
+                    VMOVQSfrom(d0, 0, x4);
+                    VMOVeS(v0, i, d0, 0);
+                }
+            }
             break;
 
         case 0x5C:
             INST_NAME("SUBSS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
+            GETGX(v0, 1);
             d1 = fpu_get_scratch(dyn);
-            GETEX(d0, 0);
+            GETEXSS(d0, 0, 0);
             FSUBS(d1, v0, d0);
             VMOVeS(v0, 0, d1, 0);
             break;
         case 0x5D:
             INST_NAME("MINSS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
-            GETEX(v1, 0);
+            GETGX(v0, 1);
+            GETEXSS(v1, 0, 0);
             // MINSS: if any input is NaN, or Ex[0]<Gx[0], copy Ex[0] -> Gx[0]
+            #if 0
             d0 = fpu_get_scratch(dyn);
             FMINNMS(d0, v0, v1);    // NaN handling may be slightly different, is that a problem?
             VMOVeS(v0, 0, d0, 0);   // to not erase uper part
+            #else
+            FCMPS(v0, v1);
+            B_NEXT(cLS);    //Less than or equal
+            VMOVeS(v0, 0, v1, 0);   // to not erase uper part
+            #endif
             break;
         case 0x5E:
             INST_NAME("DIVSS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
+            GETGX(v0, 1);
             d1 = fpu_get_scratch(dyn);
-            GETEX(d0, 0);
+            GETEXSS(d0, 0, 0);
             FDIVS(d1, v0, d0);
             VMOVeS(v0, 0, d1, 0);
             break;
         case 0x5F:
             INST_NAME("MAXSS Gx, Ex");
             nextop = F8;
-            GETGX(v0);
-            GETEX(v1, 0);
+            GETGX(v0, 1);
+            GETEXSS(v1, 0, 0);
             // MAXSS: if any input is NaN, or Ex[0]>Gx[0], copy Ex[0] -> Gx[0]
+            #if 0
             d0 = fpu_get_scratch(dyn);
             FMAXNMS(d0, v0, v1);    // NaN handling may be slightly different, is that a problem?
             VMOVeS(v0, 0, d0, 0);   // to not erase uper part
+            #else
+            FCMPS(v0, v1);
+            B_NEXT(cGE);    //Greater than or equal
+            VMOVeS(v0, 0, v1, 0);   // to not erase uper part
+            #endif
             break;
             
         case 0x6F:
             INST_NAME("MOVDQU Gx,Ex");// no alignment constraint on NEON here, so same as MOVDQA
             nextop = F8;
-            GETG;
-            v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
             if(MODREG) {
-                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3));
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7)+(rex.b<<3), 0);
+                GETGX_empty(v0);
                 VMOVQ(v0, v1);
             } else {
-                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<4, 15, rex, 0, 0);
-                VLDR128_U12(v0, ed, fixedaddress);
+                GETGX_empty(v0);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<4, 15, rex, NULL, 0, 0);
+                VLD128(v0, ed, fixedaddress);
             }
             break;
         case 0x70:
             INST_NAME("PSHUFHW Gx, Ex, Ib");
             nextop = F8;
-            GETEX(v1, 1);
-            GETGX(v0);
-
+            GETEX(v1, 0, 1) ;
+            GETGX(v0, 1);
             u8 = F8;
             // only high part need to be suffled. VTBL only handle 8bits value, so the 16bits suffles need to be changed in 8bits
             u64 = 0;
@@ -295,73 +344,122 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             VMOVQDfrom(d0, 0, x2);
             VTBL1_8(d0, v1, d0);
             VMOVeD(v0, 1, d0, 0);
+            if(v0!=v1) {
+                VMOVeD(v0, 0, v1, 0);
+            }
             break;
 
         case 0x7E:
             INST_NAME("MOVQ Gx, Ex");
             nextop = F8;
-            GETG;
             if(MODREG) {
-                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3));
-                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
+                v1 = sse_get_reg(dyn, ninst, x1, (nextop&7) + (rex.b<<3), 0);
+                GETGX_empty(v0);
                 FMOVD(v0, v1);
             } else {
-                v0 = sse_get_reg_empty(dyn, ninst, x1, gd);
-                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<3, 7, rex, 0, 0);
-                VLDR64_U12(v0, ed, fixedaddress);
+                GETGX_empty(v0);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VLD64(v0, ed, fixedaddress);
             }
             break;
         case 0x7F:
             INST_NAME("MOVDQU Ex,Gx");
             nextop = F8;
-            GETG;
+            GETGX(v0, 0);
             if(MODREG) {
-                v0 = sse_get_reg(dyn, ninst, x1, gd);
                 v1 = sse_get_reg_empty(dyn, ninst, x1, (nextop&7) + (rex.b<<3));
                 VMOVQ(v1, v0);
             } else {
-                v0 = sse_get_reg(dyn, ninst, x1, gd);
-                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<4, 15, rex, 0, 0);
-                VSTR128_U12(v0, ed, fixedaddress);
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<4, 15, rex, NULL, 0, 0);
+                VST128(v0, ed, fixedaddress);
+                SMWRITE2();
+            }
+            break;
+
+        case 0xB8:
+            INST_NAME("POPCNT Gd, Ed");
+            SETFLAGS(X_ALL, SF_SET);
+            SET_DFNONE(x1);
+            nextop = F8;
+            v1 = fpu_get_scratch(dyn);
+            GETGD;
+            if(MODREG) {
+                GETED(0);
+                if(rex.w)
+                    VMOVQDfrom(v1, 0, ed);
+                else {
+                    MOVxw_REG(x1, ed);  // need to clear uper part
+                    VMOVQDfrom(v1, 0, x1);
+                }
+            } else {
+                if(rex.w) {
+                    SMREAD();
+                    addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                    VLD64(v1, ed, fixedaddress);
+                } else {
+                    GETED(0);   // just load and clear the upper part
+                    VMOVQDfrom(v1, 0, ed);
+                }
+            }
+            CNT_8(v1, v1);
+            UADDLV_8(v1, v1);
+            VMOVQDto(gd, v1, 0);
+            IFX(X_ALL) {
+                MOV32w(x1, (1<<F_OF) | (1<<F_SF) | (1<<F_ZF) | (1<<F_AF) | (1<<F_CF) | (1<<F_PF));
+                BICw(xFlags, xFlags, x1);
+                CBNZx(gd, 4+4);
+                BFIw(xFlags, xFlags, F_ZF, 1);
             }
             break;
 
         case 0xBC:
             INST_NAME("TZCNT Gd, Ed");
-            SETFLAGS(X_CF|X_ZF, SF_SET);
+            SETFLAGS(X_CF|X_ZF, SF_SUBSET);
+            SET_DFNONE(x1);
             nextop = F8;
             GETED(0);
             GETGD;
-            SET_DFNONE(x1);
             TSTxw_REG(ed, ed);
-            BFIw(xFlags, x1, F_CF, 1);  // CF = is source 0?
-            RBITxw(x1, ed);   // reverse
-            CLZxw(gd, x1);    // x2 gets leading 0 == TZCNT
+            CSETw(x3, cEQ);
+            BFIw(xFlags, x3, F_CF, 1);  // CF = is source 0?
+            RBITxw(x3, ed);   // reverse
+            CLZxw(gd, x3);    // x2 gets leading 0 == TZCNT
             TSTxw_REG(gd, gd);
-            CSETw(x1, cEQ);
-            BFIw(xFlags, x1, F_ZF, 1);  // ZF = is dest 0?
+            CSETw(x3, cEQ);
+            BFIw(xFlags, x3, F_ZF, 1);  // ZF = is dest 0?
+            break;
+        case 0xBD:
+            INST_NAME("LZCNT Gd, Ed");
+            SETFLAGS(X_CF|X_ZF, SF_SUBSET);
+            SET_DFNONE(x1);
+            nextop = F8;
+            GETED(0);
+            GETGD;
+            TSTxw_REG(ed, ed);
+            CSETw(x3, cEQ);
+            BFIw(xFlags, x3, F_CF, 1);  // CF = is source 0?
+            CLZxw(gd, ed);    // x2 gets leading 0 == LZCNT
+            TSTxw_REG(gd, gd);
+            CSETw(x3, cEQ);
+            BFIw(xFlags, x3, F_ZF, 1);  // ZF = is dest 0?
             break;
 
         case 0xC2:
             INST_NAME("CMPSS Gx, Ex, Ib");
             nextop = F8;
-            GETGX(v0);
-            GETEX(v1, 1);
+            GETGX(v0, 1);
+            GETEXSS(v1, 0, 1);
             u8 = F8;
-            if((u8&7)==6){
-                FCMPS(v1, v0);
-            } else {
-                FCMPS(v0, v1);
-            }
+            FCMPS(v0, v1);
             switch(u8&7) {
                 case 0: CSETMw(x2, cEQ); break;   // Equal
-                case 1: CSETMw(x2, cMI); break;   // Less than
-                case 2: //CSETMw(x2, cLE); break;   // Less or equal (or unordered on ARM64, not on x86...)
-                        CSETMw(x2, cPL); CSINVw(x2, xZR, x2, cEQ); break;   // so use a 2 step here, but 1st test inverted because 2nd step invert again
+                case 1: CSETMw(x2, cCC); break;   // Less than
+                case 2: CSETMw(x2, cLS); break;   // Less or equal
                 case 3: CSETMw(x2, cVS); break;   // NaN
-                case 4: CSETMw(x2, cNE); break;   // Not Equal (or unordered on ARM, not on X86...)
+                case 4: CSETMw(x2, cNE); break;   // Not Equal or unordered
                 case 5: CSETMw(x2, cCS); break;   // Greater or equal or unordered
-                case 6: CSETMw(x2, cLT); break;   // Greater or unordered, test inverted, N!=V so unordereded or less than (inverted)
+                case 6: CSETMw(x2, cHI); break;   // Greater or unordered, test inverted, N!=V so unordered or less than (inverted)
                 case 7: CSETMw(x2, cVC); break;   // not NaN
             }
             VMOVQSfrom(v0, 0, x2);
@@ -372,19 +470,20 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
             nextop = F8;
             GETGX_empty(v0);
             if(MODREG) {
-                v1 = mmx_get_reg(dyn, ninst, x1, (nextop&7));
+                v1 = mmx_get_reg(dyn, ninst, x1, x2, x3, (nextop&7));
                 VEORQ(v0, v0, v0);  // usefull?
                 VMOV(v0, v1);
             } else {
-                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0xfff<<3, 7, rex, 0, 0);
-                VLDR64_U12(v0, ed, fixedaddress);
+                SMREAD();
+                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, &unscaled, 0xfff<<3, 7, rex, NULL, 0, 0);
+                VLD64(v0, ed, fixedaddress);
             }
             break;
 
         case 0xE6:
             INST_NAME("CVTDQ2PD Gx, Ex");
             nextop = F8;
-            GETEX(v1, 0);
+            GETEXSD(v1, 0, 0);
             GETGX_empty(v0);
             d0 = fpu_get_scratch(dyn);
             SXTL_32(v0, v1);
@@ -396,4 +495,3 @@ uintptr_t dynarec64_F30F(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int n
     }
     return addr;
 }
-

src/dynarec/arm64/dynarec_arm64_functions.c

@@ -0,0 +1,583 @@
+#define _GNU_SOURCE
+#include <stdio.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <string.h>
+#include <math.h>
+#include <signal.h>
+#include <sys/types.h>
+#include <unistd.h>
+
+#include "debug.h"
+#include "box64context.h"
+#include "dynarec.h"
+#include "emu/x64emu_private.h"
+#include "x64run.h"
+#include "x64emu.h"
+#include "box64stack.h"
+#include "callback.h"
+#include "emu/x64run_private.h"
+#include "emu/x87emu_private.h"
+#include "x64trace.h"
+#include "signals.h"
+#include "dynarec_native.h"
+#include "dynarec_arm64_private.h"
+#include "dynarec_arm64_functions.h"
+#include "custommem.h"
+#include "bridge.h"
+
+#define XMM0    0
+#define XMM8    16
+#define X870    8
+#define EMM0    8
+#define SCRATCH0    24
+
+// Get a FPU scratch reg
+int fpu_get_scratch(dynarec_arm_t* dyn)
+{
+    return SCRATCH0 + dyn->n.fpu_scratch++;  // return an Sx
+}
+// Reset scratch regs counter
+void fpu_reset_scratch(dynarec_arm_t* dyn)
+{
+    dyn->n.fpu_scratch = 0;
+}
+// Get a x87 double reg
+int fpu_get_reg_x87(dynarec_arm_t* dyn, int t, int n)
+{
+    int i=X870;
+    while (dyn->n.fpuused[i]) ++i;
+    dyn->n.fpuused[i] = 1;
+    dyn->n.neoncache[i].n = n;
+    dyn->n.neoncache[i].t = t;
+    dyn->n.news |= (1<<i);
+    return i; // return a Dx
+}
+// Free a FPU double reg
+void fpu_free_reg(dynarec_arm_t* dyn, int reg)
+{
+    // TODO: check upper limit?
+    dyn->n.fpuused[reg] = 0;
+    if(dyn->n.neoncache[reg].t!=NEON_CACHE_ST_F && dyn->n.neoncache[reg].t!=NEON_CACHE_ST_D && dyn->n.neoncache[reg].t!=NEON_CACHE_ST_I64)
+        dyn->n.neoncache[reg].v = 0;
+}
+// Get an MMX double reg
+int fpu_get_reg_emm(dynarec_arm_t* dyn, int emm)
+{
+    dyn->n.fpuused[EMM0 + emm] = 1;
+    dyn->n.neoncache[EMM0 + emm].t = NEON_CACHE_MM;
+    dyn->n.neoncache[EMM0 + emm].n = emm;
+    dyn->n.news |= (1<<(EMM0 + emm));
+    return EMM0 + emm;
+}
+// Get an XMM quad reg
+int fpu_get_reg_xmm(dynarec_arm_t* dyn, int t, int xmm)
+{
+    int i;
+    if(xmm>7) {
+        i = XMM8 + xmm - 8;
+    } else {
+        i = XMM0 + xmm;
+    }
+    dyn->n.fpuused[i] = 1;
+    dyn->n.neoncache[i].t = t;
+    dyn->n.neoncache[i].n = xmm;
+    dyn->n.news |= (1<<i);
+    return i;
+}
+// Reset fpu regs counter
+void fpu_reset_reg(dynarec_arm_t* dyn)
+{
+    dyn->n.fpu_reg = 0;
+    for (int i=0; i<24; ++i) {
+        dyn->n.fpuused[i]=0;
+        dyn->n.neoncache[i].v = 0;
+    }
+
+}
+
+int neoncache_get_st(dynarec_arm_t* dyn, int ninst, int a)
+{
+    if (dyn->insts[ninst].n.swapped) {
+        if(dyn->insts[ninst].n.combined1 == a)
+            a = dyn->insts[ninst].n.combined2;
+        else if(dyn->insts[ninst].n.combined2 == a)
+            a = dyn->insts[ninst].n.combined1;
+    }
+    for(int i=0; i<24; ++i)
+        if((dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F
+         || dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_D
+         || dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_I64)
+         && dyn->insts[ninst].n.neoncache[i].n==a)
+            return dyn->insts[ninst].n.neoncache[i].t;
+    // not in the cache yet, so will be fetched...
+    return NEON_CACHE_ST_D;
+}
+
+int neoncache_get_current_st(dynarec_arm_t* dyn, int ninst, int a)
+{
+    (void)ninst;
+    if(!dyn->insts)
+        return NEON_CACHE_ST_D;
+    for(int i=0; i<24; ++i)
+        if((dyn->n.neoncache[i].t==NEON_CACHE_ST_F
+         || dyn->n.neoncache[i].t==NEON_CACHE_ST_D
+         || dyn->n.neoncache[i].t==NEON_CACHE_ST_I64)
+         && dyn->n.neoncache[i].n==a)
+            return dyn->n.neoncache[i].t;
+    // not in the cache yet, so will be fetched...
+    return NEON_CACHE_ST_D;
+}
+
+int neoncache_get_st_f(dynarec_arm_t* dyn, int ninst, int a)
+{
+    /*if(a+dyn->insts[ninst].n.stack_next-st<0)
+        // The STx has been pushed at the end of instructon, so stop going back
+        return -1;*/
+    for(int i=0; i<24; ++i)
+        if(dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F
+         && dyn->insts[ninst].n.neoncache[i].n==a)
+            return i;
+    return -1;
+} 
+int neoncache_get_st_f_i64(dynarec_arm_t* dyn, int ninst, int a)
+{
+    /*if(a+dyn->insts[ninst].n.stack_next-st<0)
+        // The STx has been pushed at the end of instructon, so stop going back
+        return -1;*/
+    for(int i=0; i<24; ++i)
+        if((dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_I64 || dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F)
+         && dyn->insts[ninst].n.neoncache[i].n==a)
+            return i;
+    return -1;
+} 
+int neoncache_get_st_f_noback(dynarec_arm_t* dyn, int ninst, int a)
+{
+    for(int i=0; i<24; ++i)
+        if(dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F
+         && dyn->insts[ninst].n.neoncache[i].n==a)
+            return i;
+    return -1;
+} 
+int neoncache_get_st_f_i64_noback(dynarec_arm_t* dyn, int ninst, int a)
+{
+    for(int i=0; i<24; ++i)
+        if((dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_I64 || dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F)
+         && dyn->insts[ninst].n.neoncache[i].n==a)
+            return i;
+    return -1;
+} 
+int neoncache_get_current_st_f(dynarec_arm_t* dyn, int a)
+{
+    for(int i=0; i<24; ++i)
+        if(dyn->n.neoncache[i].t==NEON_CACHE_ST_F
+         && dyn->n.neoncache[i].n==a)
+            return i;
+    return -1;
+} 
+int neoncache_get_current_st_f_i64(dynarec_arm_t* dyn, int a)
+{
+    for(int i=0; i<24; ++i)
+        if((dyn->n.neoncache[i].t==NEON_CACHE_ST_I64 || dyn->n.neoncache[i].t==NEON_CACHE_ST_F)
+         && dyn->n.neoncache[i].n==a)
+            return i;
+    return -1;
+} 
+static void neoncache_promote_double_forward(dynarec_arm_t* dyn, int ninst, int maxinst, int a);
+static void neoncache_promote_double_internal(dynarec_arm_t* dyn, int ninst, int maxinst, int a);
+static void neoncache_promote_double_combined(dynarec_arm_t* dyn, int ninst, int maxinst, int a)
+{
+    if(a == dyn->insts[ninst].n.combined1 || a == dyn->insts[ninst].n.combined2) {
+        if(a == dyn->insts[ninst].n.combined1) {
+            a = dyn->insts[ninst].n.combined2;
+        } else 
+            a = dyn->insts[ninst].n.combined1;
+        int i = neoncache_get_st_f_i64_noback(dyn, ninst, a);
+        //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double_combined, ninst=%d combined%c %d i=%d (stack:%d/%d)\n", ninst, (a == dyn->insts[ninst].n.combined2)?'2':'1', a ,i, dyn->insts[ninst].n.stack_push, -dyn->insts[ninst].n.stack_pop);
+        if(i>=0) {
+            dyn->insts[ninst].n.neoncache[i].t = NEON_CACHE_ST_D;
+            if(!dyn->insts[ninst].n.barrier)
+                neoncache_promote_double_internal(dyn, ninst-1, maxinst, a-dyn->insts[ninst].n.stack_push);
+            // go forward is combined is not pop'd
+            if(a-dyn->insts[ninst].n.stack_pop>=0)
+                if(!dyn->insts[ninst+1].n.barrier)
+                    neoncache_promote_double_forward(dyn, ninst+1, maxinst, a-dyn->insts[ninst].n.stack_pop);
+        }
+    }
+}
+static void neoncache_promote_double_internal(dynarec_arm_t* dyn, int ninst, int maxinst, int a)
+{
+    if(dyn->insts[ninst+1].n.barrier)
+        return;
+    while(ninst>=0) {
+        a+=dyn->insts[ninst].n.stack_pop;    // adjust Stack depth: add pop'd ST (going backward)
+        int i = neoncache_get_st_f_i64(dyn, ninst, a);
+        //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double_internal, ninst=%d, a=%d st=%d:%d, i=%d\n", ninst, a, dyn->insts[ninst].n.stack, dyn->insts[ninst].n.stack_next, i);
+        if(i<0) return;
+        dyn->insts[ninst].n.neoncache[i].t = NEON_CACHE_ST_D;
+        // check combined propagation too
+        if(dyn->insts[ninst].n.combined1 || dyn->insts[ninst].n.combined2) {
+            if(dyn->insts[ninst].n.swapped) {
+                //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double_internal, ninst=%d swapped %d/%d vs %d with st %d\n", ninst, dyn->insts[ninst].n.combined1 ,dyn->insts[ninst].n.combined2, a, dyn->insts[ninst].n.stack);
+                if (a==dyn->insts[ninst].n.combined1)
+                    a = dyn->insts[ninst].n.combined2;
+                else if (a==dyn->insts[ninst].n.combined2)
+                    a = dyn->insts[ninst].n.combined1;
+            } else {
+                //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double_internal, ninst=%d combined %d/%d vs %d with st %d\n", ninst, dyn->insts[ninst].n.combined1 ,dyn->insts[ninst].n.combined2, a, dyn->insts[ninst].n.stack);
+                neoncache_promote_double_combined(dyn, ninst, maxinst, a);
+            }
+        }
+        a-=dyn->insts[ninst].n.stack_push;  // // adjust Stack depth: remove push'd ST (going backward)
+        --ninst;
+        if(ninst<0 || a<0 || dyn->insts[ninst].n.barrier)
+            return;
+    }
+}
+
+static void neoncache_promote_double_forward(dynarec_arm_t* dyn, int ninst, int maxinst, int a)
+{
+    while((ninst!=-1) && (ninst<maxinst) && (a>=0)) {
+        a+=dyn->insts[ninst].n.stack_push;  // // adjust Stack depth: add push'd ST (going forward)
+        if((dyn->insts[ninst].n.combined1 || dyn->insts[ninst].n.combined2) && dyn->insts[ninst].n.swapped) {
+            //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double_forward, ninst=%d swapped %d/%d vs %d with st %d\n", ninst, dyn->insts[ninst].n.combined1 ,dyn->insts[ninst].n.combined2, a, dyn->insts[ninst].n.stack);
+            if (a==dyn->insts[ninst].n.combined1)
+                a = dyn->insts[ninst].n.combined2;
+            else if (a==dyn->insts[ninst].n.combined2)
+                a = dyn->insts[ninst].n.combined1;
+        }
+        int i = neoncache_get_st_f_i64_noback(dyn, ninst, a);
+        //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double_forward, ninst=%d, a=%d st=%d:%d(%d/%d), i=%d\n", ninst, a, dyn->insts[ninst].n.stack, dyn->insts[ninst].n.stack_next, dyn->insts[ninst].n.stack_push, -dyn->insts[ninst].n.stack_pop, i);
+        if(i<0) return;
+        dyn->insts[ninst].n.neoncache[i].t = NEON_CACHE_ST_D;
+        // check combined propagation too
+        if((dyn->insts[ninst].n.combined1 || dyn->insts[ninst].n.combined2) && !dyn->insts[ninst].n.swapped) {
+            //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double_forward, ninst=%d combined %d/%d vs %d with st %d\n", ninst, dyn->insts[ninst].n.combined1 ,dyn->insts[ninst].n.combined2, a, dyn->insts[ninst].n.stack);
+            neoncache_promote_double_combined(dyn, ninst, maxinst, a);
+        }
+        a-=dyn->insts[ninst].n.stack_pop;    // adjust Stack depth: remove pop'd ST (going forward)
+        if(dyn->insts[ninst].x64.has_next && !dyn->insts[ninst].n.barrier)
+            ++ninst;
+        else
+            ninst=-1;
+    }
+    if(ninst==maxinst)
+        neoncache_promote_double(dyn, ninst, a);
+}
+
+void neoncache_promote_double(dynarec_arm_t* dyn, int ninst, int a)
+{
+    int i = neoncache_get_current_st_f_i64(dyn, a);
+    //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double, ninst=%d a=%d st=%d i=%d\n", ninst, a, dyn->n.stack, i);
+    if(i<0) return;
+    dyn->n.neoncache[i].t = NEON_CACHE_ST_D;
+    dyn->insts[ninst].n.neoncache[i].t = NEON_CACHE_ST_D;
+    // check combined propagation too
+    if(dyn->n.combined1 || dyn->n.combined2) {
+        if(dyn->n.swapped) {
+            //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double, ninst=%d swapped! %d/%d vs %d\n", ninst, dyn->n.combined1 ,dyn->n.combined2, a);
+            if(dyn->n.combined1 == a)
+                a = dyn->n.combined2;
+            else if(dyn->n.combined2 == a)
+                a = dyn->n.combined1;
+        } else {
+            //if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double, ninst=%d combined! %d/%d vs %d\n", ninst, dyn->n.combined1 ,dyn->n.combined2, a);
+            if(dyn->n.combined1 == a)
+                neoncache_promote_double(dyn, ninst, dyn->n.combined2);
+            else if(dyn->n.combined2 == a)
+                neoncache_promote_double(dyn, ninst, dyn->n.combined1);
+        }
+    }
+    a-=dyn->insts[ninst].n.stack_push;  // // adjust Stack depth: remove push'd ST (going backward)
+    if(!ninst || a<0) return;
+    neoncache_promote_double_internal(dyn, ninst-1, ninst, a);
+}
+
+int neoncache_combine_st(dynarec_arm_t* dyn, int ninst, int a, int b)
+{
+    dyn->n.combined1=a;
+    dyn->n.combined2=b;
+    if( neoncache_get_current_st(dyn, ninst, a)==NEON_CACHE_ST_F
+     && neoncache_get_current_st(dyn, ninst, b)==NEON_CACHE_ST_F )
+        return NEON_CACHE_ST_F;
+    // don't combine i64, it's only for load/store
+    /*if( neoncache_get_current_st(dyn, ninst, a)==NEON_CACHE_ST_I64
+     && neoncache_get_current_st(dyn, ninst, b)==NEON_CACHE_ST_I64 )
+        return NEON_CACHE_ST_I64;*/
+    return NEON_CACHE_ST_D;
+}
+
+static int isCacheEmpty(dynarec_native_t* dyn, int ninst) {
+    if(dyn->insts[ninst].n.stack_next) {
+        return 0;
+    }
+    for(int i=0; i<24; ++i)
+        if(dyn->insts[ninst].n.neoncache[i].v) {       // there is something at ninst for i
+            if(!(
+            (dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F 
+             || dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_D
+             || dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_I64)
+            && dyn->insts[ninst].n.neoncache[i].n<dyn->insts[ninst].n.stack_pop))
+                return 0;
+        }
+    return 1;
+
+}
+
+int fpuCacheNeedsTransform(dynarec_arm_t* dyn, int ninst) {
+    int i2 = dyn->insts[ninst].x64.jmp_insts;
+    if(i2<0)
+        return 1;
+    if((dyn->insts[i2].x64.barrier&BARRIER_FLOAT))
+        // if the barrier as already been apply, no transform needed
+        return ((dyn->insts[ninst].x64.barrier&BARRIER_FLOAT))?0:(isCacheEmpty(dyn, ninst)?0:1);
+    int ret = 0;
+    if(!i2) { // just purge
+        if(dyn->insts[ninst].n.stack_next) {
+            return 1;
+        }
+        for(int i=0; i<24 && !ret; ++i)
+            if(dyn->insts[ninst].n.neoncache[i].v) {       // there is something at ninst for i
+                if(!(
+                (dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F 
+                || dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_D
+                || dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_I64)
+                && dyn->insts[ninst].n.neoncache[i].n<dyn->insts[ninst].n.stack_pop))
+                    ret = 1;
+            }
+        return ret;
+    }
+    // Check if ninst can be compatible to i2
+    if(dyn->insts[ninst].n.stack_next != dyn->insts[i2].n.stack-dyn->insts[i2].n.stack_push) {
+        return 1;
+    }
+    neoncache_t cache_i2 = dyn->insts[i2].n;
+    neoncacheUnwind(&cache_i2);
+
+    for(int i=0; i<24; ++i) {
+        if(dyn->insts[ninst].n.neoncache[i].v) {       // there is something at ninst for i
+            if(!cache_i2.neoncache[i].v) {    // but there is nothing at i2 for i
+                ret = 1;
+            } else if(dyn->insts[ninst].n.neoncache[i].v!=cache_i2.neoncache[i].v) {  // there is something different
+                if(dyn->insts[ninst].n.neoncache[i].n!=cache_i2.neoncache[i].n) {   // not the same x64 reg
+                    ret = 1;
+                }
+                else if(dyn->insts[ninst].n.neoncache[i].t == NEON_CACHE_XMMR && cache_i2.neoncache[i].t == NEON_CACHE_XMMW)
+                    {/* nothing */ }
+                else
+                    ret = 1;
+            }
+        } else if(cache_i2.neoncache[i].v)
+            ret = 1;
+    }
+    return ret;
+}
+
+void neoncacheUnwind(neoncache_t* cache)
+{
+    if(cache->swapped) {
+        // unswap
+        int a = -1; 
+        int b = -1;
+        for(int j=0; j<24 && ((a==-1) || (b==-1)); ++j)
+            if((cache->neoncache[j].t == NEON_CACHE_ST_D || cache->neoncache[j].t == NEON_CACHE_ST_F || cache->neoncache[j].t == NEON_CACHE_ST_I64)) {
+                if(cache->neoncache[j].n == cache->combined1)
+                    a = j;
+                else if(cache->neoncache[j].n == cache->combined2)
+                    b = j;
+            }
+        if(a!=-1 && b!=-1) {
+            int tmp = cache->neoncache[a].n;
+            cache->neoncache[a].n = cache->neoncache[b].n;
+            cache->neoncache[b].n = tmp;
+        }
+        cache->swapped = 0;
+        cache->combined1 = cache->combined2 = 0;
+    }
+    if(cache->news) {
+        // reove the newly created neoncache
+        for(int i=0; i<24; ++i)
+            if(cache->news&(1<<i))
+                cache->neoncache[i].v = 0;
+        cache->news = 0;
+    }
+    if(cache->stack_push) {
+        // unpush
+        for(int j=0; j<24; ++j) {
+            if((cache->neoncache[j].t == NEON_CACHE_ST_D || cache->neoncache[j].t == NEON_CACHE_ST_F || cache->neoncache[j].t == NEON_CACHE_ST_I64)) {
+                if(cache->neoncache[j].n<cache->stack_push)
+                    cache->neoncache[j].v = 0;
+                else
+                    cache->neoncache[j].n-=cache->stack_push;
+            }
+        }
+        cache->x87stack-=cache->stack_push;
+        cache->stack-=cache->stack_push;
+        cache->stack_push = 0;
+    }
+    cache->x87stack+=cache->stack_pop;
+    cache->stack_next = cache->stack;
+    cache->stack_pop = 0;
+    cache->barrier = 0;
+    // And now, rebuild the x87cache info with neoncache
+    cache->mmxcount = 0;
+    cache->fpu_scratch = 0;
+    cache->fpu_extra_qscratch = 0;
+    cache->fpu_reg = 0;
+    for(int i=0; i<8; ++i) {
+        cache->x87cache[i] = -1;
+        cache->mmxcache[i] = -1;
+        cache->x87reg[i] = 0;
+        cache->ssecache[i*2].v = -1;
+        cache->ssecache[i*2+1].v = -1;
+    }
+    int x87reg = 0;
+    for(int i=0; i<24; ++i) {
+        if(cache->neoncache[i].v) {
+            cache->fpuused[i] = 1;
+            switch (cache->neoncache[i].t) {
+                case NEON_CACHE_MM:
+                    cache->mmxcache[cache->neoncache[i].n] = i;
+                    ++cache->mmxcount;
+                    ++cache->fpu_reg;
+                    break;
+                case NEON_CACHE_XMMR:
+                case NEON_CACHE_XMMW:
+                    cache->ssecache[cache->neoncache[i].n].reg = i;
+                    cache->ssecache[cache->neoncache[i].n].write = (cache->neoncache[i].t==NEON_CACHE_XMMW)?1:0;
+                    ++cache->fpu_reg;
+                    break;
+                case NEON_CACHE_ST_F:
+                case NEON_CACHE_ST_D:
+                case NEON_CACHE_ST_I64:
+                    cache->x87cache[x87reg] = cache->neoncache[i].n;
+                    cache->x87reg[x87reg] = i;
+                    ++x87reg;
+                    ++cache->fpu_reg;
+                    break;
+                case NEON_CACHE_SCR:
+                    cache->fpuused[i] = 0;
+                    cache->neoncache[i].v = 0;
+                    break;
+            }
+        } else {
+            cache->fpuused[i] = 0;
+        }
+    }
+}
+
+#define F8      *(uint8_t*)(addr++)
+#define F32S64  (uint64_t)(int64_t)*(int32_t*)(addr+=4, addr-4)
+// Get if ED will have the correct parity. Not emiting anything. Parity is 2 for DWORD or 3 for QWORD
+int getedparity(dynarec_arm_t* dyn, int ninst, uintptr_t addr, uint8_t nextop, int parity, int delta)
+{
+    (void)dyn; (void)ninst;
+
+    uint32_t tested = (1<<parity)-1;
+    if((nextop&0xC0)==0xC0)
+        return 0;   // direct register, no parity...
+    if(!(nextop&0xC0)) {
+        if((nextop&7)==4) {
+            uint8_t sib = F8;
+            int sib_reg = (sib>>3)&7;
+            if((sib&0x7)==5) {
+                uint64_t tmp = F32S64;
+                if (sib_reg!=4) {
+                    // if XXXXXX+reg<<N then check parity of XXXXX and N should be enough
+                    return ((tmp&tested)==0 && (sib>>6)>=parity)?1:0;
+                } else {
+                    // just a constant...
+                    return (tmp&tested)?0:1;
+                }
+            } else {
+                if(sib_reg==4 && parity<3)
+                    return 0;   // simple [reg]
+                // don't try [reg1 + reg2<<N], unless reg1 is ESP
+                return ((sib&0x7)==4 && (sib>>6)>=parity)?1:0;
+            }
+        } else if((nextop&7)==5) {
+            uint64_t tmp = F32S64;
+            tmp+=addr+delta;
+            return (tmp&tested)?0:1;
+        } else {
+            return 0;
+        }
+    } else {
+        return 0; //Form [reg1 + reg2<<N + XXXXXX]
+    }
+}
+#undef F8
+#undef F32S64
+
+const char* getCacheName(int t, int n)
+{
+    static char buff[20];
+    switch(t) {
+        case NEON_CACHE_ST_D: sprintf(buff, "ST%d", n); break;
+        case NEON_CACHE_ST_F: sprintf(buff, "st%d", n); break;
+        case NEON_CACHE_ST_I64: sprintf(buff, "STi%d", n); break;
+        case NEON_CACHE_MM: sprintf(buff, "MM%d", n); break;
+        case NEON_CACHE_XMMW: sprintf(buff, "XMM%d", n); break;
+        case NEON_CACHE_XMMR: sprintf(buff, "xmm%d", n); break;
+        case NEON_CACHE_SCR: sprintf(buff, "Scratch"); break;
+        case NEON_CACHE_NONE: buff[0]='\0'; break;
+    }
+    return buff;
+}
+
+void inst_name_pass3(dynarec_native_t* dyn, int ninst, const char* name, rex_t rex)
+{
+    if(box64_dynarec_dump) {
+        printf_x64_instruction(rex.is32bits?my_context->dec32:my_context->dec, &dyn->insts[ninst].x64, name);
+        dynarec_log(LOG_NONE, "%s%p: %d emitted opcodes, inst=%d, barrier=%d state=%d/%d(%d), %s=%X/%X, use=%X, need=%X/%X, sm=%d/%d",
+            (box64_dynarec_dump>1)?"\e[32m":"",
+            (void*)(dyn->native_start+dyn->insts[ninst].address),
+            dyn->insts[ninst].size/4,
+            ninst,
+            dyn->insts[ninst].x64.barrier,
+            dyn->insts[ninst].x64.state_flags,
+            dyn->f.pending,
+            dyn->f.dfnone,
+            dyn->insts[ninst].x64.may_set?"may":"set",
+            dyn->insts[ninst].x64.set_flags,
+            dyn->insts[ninst].x64.gen_flags,
+            dyn->insts[ninst].x64.use_flags,
+            dyn->insts[ninst].x64.need_before,
+            dyn->insts[ninst].x64.need_after,
+            dyn->smread, dyn->smwrite);
+        if(dyn->insts[ninst].pred_sz) {
+            dynarec_log(LOG_NONE, ", pred=");
+            for(int ii=0; ii<dyn->insts[ninst].pred_sz; ++ii)
+                dynarec_log(LOG_NONE, "%s%d", ii?"/":"", dyn->insts[ninst].pred[ii]);
+        }
+        if(dyn->insts[ninst].x64.jmp && dyn->insts[ninst].x64.jmp_insts>=0)
+            dynarec_log(LOG_NONE, ", jmp=%d", dyn->insts[ninst].x64.jmp_insts);
+        if(dyn->insts[ninst].x64.jmp && dyn->insts[ninst].x64.jmp_insts==-1)
+            dynarec_log(LOG_NONE, ", jmp=out");
+        if(dyn->last_ip)
+            dynarec_log(LOG_NONE, ", last_ip=%p", (void*)dyn->last_ip);
+        for(int ii=0; ii<24; ++ii) {
+            switch(dyn->insts[ninst].n.neoncache[ii].t) {
+                case NEON_CACHE_ST_D: dynarec_log(LOG_NONE, " D%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;
+                case NEON_CACHE_ST_F: dynarec_log(LOG_NONE, " S%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;
+                case NEON_CACHE_ST_I64: dynarec_log(LOG_NONE, " D%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;
+                case NEON_CACHE_MM: dynarec_log(LOG_NONE, " D%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;
+                case NEON_CACHE_XMMW: dynarec_log(LOG_NONE, " Q%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;
+                case NEON_CACHE_XMMR: dynarec_log(LOG_NONE, " Q%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;
+                case NEON_CACHE_SCR: dynarec_log(LOG_NONE, " D%d:%s", ii, getCacheName(dyn->insts[ninst].n.neoncache[ii].t, dyn->insts[ninst].n.neoncache[ii].n)); break;
+                case NEON_CACHE_NONE:
+                default:    break;
+            }
+        }
+        if(dyn->n.stack || dyn->insts[ninst].n.stack_next || dyn->insts[ninst].n.x87stack)
+            dynarec_log(LOG_NONE, " X87:%d/%d(+%d/-%d)%d", dyn->n.stack, dyn->insts[ninst].n.stack_next, dyn->insts[ninst].n.stack_push, dyn->insts[ninst].n.stack_pop, dyn->insts[ninst].n.x87stack);
+        if(dyn->insts[ninst].n.combined1 || dyn->insts[ninst].n.combined2)
+            dynarec_log(LOG_NONE, " %s:%d/%d", dyn->insts[ninst].n.swapped?"SWP":"CMB", dyn->insts[ninst].n.combined1, dyn->insts[ninst].n.combined2);
+        dynarec_log(LOG_NONE, "%s\n", (box64_dynarec_dump>1)?"\e[m":"");
+    }
+}
+
+void print_opcode(dynarec_native_t* dyn, int ninst, uint32_t opcode)
+{
+    dynarec_log(LOG_NONE, "\t%08x\t%s\n", opcode, arm64_print(opcode, (uintptr_t)dyn->block));
+}

src/dynarec/arm64/dynarec_arm64_functions.h

@@ -0,0 +1,52 @@
+#ifndef __DYNAREC_ARM_FUNCTIONS_H__
+#define __DYNAREC_ARM_FUNCTIONS_H__
+
+#include "../dynarec_native_functions.h"
+
+// Get an FPU scratch reg
+int fpu_get_scratch(dynarec_arm_t* dyn);
+// Reset scratch regs counter
+void fpu_reset_scratch(dynarec_arm_t* dyn);
+// Get an x87 double reg
+int fpu_get_reg_x87(dynarec_arm_t* dyn, int t, int n);
+// Get an MMX double reg
+int fpu_get_reg_emm(dynarec_arm_t* dyn, int emm);
+// Get an XMM quad reg
+int fpu_get_reg_xmm(dynarec_arm_t* dyn, int t, int xmm);
+// Free a FPU/MMX/XMM reg
+void fpu_free_reg(dynarec_arm_t* dyn, int reg);
+// Reset fpu regs counter
+void fpu_reset_reg(dynarec_arm_t* dyn);
+
+// ---- Neon cache functions
+// Get type for STx
+int neoncache_get_st(dynarec_arm_t* dyn, int ninst, int a);
+// Get if STx is FLOAT
+int neoncache_get_st_f(dynarec_arm_t* dyn, int ninst, int a);
+// Get if STx is FLOAT or I64
+int neoncache_get_st_f_i64(dynarec_arm_t* dyn, int ninst, int a);
+// Get actual type for STx
+int neoncache_get_current_st(dynarec_arm_t* dyn, int ninst, int a);
+// Get actual STx is FLOAT
+int neoncache_get_current_st_f(dynarec_arm_t* dyn, int a);
+// Get actual STx is FLOAT or I64
+int neoncache_get_current_st_f_i64(dynarec_arm_t* dyn, int a);
+// Back-propagate a change float->double
+void neoncache_promote_double(dynarec_arm_t* dyn, int ninst, int a);
+// Combine and propagate if needed (pass 1 only)
+int neoncache_combine_st(dynarec_arm_t* dyn, int ninst, int a, int b);  // with stack current dyn->n_stack*
+
+// FPU Cache transformation (for loops) // Specific, need to be written by backend
+int fpuCacheNeedsTransform(dynarec_arm_t* dyn, int ninst);
+
+// Undo the changes of a neoncache to get the status before the instruction
+void neoncacheUnwind(neoncache_t* cache);
+
+// Get if ED will have the correct parity. Not emiting anything. Parity is 2 for DWORD or 3 for QWORD
+int getedparity(dynarec_native_t* dyn, int ninst, uintptr_t addr, uint8_t nextop, int parity, int delta);
+
+const char* getCacheName(int t, int n);
+
+void inst_name_pass3(dynarec_native_t* dyn, int ninst, const char* name, rex_t rex);
+void print_opcode(dynarec_native_t* dyn, int ninst, uint32_t opcode);
+#endif //__DYNAREC_ARM_FUNCTIONS_H__

src/dynarec/arm64/dynarec_arm64_jmpnext.c

@@ -0,0 +1,11 @@
+#include <stdint.h>
+
+#include "arm64_emitter.h"
+
+#define EMIT(A) *block = (A); ++block
+void CreateJmpNext(void* addr, void* next)
+{
+    uint32_t* block = (uint32_t*)addr;
+    LDRx_literal(x2, (intptr_t)next - (intptr_t)addr);
+    BR(x2);
+}

src/dynarec/arm64/dynarec_arm64_pass0.h

@@ -0,0 +1,54 @@
+
+#define INIT    uintptr_t sav_addr=addr
+#define FINI    \
+    dyn->isize = addr-sav_addr;         \
+    dyn->insts[ninst].x64.addr = addr;  \
+    if(ninst) dyn->insts[ninst-1].x64.size = dyn->insts[ninst].x64.addr - dyn->insts[ninst-1].x64.addr
+
+#define MESSAGE(A, ...)  
+#define MAYSETFLAGS()   dyn->insts[ninst].x64.may_set = 1
+#define READFLAGS(A)    \
+        dyn->insts[ninst].x64.use_flags = A; dyn->f.dfnone = 1;\
+        dyn->f.pending=SF_SET
+#define SETFLAGS(A,B)   \
+        dyn->insts[ninst].x64.set_flags = A;    \
+        dyn->insts[ninst].x64.state_flags = B;  \
+        dyn->f.pending=(B)&SF_SET_PENDING;      \
+        dyn->f.dfnone=((B)&SF_SET)?1:0;
+#define EMIT(A)     
+#define JUMP(A, C)         add_next(dyn, (uintptr_t)A); dyn->insts[ninst].x64.jmp = A; dyn->insts[ninst].x64.jmp_cond = C
+#define BARRIER(A)      if(A!=BARRIER_MAYBE) {fpu_purgecache(dyn, ninst, 0, x1, x2, x3); dyn->insts[ninst].x64.barrier = A;} else dyn->insts[ninst].barrier_maybe = 1
+#define BARRIER_NEXT(A) dyn->insts[ninst+1].x64.barrier = A
+#define NEW_INST \
+        ++dyn->size;                            \
+        if(dyn->size+3>=dyn->cap) {             \
+                dyn->insts = (instruction_native_t*)dynaRealloc(dyn->insts, sizeof(instruction_native_t)*dyn->cap*2);\
+                memset(&dyn->insts[dyn->cap], 0, sizeof(instruction_native_t)*dyn->cap);   \
+                dyn->cap *= 2;                  \
+        }                                       \
+        dyn->insts[ninst].x64.addr = ip;        \
+        dyn->n.combined1 = dyn->n.combined2 = 0;\
+        dyn->n.swapped = 0; dyn->n.barrier = 0; \
+        dyn->insts[ninst].f_entry = dyn->f;     \
+        if(ninst) {dyn->insts[ninst-1].x64.size = dyn->insts[ninst].x64.addr - dyn->insts[ninst-1].x64.addr;}
+
+#define INST_EPILOG                             \
+        dyn->insts[ninst].f_exit = dyn->f;      \
+        dyn->insts[ninst].n = dyn->n;           \
+        dyn->insts[ninst].x64.has_next = (ok>0)?1:0;
+#define INST_NAME(name) 
+#define DEFAULT                         \
+        --dyn->size;                    \
+        *ok = -1;                       \
+        if(box64_dynarec_log>=LOG_INFO || box64_dynarec_dump || box64_dynarec_missing) {\
+        dynarec_log(LOG_NONE, "%p: Dynarec stopped because of %sOpcode %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X %02X", \
+        (void*)ip, rex.is32bits?"32bits ":"",\
+        PKip(0),                        \
+        PKip(1), PKip(2), PKip(3),      \
+        PKip(4), PKip(5), PKip(6),      \
+        PKip(7), PKip(8), PKip(9),      \
+        PKip(10),PKip(11),PKip(12),     \
+        PKip(13),PKip(14));             \
+        printFunctionAddr(ip, " => ");  \
+        dynarec_log(LOG_NONE, "\n");    \
+        }

src/dynarec/arm64/dynarec_arm64_pass1.h

@@ -0,0 +1,14 @@
+#define INIT    
+#define FINI
+#define MESSAGE(A, ...)  
+#define EMIT(A)     
+#define NEW_INST                                \
+        dyn->insts[ninst].f_entry = dyn->f;     \
+        dyn->n.combined1 = dyn->n.combined2 = 0;\
+        dyn->n.swapped = 0; dyn->n.barrier = 0
+
+#define INST_EPILOG                             \
+        dyn->insts[ninst].n = dyn->n;           \
+        dyn->insts[ninst].f_exit = dyn->f
+
+#define INST_NAME(name)  

src/dynarec/arm64/dynarec_arm64_pass2.h

@@ -0,0 +1,18 @@
+#define INIT        dyn->native_size = 0
+#define FINI                                                                                            \
+        if(ninst) {                                                                                     \
+                dyn->insts[ninst].address = (dyn->insts[ninst-1].address+dyn->insts[ninst-1].size);     \
+                dyn->insts_size += 1+((dyn->insts[ninst].x64.size>(dyn->insts[ninst].size/4))?dyn->insts[ninst].x64.size:(dyn->insts[ninst].size/4))/15; \
+        }
+
+#define MESSAGE(A, ...)  
+#define EMIT(A)     do{dyn->insts[ninst].size+=4; dyn->native_size+=4;}while(0)
+#define NEW_INST                                                                                        \
+        if(ninst) {                                                                                     \
+                dyn->insts[ninst].address = (dyn->insts[ninst-1].address+dyn->insts[ninst-1].size);     \
+                dyn->insts_size += 1+((dyn->insts[ninst-1].x64.size>(dyn->insts[ninst-1].size/4))?dyn->insts[ninst-1].x64.size:(dyn->insts[ninst-1].size/4))/15; \
+        }
+#define INST_EPILOG dyn->insts[ninst].epilog = dyn->native_size; 
+#define INST_NAME(name) 
+#define TABLE64(A, V)   {Table64(dyn, (V), 2); EMIT(0);}
+#define FTABLE64(A, V)  {mmx87_regs_t v = {.d = V}; Table64(dyn, v.q, 2); EMIT(0);}

src/dynarec/arm64/dynarec_arm64_pass3.h

@@ -0,0 +1,22 @@
+#define INIT    
+#define FINI        \
+    if(ninst)       \
+        addInst(dyn->instsize, &dyn->insts_size, dyn->insts[ninst].x64.size, dyn->insts[ninst].size/4); \
+    addInst(dyn->instsize, &dyn->insts_size, 0, 0);
+#define EMIT(A)                                         \
+    do{                                                 \
+        if(box64_dynarec_dump) print_opcode(dyn, ninst, (uint32_t)(A)); \
+        if((uintptr_t)dyn->block<dyn->tablestart)       \
+            *(uint32_t*)(dyn->block) = (uint32_t)(A);   \
+        dyn->block += 4; dyn->native_size += 4;         \
+        dyn->insts[ninst].size2 += 4;                   \
+    }while(0)
+
+#define MESSAGE(A, ...)  if(box64_dynarec_dump) dynarec_log(LOG_NONE, __VA_ARGS__)
+#define NEW_INST        \
+    if(ninst)                                                   \
+        addInst(dyn->instsize, &dyn->insts_size, dyn->insts[ninst-1].x64.size, dyn->insts[ninst-1].size/4);
+#define INST_EPILOG     
+#define INST_NAME(name) inst_name_pass3(dyn, ninst, name, rex)
+#define TABLE64(A, V)   {int val64offset = Table64(dyn, (V), 3); MESSAGE(LOG_DUMP, "  Table64: 0x%lx\n", (V)); LDRx_literal(A, val64offset);}
+#define FTABLE64(A, V)  {mmx87_regs_t v = {.d = V}; int val64offset = Table64(dyn, v.q, 3); MESSAGE(LOG_DUMP, "  FTable64: %g\n", v.d); VLDR64_literal(A, val64offset);}

src/dynarec/arm64/dynarec_arm64_private.h

@@ -0,0 +1,137 @@
+#ifndef __DYNAREC_ARM_PRIVATE_H_
+#define __DYNAREC_ARM_PRIVATE_H_
+
+#include "../dynarec_private.h"
+
+typedef struct x64emu_s x64emu_t;
+typedef struct dynablock_s dynablock_t;
+typedef struct instsize_s instsize_t;
+
+#define BARRIER_MAYBE   8
+
+#define NEON_CACHE_NONE     0
+#define NEON_CACHE_ST_D     1
+#define NEON_CACHE_ST_F     2
+#define NEON_CACHE_ST_I64   3
+#define NEON_CACHE_MM       4
+#define NEON_CACHE_XMMW     5
+#define NEON_CACHE_XMMR     6
+#define NEON_CACHE_SCR      7
+typedef union neon_cache_s {
+    int8_t           v;
+    struct {
+        uint8_t t:4;   // reg type
+        uint8_t n:4;   // reg number
+    };
+} neon_cache_t;
+typedef union sse_cache_s {
+    int8_t      v;
+    struct {
+        uint8_t reg:7;
+        uint8_t write:1;
+    };
+} sse_cache_t;
+typedef struct neoncache_s {
+    // Neon cache
+    neon_cache_t        neoncache[24];
+    int8_t              stack;
+    int8_t              stack_next;
+    int8_t              stack_pop;
+    int8_t              stack_push;
+    uint8_t             combined1;
+    uint8_t             combined2;
+    uint8_t             swapped;        // the combined reg were swapped
+    uint8_t             barrier;        // is there a barrier at instruction epilog?
+    uint32_t            news;           // bitmask, wich neoncache are new for this opcode
+    // fpu cache
+    int8_t              x87cache[8];    // cache status for the 8 x87 register behind the fpu stack
+    int8_t              x87reg[8];      // reg used for x87cache entry
+    int8_t              mmxcache[8];    // cache status for the 8 MMX registers
+    sse_cache_t         ssecache[16];   // cache status for the 16 SSE(2) registers
+    int8_t              fpuused[24];    // all 0..24 double reg from fpu, used by x87, sse and mmx
+    int8_t              x87stack;       // cache stack counter
+    int8_t              mmxcount;       // number of mmx register used (not both mmx and x87 at the same time)
+    int8_t              fpu_scratch;    // scratch counter
+    int8_t              fpu_extra_qscratch; // some opcode need an extra quad scratch register
+    int8_t              fpu_reg;        // x87/sse/mmx reg counter
+} neoncache_t;
+
+typedef struct flagcache_s {
+    int                 pending;    // is there a pending flags here, or to check?
+    int                 dfnone;     // if deferred flags is already set to df_none
+} flagcache_t;
+
+typedef struct instruction_arm64_s {
+    instruction_x64_t   x64;
+    uintptr_t           address;    // (start) address of the arm emitted instruction
+    uintptr_t           epilog;     // epilog of current instruction (can be start of next, or barrier stuff)
+    int                 size;       // size of the arm emitted instruction
+    int                 size2;      // size of the arm emitted instrucion after pass2
+    int                 pred_sz;    // size of predecessor list
+    int                 *pred;      // predecessor array
+    uintptr_t           mark, mark2, mark3;
+    uintptr_t           markf, markf2;
+    uintptr_t           markseg;
+    uintptr_t           marklock;
+    int                 pass2choice;// value for choices that are fixed on pass2 for pass3
+    uintptr_t           natcall;
+    int                 retn;
+    int                 barrier_maybe;
+    flagcache_t         f_exit;     // flags status at end of instruction
+    neoncache_t         n;          // neoncache at end of instruction (but before poping)
+    flagcache_t         f_entry;    // flags status before the instruction begin
+} instruction_arm64_t;
+
+typedef struct dynarec_arm_s {
+    instruction_arm64_t*insts;
+    int32_t             size;
+    int32_t             cap;
+    uintptr_t           start;      // start of the block
+    uint32_t            isize;      // size in bytes of x64 instructions included
+    void*               block;      // memory pointer where next instruction is emitted
+    uintptr_t           native_start;  // start of the arm code
+    size_t              native_size;   // size of emitted arm code
+    uintptr_t           last_ip;    // last set IP in RIP (or NULL if unclean state) TODO: move to a cache something
+    uint64_t*           table64;    // table of 64bits values
+    int                 table64size;// size of table (will be appended at end of executable code)
+    int                 table64cap;
+    uintptr_t           tablestart;
+    uintptr_t           jmp_next;   // address of the jump_next address
+    flagcache_t         f;
+    neoncache_t         n;          // cache for the 8..31 double reg from fpu, plus x87 stack delta
+    uintptr_t*          next;       // variable array of "next" jump address
+    int                 next_sz;
+    int                 next_cap;
+    int*                predecessor;// single array of all predecessor
+    dynablock_t*        dynablock;
+    instsize_t*         instsize;
+    size_t              insts_size; // size of the instruction size array (calculated)
+    uint8_t             smread;     // for strongmem model emulation
+    uint8_t             smwrite;    // for strongmem model emulation
+    uintptr_t           forward;    // address of the last end of code while testing forward
+    uintptr_t           forward_to; // address of the next jump to (to check if everything is ok)
+    int32_t             forward_size;   // size at the forward point
+    int                 forward_ninst;  // ninst at the forward point
+    uint8_t             doublepush;
+    uint8_t             doublepop;
+    uint8_t             always_test;
+} dynarec_arm_t;
+
+void add_next(dynarec_arm_t *dyn, uintptr_t addr);
+uintptr_t get_closest_next(dynarec_arm_t *dyn, uintptr_t addr);
+int is_nops(dynarec_arm_t *dyn, uintptr_t addr, int n);
+int is_instructions(dynarec_arm_t *dyn, uintptr_t addr, int n);
+
+int Table64(dynarec_arm_t *dyn, uint64_t val, int pass);  // add a value to table64 (if needed) and gives back the imm19 to use in LDR_literal
+
+void CreateJmpNext(void* addr, void* next);
+
+#define GO_TRACE(A, B)      \
+    GETIP(addr);            \
+    MOVx_REG(x1, xRIP);     \
+    STORE_XEMU_CALL(xRIP);  \
+    MOV32w(x2, B);          \
+    CALL(A, -1);            \
+    LOAD_XEMU_CALL(xRIP)
+
+#endif //__DYNAREC_ARM_PRIVATE_H_

src/dynarec/arm64_lock.S

@@ -1,115 +0,0 @@
-//arm lock helper
-//there is 2 part: read and write
-// write return 0 on success, 1 on fail (value has been changed)
-
-.text
-.align 4
-
-.global arm64_lock_read_b
-.global arm64_lock_write_b
-.global arm64_lock_read_h
-.global arm64_lock_write_h
-.global arm64_lock_read_d
-.global arm64_lock_write_d
-.global arm64_lock_read_dd
-.global arm64_lock_write_dd
-.global arm64_lock_read_dq
-.global arm64_lock_write_dq
-.global arm64_lock_xchg
-.global arm64_lock_storeifnull
-.global arm64_lock_storeifref
-
-
-arm64_lock_read_b:
-    // address is x0, return is x0
-    ldaxrb  w0, [x0]
-    ret
-
-arm64_lock_write_b:
-    // address is x0, value is x1, return is x0
-    mov     x2, x0
-    stlxrb  w0, w1, [x2]
-    ret
-
-arm64_lock_read_h:
-    // address is x0, return is x0
-    ldaxrh  w0, [x0]
-    ret
-
-arm64_lock_write_h:
-    // address is x0, value is x1, return is x0
-    mov     x2, x0
-    stlxrh  w0, w1, [x2]
-    ret
-
-arm64_lock_read_d:
-    // address is x0, return is x0
-    ldaxr    w0, [x0]
-    #ldx     w0,[x0]
-    ret
-
-arm64_lock_write_d:
-    // address is x0, value is w1, return is x0
-    mov     x2, x0
-    stlxr   w0, w1, [x2]
-    #str     w1, [x2]
-    mov     w0, 0
-    ret
-
-arm64_lock_read_dd:
-    // address is x0, return is x0
-    ldaxr   x0, [x0]
-    ret
-
-arm64_lock_write_dd:
-    // address is x0, value is x1, return is x0
-    mov     x2, x0
-    stlxr   w0, x1, [x2]
-    ret
-
-arm64_lock_read_dq:
-    // address is r2, return is r0, r1
-    ldaxp   x4, x3, [x2]
-    str     x4, [x0]
-    str     x3, [x1]
-    ret
-
-arm64_lock_write_dq:
-    // address is r2, value is r0, r1, return is r0
-    // r0 needs to be aligned
-    stlxp   w3, x0, x1, [x2]
-    mov     w0, w3
-    ret
-
-
-arm64_lock_xchg:
-    // address is x0, value is x1, return old value in x0
-    ldaxr   x2, [x0]
-    stlxr   w3, x1, [x0]
-    cbnz    w3, arm64_lock_xchg
-    mov     x0, x2
-    ret
-
-arm64_lock_storeifnull:
-    // address is x0, value is x1, x1 store to x0 only if [x0] is 0. return new [x0] value (so x1 or old value)
-    ldaxr   x2, [x0]
-    cbnz    x2, arm64_lock_storeifnull_exit
-    mov     x2, x1
-    stlxr   w3, x2, [x0]
-    cbnz    w3, arm64_lock_storeifnull
-arm64_lock_storeifnull_exit:
-    mov     x0, x2
-    ret
-
-arm64_lock_storeifref:
-    // address is x0, value is x1, x1 store to x0 only if [x0] is x3. return new [x0] value (so x1 or old value)
-    ldaxr   x3, [x0]
-    cmp     x2, x3
-    bne     arm64_lock_storeifref_exit
-    stlxr   w4, x1, [x0]
-    cbnz    w4, arm64_lock_storeifref
-    mov     x0, x1
-    ret
-arm64_lock_storeifref_exit:
-    mov     x0, x3
-    ret

src/dynarec/arm64_lock.h

@@ -1,39 +0,0 @@
-#ifndef __ARM64_LOCK__H__
-#define __ARM64_LOCK__H__
-#include <stdint.h>
-
-// LDAXRB of ADDR
-extern uint8_t arm64_lock_read_b(void* addr);
-// STLXRB of ADDR, return 0 if ok, 1 if not
-extern int arm64_lock_write_b(void* addr, uint8_t val);
-
-// LDAXRH of ADDR
-extern uint16_t arm64_lock_read_h(void* addr);
-// STLXRH of ADDR, return 0 if ok, 1 if not
-extern int arm64_lock_write_h(void* addr, uint16_t val);
-
-// LDAXR of ADDR
-extern uint32_t arm64_lock_read_d(void* addr);
-// STLXR of ADDR, return 0 if ok, 1 if not
-extern int arm64_lock_write_d(void* addr, uint32_t val);
-
-// LDAXR of ADDR
-extern uint64_t arm64_lock_read_dd(void* addr);
-// STLXR of ADDR, return 0 if ok, 1 if not
-extern int arm64_lock_write_dd(void* addr, uint64_t val);
-
-// LDAXRD of ADDR
-extern void arm64_lock_read_dq(uint64_t * a, uint64_t* b, void* addr);
-// STLXRD of ADDR, return 0 if ok, 1 if not
-extern int arm64_lock_write_dq(uint64_t a, uint64_t b, void* addr);
-
-// Atomicaly exchange value at [p] with val, return old p
-extern uintptr_t arm64_lock_xchg(void* p, uintptr_t val);
-
-// Atomicaly store value to [p] only if [p] is NULL. Return new [p] value (so val or old)
-extern void* arm64_lock_storeifnull(void*p, void* val);
-
-// Atomicaly store value to [p] only if [p] is ref. Return new [p] value (so val or old)
-extern void* arm64_lock_storeifref(void*p, void* val, void* ref);
-
-#endif  //__ARM64_LOCK__H__

src/dynarec/dynablock.c

@@ -1,13 +1,13 @@
 #include <stdio.h>
 #include <stdlib.h>
-#include <pthread.h>
 #include <errno.h>
+#include <setjmp.h>
+#include <sys/mman.h>
 
 #include "debug.h"
 #include "box64context.h"
 #include "dynarec.h"
 #include "emu/x64emu_private.h"
-#include "tools/bridge_private.h"
 #include "x64run.h"
 #include "x64emu.h"
 #include "box64stack.h"
@@ -18,17 +18,14 @@
 #include "dynablock_private.h"
 #include "dynarec_private.h"
 #include "elfloader.h"
-#ifdef ARM64
-#include "dynarec_arm64.h"
-#include "arm64_lock.h"
-#else
-#error Unsupported architecture!
-#endif
+#include "bridge.h"
+
+#include "dynarec_native.h"
+#include "native_lock.h"
+
 #include "custommem.h"
 #include "khash.h"
 
-KHASH_MAP_INIT_INT(dynablocks, dynablock_t*)
-
 uint32_t X31_hash_code(void* addr, int len)
 {
     if(!len) return 0;
@@ -38,389 +35,304 @@ uint32_t X31_hash_code(void* addr, int len)
 	return (uint32_t)h;
 }
 
-dynablocklist_t* NewDynablockList(uintptr_t text, int textsz, int direct)
-{
-    if(!textsz) {
-        printf_log(LOG_NONE, "Error, creating a NULL sized Dynablock\n");
-        return NULL;
-    }
-    dynablocklist_t* ret = (dynablocklist_t*)calloc(1, sizeof(dynablocklist_t));
-    ret->text = text;
-    ret->textsz = textsz;
-    if(direct && textsz) {
-        ret->direct = (dynablock_t**)calloc(textsz, sizeof(dynablock_t*));
-        if(!ret->direct) {printf_log(LOG_NONE, "Warning, fail to create direct block for dynablock @%p\n", (void*)text);}
-    }
-    dynarec_log(LOG_DEBUG, "New Dynablocklist %p, from %p->%p\n", ret, (void*)text, (void*)(text+textsz));
-    return ret;
-}
-
-void FreeDynablock(dynablock_t* db)
+dynablock_t* InvalidDynablock(dynablock_t* db, int need_lock)
 {
     if(db) {
-        dynarec_log(LOG_DEBUG, "FreeDynablock(%p), db->block=%p x64=%p:%p parent=%p, father=%p, with %d son(s) already gone=%d\n", db, db->block, db->x64_addr, db->x64_addr+db->x64_size, db->parent, db->father, db->sons_size, db->gone);
         if(db->gone)
-            return; // already in the process of deletion!
-        db->done = 0;
-        db->gone = 1;
-        // remove from direct if there
-        uintptr_t startdb = db->parent->text;
-        uintptr_t enddb = db->parent->text + db->parent->textsz;
-        if(db->parent->direct) {
-            uintptr_t addr = (uintptr_t)db->x64_addr;
-            if(addr>=startdb && addr<enddb)
-                arm64_lock_xchg(&db->parent->direct[addr-startdb], 0);   // secured write
-        }
+            return NULL; // already in the process of deletion!
+        dynarec_log(LOG_DEBUG, "InvalidDynablock(%p), db->block=%p x64=%p:%p already gone=%d\n", db, db->block, db->x64_addr, db->x64_addr+db->x64_size-1, db->gone);
+        if(need_lock)
+            mutex_lock(&my_context->mutex_dyndump);
         // remove jumptable
         setJumpTableDefault64(db->x64_addr);
-        // remove and free the sons
-        for (int i=0; i<db->sons_size; ++i) {
-            dynablock_t *son = (dynablock_t*)arm64_lock_xchg(&db->sons[i], 0);
-            FreeDynablock(son);
-        }
-        // only the father free the DynarecMap
-        if(!db->father) {
-            dynarec_log(LOG_DEBUG, " -- FreeDyrecMap(%p, %d)\n", db->block, db->size);
-            FreeDynarecMap(db, (uintptr_t)db->block, db->size);
-        }
-        free(db->sons);
-        free(db->instsize);
-        free(db);
+        db->done = 0;
+        db->gone = 1;
+        if(need_lock)
+            mutex_unlock(&my_context->mutex_dyndump);
     }
+    return db;
 }
 
-void FreeDynablockList(dynablocklist_t** dynablocks)
+void FreeInvalidDynablock(dynablock_t* db, int need_lock)
 {
-    if(!dynablocks)
-        return;
-    if(!*dynablocks)
-        return;
-    dynarec_log(LOG_DEBUG, "Free Dynablocklist %p, with Direct Blocks %p\n", *dynablocks, (*dynablocks)->direct);
-    if((*dynablocks)->direct) {
-        for (int i=0; i<(*dynablocks)->textsz; ++i) {
-            if((*dynablocks)->direct[i] && !(*dynablocks)->direct[i]->father) 
-                FreeDynablock((*dynablocks)->direct[i]);
-        }
-        free((*dynablocks)->direct);
+    if(db) {
+        if(!db->gone)
+            return; // already in the process of deletion!
+        dynarec_log(LOG_DEBUG, "FreeInvalidDynablock(%p), db->block=%p x64=%p:%p already gone=%d\n", db, db->block, db->x64_addr, db->x64_addr+db->x64_size-1, db->gone);
+        if(need_lock)
+            mutex_lock(&my_context->mutex_dyndump);
+        FreeDynarecMap((uintptr_t)db->actual_block);
+        customFree(db);
+        if(need_lock)
+            mutex_unlock(&my_context->mutex_dyndump);
     }
-    (*dynablocks)->direct = NULL;
-
-    free(*dynablocks);
-    *dynablocks = NULL;
 }
 
+void FreeDynablock(dynablock_t* db, int need_lock)
+{
+    if(db) {
+        if(db->gone)
+            return; // already in the process of deletion!
+        dynarec_log(LOG_DEBUG, "FreeDynablock(%p), db->block=%p x64=%p:%p already gone=%d\n", db, db->block, db->x64_addr, db->x64_addr+db->x64_size-1, db->gone);
+        if(need_lock)
+            mutex_lock(&my_context->mutex_dyndump);
+        // remove jumptable
+        setJumpTableDefault64(db->x64_addr);
+        dynarec_log(LOG_DEBUG, " -- FreeDyrecMap(%p, %d)\n", db->actual_block, db->size);
+        db->done = 0;
+        db->gone = 1;
+        if(db->previous)
+            FreeInvalidDynablock(db->previous, 0);
+        FreeDynarecMap((uintptr_t)db->actual_block);
+        customFree(db);
+        if(need_lock)
+            mutex_unlock(&my_context->mutex_dyndump);
+    }
+}
+
+
+
 void MarkDynablock(dynablock_t* db)
 {
     if(db) {
-        if(db->father)
-            db = db->father;    // mark only father
-        if(db->need_test)
-            return; // already done
-        db->need_test = 1;  // test only blocks that can be marked (and so deleted)
-        setJumpTableDefault64(db->x64_addr);
-        for(int i=0; i<db->sons_size; ++i)
-            setJumpTableDefault64(db->sons[i]->x64_addr);
+        dynarec_log(LOG_DEBUG, "MarkDynablock %p %p-%p\n", db, db->x64_addr, db->x64_addr+db->x64_size-1);
+        if(!setJumpTableIfRef64(db->x64_addr, db->jmpnext, db->block)) {
+            dynablock_t* old = db;
+            db = getDB((uintptr_t)old->x64_addr);
+            if(!old->gone && db!=old) {
+                printf_log(LOG_INFO, "Warning, couldn't mark block as dirty for %p, block=%p, current_block=%p\n", old->x64_addr, old, db);
+                // the block is lost, need to invalidate it...
+                old->gone = 1;
+                old->done = 0;
+                if(!db || db->previous)
+                    FreeInvalidDynablock(old, 1);
+                else
+                    db->previous = old;
+            }
+        }
     }
 }
 
-uintptr_t StartDynablockList(dynablocklist_t* db)
-{
-    if(db)
-        return db->text;
-    return 0;
-}
-uintptr_t EndDynablockList(dynablocklist_t* db)
-{
-    if(db)
-        return db->text+db->textsz-1;
-    return 0;
-}
-
-int IntervalIntersects(uintptr_t start1, uintptr_t end1, uintptr_t start2, uintptr_t end2)
+static int IntervalIntersects(uintptr_t start1, uintptr_t end1, uintptr_t start2, uintptr_t end2)
 {
     if(start1 > end2 || start2 > end1)
         return 0;
     return 1;
 }
 
-void MarkDirectDynablock(dynablocklist_t* dynablocks, uintptr_t addr, uintptr_t size)
+static int MarkedDynablock(dynablock_t* db)
 {
-    if(!dynablocks)
-        return;
-    if(!dynablocks->direct)
-        return;
-    uintptr_t startdb = dynablocks->text;
-    uintptr_t enddb = startdb + dynablocks->textsz -1;
-    uintptr_t start = addr;
-    uintptr_t end = addr+size-1;
-    if(start<startdb)
-        start = startdb;
-    if(end>enddb)
-        end = enddb;
-    dynablock_t *db;
-    if(end>startdb && start<enddb)
-        for(uintptr_t i = start; i<end; ++i)
-            if((db=dynablocks->direct[i-startdb]))
-                if(IntervalIntersects((uintptr_t)db->x64_addr, (uintptr_t)db->x64_addr+db->x64_size-1, addr, addr+size+1))
-                    MarkDynablock(db);
-}
-
-void FreeRangeDynablock(dynablocklist_t* dynablocks, uintptr_t addr, uintptr_t size)
-{
-    if(!dynablocks)
-        return;
-
-    if(dynablocks->direct) {
-        dynablock_t* db;
-        int ret;
-        khint_t k;
-        kh_dynablocks_t *blocks = kh_init(dynablocks);
-        // copy in a temporary list
-        if(dynablocks->direct) {
-            uintptr_t startdb = dynablocks->text;
-            uintptr_t enddb = startdb + dynablocks->textsz;
-            uintptr_t start = addr;
-            uintptr_t end = addr+size;
-            if(start<startdb)
-                start = startdb;
-            if(end>enddb)
-                end = enddb;
-            if(end>startdb && start<enddb)
-                for(uintptr_t i = start; i<end; ++i) {
-                    db = (dynablock_t*)arm64_lock_xchg(&dynablocks->direct[i-startdb], 0);
-                    if(db) {
-                        if(db->father)
-                            db = db->father;
-                        if(db->parent==dynablocks) {
-                            k = kh_put(dynablocks, blocks, (uintptr_t)db, &ret);
-                            kh_value(blocks, k) = db;
-                        }
-                    }
-                }
-        }
-        // purge the list
-        kh_foreach_value(blocks, db,
-            FreeDynablock(db);
-        );
-        kh_destroy(dynablocks, blocks);
+    if(db) {
+        if(getNeedTest((uintptr_t)db->x64_addr))
+            return 1; // already done
     }
+    return 0;
 }
-void MarkRangeDynablock(dynablocklist_t* dynablocks, uintptr_t addr, uintptr_t size)
+
+void MarkRangeDynablock(dynablock_t* db, uintptr_t addr, uintptr_t size)
 {
-    if(!dynablocks)
+    // Mark will try to find *any* blocks that intersect the range to mark
+    if(!db)
         return;
-    if(dynablocks->direct) {
-        uintptr_t new_addr = addr - dynablocks->maxsz;
-        uintptr_t new_size = size + dynablocks->maxsz;
-        MarkDirectDynablock(dynablocks, new_addr, new_size);
-        // the blocks check before
-        for(int idx=(new_addr)>>DYNAMAP_SHIFT; idx<(addr>>DYNAMAP_SHIFT); ++idx)
-            MarkDirectDynablock(getDB(idx), new_addr, new_size);
+    dynarec_log(LOG_DEBUG, "MarkRangeDynablock %p-%p .. startdb=%p, sizedb=%p\n", (void*)addr, (void*)addr+size-1, (void*)db->x64_addr, (void*)db->x64_size);
+    if(IntervalIntersects((uintptr_t)db->x64_addr, (uintptr_t)db->x64_addr+db->x64_size-1, addr, addr+size+1))
+        MarkDynablock(db);
+}
+
+int FreeRangeDynablock(dynablock_t* db, uintptr_t addr, uintptr_t size)
+{
+    if(!db)
+        return 1;
+
+    int need_lock = my_context?1:0;
+    if(IntervalIntersects((uintptr_t)db->x64_addr, (uintptr_t)db->x64_addr+db->x64_size-1, addr, addr+size+1)) {
+        FreeDynablock(db, need_lock);
+        return 0;
     }
+    return 1;
 }
 
-dynablock_t* FindDynablockDynablocklist(void* addr, kh_dynablocks_t* dynablocks)
+dynablock_t *AddNewDynablock(uintptr_t addr)
 {
-    if(!dynablocks)
-        return NULL;
-    dynablock_t* db;
-    kh_foreach_value(dynablocks, db, 
-        const uintptr_t s = (uintptr_t)db->block;
-        const uintptr_t e = (uintptr_t)db->block+db->size;
-        if((uintptr_t)addr>=s && (uintptr_t)addr<e)
-            return db->father?db->father:db;
-    )
-    return NULL;
-}
-
-static dynablocklist_t* getDBFromAddress(uintptr_t addr)
-{
-    const uintptr_t idx = (addr>>DYNAMAP_SHIFT);
-    return getDB(idx);
-}
-
-dynablock_t *AddNewDynablock(dynablocklist_t* dynablocks, uintptr_t addr, int* created)
-{
-    if(!dynablocks) {
-        dynarec_log(LOG_INFO, "Warning: Ask to create a dynablock with a NULL dynablocklist (addr=%p)\n", (void*)addr);
-        *created = 0;
+    dynablock_t* block;
+    #if 0
+    // check if memory as the correct flags
+    int prot = getProtection(addr);
+    if(!(prot&(PROT_EXEC|PROT_DYNAREC|PROT_DYNAREC_R))) {
+        dynarec_log(LOG_VERBOSE, "Block asked on a memory with no execution flags 0x%02X\n", prot);
         return NULL;
     }
-    if((addr<dynablocks->text) || (addr>=(dynablocks->text+dynablocks->textsz))) {
-        return AddNewDynablock(getDBFromAddress(addr), addr, created);
-    }
-    dynablock_t* block = NULL;
-    // first, check if it exist in direct access mode
-    if(dynablocks->direct) {
-        block = dynablocks->direct[addr-dynablocks->text];
-        if(block) {
-            dynarec_log(LOG_DUMP, "Block already exist in Direct Map\n");
-            *created = 0;
-            return block;
-        }
-    }
     
-    if (!*created)
-        return block;
-    
-    if(!dynablocks->direct) {
-        dynablock_t** p = (dynablock_t**)calloc(dynablocks->textsz, sizeof(dynablock_t*));
-        if(arm64_lock_storeifnull(&dynablocks->direct, p)!=p)
-            free(p);    // someone already create the direct array, too late...
-    }
-
+    #endif
     // create and add new block
-    dynarec_log(LOG_DUMP, "Ask for DynaRec Block creation @%p\n", (void*)addr);
-
-    block = (dynablock_t*)calloc(1, sizeof(dynablock_t));
-    block->parent = dynablocks; 
-    dynablock_t* tmp = (dynablock_t*)arm64_lock_storeifnull(&dynablocks->direct[addr-dynablocks->text], block);
-    if(tmp !=  block) {
-        // a block appeard!
-        free(block);
-        *created = 0;
-        return tmp;
-    }
-
-    *created = 1;
+    dynarec_log(LOG_VERBOSE, "Ask for DynaRec Block creation @%p\n", (void*)addr);
+    block = (dynablock_t*)customCalloc(1, sizeof(dynablock_t));
     return block;
 }
 
+//TODO: move this to dynrec_arm.c and track allocated structure to avoid memory leak
+static __thread struct __jmp_buf_tag dynarec_jmpbuf;
+
+void cancelFillBlock()
+{
+    longjmp(&dynarec_jmpbuf, 1);
+}
+
 /* 
     return NULL if block is not found / cannot be created. 
     Don't create if create==0
 */
-static dynablock_t* internalDBGetBlock(x64emu_t* emu, uintptr_t addr, uintptr_t filladdr, int create, dynablock_t* current)
+static dynablock_t* internalDBGetBlock(x64emu_t* emu, uintptr_t addr, uintptr_t filladdr, int create, int need_lock, int is32bits)
 {
-    // try the quickest way first: get parent of current and check if ok!
-    dynablocklist_t *dynablocks = NULL;
-    dynablock_t* block = NULL;
-    if(current) {
-        dynablocks = current->parent;
-        if(dynablocks && !(addr>=dynablocks->text && addr<(dynablocks->text+dynablocks->textsz)))
-            dynablocks = NULL;
-    }
-    // nope, lets do the long way
-    if(!dynablocks) {
-        dynablocks = getDBFromAddress(addr);
-        if(!dynablocks) {
-            dynablocks = GetDynablocksFromAddress(emu->context, addr);
-            if(!dynablocks)
+    if(hasAlternate((void*)addr))
+        return NULL;
+    dynablock_t* block = getDB(addr);
+    if(block || !create)
+        return block;
+
+    if(need_lock) {
+        if(box64_dynarec_wait) {
+            mutex_lock(&my_context->mutex_dyndump);
+        } else {
+            if(mutex_trylock(&my_context->mutex_dyndump))   // FillBlock not available for now
                 return NULL;
         }
-    }
-    // check direct first, without lock
-    if(dynablocks->direct/* && (addr>=dynablocks->text) && (addr<(dynablocks->text+dynablocks->textsz))*/)
-        if((block = dynablocks->direct[addr-dynablocks->text]))
+        block = getDB(addr);    // just in case
+        if(block) {
+            mutex_unlock(&my_context->mutex_dyndump);
             return block;
+        }
+    }
+    
+    block = AddNewDynablock(addr);
 
-    int created = create;
-    block = AddNewDynablock(dynablocks, addr, &created);
-    if(!created)
-        return block;   // existing block...
-
-    #if 0
-    if(box64_dynarec_dump)
-        pthread_mutex_lock(&my_context->mutex_dyndump);
-    #endif
     // fill the block
     block->x64_addr = (void*)addr;
-    pthread_mutex_lock(&my_context->mutex_dyndump);
-    void* ret = FillBlock64(block, filladdr);
-    pthread_mutex_unlock(&my_context->mutex_dyndump);
+    if(sigsetjmp(&dynarec_jmpbuf, 1)) {
+        printf_log(LOG_INFO, "FillBlock at %p triggered a segfault, canceling\n", (void*)addr);
+        FreeDynablock(block, 0);
+        if(need_lock)
+            mutex_unlock(&my_context->mutex_dyndump);
+        return NULL;
+    }
+    void* ret = FillBlock64(block, filladdr, (addr==filladdr)?0:1, is32bits);
     if(!ret) {
         dynarec_log(LOG_DEBUG, "Fillblock of block %p for %p returned an error\n", block, (void*)addr);
-        void* old = (void*)arm64_lock_storeifref(&dynablocks->direct[addr-dynablocks->text], 0, block);
-        if(old!=block && old) {// put it back in place, strange things are happening here!
-            dynarec_log(LOG_INFO, "Warning, a wild block appeared at %p: %p\n", (void*)addr, old);
-            // doing nothing else, the block as not be writen
-        }
-        free(block);
+        customFree(block);
         block = NULL;
     }
-    #if 0
-    if(box64_dynarec_dump)
-        pthread_mutex_unlock(&my_context->mutex_dyndump);
-    #endif
     // check size
-    if(block && block->x64_size) {
+    if(block) {
         int blocksz = block->x64_size;
-        if(dynablocks->maxsz<blocksz) {
-            dynablocks->maxsz = blocksz;
-            for(int idx=(addr>>DYNAMAP_SHIFT)+1; idx<=((addr+blocksz)>>DYNAMAP_SHIFT); ++idx) {
-                dynablocklist_t* dblist;
-                if((dblist = getDB(idx)))
-                    if(dblist->maxsz<blocksz)
-                        dblist->maxsz = blocksz;
-            }
-        }
-        lockDB();
-        protectDBnolock((uintptr_t)block->x64_addr, block->x64_size);
+        if(blocksz>my_context->max_db_size)
+            my_context->max_db_size = blocksz;
         // fill-in jumptable
-        addJumpTableIfDefault64(block->x64_addr, block->block);
-        for(int i=0; i<block->sons_size; ++i)
-            addJumpTableIfDefault64(block->sons[i]->x64_addr, block->sons[i]->block);
-        unlockDB();
+        if(!addJumpTableIfDefault64(block->x64_addr, block->dirty?block->jmpnext:block->block)) {
+            FreeDynablock(block, 0);
+            block = getDB(addr);
+            MarkDynablock(block);   // just in case...
+        } else {
+            if(block->x64_size)
+                block->done = 1;    // don't validate the block if the size is null, but keep the block
+        }
     }
+    if(need_lock)
+        mutex_unlock(&my_context->mutex_dyndump);
 
-    dynarec_log(LOG_DEBUG, " --- DynaRec Block %s @%p:%p (%p, 0x%x bytes, with %d son(s))\n", created?"created":"recycled", (void*)addr, (void*)(addr+((block)?block->x64_size:0)), (block)?block->block:0, (block)?block->size:0, (block)?block->sons_size:0);
+    dynarec_log(LOG_DEBUG, "%04d| --- DynaRec Block created @%p:%p (%p, 0x%x bytes)\n", GetTID(), (void*)addr, (void*)(addr+((block)?block->x64_size:1)-1), (block)?block->block:0, (block)?block->size:0);
 
     return block;
 }
 
-dynablock_t* DBGetBlock(x64emu_t* emu, uintptr_t addr, int create, dynablock_t** current)
+dynablock_t* DBGetBlock(x64emu_t* emu, uintptr_t addr, int create, int is32bits)
 {
-    dynablock_t *db = internalDBGetBlock(emu, addr, addr, create, *current);
-    if(db && db->done && db->block && (db->need_test || (db->father && db->father->need_test))) {
-        dynablock_t *father = db->father?db->father:db;
-        uint32_t hash = X31_hash_code(father->x64_addr, father->x64_size);
-        if(hash!=father->hash) {
-            dynarec_log(LOG_DEBUG, "Invalidating block %p from %p:%p (hash:%X/%X) with %d son(s) for %p\n", father, father->x64_addr, father->x64_addr+father->x64_size, hash, father->hash, father->sons_size, (void*)addr);
-            // no more current if it gets invalidated too
-            if(*current && father->x64_addr>=(*current)->x64_addr && (father->x64_addr+father->x64_size)<(*current)->x64_addr)
-                *current = NULL;
-            // Free father, it's now invalid!
-            FreeDynablock(father);
-            // start again... (will create a new block)
-            db = internalDBGetBlock(emu, addr, addr, create, *current);
-        } else {
-            father->need_test = 0;
-            lockDB();
-            protectDBnolock((uintptr_t)father->x64_addr, father->x64_size);
-            // fill back jumptable
-            addJumpTableIfDefault64(father->x64_addr, father->block);
-            for(int i=0; i<father->sons_size; ++i)
-                addJumpTableIfDefault64(father->sons[i]->x64_addr, father->sons[i]->block);
-            unlockDB();
+    dynablock_t *db = internalDBGetBlock(emu, addr, addr, create, 1, is32bits);
+    if(db && db->done && db->block && getNeedTest(addr)) {
+        if(db->always_test)
+            sched_yield();  // just calm down...
+        if(AreaInHotPage((uintptr_t)db->x64_addr, (uintptr_t)db->x64_addr + db->x64_size - 1)) {
+            emu->test.test = 0;
+            if(box64_dynarec_fastpage) {
+                uint32_t hash = X31_hash_code(db->x64_addr, db->x64_size);
+                if(hash==db->hash) { // seems ok, run it without reprotecting it
+                    setJumpTableIfRef64(db->x64_addr, db->block, db->jmpnext);
+                    return db;
+                }
+                db->done = 0;   // invalidating the block, it's already not good
+                dynarec_log(LOG_DEBUG, "Invalidating block %p from %p:%p (hash:%X/%X) for %p\n", db, db->x64_addr, db->x64_addr+db->x64_size-1, hash, db->hash, (void*)addr);
+                // Free db, it's now invalid!
+                FreeDynablock(db, 1);
+                return NULL;    // not building a new one, it's still a hotpage
+            } else {
+                dynarec_log(LOG_INFO, "Not running block %p from %p:%p with for %p because it's in a hotpage\n", db, db->x64_addr, db->x64_addr+db->x64_size-1, (void*)addr);
+                return NULL;
+            }
         }
+        uint32_t hash = X31_hash_code(db->x64_addr, db->x64_size);
+        int need_lock = mutex_trylock(&my_context->mutex_dyndump);
+        if(hash!=db->hash) {
+            db->done = 0;   // invalidating the block
+            dynarec_log(LOG_DEBUG, "Invalidating block %p from %p:%p (hash:%X/%X) for %p\n", db, db->x64_addr, db->x64_addr+db->x64_size-1, hash, db->hash, (void*)addr);
+            // Free db, it's now invalid!
+            dynablock_t* old = InvalidDynablock(db, need_lock);
+            // start again... (will create a new block)
+            db = internalDBGetBlock(emu, addr, addr, create, need_lock, is32bits);
+            if(db) {
+                if(db->previous)
+                    FreeInvalidDynablock(db->previous, need_lock);
+                db->previous = old;
+            } else
+                FreeInvalidDynablock(old, need_lock);
+        } else {
+            dynarec_log(LOG_DEBUG, "Validating block %p from %p:%p (hash:%X) for %p\n", db, db->x64_addr, db->x64_addr+db->x64_size-1, db->hash, (void*)addr);
+            protectDB((uintptr_t)db->x64_addr, db->x64_size);
+            // fill back jumptable
+            if(isprotectedDB((uintptr_t)db->x64_addr, db->x64_size) && !db->always_test) {
+                setJumpTableIfRef64(db->x64_addr, db->block, db->jmpnext);
+            }
+        }
+        if(!need_lock)
+            mutex_unlock(&my_context->mutex_dyndump);
     } 
+    if(!db || !db->block || !db->done)
+        emu->test.test = 0;
     return db;
 }
 
-dynablock_t* DBAlternateBlock(x64emu_t* emu, uintptr_t addr, uintptr_t filladdr)
+dynablock_t* DBAlternateBlock(x64emu_t* emu, uintptr_t addr, uintptr_t filladdr, int is32bits)
 {
-    dynarec_log(LOG_DEBUG, "Creating AlternateBlock at %p for %p\n", (void*)addr, (void*)filladdr);
+    dynarec_log(LOG_DEBUG, "Creating AlternateBlock at %p for %p%s\n", (void*)addr, (void*)filladdr, is32bits?" 32bits":"");
     int create = 1;
-    dynablock_t *db = internalDBGetBlock(emu, addr, filladdr, create, NULL);
-    if(db && db->done && db->block && (db->need_test || (db->father && db->father->need_test))) {
-        dynablock_t *father = db->father?db->father:db;
-        uint32_t hash = X31_hash_code(father->x64_addr, father->x64_size);
-        if(hash!=father->hash) {
-            dynarec_log(LOG_DEBUG, "Invalidating alt block %p from %p:%p (hash:%X/%X) with %d son(s) for %p\n", father, father->x64_addr, father->x64_addr+father->x64_size, hash, father->hash, father->sons_size, (void*)addr);
-            // Free father, it's now invalid!
-            FreeDynablock(father);
+    dynablock_t *db = internalDBGetBlock(emu, addr, filladdr, create, 1, is32bits);
+    if(db && db->done && db->block && getNeedTest(filladdr)) {
+        if(db->always_test)
+            sched_yield();  // just calm down...
+        int need_lock = mutex_trylock(&my_context->mutex_dyndump);
+        uint32_t hash = X31_hash_code(db->x64_addr, db->x64_size);
+        if(hash!=db->hash) {
+            db->done = 0;   // invalidating the block
+            dynarec_log(LOG_DEBUG, "Invalidating alt block %p from %p:%p (hash:%X/%X) for %p\n", db, db->x64_addr, db->x64_addr+db->x64_size, hash, db->hash, (void*)addr);
+            // Free db, it's now invalid!
+            dynablock_t* old = InvalidDynablock(db, need_lock);
             // start again... (will create a new block)
-            db = internalDBGetBlock(emu, addr, filladdr, create, NULL);
+            db = internalDBGetBlock(emu, addr, filladdr, create, need_lock, is32bits);
+            if(db) {
+                if(db->previous)
+                    FreeInvalidDynablock(db->previous, need_lock);
+                db->previous = old;
+            } else
+                FreeInvalidDynablock(old, need_lock);
         } else {
-            father->need_test = 0;
-            lockDB();
-            protectDBnolock((uintptr_t)father->x64_addr, father->x64_size);
+            protectDB((uintptr_t)db->x64_addr, db->x64_size);
             // fill back jumptable
-            addJumpTableIfDefault64(father->x64_addr, father->block);
-            for(int i=0; i<father->sons_size; ++i)
-                addJumpTableIfDefault64(father->sons[i]->x64_addr, father->sons[i]->block);
-            unlockDB();
+            if(isprotectedDB((uintptr_t)db->x64_addr, db->x64_size) && !db->always_test) {
+                setJumpTableIfRef64(db->x64_addr, db->block, db->jmpnext);
+            }
         }
+        if(!need_lock)
+            mutex_unlock(&my_context->mutex_dyndump);
     } 
+    if(!db || !db->block || !db->done)
+        emu->test.test = 0;
     return db;
 }

src/dynarec/dynablock_private.h

@@ -1,36 +1,26 @@
 #ifndef __DYNABLOCK_PRIVATE_H_
 #define __DYNABLOCK_PRIVATE_H_
 
-typedef struct dynablocklist_s  dynablocklist_t;
-
 typedef struct instsize_s {
-    unsigned int x64:4;
-    unsigned int nat:4;
+    unsigned char x64:4;
+    unsigned char nat:4;
 } instsize_t;
 
 typedef struct dynablock_s {
-    dynablocklist_t* parent;
-    void*           block;
+    void*           block;  // block-sizeof(void*) == self
+    void*           actual_block;   // the actual start of the block (so block-sizeof(void*))
+    struct dynablock_s*    previous;   // a previous block that might need to be freed
     int             size;
     void*           x64_addr;
     uintptr_t       x64_size;
     uint32_t        hash;
-    uint8_t         need_test;
     uint8_t         done;
     uint8_t         gone;
-    uint8_t         dummy;
+    uint8_t         always_test;
+    uint8_t         dirty;      // if need to be tested as soon as it's created
     int             isize;
-    dynablock_t**   sons;   // sons (kind-of dummy dynablock...)
-    int             sons_size;
-    dynablock_t*    father; // set only in the case of a son
     instsize_t*     instsize;
+    void*           jmpnext;    // a branch jmpnext code when block is marked
 } dynablock_t;
 
-typedef struct dynablocklist_s {
-    uintptr_t           text;
-    int                 textsz;
-    int                 maxsz;     // maxblock size (for this block or previous block)
-    dynablock_t**       direct;    // direct mapping (waste of space, so the array is created at first write)
-} dynablocklist_t;
-
 #endif //__DYNABLOCK_PRIVATE_H_

src/dynarec/dynarec.c

@@ -1,6 +1,5 @@
 #include <stdio.h>
 #include <stdlib.h>
-#include <pthread.h>
 #include <errno.h>
 #include <setjmp.h>
 
@@ -8,7 +7,6 @@
 #include "box64context.h"
 #include "dynarec.h"
 #include "emu/x64emu_private.h"
-#include "tools/bridge_private.h"
 #include "x64run.h"
 #include "x64emu.h"
 #include "box64stack.h"
@@ -19,46 +17,56 @@
 #ifdef DYNAREC
 #include "dynablock.h"
 #include "dynablock_private.h"
+#include "bridge.h"
+#include "dynarec_next.h"
 #endif
-
-#ifdef DYNAREC
-#ifdef ARM64
-void arm64_prolog(x64emu_t* emu, void* addr) EXPORTDYN;
-void arm64_epilog() EXPORTDYN;
-void arm64_epilog_fast() EXPORTDYN;
-#endif
-#endif
-
-#ifdef DYNAREC
 #ifdef HAVE_TRACE
-uintptr_t getX64Address(dynablock_t* db, uintptr_t arm_addr);
+#include "elfloader.h"
 #endif
-void* LinkNext(x64emu_t* emu, uintptr_t addr, void* x2)
+
+#ifdef DYNAREC
+uintptr_t getX64Address(dynablock_t* db, uintptr_t arm_addr);
+
+void* LinkNext(x64emu_t* emu, uintptr_t addr, void* x2, uintptr_t* x3)
 {
+    int is32bits = (R_CS == 0x23);
     #ifdef HAVE_TRACE
     if(!addr) {
         dynablock_t* db = FindDynablockFromNativeAddress(x2-4);
-        printf_log(LOG_NONE, "Warning, jumping to NULL address from %p (db=%p, x64addr=%p)\n", x2-4, db, db?(void*)getX64Address(db, (uintptr_t)x2-4):NULL);
+        printf_log(LOG_NONE, "Warning, jumping to NULL address from %p (db=%p, x64addr=%p/%s)\n", x2-4, db, db?(void*)getX64Address(db, (uintptr_t)x2-4):NULL, db?getAddrFunctionName(getX64Address(db, (uintptr_t)x2-4)):"(nil)");
     }
     #endif
-    dynablock_t* current = NULL;
     void * jblock;
-    dynablock_t* block = DBGetBlock(emu, addr, 1, &current);
+    dynablock_t* block = NULL;
+    if(hasAlternate((void*)addr)) {
+        printf_log(LOG_DEBUG, "Jmp address has alternate: %p", (void*)addr);
+        if(box64_log<LOG_DEBUG) dynarec_log(LOG_INFO, "Jmp address has alternate: %p", (void*)addr);
+        uintptr_t old_addr = addr;
+        addr = (uintptr_t)getAlternate((void*)addr);    // set new address
+        R_RIP = addr;   // but also new RIP!
+        *x3 = addr; // and the RIP in x27 register
+        printf_log(LOG_DEBUG, " -> %p\n", (void*)addr);
+        block = DBAlternateBlock(emu, old_addr, addr, is32bits);
+    } else
+        block = DBGetBlock(emu, addr, 1, is32bits);
     if(!block) {
-        // no block, let link table as is...
-dynablock_t* db = FindDynablockFromNativeAddress(x2-4);
-printf_log(LOG_NONE, "Warning, jumping to a no-block address %p from %p (db=%p, x64addr=%p)\n", (void*)addr, x2-4, db, db?(void*)getX64Address(db, (uintptr_t)x2-4):NULL);
-        //tableupdate(arm64_epilog, addr, table);
-        return arm64_epilog;
+        #ifdef HAVE_TRACE
+        if(LOG_INFO<=box64_dynarec_log) {
+            dynablock_t* db = FindDynablockFromNativeAddress(x2-4);
+            elfheader_t* h = FindElfAddress(my_context, (uintptr_t)x2-4);
+            dynarec_log(LOG_INFO, "Warning, jumping to a no-block address %p from %p (db=%p, x64addr=%p(elf=%s))\n", (void*)addr, x2-4, db, db?(void*)getX64Address(db, (uintptr_t)x2-4):NULL, h?ElfName(h):"(none)");
+        }
+        #endif
+        //tableupdate(native_epilog, addr, table);
+        return native_epilog;
     }
     if(!block->done) {
         // not finished yet... leave linker
-        //tableupdate(arm_linker, addr, table);
-        return arm64_epilog;
+        return native_epilog;
     }
     if(!(jblock=block->block)) {
         // null block, but done: go to epilog, no linker here
-        return arm64_epilog;
+        return native_epilog;
     }
     //dynablock_t *father = block->father?block->father:block;
     return jblock;
@@ -67,151 +75,89 @@ printf_log(LOG_NONE, "Warning, jumping to a no-block address %p from %p (db=%p,
 
 void DynaCall(x64emu_t* emu, uintptr_t addr)
 {
-    // prepare setjump for signal handling
-    emu_jmpbuf_t *ejb = NULL;
-    int jmpbuf_reset = 0;
-    if(emu->type == EMUTYPE_MAIN) {
-        ejb = GetJmpBuf();
-        if(!ejb->jmpbuf_ok) {
-            ejb->emu = emu;
-            ejb->jmpbuf_ok = 1;
-            jmpbuf_reset = 1;
-            if(setjmp((struct __jmp_buf_tag*)ejb->jmpbuf)) {
-                printf_log(LOG_DEBUG, "Setjmp DynaCall, fs=0x%x\n", ejb->emu->segs[_FS]);
-                addr = R_RIP;   // not sure if it should still be inside DynaCall!
-            }
-        }
+    uint64_t old_rsp = R_RSP;
+    uint64_t old_rbx = R_RBX;
+    uint64_t old_rdi = R_RDI;
+    uint64_t old_rsi = R_RSI;
+    uint64_t old_rbp = R_RBP;
+    uint64_t old_rip = R_RIP;
+    PushExit(emu);
+    R_RIP = addr;
+    emu->df = d_none;
+    DynaRun(emu);
+    emu->quit = 0;  // reset Quit flags...
+    emu->df = d_none;
+    if(emu->flags.quitonlongjmp && emu->flags.longjmp) {
+        if(emu->flags.quitonlongjmp==1)
+            emu->flags.longjmp = 0;   // don't change anything because of the longjmp
+    } else {
+        R_RBX = old_rbx;
+        R_RDI = old_rdi;
+        R_RSI = old_rsi;
+        R_RBP = old_rbp;
+        R_RSP = old_rsp;
+        R_RIP = old_rip;  // and set back instruction pointer
     }
-#ifdef DYNAREC
-    if(!box64_dynarec)
-#endif
-        EmuCall(emu, addr);
-#ifdef DYNAREC
-    else {
-        uint64_t old_rsp = R_RSP;
-        uint64_t old_rbx = R_RBX;
-        uint64_t old_rdi = R_RDI;
-        uint64_t old_rsi = R_RSI;
-        uint64_t old_rbp = R_RBP;
-        uint64_t old_rip = R_RIP;
-        PushExit(emu);
-        R_RIP = addr;
-        emu->df = d_none;
-        dynablock_t* block = NULL;
-        dynablock_t* current = NULL;
-        while(!emu->quit) {
-            block = DBGetBlock(emu, R_RIP, 1, &current);
-            current = block;
-            if(!block || !block->block || !block->done) {
-                // no block, of block doesn't have DynaRec content (yet, temp is not null)
-                // Use interpreter (should use single instruction step...)
-                dynarec_log(LOG_DEBUG, "%04d|Calling Interpretor @%p, emu=%p\n", GetTID(), (void*)R_RIP, emu);
-                Run(emu, 1);
-            } else {
-                dynarec_log(LOG_DEBUG, "%04d|Calling DynaRec Block @%p (%p) of %d x64 instructions (father=%p) emu=%p\n", GetTID(), (void*)R_RIP, block->block, block->isize ,block->father, emu);
-                CHECK_FLAGS(emu);
-                // block is here, let's run it!
-                #ifdef ARM64
-                arm64_prolog(emu, block->block);
-                #endif
-            }
-            if(emu->fork) {
-                int forktype = emu->fork;
-                emu->quit = 0;
-                emu->fork = 0;
-                emu = x64emu_fork(emu, forktype);
-                if(emu->type == EMUTYPE_MAIN) {
-                    ejb = GetJmpBuf();
-                    ejb->emu = emu;
-                    ejb->jmpbuf_ok = 1;
-                    jmpbuf_reset = 1;
-                    if(setjmp((struct __jmp_buf_tag*)ejb->jmpbuf)) {
-                        printf_log(LOG_DEBUG, "Setjmp inner DynaCall, fs=0x%x\n", ejb->emu->segs[_FS]);
-                        addr = R_RIP;
-                    }
-                }
-            }
-        }
-        emu->quit = 0;  // reset Quit flags...
-        emu->df = d_none;
-        if(emu->quitonlongjmp && emu->longjmp) {
-            emu->longjmp = 0;   // don't change anything because of the longjmp
-        } else {
-            R_RBX = old_rbx;
-            R_RDI = old_rdi;
-            R_RSI = old_rsi;
-            R_RBP = old_rbp;
-            R_RSP = old_rsp;
-            R_RIP = old_rip;  // and set back instruction pointer
-        }
-    }
-#endif
-    // clear the setjmp
-    if(ejb && jmpbuf_reset)
-        ejb->jmpbuf_ok = 0;
 }
 
-int DynaRun(x64emu_t* emu)
+void DynaRun(x64emu_t* emu)
 {
     // prepare setjump for signal handling
-    emu_jmpbuf_t *ejb = NULL;
-#ifdef DYNAREC
-    int jmpbuf_reset = 1;
-#endif
-    if(emu->type == EMUTYPE_MAIN) {
-        ejb = GetJmpBuf();
-        if(!ejb->jmpbuf_ok) {
-            ejb->emu = emu;
-            ejb->jmpbuf_ok = 1;
-#ifdef DYNAREC
-            jmpbuf_reset = 1;
-#endif
-            if(setjmp((struct __jmp_buf_tag*)ejb->jmpbuf))
-                printf_log(LOG_DEBUG, "Setjmp DynaRun, fs=0x%x\n", ejb->emu->segs[_FS]);
+    struct __jmp_buf_tag jmpbuf[1] = {0};
+    int skip = 0;
+    struct __jmp_buf_tag *old_jmpbuf = emu->jmpbuf;
+    emu->flags.jmpbuf_ready = 0;
+
+    while(!(emu->quit)) {
+        if(!emu->jmpbuf || (emu->flags.need_jmpbuf && emu->jmpbuf!=jmpbuf)) {
+            emu->jmpbuf = jmpbuf;
+            emu->flags.jmpbuf_ready = 1;
+            if((skip=sigsetjmp(emu->jmpbuf, 1))) {
+                printf_log(LOG_DEBUG, "Setjmp DynaRun, fs=0x%x\n", emu->segs[_FS]);
+                #ifdef DYNAREC
+                if(box64_dynarec_test) {
+                    if(emu->test.clean)
+                        x64test_check(emu, R_RIP);
+                    emu->test.clean = 0;
+                }
+                #endif
+            }
         }
-    }
+        if(emu->flags.need_jmpbuf)
+            emu->flags.need_jmpbuf = 0;
+
 #ifdef DYNAREC
-    if(!box64_dynarec)
+        if(!box64_dynarec)
 #endif
-        return Run(emu, 0);
+            Run(emu, 0);
 #ifdef DYNAREC
-    else {
-        dynablock_t* block = NULL;
-        dynablock_t* current = NULL;
-        while(!emu->quit) {
-            block = DBGetBlock(emu, R_RIP, 1, &current);
-            current = block;
+        else {
+            int is32bits = (emu->segs[_CS]==0x23);
+            dynablock_t* block = (skip)?NULL:DBGetBlock(emu, R_RIP, 1, is32bits);
             if(!block || !block->block || !block->done) {
+                skip = 0;
                 // no block, of block doesn't have DynaRec content (yet, temp is not null)
                 // Use interpreter (should use single instruction step...)
-                dynarec_log(LOG_DEBUG, "%04d|Running Interpretor @%p, emu=%p\n", GetTID(), (void*)R_RIP, emu);
+                dynarec_log(LOG_DEBUG, "%04d|Running Interpreter @%p, emu=%p\n", GetTID(), (void*)R_RIP, emu);
+                if(box64_dynarec_test)
+                    emu->test.clean = 0;
                 Run(emu, 1);
             } else {
-                dynarec_log(LOG_DEBUG, "%04d|Running DynaRec Block @%p (%p) of %d x64 insts (father=%p) emu=%p\n", GetTID(), (void*)R_RIP, block->block, block->isize, block->father, emu);
+                dynarec_log(LOG_DEBUG, "%04d|Running DynaRec Block @%p (%p) of %d x64 insts (hash=0x%x) emu=%p\n", GetTID(), (void*)R_RIP, block->block, block->isize, block->hash, emu);
                 // block is here, let's run it!
-                #ifdef ARM64
-                arm64_prolog(emu, block->block);
-                #endif
+                native_prolog(emu, block->block);
             }
             if(emu->fork) {
                 int forktype = emu->fork;
                 emu->quit = 0;
                 emu->fork = 0;
                 emu = x64emu_fork(emu, forktype);
-                if(emu->type == EMUTYPE_MAIN) {
-                    ejb = GetJmpBuf();
-                    ejb->emu = emu;
-                    ejb->jmpbuf_ok = 1;
-                    jmpbuf_reset = 1;
-                    if(setjmp((struct __jmp_buf_tag*)ejb->jmpbuf))
-                        printf_log(LOG_DEBUG, "Setjmp inner DynaRun, fs=0x%x\n", ejb->emu->segs[_FS]);
-                }
             }
         }
+#endif
+        if(emu->flags.need_jmpbuf)
+            emu->quit = 0;
     }
     // clear the setjmp
-    if(ejb && jmpbuf_reset)
-        ejb->jmpbuf_ok = 0;
-    return 0;
-#endif
-}
+    emu->jmpbuf = old_jmpbuf;
+}

src/dynarec/dynarec_arch.h

@@ -0,0 +1,48 @@
+#ifndef __DYNAREC_ARCH__H_
+#define __DYNAREC_ARCH__H_
+
+#ifdef ARM64
+
+#define instruction_native_t        instruction_arm64_t
+#define dynarec_native_t            dynarec_arm_t
+
+#define ADDITIONNAL_DEFINITION()  \
+    int fpuCacheNeedsTransform(dynarec_native_t* dyn, int ninst);
+
+#define OTHER_CACHE()   \
+    if (fpuCacheNeedsTransform(dyn, ninst)) ret|=2;
+
+#include "arm64/arm64_printer.h"
+#include "arm64/dynarec_arm64_private.h"
+#include "arm64/dynarec_arm64_functions.h"
+#elif defined(LA464)
+
+#define instruction_native_t        instruction_la464_t
+#define dynarec_native_t            dynarec_la464_t
+
+#define ADDITIONNAL_DEFINITION()
+
+#define OTHER_CACHE()
+
+#include "la464/la464_printer.h"
+#include "la464/dynarec_la464_private.h"
+#include "la464/dynarec_la464_functions.h"
+#elif defined(RV64)
+
+#define instruction_native_t        instruction_rv64_t
+#define dynarec_native_t            dynarec_rv64_t
+
+#define ADDITIONNAL_DEFINITION()  \
+    int fpuCacheNeedsTransform(dynarec_native_t* dyn, int ninst);
+
+#define OTHER_CACHE()   \
+    if (fpuCacheNeedsTransform(dyn, ninst)) ret|=2;
+
+#include "rv64/rv64_printer.h"
+#include "rv64/dynarec_rv64_private.h"
+#include "rv64/dynarec_rv64_functions.h"
+#else
+#error Unsupported platform
+#endif
+
+#endif //__DYNAREC_ARCH__H_

src/dynarec/dynarec_arm64.c

@@ -1,496 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <pthread.h>
-#include <errno.h>
-#include <string.h>
-
-#include "debug.h"
-#include "box64context.h"
-#include "custommem.h"
-#include "dynarec.h"
-#include "emu/x64emu_private.h"
-#include "tools/bridge_private.h"
-#include "x64run.h"
-#include "x64emu.h"
-#include "box64stack.h"
-#include "callback.h"
-#include "emu/x64run_private.h"
-#include "x64trace.h"
-#include "dynablock.h"
-#include "dynablock_private.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "dynarec_arm64_functions.h"
-#include "elfloader.h"
-
-void printf_x64_instruction(zydis_dec_t* dec, instruction_x64_t* inst, const char* name) {
-    uint8_t *ip = (uint8_t*)inst->addr;
-    if(ip[0]==0xcc && ip[1]=='S' && ip[2]=='C') {
-        uintptr_t a = *(uintptr_t*)(ip+3);
-        if(a==0) {
-            dynarec_log(LOG_NONE, "%s%p: Exit x64emu%s\n", (box64_dynarec_dump>1)?"\e[1m":"", (void*)ip, (box64_dynarec_dump>1)?"\e[m":"");
-        } else {
-            dynarec_log(LOG_NONE, "%s%p: Native call to %p%s\n", (box64_dynarec_dump>1)?"\e[1m":"", (void*)ip, (void*)a, (box64_dynarec_dump>1)?"\e[m":"");
-        }
-    } else {
-        if(dec) {
-            dynarec_log(LOG_NONE, "%s%p: %s", (box64_dynarec_dump>1)?"\e[1m":"", ip, DecodeX64Trace(dec, inst->addr));
-        } else {
-            dynarec_log(LOG_NONE, "%s%p: ", (box64_dynarec_dump>1)?"\e[1m":"", ip);
-            for(int i=0; i<inst->size; ++i) {
-                dynarec_log(LOG_NONE, "%02X ", ip[i]);
-            }
-            dynarec_log(LOG_NONE, " %s", name);
-        }
-        // print Call function name if possible
-        if(ip[0]==0xE8 || ip[0]==0xE9) { // Call / Jmp
-            uintptr_t nextaddr = (uintptr_t)ip + 5 + *((int32_t*)(ip+1));
-            printFunctionAddr(nextaddr, "=> ");
-        } else if(ip[0]==0xFF) {
-            if(ip[1]==0x25) {
-                uintptr_t nextaddr = (uintptr_t)ip + 6 + *((int32_t*)(ip+2));
-                printFunctionAddr(nextaddr, "=> ");
-            }
-        }
-        // end of line and colors
-        dynarec_log(LOG_NONE, "%s\n", (box64_dynarec_dump>1)?"\e[m":"");
-    }
-}
-
-void add_next(dynarec_arm_t *dyn, uintptr_t addr) {
-    if(dyn->next_sz == dyn->next_cap) {
-        dyn->next_cap += 16;
-        dyn->next = (uintptr_t*)realloc(dyn->next, dyn->next_cap*sizeof(uintptr_t));
-    }
-    for(int i=0; i<dyn->next_sz; ++i)
-        if(dyn->next[i]==addr)
-            return;
-    dyn->next[dyn->next_sz++] = addr;
-}
-uintptr_t get_closest_next(dynarec_arm_t *dyn, uintptr_t addr) {
-    // get closest, but no addresses befores
-    uintptr_t best = 0;
-    int i = 0;
-    while((i<dyn->next_sz) && (best!=addr)) {
-        if(dyn->next[i]<addr) { // remove the address, it's before current address
-            memmove(dyn->next+i, dyn->next+i+1, (dyn->next_sz-i-1)*sizeof(uintptr_t));
-            --dyn->next_sz;
-        } else {
-            if((dyn->next[i]<best) || !best)
-                best = dyn->next[i];
-            ++i;
-        }
-    }
-    return best;
-}
-#define PK(A) (*((uint8_t*)(addr+(A))))
-int is_nops(dynarec_arm_t *dyn, uintptr_t addr, int n)
-{
-    if(!n)
-        return 1;
-    if(PK(0)==0x90)
-        return is_nops(dyn, addr+1, n-1);
-    if(n>1 && PK(0)==0x66)  // if opcode start with 0x66, and there is more after, than is *can* be a NOP
-        return is_nops(dyn, addr+1, n-1);
-    if(n>2 && PK(0)==0x0f && PK(1)==0x1f && PK(2)==0x00)
-        return is_nops(dyn, addr+3, n-3);
-    if(n>2 && PK(0)==0x8d && PK(1)==0x76 && PK(2)==0x00)    // lea esi, [esi]
-        return is_nops(dyn, addr+3, n-3);
-    if(n>3 && PK(0)==0x0f && PK(1)==0x1f && PK(2)==0x40 && PK(3)==0x00)
-        return is_nops(dyn, addr+4, n-4);
-    if(n>3 && PK(0)==0x8d && PK(1)==0x74 && PK(2)==0x26 && PK(3)==0x00)
-        return is_nops(dyn, addr+4, n-4);
-    if(n>4 && PK(0)==0x0f && PK(1)==0x1f && PK(2)==0x44 && PK(3)==0x00 && PK(4)==0x00)
-        return is_nops(dyn, addr+5, n-5);
-    if(n>5 && PK(0)==0x8d && PK(1)==0xb6 && PK(2)==0x00 && PK(3)==0x00 && PK(4)==0x00 && PK(5)==0x00)
-        return is_nops(dyn, addr+6, n-6);
-    if(n>6 && PK(0)==0x0f && PK(1)==0x1f && PK(2)==0x80 && PK(3)==0x00 && PK(4)==0x00 && PK(5)==0x00 && PK(6)==0x00)
-        return is_nops(dyn, addr+7, n-7);
-    if(n>6 && PK(0)==0x8d && PK(1)==0xb4 && PK(2)==0x26 && PK(3)==0x00 && PK(4)==0x00 && PK(5)==0x00 && PK(6)==0x00) // lea esi, [esi+0]
-        return is_nops(dyn, addr+7, n-7);
-    if(n>7 && PK(0)==0x0f && PK(1)==0x1f && PK(2)==0x84 && PK(3)==0x00 && PK(4)==0x00 && PK(5)==0x00 && PK(6)==0x00 && PK(7)==0x00)
-        return is_nops(dyn, addr+8, n-8);
-    return 0;
-}
-
-// return size of next instuciton, -1 is unknown
-// not all instrction are setup
-int next_instruction(dynarec_arm_t *dyn, uintptr_t addr)
-{
-    uint8_t opcode = PK(0);
-    uint8_t nextop;
-    switch (opcode) {
-        case 0x66:
-            opcode = PK(1);
-            switch(opcode) {
-                case 0x90:
-                    return 2;
-            }
-            break;
-        case 0x81:
-            nextop = PK(1);
-            return fakeed(dyn, addr+2, 0, nextop)-addr + 4;
-        case 0x83:
-            nextop = PK(1);
-            return fakeed(dyn, addr+2, 0, nextop)-addr + 1;
-        case 0x84:
-        case 0x85:
-        case 0x88:
-        case 0x89:
-        case 0x8A:
-        case 0x8B:
-        case 0x8C:
-        case 0x8D:
-        case 0x8E:
-        case 0x8F:
-            nextop = PK(1);
-            return fakeed(dyn, addr+2, 0, nextop)-addr;
-        case 0x50:
-        case 0x51:
-        case 0x52:
-        case 0x53:
-        case 0x54:
-        case 0x55:
-        case 0x56:
-        case 0x57:
-        case 0x58:
-        case 0x59:
-        case 0x5A:
-        case 0x5B:
-        case 0x5C:
-        case 0x5D:
-        case 0x5E:
-        case 0x5F:
-        case 0x90:
-        case 0x91:
-        case 0x92:
-        case 0x93:
-        case 0x94:
-        case 0x95:
-        case 0x96:
-        case 0x97:
-        case 0x98:
-        case 0x99:
-        case 0x9B:
-        case 0x9C:
-        case 0x9D:
-        case 0x9E:
-        case 0x9F:
-            return 1;
-        case 0xA0:
-        case 0xA1:
-        case 0xA2:
-        case 0xA3:
-            return 5;
-        case 0xB0:
-        case 0xB1:
-        case 0xB2:
-        case 0xB3:
-        case 0xB4:
-        case 0xB5:
-        case 0xB6:
-        case 0xB7:
-            return 2;
-        case 0xB8:
-        case 0xB9:
-        case 0xBA:
-        case 0xBB:
-        case 0xBC:
-        case 0xBD:
-        case 0xBE:
-        case 0xBF:
-            return 5;
-        case 0xFF:
-            nextop = PK(1);
-            switch((nextop>>3)&7) {
-                case 0: // INC Ed
-                case 1: //DEC Ed
-                case 2: // CALL Ed
-                case 4: // JMP Ed
-                case 6: // Push Ed
-                    return fakeed(dyn, addr+2, 0, nextop)-addr;
-            }
-            break;
-        default:
-            break;
-    }
-    return -1;
-}
-#undef PK
-
-int is_instructions(dynarec_arm_t *dyn, uintptr_t addr, int n)
-{
-    int i = 0;
-    while(i<n) {
-        int j=next_instruction(dyn, addr+i);
-        if(j<=0) return 0;
-        i+=j;
-    }
-    return (i==n)?1:0;
-}
-
-uint32_t needed_flags(dynarec_arm_t *dyn, int ninst, uint32_t setf, int recurse)
-{
-    if(recurse == 10)
-        return X_PEND;
-    if(ninst == dyn->size)
-        return X_PEND; // no more instructions, or too many jmp loop, stop
-    
-    uint32_t needed = dyn->insts[ninst].x64.use_flags;
-    if(needed) {
-        setf &= ~needed;
-        if(!setf)   // all flags already used, no need to continue
-            return needed;
-    }
-
-    if(!needed && !dyn->insts[ninst].x64.set_flags && !dyn->insts[ninst].x64.jmp_insts) {
-        int start = ninst;
-        int end = ninst;
-        while(end<dyn->size && !dyn->insts[end].x64.use_flags && !dyn->insts[end].x64.set_flags && !dyn->insts[end].x64.jmp_insts)
-            ++end;
-        needed = needed_flags(dyn, end, setf, recurse);
-        for(int i=start; i<end; ++i)
-            dyn->insts[i].x64.need_flags = needed;
-        return needed;
-    }
-
-    if(dyn->insts[ninst].x64.set_flags && (dyn->insts[ninst].x64.state_flags!=SF_MAYSET)) {
-        if((setf & ~dyn->insts[ninst].x64.set_flags) == 0)
-            return needed;    // all done, gives all the flags needed
-        setf |= dyn->insts[ninst].x64.set_flags;    // add new flags to continue
-    }
-
-    int jinst = dyn->insts[ninst].x64.jmp_insts;
-    if(dyn->insts[ninst].x64.jmp) {
-        dyn->insts[ninst].x64.need_flags = (jinst==-1)?X_PEND:needed_flags(dyn, jinst, setf, recurse+1);
-        if(dyn->insts[ninst].x64.use_flags)  // conditionnal jump
-             dyn->insts[ninst].x64.need_flags |= needed_flags(dyn, ninst+1, setf, recurse);
-    } else
-        dyn->insts[ninst].x64.need_flags = needed_flags(dyn, ninst+1, setf, recurse);
-    if(dyn->insts[ninst].x64.state_flags==SF_MAYSET)
-        needed |= dyn->insts[ninst].x64.need_flags;
-    else
-        needed |= (dyn->insts[ninst].x64.need_flags & ~dyn->insts[ninst].x64.set_flags);
-    if(needed == (X_PEND|X_ALL))
-        needed = X_ALL;
-    return needed;
-}
-
-instsize_t* addInst(instsize_t* insts, size_t* size, size_t* cap, int x64_size, int arm_size)
-{
-    // x64 instruction is <16 bytes
-    int toadd;
-    if(x64_size>arm_size)
-        toadd = 1 + x64_size/15;
-    else
-        toadd = 1 + arm_size/15;
-    if((*size)+toadd>(*cap)) {
-        *cap = (*size)+toadd;
-        insts = (instsize_t*)realloc(insts, (*cap)*sizeof(instsize_t));
-    }
-    while(toadd) {
-        if(x64_size>15)
-            insts[*size].x64 = 15;    
-        else
-            insts[*size].x64 = x64_size;
-        x64_size -= insts[*size].x64;
-        if(arm_size>15)
-            insts[*size].nat = 15;
-        else
-            insts[*size].nat = arm_size;
-        arm_size -= insts[*size].nat;
-        ++(*size);
-        --toadd;
-    }
-    return insts;
-}
-
-// add a value to table64 (if needed) and gives back the imm19 to use in LDR_literal
-int Table64(dynarec_arm_t *dyn, uint64_t val)
-{
-    // find the value if already present
-    int idx = -1;
-    for(int i=0; i<dyn->table64size && (idx==-1); ++i)
-        if(dyn->table64[i] == val)
-            idx = i;
-    // not found, add it
-    if(idx==-1) {
-        if(dyn->table64size == dyn->table64cap) {
-            dyn->table64cap+=4;
-            dyn->table64 = (uint64_t*)realloc(dyn->table64, dyn->table64cap * sizeof(uint64_t));
-        }
-        idx = dyn->table64size++;
-        dyn->table64[idx] = val;
-    }
-    // calculate offset
-    int delta = dyn->tablestart + idx*sizeof(uint64_t) - (uintptr_t)dyn->block;
-    return delta;
-}
-
-
-uintptr_t arm_pass0(dynarec_arm_t* dyn, uintptr_t addr);
-uintptr_t arm_pass1(dynarec_arm_t* dyn, uintptr_t addr);
-uintptr_t arm_pass2(dynarec_arm_t* dyn, uintptr_t addr);
-uintptr_t arm_pass3(dynarec_arm_t* dyn, uintptr_t addr);
-
-void* FillBlock64(dynablock_t* block, uintptr_t addr) {
-    if(addr>=box64_nodynarec_start && addr<box64_nodynarec_end) {
-        block->done = 1;
-        return (void*)block;
-    }
-    // init the helper
-    dynarec_arm_t helper = {0};
-    helper.start = addr;
-    uintptr_t start = addr;
-    uintptr_t end = arm_pass0(&helper, addr);
-    if(!helper.size) {
-        dynarec_log(LOG_DEBUG, "Warning, null-sized dynarec block (%p)\n", (void*)addr);
-        block->done = 1;
-        return (void*)block;
-    }
-    helper.cap = helper.size+3; // needs epilog handling
-    helper.insts = (instruction_arm64_t*)calloc(helper.cap, sizeof(instruction_arm64_t));
-    // already protect the block and compute hash signature
-    protectDB(addr, end-addr+1);
-    uint32_t hash = X31_hash_code((void*)addr, end-addr+1);
-    // pass 1, addresses, x64 jump addresses, flags
-    arm_pass1(&helper, addr);
-    // calculate barriers
-    for(int i=0; i<helper.size; ++i)
-        if(helper.insts[i].x64.jmp) {
-            uintptr_t j = helper.insts[i].x64.jmp;
-            if(j<start || j>=end)
-                helper.insts[i].x64.jmp_insts = -1;
-            else {
-                // find jump address instruction
-                int k=-1;
-                for(int i2=0; i2<helper.size && k==-1; ++i2) {
-                    if(helper.insts[i2].x64.addr==j)
-                        k=i2;
-                }
-                if(k!=-1)   // -1 if not found, mmm, probably wrong, exit anyway
-                    helper.insts[k].x64.barrier = 1;
-                helper.insts[i].x64.jmp_insts = k;
-            }
-        }
-    for(int i=0; i<helper.size; ++i)
-        if(helper.insts[i].x64.set_flags && !helper.insts[i].x64.need_flags) {
-            helper.insts[i].x64.need_flags = needed_flags(&helper, i+1, helper.insts[i].x64.set_flags, 0);
-            if((helper.insts[i].x64.need_flags&X_PEND) && (helper.insts[i].x64.state_flags==SF_MAYSET))
-                helper.insts[i].x64.need_flags = X_ALL;
-        }
-    
-    // pass 2, instruction size
-    arm_pass2(&helper, addr);
-    // ok, now allocate mapped memory, with executable flag on
-    int sz = helper.arm_size + helper.table64size*sizeof(uint64_t);
-    void* p = (void*)AllocDynarecMap(block, sz);
-    if(p==NULL) {
-        dynarec_log(LOG_DEBUG, "AllocDynarecMap(%p, %d) failed, cancelling block\n", block, sz);
-        free(helper.insts);
-        free(helper.next);
-        free(helper.table64);
-        return NULL;
-    }
-    helper.block = p;
-    helper.arm_start = (uintptr_t)p;
-    helper.tablestart = helper.arm_start + helper.arm_size;
-    if(helper.sons_size) {
-        helper.sons_x64 = (uintptr_t*)calloc(helper.sons_size, sizeof(uintptr_t));
-        helper.sons_arm = (void**)calloc(helper.sons_size, sizeof(void*));
-    }
-    // pass 3, emit (log emit arm opcode)
-    if(box64_dynarec_dump) {
-        dynarec_log(LOG_NONE, "%s%04d|Emitting %d bytes for %d x64 bytes", (box64_dynarec_dump>1)?"\e[01;36m":"", GetTID(), helper.arm_size, helper.isize); 
-        printFunctionAddr(helper.start, " => ");
-        dynarec_log(LOG_NONE, "%s\n", (box64_dynarec_dump>1)?"\e[m":"");
-    }
-    int oldtable64size = helper.table64size;
-    int oldarmsize = helper.arm_size;
-    helper.arm_size = 0;
-    helper.table64size = 0; // reset table64 (but not the cap)
-    arm_pass3(&helper, addr);
-    if((oldarmsize!=helper.arm_size) || (oldtable64size<helper.table64size)) {
-        printf_log(LOG_NONE, "BOX64: Warning, size difference in block between pass2 (%d) & pass3 (%d)!\n", sz, helper.arm_size+helper.table64size*8);
-        uint8_t *dump = (uint8_t*)helper.start;
-        printf_log(LOG_NONE, "Dump of %d x64 opcodes:\n", helper.size);
-        for(int i=0; i<helper.size; ++i) {
-            printf_log(LOG_NONE, "%p:", dump);
-            for(; dump<(uint8_t*)helper.insts[i+1].x64.addr; ++dump)
-                printf_log(LOG_NONE, " %02X", *dump);
-            printf_log(LOG_NONE, "\t%d -> %d\n", helper.insts[i].size2, helper.insts[i].size);
-        }
-        printf_log(LOG_NONE, "Table64 \t%d -> %d\n", oldtable64size*8, helper.table64size*8);
-        printf_log(LOG_NONE, " ------------\n");
-        //TODO: Cancel block and return empty one
-    }
-    // add table64 if needed
-    if(helper.table64size) {
-        memcpy((void*)helper.tablestart, helper.table64, helper.table64size*8);
-    }
-    // all done...
-    __clear_cache(p, p+sz);   // need to clear the cache before execution...
-    // keep size of instructions for signal handling
-    {
-        size_t cap = 1;
-        for(int i=0; i<helper.size; ++i)
-            cap += 1 + ((helper.insts[i].x64.size>helper.insts[i].size)?helper.insts[i].x64.size:helper.insts[i].size)/15;
-        size_t size = 0;
-        block->instsize = (instsize_t*)calloc(cap, sizeof(instsize_t));
-        for(int i=0; i<helper.size; ++i)
-            block->instsize = addInst(block->instsize, &size, &cap, helper.insts[i].x64.size, helper.insts[i].size/4);
-        block->instsize = addInst(block->instsize, &size, &cap, 0, 0);    // add a "end of block" mark, just in case
-    }
-    // ok, free the helper now
-    free(helper.insts);
-    free(helper.next);
-    free(helper.table64);
-    block->size = sz;
-    block->isize = helper.size;
-    block->block = p;
-    block->need_test = 0;
-    //block->x64_addr = (void*)start;
-    block->x64_size = end-start+1;
-    if(box64_dynarec_largest<block->x64_size)
-        box64_dynarec_largest = block->x64_size;
-    block->hash = X31_hash_code(block->x64_addr, block->x64_size);
-    // Check if something changed, to abbort if it as
-    if(block->hash != hash) {
-        dynarec_log(LOG_INFO, "Warning, a block changed while beeing processed hash(%p:%ld)=%x/%x\n", block->x64_addr, block->x64_size, block->hash, hash);
-        free(helper.sons_x64);
-        free(helper.sons_arm);
-        FreeDynarecMap(block, (uintptr_t)p, sz);
-        return NULL;
-    }    // fill sons if any
-    dynablock_t** sons = NULL;
-    int sons_size = 0;
-    if(helper.sons_size) {
-        sons = (dynablock_t**)calloc(helper.sons_size, sizeof(dynablock_t*));
-        for (int i=0; i<helper.sons_size; ++i) {
-            int created = 1;
-            dynablock_t *son = AddNewDynablock(block->parent, helper.sons_x64[i], &created);
-            if(created) {    // avoid breaking a working block!
-                son->block = helper.sons_arm[i];
-                son->x64_addr = (void*)helper.sons_x64[i];
-                son->x64_size = end-helper.sons_x64[i];
-                if(!son->x64_size) {printf_log(LOG_NONE, "Warning, son with null x64 size! (@%p / ARM=%p)", son->x64_addr, son->block);}
-                son->father = block;
-                son->size = sz + son->block - block->block; // update size count, for debugging
-                son->done = 1;
-                if(!son->parent)
-                    son->parent = block->parent;
-                sons[sons_size] = son;
-                ++sons_size;
-            }
-        }
-        if(sons_size) {
-            block->sons = sons;
-            block->sons_size = sons_size;
-        } else
-            free(sons);
-    }
-    free(helper.sons_x64);
-    free(helper.sons_arm);
-    block->done = 1;
-    return (void*)block;
-}

src/dynarec/dynarec_arm64_64.c

@@ -1,222 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-#include <stddef.h>
-#include <pthread.h>
-#include <errno.h>
-
-#include "debug.h"
-#include "box64context.h"
-#include "dynarec.h"
-#include "emu/x64emu_private.h"
-#include "emu/x64run_private.h"
-#include "x64run.h"
-#include "x64emu.h"
-#include "box64stack.h"
-#include "callback.h"
-#include "emu/x64run_private.h"
-#include "x64trace.h"
-#include "dynarec_arm64.h"
-#include "dynarec_arm64_private.h"
-#include "arm64_printer.h"
-
-#include "dynarec_arm64_helper.h"
-#include "dynarec_arm64_functions.h"
-
-
-uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int ninst, rex_t rex, int rep, int* ok, int* need_epilog)
-{
-    uint8_t opcode = F8;
-    uint8_t nextop;
-    uint8_t u8;
-    int32_t j32;
-    uint8_t gd, ed, eb1, eb2;
-    uint8_t wback;
-    int64_t i64;
-    int fixedaddress;
-    MAYUSE(j32);
-    MAYUSE(eb1);
-    MAYUSE(eb2);
-
-    while((opcode==0xF2) || (opcode==0xF3)) {
-        rep = opcode-0xF1;
-        opcode = F8;
-    }
-    // REX prefix before the F0 are ignored
-    rex.rex = 0;
-    while(opcode>=0x40 && opcode<=0x4f) {
-        rex.rex = opcode;
-        opcode = F8;
-    }
-
-    switch(opcode) {
-
-        case 0x03:
-            INST_NAME("ADD Gd, FS:Ed");
-            SETFLAGS(X_ALL, SF_SET);
-            grab_segdata(dyn, addr, ninst, x4, _FS);
-            nextop = F8;
-            GETGD;
-            GETEDO(x4, 0);
-            emit_add32(dyn, ninst, rex, gd, ed, x3, x4);
-            break;
-
-        case 0x33:
-            INST_NAME("XOR Gd, FS:Ed");
-            SETFLAGS(X_ALL, SF_SET);
-            grab_segdata(dyn, addr, ninst, x4, _FS);
-            nextop = F8;
-            GETGD;
-            GETEDO(x4, 0);
-            emit_xor32(dyn, ninst, rex, gd, ed, x3, x4);
-            break;
-                    
-        case 0x81:
-        case 0x83:
-            nextop = F8;
-            grab_segdata(dyn, addr, ninst, x6, _FS);
-            switch((nextop>>3)&7) {
-                case 0: //ADD
-                    if(opcode==0x81) {INST_NAME("ADD Ed, Id");} else {INST_NAME("ADD Ed, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
-                    GETEDO(x6, (opcode==0x81)?4:1);
-                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                    emit_add32c(dyn, ninst, rex, ed, i64, x3, x4, x5);
-                    WBACKO(x6);
-                    break;
-                case 1: //OR
-                    if(opcode==0x81) {INST_NAME("OR Ed, Id");} else {INST_NAME("OR Ed, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
-                    GETEDO(x6, (opcode==0x81)?4:1);
-                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                    emit_or32c(dyn, ninst, rex, ed, i64, x3, x4);
-                    WBACKO(x6);
-                    break;
-                case 2: //ADC
-                    if(opcode==0x81) {INST_NAME("ADC Ed, Id");} else {INST_NAME("ADC Ed, Ib");}
-                    READFLAGS(X_CF);
-                    SETFLAGS(X_ALL, SF_SET);
-                    GETEDO(x6, (opcode==0x81)?4:1);
-                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                    MOV64xw(x5, i64);
-                    emit_adc32(dyn, ninst, rex, ed, x5, x3, x4);
-                    WBACKO(x6);
-                    break;
-                case 3: //SBB
-                    if(opcode==0x81) {INST_NAME("SBB Ed, Id");} else {INST_NAME("SBB Ed, Ib");}
-                    READFLAGS(X_CF);
-                    SETFLAGS(X_ALL, SF_SET);
-                    GETEDO(x6, (opcode==0x81)?4:1);
-                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                    MOV64xw(x5, i64);
-                    emit_sbb32(dyn, ninst, rex, ed, x5, x3, x4);
-                    WBACKO(x6);
-                    break;
-                case 4: //AND
-                    if(opcode==0x81) {INST_NAME("AND Ed, Id");} else {INST_NAME("AND Ed, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
-                    GETEDO(x6, (opcode==0x81)?4:1);
-                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                    emit_and32c(dyn, ninst, rex, ed, i64, x3, x4);
-                    WBACKO(x6);
-                    break;
-                case 5: //SUB
-                    if(opcode==0x81) {INST_NAME("SUB Ed, Id");} else {INST_NAME("SUB Ed, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
-                    GETEDO(x6, (opcode==0x81)?4:1);
-                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                    emit_sub32c(dyn, ninst, rex, ed, i64, x3, x4, x5);
-                    WBACKO(x6);
-                    break;
-                case 6: //XOR
-                    if(opcode==0x81) {INST_NAME("XOR Ed, Id");} else {INST_NAME("XOR Ed, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
-                    GETEDO(x6, (opcode==0x81)?4:1);
-                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                    emit_xor32c(dyn, ninst, rex, ed, i64, x3, x4);
-                    WBACKO(x6);
-                    break;
-                case 7: //CMP
-                    if(opcode==0x81) {INST_NAME("CMP Ed, Id");} else {INST_NAME("CMP Ed, Ib");}
-                    SETFLAGS(X_ALL, SF_SET);
-                    GETEDO(x6, (opcode==0x81)?4:1);
-                    if(opcode==0x81) i64 = F32S; else i64 = F8S;
-                    if(i64) {
-                        MOV64xw(x2, i64);
-                        emit_cmp32(dyn, ninst, rex, ed, x2, x3, x4, x5);
-                    } else
-                        emit_cmp32_0(dyn, ninst, rex, ed, x3, x4);
-                    break;
-            }
-            break;
-            
-        case 0x89:
-            INST_NAME("MOV FS:Ed, Gd");
-            grab_segdata(dyn, addr, ninst, x4, _FS);
-            nextop=F8;
-            GETGD;
-            if(MODREG) {   // reg <= reg
-                MOVxw_REG(xRAX+(nextop&7)+(rex.b<<3), gd);
-            } else {                    // mem <= reg
-                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0, rex, 0, 0);
-                STRxw_REG(gd, ed, x4);
-            }
-            break;
-
-        case 0x8B:
-            INST_NAME("MOV Gd, FS:Ed");
-            grab_segdata(dyn, addr, ninst, x4, _FS);
-            nextop=F8;
-            GETGD;
-            if(MODREG) {   // reg <= reg
-                MOVxw_REG(gd, xRAX+(nextop&7)+(rex.b<<3));
-            } else {                    // mem <= reg
-                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0, rex, 0, 0);
-                LDRxw_REG(gd, ed, x4);
-            }
-            break;
-
-        case 0xC6:
-            INST_NAME("MOV FS:Eb, Ib");
-            grab_segdata(dyn, addr, ninst, x4, _FS);
-            nextop=F8;
-            if(MODREG) {   // reg <= u8
-                u8 = F8;
-                if(!rex.rex) {
-                    ed = (nextop&7);
-                    eb1 = xRAX+(ed&3);  // Ax, Cx, Dx or Bx
-                    eb2 = (ed&4)>>2;    // L or H
-                } else {
-                    eb1 = xRAX+(nextop&7)+(rex.b<<3);
-                    eb2 = 0;            
-                }
-                MOV32w(x3, u8);
-                BFIx(eb1, x3, eb2*8, 8);
-            } else {                    // mem <= u8
-                addr = geted(dyn, addr, ninst, nextop, &ed, x1, &fixedaddress, 0, 0, rex, 0, 1);
-                u8 = F8;
-                MOV32w(x3, u8);
-                STRB_REG(x3, ed, x4);
-            }
-            break;
-        case 0xC7:
-            INST_NAME("MOV FS:Ed, Id");
-            grab_segdata(dyn, addr, ninst, x4, _FS);
-            nextop=F8;
-            if(MODREG) {   // reg <= i32
-                i64 = F32S;
-                ed = xRAX+(nextop&7)+(rex.b<<3);
-                MOV64xw(ed, i64);
-            } else {                    // mem <= i32
-                addr = geted(dyn, addr, ninst, nextop, &ed, x2, &fixedaddress, 0, 0, rex, 0, 4);
-                i64 = F32S;
-                MOV64xw(x3, i64);
-                STRxw_REG(x3, ed, x4);
-            }
-            break;
-
-        default:
-            DEFAULT;
-    }
-    return addr;
-}
-