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M68k rzil base (#6706)

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billow
2026-10-11 12:06:06 +00:00
committed by GitHub
parent d94fee433c
commit e16786f799
33 changed files with 15239 additions and 2753 deletions
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librz/arch/isa/m68k/m68k_cs.c
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// SPDX-FileCopyrightText: 2026 RizinOrg <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only
#include "m68k/m68k_cs.h"
#include <string.h>
#include <rz_util/rz_assert.h>
#define M68K_FPU_EXT_DST(ext) (((ext) >> 7) & 7)
RZ_IPI bool rz_m68k_reg_is_dreg(m68k_reg reg) {
return reg >= M68K_REG_D0 && reg <= M68K_REG_D7;
}
RZ_IPI bool rz_m68k_reg_is_areg(m68k_reg reg) {
return reg >= M68K_REG_A0 && reg <= M68K_REG_A7;
}
RZ_IPI bool rz_m68k_reg_is_gpr(m68k_reg reg) {
return rz_m68k_reg_is_dreg(reg) || rz_m68k_reg_is_areg(reg);
}
RZ_IPI bool rz_m68k_reg_is_control(m68k_reg reg) {
switch (reg) {
case M68K_REG_SFC:
case M68K_REG_DFC:
case M68K_REG_USP:
case M68K_REG_VBR:
case M68K_REG_CACR:
case M68K_REG_CAAR:
case M68K_REG_MSP:
case M68K_REG_ISP:
case M68K_REG_TC:
case M68K_REG_ITT0:
case M68K_REG_ITT1:
case M68K_REG_DTT0:
case M68K_REG_DTT1:
case M68K_REG_MMUSR:
case M68K_REG_URP:
case M68K_REG_SRP:
return true;
default:
return false;
}
}
RZ_IPI bool rz_m68k_op_is_control_reg(RZ_NONNULL const cs_m68k_op *op) {
rz_return_val_if_fail(op, false);
if (op->type != M68K_OP_REG) {
return false;
}
return rz_m68k_reg_is_control(op->reg);
}
RZ_IPI bool rz_m68k_mode_is_coldfire(cs_mode mode) {
#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE
return mode == CS_MODE_M68K_CFV1 ||
mode == CS_MODE_M68K_CFV2 ||
mode == CS_MODE_M68K_CFV3 ||
mode == CS_MODE_M68K_CFV4 ||
mode == CS_MODE_M68K_CFV4E ||
mode == CS_MODE_M68K_CFV5 ||
mode == CS_MODE_M68K_COLDFIRE;
#else
(void)mode;
return false;
#endif
}
RZ_IPI bool rz_m68k_mode_has_fsave(cs_mode mode) {
return mode == CS_MODE_M68K_020 || mode == CS_MODE_M68K_030 ||
mode == CS_MODE_M68K_040 || mode == CS_MODE_M68K_060;
}
RZ_IPI bool rz_m68k_mode_has_emac(cs_mode mode) {
#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE
return mode == CS_MODE_M68K_CFV4E || mode == CS_MODE_M68K_CFV5;
#else
(void)mode;
return false;
#endif
}
RZ_IPI bool rz_m68k_control_reg_implemented(cs_mode mode, m68k_reg reg) {
if (rz_m68k_mode_is_coldfire(mode)) {
return reg == M68K_REG_CACR || reg == M68K_REG_VBR;
}
switch (reg) {
case M68K_REG_SFC:
case M68K_REG_DFC:
case M68K_REG_USP:
case M68K_REG_VBR:
return mode == CS_MODE_M68K_010 || mode == CS_MODE_M68K_020 ||
mode == CS_MODE_M68K_030 || mode == CS_MODE_M68K_040 ||
mode == CS_MODE_M68K_060
#ifdef RZ_CAPSTONE_HAS_M68K_CPU32
|| mode == CS_MODE_M68K_CPU32
#endif
;
case M68K_REG_CACR:
return mode == CS_MODE_M68K_020 || mode == CS_MODE_M68K_030 ||
mode == CS_MODE_M68K_040 || mode == CS_MODE_M68K_060;
case M68K_REG_CAAR:
return mode == CS_MODE_M68K_020 || mode == CS_MODE_M68K_030;
case M68K_REG_MSP:
case M68K_REG_ISP:
return mode == CS_MODE_M68K_020 || mode == CS_MODE_M68K_030 ||
mode == CS_MODE_M68K_040;
case M68K_REG_TC:
case M68K_REG_ITT0:
case M68K_REG_ITT1:
case M68K_REG_DTT0:
case M68K_REG_DTT1:
case M68K_REG_URP:
case M68K_REG_SRP:
return mode == CS_MODE_M68K_040 || mode == CS_MODE_M68K_060;
case M68K_REG_MMUSR:
return mode == CS_MODE_M68K_040;
default:
return false;
}
}
RZ_IPI bool rz_m68k_reg_name_is_mmu_root_pointer(RZ_NULLABLE const char *name) {
return RZ_STR_EQ(name, "srp") || RZ_STR_EQ(name, "crp");
}
RZ_IPI bool rz_m68k_reg_is_fpu(m68k_reg reg) {
return reg >= M68K_REG_FP0 && reg <= M68K_REG_FP7;
}
RZ_IPI bool rz_m68k_op_is_fpu_reg(RZ_NONNULL const cs_m68k_op *op) {
rz_return_val_if_fail(op, false);
if (op->type != M68K_OP_REG) {
return false;
}
return rz_m68k_reg_is_fpu(op->reg);
}
RZ_IPI bool rz_m68k_reg_is_fpu_control(m68k_reg reg) {
return reg == M68K_REG_FPCR || reg == M68K_REG_FPSR || reg == M68K_REG_FPIAR;
}
RZ_IPI bool rz_m68k_reg_is_acc(m68k_reg reg) {
#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE
return reg == M68K_REG_ACC || (reg >= M68K_REG_ACC0 && reg <= M68K_REG_ACC3);
#else
return false;
#endif
}
RZ_IPI bool rz_m68k_op_is_predec_areg(RZ_NONNULL const cs_m68k_op *op) {
rz_return_val_if_fail(op, false);
if (op->address_mode != M68K_AM_REGI_ADDR_PRE_DEC) {
return false;
}
return rz_m68k_reg_is_areg(op->reg);
}
RZ_IPI bool rz_m68k_op_is_data_reg(RZ_NONNULL const cs_m68k_op *op) {
rz_return_val_if_fail(op, false);
if (op->type != M68K_OP_REG) {
return false;
}
return rz_m68k_reg_is_dreg(op->reg);
}
RZ_IPI bool rz_m68k_op_is_addr_reg(RZ_NONNULL const cs_m68k_op *op) {
rz_return_val_if_fail(op, false);
if (op->type != M68K_OP_REG) {
return false;
}
return rz_m68k_reg_is_areg(op->reg);
}
RZ_IPI bool rz_m68k_op_is_gpr(RZ_NONNULL const cs_m68k_op *op) {
rz_return_val_if_fail(op, false);
if (op->type != M68K_OP_REG) {
return false;
}
return rz_m68k_reg_is_gpr(op->reg);
}
RZ_IPI bool rz_m68k_op_is_status_reg(RZ_NONNULL const cs_m68k_op *op) {
rz_return_val_if_fail(op, false);
if (op->type != M68K_OP_REG) {
return false;
}
return op->reg == M68K_REG_CCR || op->reg == M68K_REG_SR;
}
RZ_IPI bool rz_m68k_op_is_acc_reg(RZ_NONNULL const cs_m68k_op *op) {
rz_return_val_if_fail(op, false);
if (op->type != M68K_OP_REG) {
return false;
}
return rz_m68k_reg_is_acc(op->reg);
}
RZ_IPI bool rz_m68k_op_is_fpu_control_reg(RZ_NONNULL const cs_m68k_op *op) {
rz_return_val_if_fail(op, false);
if (op->type != M68K_OP_REG) {
return false;
}
return rz_m68k_reg_is_fpu_control(op->reg);
}
RZ_IPI bool rz_m68k_insn_uses_fpu_operand(RZ_NONNULL const cs_m68k *m68k) {
rz_return_val_if_fail(m68k, false);
for (ut8 i = 0; i < m68k->op_count; i++) {
const cs_m68k_op *op = &m68k->operands[i];
switch (op->type) {
case M68K_OP_INVALID:
// Capstone can leave M68K_OP_INVALID on malformed FPU encodings.
continue;
case M68K_OP_FP_SINGLE:
case M68K_OP_FP_DOUBLE:
#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS
case M68K_OP_FP_EXTENDED:
case M68K_OP_FP_PACKED:
#endif
return true;
case M68K_OP_REG:
if (rz_m68k_reg_is_fpu(op->reg)) {
return true;
}
break;
default:
break;
}
}
return false;
}
RZ_IPI ut32 rz_m68k_detail_op_bits(RZ_NONNULL const cs_m68k *m68k, ut32 fallback_bits) {
rz_return_val_if_fail(m68k, fallback_bits);
if (m68k->op_size.type == M68K_SIZE_TYPE_CPU) {
switch (m68k->op_size.cpu_size) {
case M68K_CPU_SIZE_BYTE:
return 8;
case M68K_CPU_SIZE_WORD:
return 16;
case M68K_CPU_SIZE_LONG:
return 32;
default:
break;
}
}
if (m68k->op_size.type == M68K_SIZE_TYPE_FPU) {
switch (m68k->op_size.fpu_size) {
case M68K_FPU_SIZE_SINGLE:
return 32;
case M68K_FPU_SIZE_DOUBLE:
return 64;
case M68K_FPU_SIZE_EXTENDED:
return 80;
#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS
case M68K_FPU_SIZE_PACKED:
return 80;
#endif
default:
break;
}
}
return fallback_bits;
}
RZ_IPI ut32 rz_m68k_bits_access_bytes(ut32 bits) {
return RZ_MAX(1, bits / 8);
}
RZ_IPI ut32 rz_m68k_reg_stack_access_bytes(cs_mode mode, m68k_reg reg, ut32 bits) {
ut32 bytes = rz_m68k_bits_access_bytes(bits);
// A7 is 32 bits; this is the address-register delta, not its width. A
// byte-sized predecrement/postincrement adjusts A7 by 2 bytes to preserve
// stack word alignment on classic M680x0. ColdFire treats A7 like every
// other address register and adjusts it by one for byte operands (CFPRM).
return reg == M68K_REG_A7 && bytes == 1 && !rz_m68k_mode_is_coldfire(mode) ? 2 : bytes;
}
RZ_IPI m68k_reg rz_m68k_op_base_reg(RZ_NONNULL const cs_m68k_op *op) {
rz_return_val_if_fail(op, M68K_REG_INVALID);
if (op->mem.base_reg != M68K_REG_INVALID) {
return op->mem.base_reg;
}
return rz_m68k_reg_is_areg(op->reg) ? op->reg : M68K_REG_INVALID;
}
RZ_IPI ut32 rz_m68k_op_absolute_address(RZ_NONNULL const cs_m68k_op *op, bool short_addr) {
rz_return_val_if_fail(op, 0);
#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE
st64 address = op->mem.address;
#else
st64 address = op->imm ? op->imm : op->mem.disp;
#endif
return short_addr ? (ut32)(st32)(st16)address : (ut32)address;
}
RZ_IPI bool rz_m68k_op_is_mem_addr(RZ_NONNULL const cs_m68k_op *op) {
rz_return_val_if_fail(op, false);
switch (op->address_mode) {
case M68K_AM_REGI_ADDR:
case M68K_AM_REGI_ADDR_POST_INC:
case M68K_AM_REGI_ADDR_PRE_DEC:
case M68K_AM_REGI_ADDR_DISP:
case M68K_AM_AREGI_INDEX_8_BIT_DISP:
case M68K_AM_AREGI_INDEX_BASE_DISP:
case M68K_AM_MEMI_PRE_INDEX:
case M68K_AM_MEMI_POST_INDEX:
case M68K_AM_PCI_DISP:
case M68K_AM_PCI_INDEX_8_BIT_DISP:
case M68K_AM_PCI_INDEX_BASE_DISP:
case M68K_AM_PC_MEMI_PRE_INDEX:
case M68K_AM_PC_MEMI_POST_INDEX:
case M68K_AM_ABSOLUTE_DATA_SHORT:
case M68K_AM_ABSOLUTE_DATA_LONG:
return true;
default:
return op->type == M68K_OP_MEM;
}
}
RZ_IPI ut64 rz_m68k_op_absolute_mem_address(RZ_NONNULL const cs_m68k_op *operand) {
rz_return_val_if_fail(operand, 0);
if (operand->type != M68K_OP_MEM) {
return 0;
}
// M68000PRM 2.2.16: an absolute short address is sign-extended to 32 bits.
if (operand->address_mode == M68K_AM_ABSOLUTE_DATA_SHORT) {
return rz_m68k_op_absolute_address(operand, true);
}
#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE
return operand->mem.address;
#else
if (operand->imm) {
return operand->imm;
}
return (ut64)(st64)(operand->mem.disp + operand->mem.in_disp + operand->mem.out_disp);
#endif
}
RZ_IPI bool rz_m68k_op_is_absolute_mem(RZ_NONNULL const cs_m68k_op *operand) {
rz_return_val_if_fail(operand, false);
if (operand->type != M68K_OP_MEM) {
return false;
}
switch (operand->address_mode) {
case M68K_AM_ABSOLUTE_DATA_SHORT:
case M68K_AM_ABSOLUTE_DATA_LONG:
return true;
default:
break;
}
return operand->mem.base_reg == M68K_REG_INVALID &&
operand->mem.index_reg == M68K_REG_INVALID &&
operand->mem.in_base_reg == M68K_REG_INVALID;
}
RZ_IPI bool rz_m68k_insn_cache_requires_address(ut32 insn_id) {
switch (insn_id) {
#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE
case M68K_INS_INTOUCH:
#endif
case M68K_INS_CINVL:
case M68K_INS_CINVP:
case M68K_INS_CPUSHL:
case M68K_INS_CPUSHP:
return true;
default:
return false;
}
}
RZ_IPI bool rz_m68k_op_is_data_reg_pair(RZ_NONNULL const cs_m68k_op *op) {
rz_return_val_if_fail(op, false);
if (op->type != M68K_OP_REG_PAIR) {
return false;
}
return rz_m68k_reg_is_dreg(op->reg_pair.reg_0) && rz_m68k_reg_is_dreg(op->reg_pair.reg_1);
}
RZ_IPI bool rz_m68k_op_is_gpr_reg_pair(RZ_NONNULL const cs_m68k_op *op) {
rz_return_val_if_fail(op, false);
if (op->type != M68K_OP_REG_PAIR) {
return false;
}
m68k_reg r0 = op->reg_pair.reg_0;
m68k_reg r1 = op->reg_pair.reg_1;
return rz_m68k_reg_is_gpr(r0) && rz_m68k_reg_is_gpr(r1);
}
#ifdef RZ_CAPSTONE_HAS_M68K_CPU32
RZ_IPI bool rz_m68k_tbl_insn_is_signed(m68k_insn insn) {
return insn == M68K_INS_TBLS || insn == M68K_INS_TBLSN;
}
RZ_IPI bool rz_m68k_tbl_insn_is_unrounded(m68k_insn insn) {
return insn == M68K_INS_TBLSN || insn == M68K_INS_TBLUN;
}
#endif
RZ_IPI bool rz_m68k_fpu_insn_extension_word(RZ_NONNULL const cs_insn *insn, RZ_NONNULL ut16 *extension) {
rz_return_val_if_fail(insn && extension, false);
if (insn->size < 4) {
return false;
}
*extension = ((ut16)insn->bytes[2] << 8) | insn->bytes[3];
return true;
}
RZ_IPI m68k_reg rz_m68k_fpu_insn_extension_dst_reg(RZ_NONNULL const cs_insn *insn) {
rz_return_val_if_fail(insn, M68K_REG_INVALID);
ut16 extension = 0;
if (!rz_m68k_fpu_insn_extension_word(insn, &extension)) {
return M68K_REG_INVALID;
}
return M68K_REG_FP0 + M68K_FPU_EXT_DST(extension);
}
// Capstone collapses some FPU read-modify-write instructions to one operand
// when source and destination are the same (for example "frem fp0"). The
// destination remains encoded in the FPU extension word; materialize it as a
// synthetic second operand so analysis and IL can use a uniform two-operand
// form.
RZ_IPI bool rz_m68k_fpu_insn_hidden_dst_op(RZ_NONNULL const cs_insn *insn, RZ_NONNULL cs_m68k_op *dst) {
rz_return_val_if_fail(insn && dst, false);
m68k_reg reg = rz_m68k_fpu_insn_extension_dst_reg(insn);
if (!rz_m68k_reg_is_fpu(reg)) {
return false;
}
memset(dst, 0, sizeof(*dst));
dst->type = M68K_OP_REG;
dst->reg = reg;
return true;
}
RZ_IPI bool rz_m68k_fpu_op_from_reg(RZ_NONNULL cs_m68k_op *op, m68k_reg reg) {
rz_return_val_if_fail(op, false);
if (!rz_m68k_reg_is_fpu(reg)) {
return false;
}
memset(op, 0, sizeof(*op));
op->type = M68K_OP_REG;
op->reg = reg;
return true;
}
RZ_IPI RZ_NULLABLE const cs_m68k_op *rz_m68k_fpu_insn_second_op_or_hidden_dst(RZ_NONNULL const cs_insn *insn, RZ_NONNULL cs_m68k_op *hidden_dst) {
rz_return_val_if_fail(insn && insn->detail && hidden_dst, NULL);
const cs_m68k *m68k = &insn->detail->m68k;
if (m68k->op_count > 1) {
return &m68k->operands[1];
}
return rz_m68k_fpu_insn_hidden_dst_op(insn, hidden_dst) ? hidden_dst : NULL;
}
RZ_IPI RZ_NULLABLE const cs_m68k_op *rz_m68k_fpu_insn_unary_dst_op(RZ_NONNULL const cs_insn *insn, RZ_NONNULL const cs_m68k_op *src, RZ_NONNULL cs_m68k_op *hidden_dst) {
rz_return_val_if_fail(insn && insn->detail && src && hidden_dst, NULL);
const cs_m68k *m68k = &insn->detail->m68k;
if (m68k->op_count > 1) {
return &m68k->operands[1];
}
if (rz_m68k_op_is_fpu_reg(src)) {
m68k_reg reg = rz_m68k_fpu_insn_extension_dst_reg(insn);
if (rz_m68k_reg_is_fpu(reg) && reg != src->reg && rz_m68k_fpu_insn_hidden_dst_op(insn, hidden_dst)) {
return hidden_dst;
}
return src;
}
return rz_m68k_fpu_insn_hidden_dst_op(insn, hidden_dst) ? hidden_dst : NULL;
}
RZ_IPI bool rz_m68k_fpu_insn_has_data_dst(ut32 insn_id) {
switch (insn_id) {
case M68K_INS_FMOVECR:
case M68K_INS_FABS:
case M68K_INS_FSABS:
case M68K_INS_FDABS:
case M68K_INS_FACOS:
case M68K_INS_FASIN:
case M68K_INS_FATAN:
case M68K_INS_FATANH:
case M68K_INS_FCOS:
case M68K_INS_FCOSH:
case M68K_INS_FETOX:
case M68K_INS_FETOXM1:
case M68K_INS_FLOG10:
case M68K_INS_FLOG2:
case M68K_INS_FLOGN:
case M68K_INS_FLOGNP1:
case M68K_INS_FNEG:
case M68K_INS_FSNEG:
case M68K_INS_FDNEG:
case M68K_INS_FSIN:
case M68K_INS_FSINH:
case M68K_INS_FSQRT:
case M68K_INS_FSSQRT:
case M68K_INS_FDSQRT:
case M68K_INS_FTAN:
case M68K_INS_FTANH:
case M68K_INS_FTENTOX:
case M68K_INS_FTWOTOX:
case M68K_INS_FINT:
case M68K_INS_FINTRZ:
case M68K_INS_FGETEXP:
case M68K_INS_FGETMAN:
case M68K_INS_FADD:
case M68K_INS_FSADD:
case M68K_INS_FDADD:
case M68K_INS_FSUB:
case M68K_INS_FSSUB:
case M68K_INS_FDSUB:
case M68K_INS_FMUL:
case M68K_INS_FSMUL:
case M68K_INS_FDMUL:
case M68K_INS_FSGLMUL:
case M68K_INS_FDIV:
case M68K_INS_FSDIV:
case M68K_INS_FDDIV:
case M68K_INS_FSGLDIV:
case M68K_INS_FMOD:
case M68K_INS_FREM:
case M68K_INS_FSCALE:
case M68K_INS_FCMP:
return true;
default:
return false;
}
}
RZ_IPI bool rz_m68k_fpu_insn_single_op_is_complete(RZ_NONNULL const cs_insn *insn) {
rz_return_val_if_fail(insn && insn->detail, false);
if (insn->detail->m68k.op_count != 1) {
return false;
}
const cs_m68k_op *operand = &insn->detail->m68k.operands[0];
if (!rz_m68k_op_is_fpu_reg(operand)) {
return false;
}
switch (insn->id) {
case M68K_INS_FABS:
case M68K_INS_FSABS:
case M68K_INS_FDABS:
case M68K_INS_FACOS:
case M68K_INS_FASIN:
case M68K_INS_FATAN:
case M68K_INS_FATANH:
case M68K_INS_FCOS:
case M68K_INS_FCOSH:
case M68K_INS_FETOX:
case M68K_INS_FETOXM1:
case M68K_INS_FLOG10:
case M68K_INS_FLOG2:
case M68K_INS_FLOGN:
case M68K_INS_FLOGNP1:
case M68K_INS_FNEG:
case M68K_INS_FSNEG:
case M68K_INS_FDNEG:
case M68K_INS_FSIN:
case M68K_INS_FSINH:
case M68K_INS_FSQRT:
case M68K_INS_FSSQRT:
case M68K_INS_FDSQRT:
case M68K_INS_FTAN:
case M68K_INS_FTANH:
case M68K_INS_FTENTOX:
case M68K_INS_FTWOTOX:
case M68K_INS_FINT:
case M68K_INS_FINTRZ:
case M68K_INS_FGETEXP:
case M68K_INS_FGETMAN:
case M68K_INS_FTST:
return rz_m68k_fpu_insn_extension_dst_reg(insn) == operand->reg;
default:
return false;
}
}
RZ_IPI bool rz_m68k_fpu_insn_needs_hidden_dst(RZ_NONNULL const cs_insn *insn) {
rz_return_val_if_fail(insn && insn->detail, false);
if (insn->detail->m68k.op_count != 1 || !rz_m68k_fpu_insn_has_data_dst(insn->id)) {
return false;
}
if (rz_m68k_fpu_insn_single_op_is_complete(insn)) {
return false;
}
return rz_m68k_reg_is_fpu(rz_m68k_fpu_insn_extension_dst_reg(insn));
}
RZ_IPI bool rz_m68k_fpu_size_is_extended(RZ_NONNULL const cs_m68k *m68k) {
rz_return_val_if_fail(m68k, false);
return m68k->op_size.type == M68K_SIZE_TYPE_FPU && m68k->op_size.fpu_size == M68K_FPU_SIZE_EXTENDED;
}
#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS
RZ_IPI bool rz_m68k_fpu_size_is_packed(RZ_NONNULL const cs_m68k *m68k) {
rz_return_val_if_fail(m68k, false);
return m68k->op_size.type == M68K_SIZE_TYPE_FPU && m68k->op_size.fpu_size == M68K_FPU_SIZE_PACKED;
}
#endif
RZ_IPI bool rz_m68k_op_detail_is_invalid(RZ_NULLABLE const cs_m68k_op *op) {
return !op ||
op->type == M68K_OP_INVALID ||
(op->type == M68K_OP_REG && op->reg == M68K_REG_INVALID) ||
(op->type == M68K_OP_MEM && op->address_mode == M68K_AM_NONE);
}
RZ_IPI bool rz_m68k_fpu_op_is_illegal_read(RZ_NONNULL const cs_m68k *m68k, RZ_NONNULL const cs_m68k_op *op) {
rz_return_val_if_fail(m68k && op, false);
if (rz_m68k_op_is_fpu_reg(op)) {
return false;
}
// Capstone produced no usable operand data; there is nothing to read.
if (rz_m68k_op_detail_is_invalid(op)) {
return true;
}
// A GPR cannot supply an FPU-sized operand (e.g. fmove.x d0, fp0 is illegal).
if (m68k->op_size.type == M68K_SIZE_TYPE_FPU && rz_m68k_op_is_gpr(op)) {
return true;
}
// FP immediates use dedicated M68K_OP_FP_* types; an integer immediate
// cannot encode an FPU-sized value.
if (m68k->op_size.type == M68K_SIZE_TYPE_FPU && op->type == M68K_OP_IMM) {
return true;
}
// An immediate cannot encode an 80-bit extended precision value.
if (op->type == M68K_OP_IMM && rz_m68k_detail_op_bits(m68k, 80) == 80) {
return true;
}
return false;
}
static bool m68k_address_mode_is_pc_relative(m68k_address_mode mode) {
switch (mode) {
case M68K_AM_PCI_DISP:
case M68K_AM_PCI_INDEX_8_BIT_DISP:
case M68K_AM_PCI_INDEX_BASE_DISP:
case M68K_AM_PC_MEMI_PRE_INDEX:
case M68K_AM_PC_MEMI_POST_INDEX:
return true;
default:
return false;
}
}
RZ_IPI bool rz_m68k_fpu_op_is_illegal_write(RZ_NONNULL const cs_m68k *m68k, RZ_NONNULL const cs_m68k_op *op) {
rz_return_val_if_fail(m68k && op, false);
if (rz_m68k_op_is_fpu_reg(op)) {
return false;
}
if (rz_m68k_op_detail_is_invalid(op)) {
return true;
}
// PC-relative addressing is never alterable and cannot be a destination.
if (m68k_address_mode_is_pc_relative(op->address_mode)) {
return true;
}
if (m68k->op_size.type == M68K_SIZE_TYPE_FPU) {
return !rz_m68k_op_is_mem_addr(op);
}
return op->type != M68K_OP_REG && !rz_m68k_op_is_mem_addr(op);
}
RZ_IPI bool rz_m68k_fpu_insn_data_alias_has_dst(RZ_NONNULL const cs_insn *insn) {
rz_return_val_if_fail(insn && insn->detail, false);
if (insn->detail->m68k.op_count < 1) {
return false;
}
cs_m68k_op hidden_dst;
const cs_m68k_op *dst = rz_m68k_fpu_insn_second_op_or_hidden_dst(insn, &hidden_dst);
return dst && rz_m68k_op_is_fpu_reg(dst);
}
librz/arch/isa/m68k/m68k_cs.h
+62 -2
View File
@@ -4,12 +4,14 @@
#ifndef RZ_M68K_CS_H
#define RZ_M68K_CS_H
#include <rz_types.h>
#include <rz_util/rz_str.h>
#include <capstone/capstone.h>
#define M68K_LONGEST_INSTRUCTION 22
#define M68K_MIN_OP_SIZE 2
#define M68K_MAX_OP_SIZE 22
static inline cs_mode rz_m68k_cs_mode(const char *cpu) {
static inline cs_mode rz_m68k_cs_mode(RZ_NULLABLE const char *cpu) {
if (!cpu) {
return CS_MODE_M68K_040;
}
@@ -62,4 +64,62 @@ static inline cs_mode rz_m68k_cs_mode(const char *cpu) {
return CS_MODE_M68K_040;
}
RZ_IPI bool rz_m68k_reg_is_dreg(m68k_reg reg);
RZ_IPI bool rz_m68k_reg_is_areg(m68k_reg reg);
RZ_IPI bool rz_m68k_reg_is_gpr(m68k_reg reg);
RZ_IPI bool rz_m68k_reg_is_control(m68k_reg reg);
RZ_IPI bool rz_m68k_op_is_control_reg(RZ_NONNULL const cs_m68k_op *op);
RZ_IPI bool rz_m68k_mode_is_coldfire(cs_mode mode);
RZ_IPI bool rz_m68k_mode_has_fsave(cs_mode mode);
RZ_IPI bool rz_m68k_mode_has_emac(cs_mode mode);
RZ_IPI bool rz_m68k_control_reg_implemented(cs_mode mode, m68k_reg reg);
RZ_IPI bool rz_m68k_reg_name_is_mmu_root_pointer(RZ_NULLABLE const char *name);
RZ_IPI bool rz_m68k_reg_is_fpu(m68k_reg reg);
RZ_IPI bool rz_m68k_op_is_fpu_reg(RZ_NONNULL const cs_m68k_op *op);
RZ_IPI bool rz_m68k_reg_is_fpu_control(m68k_reg reg);
RZ_IPI bool rz_m68k_reg_is_acc(m68k_reg reg);
RZ_IPI bool rz_m68k_op_is_predec_areg(RZ_NONNULL const cs_m68k_op *op);
RZ_IPI bool rz_m68k_op_is_data_reg(RZ_NONNULL const cs_m68k_op *op);
RZ_IPI bool rz_m68k_op_is_addr_reg(RZ_NONNULL const cs_m68k_op *op);
RZ_IPI bool rz_m68k_op_is_gpr(RZ_NONNULL const cs_m68k_op *op);
RZ_IPI bool rz_m68k_op_is_status_reg(RZ_NONNULL const cs_m68k_op *op);
RZ_IPI bool rz_m68k_op_is_acc_reg(RZ_NONNULL const cs_m68k_op *op);
RZ_IPI bool rz_m68k_op_is_fpu_control_reg(RZ_NONNULL const cs_m68k_op *op);
RZ_IPI bool rz_m68k_insn_uses_fpu_operand(RZ_NONNULL const cs_m68k *m68k);
RZ_IPI ut32 rz_m68k_detail_op_bits(RZ_NONNULL const cs_m68k *m68k, ut32 fallback_bits);
RZ_IPI ut32 rz_m68k_bits_access_bytes(ut32 bits);
RZ_IPI ut32 rz_m68k_reg_stack_access_bytes(cs_mode mode, m68k_reg reg, ut32 bits);
RZ_IPI m68k_reg rz_m68k_op_base_reg(RZ_NONNULL const cs_m68k_op *op);
RZ_IPI ut32 rz_m68k_op_absolute_address(RZ_NONNULL const cs_m68k_op *op, bool short_addr);
RZ_IPI bool rz_m68k_op_is_mem_addr(RZ_NONNULL const cs_m68k_op *op);
RZ_IPI ut64 rz_m68k_op_absolute_mem_address(RZ_NONNULL const cs_m68k_op *operand);
RZ_IPI bool rz_m68k_op_is_absolute_mem(RZ_NONNULL const cs_m68k_op *operand);
RZ_IPI bool rz_m68k_insn_cache_requires_address(ut32 insn_id);
RZ_IPI bool rz_m68k_op_is_data_reg_pair(RZ_NONNULL const cs_m68k_op *op);
RZ_IPI bool rz_m68k_op_is_gpr_reg_pair(RZ_NONNULL const cs_m68k_op *op);
#ifdef RZ_CAPSTONE_HAS_M68K_CPU32
RZ_IPI bool rz_m68k_tbl_insn_is_signed(m68k_insn insn);
RZ_IPI bool rz_m68k_tbl_insn_is_unrounded(m68k_insn insn);
#endif
RZ_IPI bool rz_m68k_fpu_insn_extension_word(RZ_NONNULL const cs_insn *insn, RZ_NONNULL ut16 *extension);
RZ_IPI m68k_reg rz_m68k_fpu_insn_extension_dst_reg(RZ_NONNULL const cs_insn *insn);
RZ_IPI bool rz_m68k_fpu_insn_hidden_dst_op(RZ_NONNULL const cs_insn *insn, RZ_NONNULL cs_m68k_op *dst);
RZ_IPI bool rz_m68k_fpu_op_from_reg(RZ_NONNULL cs_m68k_op *op, m68k_reg reg);
RZ_IPI RZ_NULLABLE const cs_m68k_op *rz_m68k_fpu_insn_second_op_or_hidden_dst(RZ_NONNULL const cs_insn *insn, RZ_NONNULL cs_m68k_op *hidden_dst);
RZ_IPI RZ_NULLABLE const cs_m68k_op *rz_m68k_fpu_insn_unary_dst_op(RZ_NONNULL const cs_insn *insn, RZ_NONNULL const cs_m68k_op *src, RZ_NONNULL cs_m68k_op *hidden_dst);
RZ_IPI bool rz_m68k_fpu_insn_has_data_dst(ut32 insn_id);
RZ_IPI bool rz_m68k_fpu_insn_single_op_is_complete(RZ_NONNULL const cs_insn *insn);
RZ_IPI bool rz_m68k_fpu_insn_needs_hidden_dst(RZ_NONNULL const cs_insn *insn);
RZ_IPI bool rz_m68k_fpu_size_is_extended(RZ_NONNULL const cs_m68k *m68k);
#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS
RZ_IPI bool rz_m68k_fpu_size_is_packed(RZ_NONNULL const cs_m68k *m68k);
#endif
RZ_IPI bool rz_m68k_op_detail_is_invalid(RZ_NULLABLE const cs_m68k_op *op);
RZ_IPI bool rz_m68k_fpu_op_is_illegal_read(RZ_NONNULL const cs_m68k *m68k, RZ_NONNULL const cs_m68k_op *op);
RZ_IPI bool rz_m68k_fpu_op_is_illegal_write(RZ_NONNULL const cs_m68k *m68k, RZ_NONNULL const cs_m68k_op *op);
RZ_IPI bool rz_m68k_fpu_insn_data_alias_has_dst(RZ_NONNULL const cs_insn *insn);
#endif // RZ_M68K_CS_H
librz/arch/isa/m68k/m68k_il.c
+4556
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File diff suppressed because it is too large Load Diff
librz/arch/isa/m68k/m68k_il.h
+14
View File
@@ -0,0 +1,14 @@
// SPDX-FileCopyrightText: 2026 RizinOrg <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only
#ifndef RZ_M68K_IL_H
#define RZ_M68K_IL_H
#include <rz_analysis.h>
#include <rz_il.h>
#include <capstone/capstone.h>
RZ_IPI RzAnalysisILConfig *rz_m68k_cs_il_config(RZ_NONNULL RzAnalysis *analysis);
RZ_IPI RzILOpEffect *rz_m68k_cs_get_il_op(csh handle, cs_mode mode, RZ_NONNULL const cs_insn *insn, ut64 addr);
#endif // RZ_M68K_IL_H
librz/arch/isa/m68k/m68k_il_helpers.c
+970
View File
@@ -0,0 +1,970 @@
// SPDX-FileCopyrightText: 2026 RizinOrg <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only
#include "m68k/m68k_il_helpers.h"
#include <rz_il/rz_il_opbuilder_begin.h>
#include <rz_util/rz_assert.h>
static inline bool m68k_mode_has_master_stack(cs_mode mode) {
/* MC68060UM 11.1.2: the 68060 retains SR.M for software use, but has
* only one supervisor stack. */
return mode == CS_MODE_M68K_020 || mode == CS_MODE_M68K_030 ||
mode == CS_MODE_M68K_040;
}
static RzILOpBool *sr_bit(ut32 bit) {
return NON_ZERO(LOGAND(UNSIGNED(16, VARG("sr")), U16((ut16)(1u << bit))));
}
static bool is_supervisor_stack_bank(const M68KILCtx *ctx, m68k_reg reg) {
rz_return_val_if_fail(ctx, false);
return m68k_mode_has_master_stack(ctx->mode) &&
(reg == M68K_REG_ISP || reg == M68K_REG_MSP);
}
static RzILOpBool *supervisor_stack_bank_active(m68k_reg reg) {
/* M68000PRM 1.3.1/1.3.2: ISP and MSP name the physical A7 banks.
* Their globals hold saved values only while the bank is inactive. */
return AND(sr_bit(M68K_SR_S), reg == M68K_REG_MSP ? sr_bit(M68K_SR_M) : INV(sr_bit(M68K_SR_M)));
}
RZ_IPI RzILOpPure *m68k_reg_value(M68KILCtx *ctx, m68k_reg reg) {
const char *name = cs_reg_name(ctx->handle, reg);
if (!name) {
rz_warn_if_reached();
return NULL;
}
if (is_supervisor_stack_bank(ctx, reg)) {
return ITE(supervisor_stack_bank_active(reg), VARG("a7"), VARG(name));
}
return VARG(name);
}
RZ_IPI RzILOpPure *m68k_read_reg_sized(M68KILCtx *ctx, m68k_reg reg, ut32 bits) {
const char *name = cs_reg_name(ctx->handle, reg);
if (!name) {
rz_warn_if_reached();
return NULL;
}
switch (reg) {
case M68K_REG_A0:
case M68K_REG_A1:
case M68K_REG_A2:
case M68K_REG_A3:
case M68K_REG_A4:
case M68K_REG_A5:
case M68K_REG_A6:
case M68K_REG_A7:
case M68K_REG_PC:
case M68K_REG_USP:
return bits == 32 ? VARG(name) : UNSIGNED(bits, VARG(name));
case M68K_REG_MSP:
case M68K_REG_ISP:
return bits == 32 ? m68k_reg_value(ctx, reg) : UNSIGNED(bits, m68k_reg_value(ctx, reg));
case M68K_REG_CCR:
return bits <= 8
? UNSIGNED(bits, VARG("sr"))
: UNSIGNED(bits, UNSIGNED(8, VARG("sr")));
case M68K_REG_SR:
return bits == 16 ? VARG(name) : UNSIGNED(bits, VARG(name));
case M68K_REG_FP0:
case M68K_REG_FP1:
case M68K_REG_FP2:
case M68K_REG_FP3:
case M68K_REG_FP4:
case M68K_REG_FP5:
case M68K_REG_FP6:
case M68K_REG_FP7:
return bits == 80 ? VARG(name) : UNSIGNED(bits, VARG(name));
default:
break;
}
if (rz_m68k_reg_name_is_mmu_root_pointer(name)) {
return bits == 64 ? VARG(name) : UNSIGNED(bits, VARG(name));
}
return bits == 32 ? VARG(name) : UNSIGNED(bits, VARG(name));
}
RZ_IPI RzILOpEffect *m68k_set_ccr_from_value(RzILOpPure *new_ccr) {
RzILOpPure *ccr8 = UNSIGNED(8, new_ccr);
return SETG("sr", LOGOR(LOGAND(VARG("sr"), U16(0xff00)), UNSIGNED(16, ccr8)));
}
RZ_IPI RzILOpBool *m68k_ccr_bit(ut32 bit) {
rz_return_val_if_fail(bit < 8, NULL);
return NON_ZERO(LOGAND(UNSIGNED(8, VARG("sr")), U8(1u << bit)));
}
static RzILOpBool *cacr_eusp(RzILOpPure *cacr) {
return NON_ZERO(LOGAND(UNSIGNED(32, cacr), U32(1u << M68K_CACR_EUSP)));
}
static RzILOpBool *coldfire_supervisor_stack(RzILOpPure *sr) {
/* MCF5208RM 3.2.3 and 5.2.1: the second A7 bank participates only
* while CACR[EUSP] is enabled. */
return AND(
NON_ZERO(LOGAND(UNSIGNED(16, sr), U16(1u << M68K_SR_S))),
cacr_eusp(VARG("cacr")));
}
RZ_IPI RzILOpBool *m68k_supervisor_mode(void) {
return sr_bit(M68K_SR_S);
}
RZ_IPI RzILOpPure *m68k_ccr_with_flag(RzILOpPure *ccr, ut32 bit, RzILOpBool *value) {
RzILOpPure *cleared = LOGAND(ccr, U8((ut8) ~(1u << bit)));
RzILOpPure *flag = SHIFTL0(BOOL_TO_BV(value, 8), U8(bit));
return LOGOR(cleared, flag);
}
RZ_IPI RzILOpEffect *m68k_set_flags_nzvcx(RzILOpPure *value, ut32 bits, RzILOpBool *v, RzILOpBool *c, RzILOpBool *x) {
RzILOpPure *val = UNSIGNED(bits, value);
RzILOpPure *ccr = LOGAND(UNSIGNED(8, VARG("sr")), U8(0xe0));
ccr = m68k_ccr_with_flag(ccr, M68K_CCR_N, MSB(DUP(val)));
ccr = m68k_ccr_with_flag(ccr, M68K_CCR_Z, IS_ZERO(val));
ccr = m68k_ccr_with_flag(ccr, M68K_CCR_V, v ? v : IL_FALSE);
ccr = m68k_ccr_with_flag(ccr, M68K_CCR_C, c ? c : IL_FALSE);
if (x) {
ccr = m68k_ccr_with_flag(ccr, M68K_CCR_X, x);
} else {
ccr = LOGOR(ccr, LOGAND(UNSIGNED(8, VARG("sr")), U8(1u << M68K_CCR_X)));
}
return m68k_set_ccr_from_value(ccr);
}
RZ_IPI RzILOpEffect *m68k_set_flags_nzvcx_extend(RzILOpPure *value, ut32 bits, RzILOpBool *v, RzILOpBool *c) {
RzILOpPure *val = UNSIGNED(bits, value);
RzILOpPure *ccr = LOGAND(UNSIGNED(8, VARG("sr")), U8(0xe0));
ccr = m68k_ccr_with_flag(ccr, M68K_CCR_N, MSB(DUP(val)));
ccr = m68k_ccr_with_flag(ccr, M68K_CCR_Z, AND(m68k_ccr_bit(M68K_CCR_Z), IS_ZERO(val)));
ccr = m68k_ccr_with_flag(ccr, M68K_CCR_V, v);
ccr = m68k_ccr_with_flag(ccr, M68K_CCR_C, c);
ccr = m68k_ccr_with_flag(ccr, M68K_CCR_X, (RzILOpBool *)DUP(c));
return m68k_set_ccr_from_value(ccr);
}
RZ_IPI RzILOpEffect *m68k_set_flags_div(RzILOpPure *quotient, ut32 bits, RzILOpBool *overflow) {
RzILOpPure *quotient_sized = UNSIGNED(bits, quotient);
RzILOpPure *ccr = LOGAND(UNSIGNED(8, VARG("sr")), U8(0xe0));
RzILOpBool *no_overflow = INV((RzILOpBool *)DUP(overflow));
ccr = m68k_ccr_with_flag(ccr, M68K_CCR_N, AND(no_overflow, MSB(DUP(quotient_sized))));
ccr = m68k_ccr_with_flag(ccr, M68K_CCR_Z, AND(INV((RzILOpBool *)DUP(overflow)), IS_ZERO(quotient_sized)));
ccr = m68k_ccr_with_flag(ccr, M68K_CCR_V, overflow);
ccr = m68k_ccr_with_flag(ccr, M68K_CCR_C, IL_FALSE);
ccr = LOGOR(ccr, LOGAND(UNSIGNED(8, VARG("sr")), U8(1u << M68K_CCR_X)));
return m68k_set_ccr_from_value(ccr);
}
RZ_IPI RzILOpBool *m68k_add_overflow(RzILOpPure *a, RzILOpPure *b, RzILOpPure *r) {
RzILOpBool *same_sign = EQ(BOOL_TO_BV(MSB(DUP(a)), 1), BOOL_TO_BV(MSB(b), 1));
RzILOpBool *diff_result = NE(BOOL_TO_BV(MSB(a), 1), BOOL_TO_BV(MSB(r), 1));
return AND(same_sign, diff_result);
}
RZ_IPI RzILOpBool *m68k_sub_overflow(RzILOpPure *a, RzILOpPure *b, RzILOpPure *r) {
RzILOpBool *diff_sign = NE(BOOL_TO_BV(MSB(DUP(a)), 1), BOOL_TO_BV(MSB(b), 1));
RzILOpBool *diff_result = NE(BOOL_TO_BV(MSB(a), 1), BOOL_TO_BV(MSB(r), 1));
return AND(diff_sign, diff_result);
}
RZ_IPI RzILOpBool *m68k_signed_out_of_range(RzILOpPure *value, ut32 bits) {
st64 min = -(1LL << (bits - 1));
st64 max = (1LL << (bits - 1)) - 1;
return OR(SLT(DUP(value), S64(min)), SGT(value, S64(max)));
}
RZ_IPI RzILOpBool *m68k_addx_overflow(ut32 bits) {
RzILOpPure *sum = ADD(ADD(SIGNED(64, VARL("dst")), SIGNED(64, VARL("src"))), UNSIGNED(64, VARL("x")));
return m68k_signed_out_of_range(sum, bits);
}
RZ_IPI RzILOpBool *m68k_subx_overflow(ut32 bits) {
RzILOpPure *diff = SUB(SUB(SIGNED(64, VARL("dst")), SIGNED(64, VARL("src"))), UNSIGNED(64, VARL("x")));
return m68k_signed_out_of_range(diff, bits);
}
RZ_IPI RzILOpBool *m68k_negx_overflow(ut32 bits) {
RzILOpPure *diff = SUB(SUB(S64(0), SIGNED(64, VARL("dst"))), UNSIGNED(64, VARL("borrow")));
return m68k_signed_out_of_range(diff, bits);
}
static RzILOpPure *reg_write_value(M68KILCtx *ctx, m68k_reg reg, ut32 bits, RzILOpPure *value) {
if (rz_m68k_reg_is_dreg(reg) && bits < 32) {
ut32 mask = bits == 8 ? 0xffffff00u : 0xffff0000u;
return LOGOR(LOGAND(m68k_reg_value(ctx, reg), U32(mask)), UNSIGNED(32, value));
}
if (rz_m68k_reg_is_areg(reg) && bits == 16) {
return SIGNED(32, value);
}
if (reg == M68K_REG_CCR) {
return UNSIGNED(8, value);
}
if (reg == M68K_REG_SR) {
return UNSIGNED(16, value);
}
if (rz_m68k_reg_is_fpu(reg)) {
return UNSIGNED(80, value);
}
const char *name = cs_reg_name(ctx->handle, reg);
if (rz_m68k_reg_name_is_mmu_root_pointer(name)) {
if (bits == 64) {
return UNSIGNED(64, value);
}
return LOGOR(LOGAND(m68k_reg_value(ctx, reg), U64(0xffffffff00000000ULL)), UNSIGNED(64, value));
}
return UNSIGNED(32, value);
}
RZ_IPI RzILOpEffect *m68k_write_reg_sized(M68KILCtx *ctx, m68k_reg reg, ut32 bits, RzILOpPure *value) {
const char *name = cs_reg_name(ctx->handle, reg);
if (!name) {
rz_warn_if_reached();
rz_il_op_pure_free(value);
return NULL;
}
if (reg == M68K_REG_PC) {
return JMP(UNSIGNED(32, value));
}
if (reg == M68K_REG_CCR) {
return m68k_set_ccr_from_value(value);
}
if (is_supervisor_stack_bank(ctx, reg)) {
RzILOpPure *sp = UNSIGNED(32, value);
return BRANCH(supervisor_stack_bank_active(reg), SETG("a7", DUP(sp)), SETG(name, sp));
}
if (reg == M68K_REG_CACR && rz_m68k_mode_is_coldfire(ctx->mode)) {
/* Changing EUSP in supervisor mode changes which physical A7 is
* active, so preserve the outgoing bank before loading the incoming
* one. */
RzILOpEffect *enable_eusp = SEQ2(
SETG("usp", UNSIGNED(32, VARG("a7"))),
SETG("a7", UNSIGNED(32, VARG("isp"))));
RzILOpEffect *disable_eusp = SEQ2(
SETG("isp", UNSIGNED(32, VARG("a7"))),
SETG("a7", UNSIGNED(32, VARG("usp"))));
RzILOpEffect *switch_sp = BRANCH(
cacr_eusp(VARG("cacr")),
disable_eusp,
enable_eusp);
return SEQ3(
SETL("cacr_write_value", UNSIGNED(32, value)),
BRANCH(
AND(
m68k_supervisor_mode(),
XOR(cacr_eusp(VARG("cacr")), cacr_eusp(VARL("cacr_write_value")))),
switch_sp,
EMPTY()),
SETG("cacr", VARL("cacr_write_value")));
}
if (reg == M68K_REG_SR) {
if (rz_m68k_mode_is_coldfire(ctx->mode)) {
RzILOpEffect *save_old_sp = BRANCH(
coldfire_supervisor_stack(VARG("sr")),
SETG("isp", UNSIGNED(32, VARG("a7"))),
SETG("usp", UNSIGNED(32, VARG("a7"))));
RzILOpEffect *load_new_sp = BRANCH(
coldfire_supervisor_stack(VARL("sr_write_value")),
SETG("a7", UNSIGNED(32, VARG("isp"))),
SETG("a7", UNSIGNED(32, VARG("usp"))));
RzILOpPure *old_bank = ITE(coldfire_supervisor_stack(VARG("sr")), U8(1), U8(0));
RzILOpPure *new_bank = ITE(coldfire_supervisor_stack(VARL("sr_write_value")), U8(1), U8(0));
return SEQ3(
SETL("sr_write_value", UNSIGNED(16, value)),
BRANCH(NE(old_bank, new_bank), SEQ2(save_old_sp, load_new_sp), EMPTY()),
SETG("sr", VARL("sr_write_value")));
}
bool has_master_stack = m68k_mode_has_master_stack(ctx->mode);
ut16 master_mask = has_master_stack ? 1u << M68K_SR_M : 0;
RzILOpEffect *save_old_sp = BRANCH(
IS_ZERO(LOGAND(UNSIGNED(16, VARG("sr")), U16(1u << M68K_SR_S))),
SETG("usp", UNSIGNED(32, VARG("a7"))),
BRANCH(
NON_ZERO(LOGAND(UNSIGNED(16, VARG("sr")), U16(master_mask))),
SETG("msp", UNSIGNED(32, VARG("a7"))),
SETG("isp", UNSIGNED(32, VARG("a7")))));
RzILOpEffect *load_new_sp = BRANCH(
IS_ZERO(LOGAND(VARL("sr_write_value"), U16(1u << M68K_SR_S))),
SETG("a7", UNSIGNED(32, VARG("usp"))),
BRANCH(
NON_ZERO(LOGAND(VARL("sr_write_value"), U16(master_mask))),
SETG("a7", UNSIGNED(32, VARG("msp"))),
SETG("a7", UNSIGNED(32, VARG("isp")))));
RzILOpPure *old_bank = ITE(
IS_ZERO(LOGAND(UNSIGNED(16, VARG("sr")), U16(1u << M68K_SR_S))),
U8(0),
ITE(NON_ZERO(LOGAND(UNSIGNED(16, VARG("sr")), U16(master_mask))), U8(2), U8(1)));
RzILOpPure *new_bank = ITE(
IS_ZERO(LOGAND(VARL("sr_write_value"), U16(1u << M68K_SR_S))),
U8(0),
ITE(NON_ZERO(LOGAND(VARL("sr_write_value"), U16(master_mask))), U8(2), U8(1)));
return SEQ3(
SETL("sr_write_value", UNSIGNED(16, value)),
BRANCH(NE(old_bank, new_bank), SEQ2(save_old_sp, load_new_sp), EMPTY()),
SETG("sr", VARL("sr_write_value")));
}
return SETG(name, reg_write_value(ctx, reg, bits, value));
}
RZ_IPI bool m68k_mode_uses_later_movem_base_value(cs_mode mode) {
if (mode == CS_MODE_M68K_020 || mode == CS_MODE_M68K_030 ||
mode == CS_MODE_M68K_040 || mode == CS_MODE_M68K_060) {
return true;
}
#ifdef RZ_CAPSTONE_HAS_M68K_CPU32
return mode == CS_MODE_M68K_CPU32;
#else
return false;
#endif
}
RZ_IPI bool m68k_mode_has_format_word(cs_mode mode) {
return mode != CS_MODE_M68K_000;
}
RZ_IPI RzILOpBool *m68k_rte_format_valid(cs_mode mode) {
switch (mode) {
case CS_MODE_M68K_010:
return OR(EQ(VARL("format"), U16(0)), EQ(VARL("format"), U16(8)));
case CS_MODE_M68K_020:
case CS_MODE_M68K_030:
return OR(
ULT(VARL("format"), U16(3)),
AND(UGE(VARL("format"), U16(9)), ULT(VARL("format"), U16(12))));
case CS_MODE_M68K_040:
return OR(ULT(VARL("format"), U16(5)), EQ(VARL("format"), U16(7)));
case CS_MODE_M68K_060:
return AND(ULT(VARL("format"), U16(5)), NE(VARL("format"), U16(1)));
default:
break;
}
#ifdef RZ_CAPSTONE_HAS_M68K_CPU32
if (mode == CS_MODE_M68K_CPU32) {
return OR(ULT(VARL("format"), U16(3)), EQ(VARL("format"), U16(12)));
}
#endif
return AND(
ULT(VARL("format"), U16(12)),
AND(NE(VARL("format"), U16(5)), NE(VARL("format"), U16(6))));
}
RZ_IPI RzILOpPure *m68k_rte_frame_size(cs_mode mode) {
RzILOpPure *size = ITE(EQ(VARL("format"), U16(0)), U32(8),
ITE(EQ(VARL("format"), U16(1)), U32(8),
ITE(EQ(VARL("format"), U16(2)), U32(12),
ITE(EQ(VARL("format"), U16(3)), U32(12),
ITE(EQ(VARL("format"), U16(4)), U32(16),
ITE(EQ(VARL("format"), U16(7)), U32(60),
ITE(EQ(VARL("format"), U16(8)), U32(58),
ITE(EQ(VARL("format"), U16(9)), U32(20),
ITE(EQ(VARL("format"), U16(10)), U32(32), U32(92))))))))));
#ifdef RZ_CAPSTONE_HAS_M68K_CPU32
if (mode == CS_MODE_M68K_CPU32) {
size = ITE(EQ(VARL("format"), U16(12)), U32(24), size);
}
#else
(void)mode;
#endif
return size;
}
static RzILOpPure *index_value(M68KILCtx *ctx, const cs_m68k_op *op) {
if (op->mem.index_reg == M68K_REG_INVALID) {
return U32(0);
}
RzILOpPure *idx = m68k_read_reg_sized(ctx, op->mem.index_reg, op->mem.index_size ? 32 : 16);
if (!idx) {
return NULL;
}
idx = !op->mem.index_size ? SIGNED(32, idx) : UNSIGNED(32, idx);
ut8 scale = op->mem.scale ? op->mem.scale : 1;
if (scale > 1) {
idx = MUL(idx, U32(scale));
}
return idx;
}
#if !defined(RZ_CAPSTONE_HAS_M68K_CPU32) && !defined(RZ_CAPSTONE_HAS_M68K_COLDFIRE)
// Older Capstone releases report raw PC-relative displacements. Recover the
// encoded extension word address so operands after other extension words lift
// to the expected address.
static bool insn_word_at(const M68KILCtx *ctx, ut32 offset, ut16 *ext_word) {
rz_return_val_if_fail(ctx && ctx->insn && ext_word, false);
if (offset + 1 >= ctx->insn->size || offset + 1 >= sizeof(ctx->insn->bytes)) {
return false;
}
*ext_word = ((ut16)ctx->insn->bytes[offset] << 8) | ctx->insn->bytes[offset + 1];
return true;
}
static ut32 mem_extension_bytes(const cs_m68k_op *op) {
switch (op->address_mode) {
case M68K_AM_REGI_ADDR_DISP:
case M68K_AM_PCI_DISP:
case M68K_AM_ABSOLUTE_DATA_SHORT:
return 2;
case M68K_AM_AREGI_INDEX_8_BIT_DISP:
case M68K_AM_PCI_INDEX_8_BIT_DISP:
return 2;
case M68K_AM_ABSOLUTE_DATA_LONG:
return 4;
case M68K_AM_AREGI_INDEX_BASE_DISP:
case M68K_AM_MEMI_PRE_INDEX:
case M68K_AM_MEMI_POST_INDEX:
case M68K_AM_PCI_INDEX_BASE_DISP:
case M68K_AM_PC_MEMI_PRE_INDEX:
case M68K_AM_PC_MEMI_POST_INDEX: {
ut32 bytes = 2;
if (op->mem.in_disp) {
bytes += 2;
}
if (op->mem.out_disp) {
bytes += 2;
}
return bytes;
}
default:
return 0;
}
}
static ut32 operand_extension_bytes(const M68KILCtx *ctx, const cs_m68k_op *op) {
switch (op->type) {
case M68K_OP_IMM:
return rz_m68k_detail_op_bits(ctx->m68k, 16) > 16 ? 4 : 2;
case M68K_OP_FP_SINGLE:
return 4;
case M68K_OP_FP_DOUBLE:
return 8;
#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS
case M68K_OP_FP_EXTENDED:
case M68K_OP_FP_PACKED:
return 12;
#endif
case M68K_OP_BR_DISP:
switch (op->br_disp.disp_size) {
case M68K_OP_BR_DISP_SIZE_BYTE:
return 0;
case M68K_OP_BR_DISP_SIZE_WORD:
return 2;
case M68K_OP_BR_DISP_SIZE_LONG:
return 4;
default:
return 0;
}
case M68K_OP_MEM:
return mem_extension_bytes(op);
case M68K_OP_INVALID:
case M68K_OP_REG:
case M68K_OP_REG_BITS:
case M68K_OP_REG_PAIR:
#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE
case M68K_OP_SHIFT:
#endif
default:
return 0;
}
}
static ut32 hidden_extension_bytes_before_ea(const M68KILCtx *ctx) {
switch (ctx->insn->id) {
case M68K_INS_MULS:
case M68K_INS_MULU:
case M68K_INS_DIVS:
case M68K_INS_DIVU:
case M68K_INS_DIVSL:
case M68K_INS_DIVUL:
/* M68000PRM long MUL/DIV: the register/size extension precedes EA. */
return rz_m68k_detail_op_bits(ctx->m68k, 16) == 32 ? 2 : 0;
case M68K_INS_BFCHG:
case M68K_INS_BFCLR:
case M68K_INS_BFEXTS:
case M68K_INS_BFEXTU:
case M68K_INS_BFFFO:
case M68K_INS_BFINS:
case M68K_INS_BFSET:
case M68K_INS_BFTST:
case M68K_INS_CHK2:
case M68K_INS_CMP2:
case M68K_INS_MOVES:
return 2;
default:
break;
}
return ctx->insn->size >= 4 && (ctx->insn->bytes[0] & 0xf0) == 0xf0 ? 2 : 0;
}
static ut32 expected_pc_relative_extension_offset(const M68KILCtx *ctx, const cs_m68k_op *op) {
ut32 offset = 2 + hidden_extension_bytes_before_ea(ctx);
for (ut8 i = 0; i < ctx->m68k->op_count; i++) {
const cs_m68k_op *cur = &ctx->m68k->operands[i];
if (cur == op) {
break;
}
offset += operand_extension_bytes(ctx, cur);
}
return offset;
}
/* 680x0 brief/full index extension word (M68000PRM indexed addressing). */
enum {
M68K_EXT_WORD_INDEX_ADDR_REG = 0x8000, /* D/A, bit 15 */
M68K_EXT_WORD_INDEX_LONG = 0x0800, /* W/L, bit 11 */
M68K_EXT_WORD_FULL_FORMAT = 0x0100, /* 0=brief, 1=full, bit 8 */
M68K_EXT_WORD_INDEX_SUPPRESS = 0x0040, /* full-format IS, bit 6 */
};
static bool index_extension_word_matches(const cs_m68k_op *op, ut16 ext_word, bool full) {
if (((ext_word & M68K_EXT_WORD_FULL_FORMAT) != 0) != full) {
return false;
}
if (op->mem.index_reg == M68K_REG_INVALID) {
return full && (ext_word & M68K_EXT_WORD_INDEX_SUPPRESS);
}
m68k_reg index_reg = ((ext_word & M68K_EXT_WORD_INDEX_ADDR_REG) ? M68K_REG_A0 : M68K_REG_D0) +
((ext_word >> 12) & 7);
if (op->mem.index_reg != index_reg) {
return false;
}
if (op->mem.index_size != ((ext_word & M68K_EXT_WORD_INDEX_LONG) ? 1 : 0)) {
return false;
}
ut8 scale = 1 << ((ext_word >> 9) & 3);
return (op->mem.scale ? op->mem.scale : 1) == scale;
}
static bool pc_relative_extension_word_matches(const cs_m68k_op *op, ut16 ext_word) {
switch (op->address_mode) {
case M68K_AM_PCI_DISP:
return (st16)ext_word == op->mem.disp;
case M68K_AM_PCI_INDEX_8_BIT_DISP:
return index_extension_word_matches(op, ext_word, false) && (st8)(ext_word & 0xff) == op->mem.disp;
case M68K_AM_PCI_INDEX_BASE_DISP:
case M68K_AM_PC_MEMI_PRE_INDEX:
case M68K_AM_PC_MEMI_POST_INDEX:
return index_extension_word_matches(op, ext_word, true);
default:
return false;
}
}
static ut32 pc_relative_extension_offset(const M68KILCtx *ctx, const cs_m68k_op *op) {
ut32 expected = expected_pc_relative_extension_offset(ctx, op);
ut16 ext_word = 0;
if (insn_word_at(ctx, expected, &ext_word) && pc_relative_extension_word_matches(op, ext_word)) {
return expected;
}
ut32 fallback = expected;
bool found = false;
for (ut32 offset = 2; offset + 1 < ctx->insn->size; offset += 2) {
if (!insn_word_at(ctx, offset, &ext_word) || !pc_relative_extension_word_matches(op, ext_word)) {
continue;
}
if (offset >= expected) {
return offset;
}
if (!found) {
fallback = offset;
found = true;
}
}
return fallback;
}
#endif
static ut64 branch_disp_base(const M68KILCtx *ctx) {
/* Capstone br_disp is relative to the opcode-word successor (addr+2).
* FDBcc's encoding displacement is relative to the 16-bit displacement
* word (addr+4 / MC68020 UM 7.2.2.3.2). Capstone already adds that extra
* two bytes into br_disp.disp, so using addr+2 here is correct for both
* DBcc/FBcc and FDBcc. Do not switch FDBcc to addr+4 or the offset is
* applied twice. */
return ctx->addr + 2;
}
static ut64 pc_relative_base(M68KILCtx *ctx, const cs_m68k_op *op) {
#if defined(RZ_CAPSTONE_HAS_M68K_CPU32) || defined(RZ_CAPSTONE_HAS_M68K_COLDFIRE)
(void)op;
return branch_disp_base(ctx);
#else
return ctx->addr + pc_relative_extension_offset(ctx, op);
#endif
}
RZ_IPI RzILOpPure *m68k_branch_disp_target(const M68KILCtx *ctx, const cs_m68k_op *op) {
rz_return_val_if_fail(ctx && op, NULL);
if (op->type != M68K_OP_BR_DISP) {
return NULL;
}
return U32(branch_disp_base(ctx) + op->br_disp.disp);
}
RZ_IPI RzILOpEffect *m68k_set_addr_reg_delta(M68KILCtx *ctx, m68k_reg reg, st32 delta) {
if (!rz_m68k_reg_is_areg(reg)) {
return NULL;
}
RzILOpPure *base = m68k_reg_value(ctx, reg);
RzILOpPure *res = delta >= 0 ? ADD(base, U32((ut32)delta)) : SUB(base, U32((ut32)-delta));
return m68k_write_reg_sized(ctx, reg, 32, res);
}
RZ_IPI M68KEA m68k_effective_addr(M68KILCtx *ctx, const cs_m68k_op *op, ut32 bits) {
M68KEA ea = { 0 };
rz_return_val_if_fail(ctx && op, ea);
RzILOpPure *base = NULL;
RzILOpPure *idx = NULL;
m68k_reg base_reg = rz_m68k_op_base_reg(op);
switch (op->address_mode) {
case M68K_AM_REGI_ADDR:
ea.addr = m68k_reg_value(ctx, base_reg);
break;
case M68K_AM_REGI_ADDR_POST_INC:
ea.addr = m68k_reg_value(ctx, base_reg);
ea.post = m68k_set_addr_reg_delta(ctx, base_reg, rz_m68k_reg_stack_access_bytes(ctx->mode, base_reg, bits));
break;
case M68K_AM_REGI_ADDR_PRE_DEC:
ea.pre = m68k_set_addr_reg_delta(ctx, base_reg, -(st32)rz_m68k_reg_stack_access_bytes(ctx->mode, base_reg, bits));
ea.addr = m68k_reg_value(ctx, base_reg);
break;
case M68K_AM_REGI_ADDR_DISP:
ea.addr = ADD(UNSIGNED(32, m68k_reg_value(ctx, base_reg)), UNSIGNED(32, S32((st32)op->mem.disp)));
break;
case M68K_AM_AREGI_INDEX_8_BIT_DISP:
case M68K_AM_AREGI_INDEX_BASE_DISP: {
st64 disp = op->address_mode == M68K_AM_AREGI_INDEX_BASE_DISP ? op->mem.in_disp : op->mem.disp;
base = base_reg != M68K_REG_INVALID ? m68k_reg_value(ctx, base_reg) : U32(0);
idx = index_value(ctx, op);
ea.addr = ADD(ADD(UNSIGNED(32, base), UNSIGNED(32, S32((st32)disp))), idx);
break;
}
case M68K_AM_MEMI_PRE_INDEX:
base = base_reg != M68K_REG_INVALID ? m68k_reg_value(ctx, base_reg) : U32(0);
idx = index_value(ctx, op);
ea.addr = ADD(LOADW(32, ADD(ADD(base, idx), S32((st32)op->mem.in_disp))), S32((st32)op->mem.out_disp));
break;
case M68K_AM_MEMI_POST_INDEX:
base = base_reg != M68K_REG_INVALID ? m68k_reg_value(ctx, base_reg) : U32(0);
idx = index_value(ctx, op);
ea.addr = ADD(ADD(LOADW(32, ADD(base, S32((st32)op->mem.in_disp))), idx), S32((st32)op->mem.out_disp));
break;
case M68K_AM_PCI_DISP:
ea.addr = U32(pc_relative_base(ctx, op) + op->mem.disp);
break;
case M68K_AM_PCI_INDEX_8_BIT_DISP:
case M68K_AM_PCI_INDEX_BASE_DISP: {
st64 disp = op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP ? op->mem.in_disp : op->mem.disp;
idx = index_value(ctx, op);
ut64 pc_base = op->address_mode == M68K_AM_PCI_INDEX_BASE_DISP && base_reg == M68K_REG_INVALID
? 0
: pc_relative_base(ctx, op);
ea.addr = ADD(U32(pc_base + disp), idx);
break;
}
case M68K_AM_PC_MEMI_PRE_INDEX:
base = base_reg != M68K_REG_INVALID ? U32(pc_relative_base(ctx, op)) : U32(0);
idx = index_value(ctx, op);
ea.addr = ADD(LOADW(32, ADD(ADD(base, idx), S32((st32)op->mem.in_disp))), S32((st32)op->mem.out_disp));
break;
case M68K_AM_PC_MEMI_POST_INDEX:
base = base_reg != M68K_REG_INVALID ? U32(pc_relative_base(ctx, op)) : U32(0);
idx = index_value(ctx, op);
ea.addr = ADD(ADD(LOADW(32, ADD(base, S32((st32)op->mem.in_disp))), idx), S32((st32)op->mem.out_disp));
break;
case M68K_AM_ABSOLUTE_DATA_SHORT:
ea.addr = U32(rz_m68k_op_absolute_address(op, true));
break;
case M68K_AM_ABSOLUTE_DATA_LONG:
ea.addr = U32(rz_m68k_op_absolute_address(op, false));
break;
default:
if (rz_m68k_op_is_mem_addr(op) && base_reg != M68K_REG_INVALID) {
ea.addr = ADD(m68k_reg_value(ctx, base_reg), S32((st32)op->mem.disp));
} else if (rz_m68k_op_is_mem_addr(op)) {
ea.addr = U32(rz_m68k_op_absolute_address(op, false));
}
break;
}
return ea;
}
RZ_IPI RzILOpPure *m68k_read_operand(M68KILCtx *ctx, const cs_m68k_op *op, ut32 bits, RzILOpEffect **pre, RzILOpEffect **post) {
if (pre) {
*pre = NULL;
}
if (post) {
*post = NULL;
}
rz_return_val_if_fail(ctx && op, NULL);
if (rz_m68k_op_is_mem_addr(op)) {
M68KEA ea = m68k_effective_addr(ctx, op, bits);
if (!ea.addr) {
m68k_ea_fini(&ea);
return NULL;
}
RzILOpPure *addr = ea.addr;
ea.addr = NULL;
if (pre) {
*pre = ea.pre;
ea.pre = NULL;
}
if (post) {
*post = ea.post;
ea.post = NULL;
}
m68k_ea_fini(&ea);
return LOADW(bits, addr);
}
switch (op->type) {
case M68K_OP_REG:
return m68k_read_reg_sized(ctx, op->reg, bits);
case M68K_OP_IMM:
return UN(bits, op->imm);
case M68K_OP_BR_DISP:
return m68k_branch_disp_target(ctx, op);
case M68K_OP_FP_SINGLE:
return F2BV(F32(op->simm));
case M68K_OP_FP_DOUBLE:
return F2BV(F64(op->dimm));
case M68K_OP_INVALID:
default:
return NULL;
}
}
static RzILOpEffect *write_operand_before_store(M68KILCtx *ctx, const cs_m68k_op *op, ut32 bits,
RzILOpEffect *before_store, RzILOpPure *value) {
if (!ctx || !op) {
rz_il_op_effect_free(before_store);
rz_il_op_pure_free(value);
}
rz_return_val_if_fail(ctx && op, NULL);
if (rz_m68k_op_is_mem_addr(op)) {
M68KEA ea = m68k_effective_addr(ctx, op, bits);
if (!ea.addr) {
rz_il_op_effect_free(before_store);
rz_il_op_pure_free(value);
m68k_ea_fini(&ea);
return NULL;
}
RzILOpPure *addr = ea.addr;
RzILOpEffect *pre = ea.pre;
RzILOpEffect *post = ea.post;
ea.addr = NULL;
ea.pre = NULL;
ea.post = NULL;
m68k_ea_fini(&ea);
RzILOpEffect *store = STOREW(addr, UNSIGNED(bits, value));
if (before_store) {
store = SEQ2(before_store, store);
}
return m68k_effect_pre_post(pre, store, post);
}
switch (op->type) {
case M68K_OP_REG: {
RzILOpEffect *write = m68k_write_reg_sized(ctx, op->reg, bits, value);
if (!write) {
rz_il_op_effect_free(before_store);
return NULL;
}
return before_store ? SEQ2(before_store, write) : write;
}
default:
rz_il_op_effect_free(before_store);
rz_il_op_pure_free(value);
return NULL;
}
}
/**
* \brief Write \p value to \p op, including EA predecrement/postincrement.
*
* \param ctx Lift context
* \param op Destination operand
* \param bits Access width
* \param value Value to store; consumed on all paths
* \return `pre ; store ; post`. EA side effects are part of the returned effect.
*
* Do not sequence a SETL that the store reads *before* this effect: `pre` runs
* first and must not be assumed to commute with caller locals. Bind such a
* local with m68k_write_operand_local() so it is set after `pre`.
*/
RZ_IPI RZ_OWN RzILOpEffect *m68k_write_operand(M68KILCtx *ctx, const cs_m68k_op *op,
ut32 bits, RZ_OWN RzILOpPure *value) {
return write_operand_before_store(ctx, op, bits, NULL, value);
}
/**
* \brief Bind \p value to \p name after EA pre-effects, then store that local.
*
* \return `pre ; SETL(name, value) ; store(VARL(name)) ; post`
*/
RZ_IPI RZ_OWN RzILOpEffect *m68k_write_operand_local(M68KILCtx *ctx, const cs_m68k_op *op,
ut32 bits, const char *name, RZ_OWN RzILOpPure *value) {
if (!name) {
rz_il_op_pure_free(value);
}
rz_return_val_if_fail(name, NULL);
return write_operand_before_store(ctx, op, bits, SETL(name, value), VARL(name));
}
RZ_IPI RzILOpEffect *m68k_label(const char *label) {
if (RZ_STR_EQ(label, "m68k_illegal")) {
return SEQ3(
SETL("trap_op", U32((ut32)M68K_TRAP_OP_ILLEGAL)),
SETL("trap_vector", U32((ut32)M68K_VECTOR_ILLEGAL)),
GOTO(label));
}
if (RZ_STR_EQ(label, "m68k_privilege")) {
return SEQ3(
SETL("trap_op", U32((ut32)M68K_TRAP_OP_PRIVILEGE)),
SETL("trap_vector", U32((ut32)M68K_VECTOR_PRIVILEGE)),
GOTO(label));
}
return GOTO(label);
}
RZ_IPI RzILOpEffect *m68k_guard_supervisor(RzILOpEffect *effect) {
return effect ? BRANCH(m68k_supervisor_mode(), effect, m68k_label("m68k_privilege")) : NULL;
}
RZ_IPI RzILOpEffect *m68k_write_status_reg_unchecked(M68KILCtx *ctx, m68k_reg reg, RzILOpPure *value) {
ut32 bits = reg == M68K_REG_CCR ? 8 : 16;
return m68k_write_reg_sized(ctx, reg, bits, value);
}
RZ_IPI RzILOpEffect *m68k_write_status_reg(M68KILCtx *ctx, m68k_reg reg, RzILOpPure *value) {
RzILOpEffect *write = m68k_write_status_reg_unchecked(ctx, reg, value);
if (!write) {
return NULL;
}
return reg == M68K_REG_SR ? BRANCH(m68k_supervisor_mode(), write, m68k_label("m68k_privilege")) : write;
}
RZ_IPI void m68k_ea_fini(M68KEA *ea) {
if (!ea) {
return;
}
rz_il_op_pure_free(ea->addr);
rz_il_op_effect_free(ea->pre);
rz_il_op_effect_free(ea->post);
*ea = (M68KEA){ 0 };
}
/**
* \brief Sequence optional bookends around a required effect: pre, then \p eff, then post.
*
* \param pre Side effects before \p eff, or NULL
* \param eff Required effect
* \param post Side effects after \p eff, or NULL
* \return `pre ; eff ; post`. `pre` and `post` are skipped when NULL.
*/
RZ_IPI RZ_OWN RzILOpEffect *m68k_effect_pre_post(RZ_NULLABLE RZ_OWN RzILOpEffect *pre,
RZ_NONNULL RZ_OWN RzILOpEffect *eff, RZ_NULLABLE RZ_OWN RzILOpEffect *post) {
if (!eff) {
rz_il_op_effect_free(pre);
rz_il_op_effect_free(post);
rz_return_val_if_fail(eff, NULL);
return NULL;
}
if (post) {
eff = SEQ2(eff, post);
}
if (pre) {
eff = SEQ2(pre, eff);
}
return eff;
}
RZ_IPI void m68k_rw_operand_fini(M68KRWOperand *rw) {
if (!rw) {
return;
}
rz_il_op_effect_free(rw->post);
*rw = (M68KRWOperand){ 0 };
}
RZ_IPI void m68k_bitfield_target_fini(M68KBitfieldTarget *target) {
if (!target) {
return;
}
rz_il_op_effect_free(target->post);
*target = (M68KBitfieldTarget){ 0 };
}
RZ_IPI RzILOpEffect *m68k_exception(M68KTrapOp trap_op, M68KExceptionVector vector, const char *label) {
return SEQ3(
SETL("trap_op", U32((ut32)trap_op)),
SETL("trap_vector", U32((ut32)vector)),
m68k_label(label));
}
RZ_IPI bool m68k_operand_to_local(M68KILCtx *ctx, const char *name, const cs_m68k_op *op, ut32 bits, RzILOpEffect **seq) {
rz_return_val_if_fail(ctx && name && op && seq, false);
RzILOpEffect *pre = NULL;
RzILOpEffect *post = NULL;
RzILOpPure *value = m68k_read_operand(ctx, op, bits, &pre, &post);
if (!value) {
return false;
}
RzILOpEffect *set = m68k_effect_pre_post(pre, SETL(name, value), post);
*seq = *seq ? SEQ2(*seq, set) : set;
return true;
}
RZ_IPI bool m68k_rw_operand_to_local(M68KILCtx *ctx, M68KRWOperand *rw, const char *value_local, const char *addr_local, const cs_m68k_op *op, ut32 bits, RzILOpEffect **seq) {
rz_return_val_if_fail(ctx && rw && value_local && addr_local && op && seq, false);
*rw = (M68KRWOperand){
.op = op,
.addr_local = addr_local,
.post = NULL,
};
if (rz_m68k_op_is_mem_addr(op)) {
M68KEA ea = m68k_effective_addr(ctx, op, bits);
if (!ea.addr) {
m68k_ea_fini(&ea);
return false;
}
RzILOpEffect *pre = ea.pre;
ea.pre = NULL;
RzILOpPure *addr = ea.addr;
ea.addr = NULL;
RzILOpEffect *load = m68k_effect_pre_post(pre,
SEQ2(SETL(addr_local, UNSIGNED(32, addr)),
SETL(value_local, LOADW(bits, VARL(addr_local)))),
NULL);
*seq = *seq ? SEQ2(*seq, load) : load;
rw->post = ea.post;
ea.post = NULL;
m68k_ea_fini(&ea);
return true;
}
switch (op->type) {
case M68K_OP_REG: {
RzILOpPure *value = m68k_read_reg_sized(ctx, op->reg, bits);
if (!value) {
return false;
}
*seq = *seq ? SEQ2(*seq, SETL(value_local, value)) : SETL(value_local, value);
return true;
}
default:
return false;
}
}
RZ_IPI RzILOpEffect *m68k_write_rw_operand(M68KILCtx *ctx, const M68KRWOperand *rw, ut32 bits, RzILOpPure *value) {
rz_return_val_if_fail(ctx && rw && rw->op, NULL);
if (rz_m68k_op_is_mem_addr(rw->op)) {
return STOREW(VARL(rw->addr_local), UNSIGNED(bits, value));
}
switch (rw->op->type) {
case M68K_OP_REG:
return m68k_write_reg_sized(ctx, rw->op->reg, bits, value);
default:
rz_il_op_pure_free(value);
return NULL;
}
}
#include <rz_il/rz_il_opbuilder_end.h>
librz/arch/isa/m68k/m68k_il_helpers.h
+177
View File
@@ -0,0 +1,177 @@
// SPDX-FileCopyrightText: 2026 RizinOrg <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only
#ifndef RZ_M68K_IL_HELPERS_H
#define RZ_M68K_IL_HELPERS_H
#include "m68k/m68k_cs.h"
#include <rz_il.h>
#define M68K_ADDR_BITS 32
#define M68K_CCR_C 0
#define M68K_CCR_V 1
#define M68K_CCR_Z 2
#define M68K_CCR_N 3
#define M68K_CCR_X 4
#define M68K_SR_M 12
#define M68K_SR_S 13
#define M68K_CACR_EUSP 4
/* ColdFire MACSR. Integer S/U=0 is signed, S/U=1 is unsigned (CFPRM).
* EMAC EV is bit 0. Bit 4 is R/T (mode), not a result flag. */
#define M68K_MACSR_EV 0
#define M68K_MACSR_V 1
#define M68K_MACSR_Z 2
#define M68K_MACSR_N 3
#define M68K_MACSR_RT 4
#define M68K_MACSR_FI 5
#define M68K_MACSR_SU 6
#define M68K_MACSR_OMC 7
#define M68K_MACSR_PAV0 8
#define M68K_MACSR_NZVE_MASK ((1u << M68K_MACSR_N) | (1u << M68K_MACSR_Z) | (1u << M68K_MACSR_V) | (1u << M68K_MACSR_EV))
#define M68K_MAC_MASK_RESET 0xffffffffu
// Capstone 4 and 5 do not expose the bitfield register encoding helpers that
// newer releases provide. Keep the encoding local to the M68K lifter.
#ifndef M68K_BF_REG_FLAG
#define M68K_BF_REG_FLAG 0x80
#define M68K_BF_IS_REG(v) ((v) & M68K_BF_REG_FLAG)
#define M68K_BF_REG_NUM(v) ((v) & 7)
#endif
/** Capstone decode context and addresses for one lifted instruction. */
typedef struct {
csh handle; ///< Capstone handle used for register names
cs_mode mode; ///< Capstone M68K CPU mode
const cs_insn *insn; ///< current instruction
const cs_m68k *m68k; ///< Capstone M68K detail for \p insn
ut64 addr; ///< instruction address
ut64 next_addr; ///< fallthrough address
} M68KILCtx;
/** Effective-address value and optional access side effects. */
typedef struct {
RzILOpPure *addr; ///< computed effective address, or NULL on failure
RzILOpEffect *pre; ///< side effects before the access, or NULL
RzILOpEffect *post; ///< side effects after the access, or NULL
} M68KEA;
/** Read/write operand: the Capstone operand plus optional memory state. */
typedef struct {
const cs_m68k_op *op; ///< Capstone operand
const char *addr_local; ///< IL local holding the memory address, or NULL
RzILOpEffect *post; ///< post-access side effects, or NULL
} M68KRWOperand;
/** Bitfield destination: register or memory field plus optional side effects. */
typedef struct {
const cs_m68k_op *op; ///< Capstone operand
bool memory; ///< true when the field is in memory
const char *addr_local; ///< IL local holding the memory address, or NULL
RzILOpEffect *post; ///< post-access side effects, or NULL
} M68KBitfieldTarget;
typedef enum {
M68K_CACHE_OP_TOUCH,
M68K_CACHE_OP_INVALIDATE,
M68K_CACHE_OP_PUSH
} M68KCacheOp;
typedef enum {
M68K_DEBUG_OP_DATA,
M68K_DEBUG_OP_DEBUG
} M68KDebugOp;
typedef enum {
M68K_SYSTEM_OP_RESET,
M68K_SYSTEM_OP_STOP,
M68K_SYSTEM_OP_LPSTOP,
M68K_SYSTEM_OP_HALT,
M68K_SYSTEM_OP_PULSE
} M68KSystemOp;
typedef enum {
M68K_CP_OP_NOP,
M68K_CP_OP_BRANCH,
M68K_CP_OP_LOAD,
M68K_CP_OP_STORE
} M68KCoprocessorOp;
typedef enum {
M68K_TRAP_OP_TRAP,
M68K_TRAP_OP_BKPT,
M68K_TRAP_OP_TRAPCC,
M68K_TRAP_OP_FTRAPCC,
M68K_TRAP_OP_TRAPV,
M68K_TRAP_OP_BGND,
M68K_TRAP_OP_DIV_ZERO,
M68K_TRAP_OP_CHK,
M68K_TRAP_OP_ILLEGAL,
M68K_TRAP_OP_PRIVILEGE,
M68K_TRAP_OP_FORMAT
} M68KTrapOp;
typedef enum {
M68K_VECTOR_ILLEGAL = 4,
M68K_VECTOR_ZERO_DIVIDE = 5,
M68K_VECTOR_CHK = 6,
M68K_VECTOR_TRAPV_TRAPCC = 7,
M68K_VECTOR_PRIVILEGE = 8,
M68K_VECTOR_FORMAT_ERROR = 14
} M68KExceptionVector;
#define M68K_VECTOR_TRAP_BASE 32
typedef enum {
M68K_MMU_OP_LOAD,
M68K_MMU_OP_FLUSH,
M68K_MMU_OP_TEST,
M68K_MMU_OP_MOVE,
M68K_MMU_OP_LOAD_PHYSICAL
} M68KMMUOp;
RZ_IPI RzILOpPure *m68k_reg_value(M68KILCtx *ctx, m68k_reg reg);
RZ_IPI RzILOpPure *m68k_read_reg_sized(M68KILCtx *ctx, m68k_reg reg, ut32 bits);
RZ_IPI RzILOpEffect *m68k_set_ccr_from_value(RzILOpPure *new_ccr);
RZ_IPI RzILOpBool *m68k_ccr_bit(ut32 bit);
RZ_IPI RzILOpBool *m68k_supervisor_mode(void);
RZ_IPI RzILOpPure *m68k_ccr_with_flag(RzILOpPure *ccr, ut32 bit, RzILOpBool *value);
RZ_IPI RzILOpEffect *m68k_set_flags_nzvcx(RzILOpPure *value, ut32 bits, RzILOpBool *v, RzILOpBool *c, RzILOpBool *x);
RZ_IPI RzILOpEffect *m68k_set_flags_nzvcx_extend(RzILOpPure *value, ut32 bits, RzILOpBool *v, RzILOpBool *c);
RZ_IPI RzILOpEffect *m68k_set_flags_div(RzILOpPure *quotient, ut32 bits, RzILOpBool *overflow);
RZ_IPI RzILOpBool *m68k_add_overflow(RzILOpPure *a, RzILOpPure *b, RzILOpPure *r);
RZ_IPI RzILOpBool *m68k_sub_overflow(RzILOpPure *a, RzILOpPure *b, RzILOpPure *r);
RZ_IPI RzILOpBool *m68k_signed_out_of_range(RzILOpPure *value, ut32 bits);
RZ_IPI RzILOpBool *m68k_addx_overflow(ut32 bits);
RZ_IPI RzILOpBool *m68k_subx_overflow(ut32 bits);
RZ_IPI RzILOpBool *m68k_negx_overflow(ut32 bits);
RZ_IPI RzILOpEffect *m68k_write_reg_sized(M68KILCtx *ctx, m68k_reg reg, ut32 bits, RzILOpPure *value);
RZ_IPI bool m68k_mode_uses_later_movem_base_value(cs_mode mode);
RZ_IPI bool m68k_mode_has_format_word(cs_mode mode);
RZ_IPI RzILOpBool *m68k_rte_format_valid(cs_mode mode);
RZ_IPI RzILOpPure *m68k_rte_frame_size(cs_mode mode);
RZ_IPI RzILOpPure *m68k_branch_disp_target(const M68KILCtx *ctx, const cs_m68k_op *op);
RZ_IPI RzILOpEffect *m68k_set_addr_reg_delta(M68KILCtx *ctx, m68k_reg reg, st32 delta);
RZ_IPI M68KEA m68k_effective_addr(M68KILCtx *ctx, const cs_m68k_op *op, ut32 bits);
RZ_IPI RzILOpPure *m68k_read_operand(M68KILCtx *ctx, const cs_m68k_op *op, ut32 bits, RzILOpEffect **pre, RzILOpEffect **post);
RZ_IPI RZ_OWN RzILOpEffect *m68k_write_operand(M68KILCtx *ctx, const cs_m68k_op *op,
ut32 bits, RZ_OWN RzILOpPure *value);
RZ_IPI RZ_OWN RzILOpEffect *m68k_write_operand_local(M68KILCtx *ctx, const cs_m68k_op *op,
ut32 bits, const char *name, RZ_OWN RzILOpPure *value);
RZ_IPI RzILOpEffect *m68k_label(const char *label);
RZ_IPI RzILOpEffect *m68k_guard_supervisor(RzILOpEffect *effect);
RZ_IPI RzILOpEffect *m68k_write_status_reg_unchecked(M68KILCtx *ctx, m68k_reg reg, RzILOpPure *value);
RZ_IPI RzILOpEffect *m68k_write_status_reg(M68KILCtx *ctx, m68k_reg reg, RzILOpPure *value);
RZ_IPI void m68k_ea_fini(M68KEA *ea);
RZ_IPI RZ_OWN RzILOpEffect *m68k_effect_pre_post(RZ_NULLABLE RZ_OWN RzILOpEffect *pre,
RZ_NONNULL RZ_OWN RzILOpEffect *eff, RZ_NULLABLE RZ_OWN RzILOpEffect *post);
RZ_IPI void m68k_rw_operand_fini(M68KRWOperand *rw);
RZ_IPI void m68k_bitfield_target_fini(M68KBitfieldTarget *target);
RZ_IPI RzILOpEffect *m68k_exception(M68KTrapOp trap_op, M68KExceptionVector vector, const char *label);
RZ_IPI bool m68k_operand_to_local(M68KILCtx *ctx, const char *name, const cs_m68k_op *op, ut32 bits, RzILOpEffect **seq);
RZ_IPI bool m68k_rw_operand_to_local(M68KILCtx *ctx, M68KRWOperand *rw, const char *value_local, const char *addr_local, const cs_m68k_op *op, ut32 bits, RzILOpEffect **seq);
RZ_IPI RzILOpEffect *m68k_write_rw_operand(M68KILCtx *ctx, const M68KRWOperand *rw, ut32 bits, RzILOpPure *value);
#endif // RZ_M68K_IL_HELPERS_H
librz/arch/meson.build
+3
View File
@@ -249,6 +249,9 @@ arch_isa_sources = [
'isa/luac/luajit/asm_2.1.c',
'isa/luac/luajit/opcode_2.1.c',
'isa/mcore/mcore.c',
'isa/m68k/m68k_cs.c',
'isa/m68k/m68k_il.c',
'isa/m68k/m68k_il_helpers.c',
'isa/milstd1750/milstd1750_disas.c',
'isa/mips/mips_assembler.c',
'isa/mips/mips_esil.c',
librz/arch/p/analysis/analysis_m68k_cs.c
+352 -90
View File
@@ -19,6 +19,7 @@
#if CAPSTONE_HAS_M68K
#include <capstone/m68k.h>
#include "m68k/m68k_cs.h"
#include "m68k/m68k_il.h"
// http://www.mrc.uidaho.edu/mrc/people/jff/digital/M68Kir.html
#define OPERAND(x) insn->detail->m68k.operands[x]
@@ -32,36 +33,6 @@ static inline ut64 make_64bits_address(ut64 address) {
return UT32_MAX & address;
}
static inline ut64 m68k_mem_operand_absolute_address(const cs_m68k_op *operand) {
if (!operand || operand->type != M68K_OP_MEM) {
return 0;
}
#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE
return operand->mem.address;
#else
if (operand->imm) {
return operand->imm;
}
return (ut64)(st64)(operand->mem.disp + operand->mem.in_disp + operand->mem.out_disp);
#endif
}
static inline bool m68k_mem_operand_is_absolute(const cs_m68k_op *operand) {
if (!operand || operand->type != M68K_OP_MEM) {
return false;
}
switch (operand->address_mode) {
case M68K_AM_ABSOLUTE_DATA_SHORT:
case M68K_AM_ABSOLUTE_DATA_LONG:
return true;
default:
break;
}
return operand->mem.base_reg == M68K_REG_INVALID &&
operand->mem.index_reg == M68K_REG_INVALID &&
operand->mem.in_base_reg == M68K_REG_INVALID;
}
static inline void handle_branch_instruction(RzAnalysisOp *op, ut64 addr, cs_m68k *m68k, ut32 type, int index) {
if (m68k->operands[index].type == M68K_OP_BR_DISP) {
op->type = type;
@@ -85,9 +56,9 @@ static inline void handle_jump_instruction(RzAnalysisOp *op, ut64 addr, cs_m68k
} else if (operand->type == M68K_OP_IMM) {
op->type = type;
op->jump = make_64bits_address(operand->imm);
} else if (m68k_mem_operand_is_absolute(operand)) {
} else if (rz_m68k_op_is_absolute_mem(operand)) {
op->type = type;
op->jump = make_64bits_address(m68k_mem_operand_absolute_address(operand));
op->jump = make_64bits_address(rz_m68k_op_absolute_mem_address(operand));
} else {
op->type = (type == RZ_ANALYSIS_OP_TYPE_CALL) ? RZ_ANALYSIS_OP_TYPE_ICALL : RZ_ANALYSIS_OP_TYPE_IJMP;
}
@@ -95,6 +66,11 @@ static inline void handle_jump_instruction(RzAnalysisOp *op, ut64 addr, cs_m68k
op->fail = make_64bits_address(addr + op->size);
}
static inline void m68k_opex_add_reg(csh handle, RzStructuredData *operand, m68k_reg reg) {
rz_structured_data_map_add_string(operand, "type", "reg");
rz_structured_data_map_add_string(operand, "value", cs_reg_name(handle, reg));
}
static RzStructuredData *mk68_opex(csh handle, cs_insn *insn) {
if (!insn->detail) {
return NULL;
@@ -122,9 +98,15 @@ static RzStructuredData *mk68_opex(csh handle, cs_insn *insn) {
}
#endif
switch (op->type) {
case M68K_OP_INVALID:
rz_structured_data_map_add_string(operand, "type", "invalid");
break;
case M68K_OP_REG:
rz_structured_data_map_add_string(operand, "type", "reg");
rz_structured_data_map_add_string(operand, "value", cs_reg_name(handle, op->reg));
if (op->reg == M68K_REG_INVALID) {
rz_structured_data_map_add_string(operand, "type", "invalid");
} else {
m68k_opex_add_reg(handle, operand, op->reg);
}
break;
case M68K_OP_REG_PAIR:
rz_structured_data_map_add_string(operand, "type", "reg_pair");
@@ -143,6 +125,19 @@ static RzStructuredData *mk68_opex(csh handle, cs_insn *insn) {
rz_structured_data_map_add_string(operand, "type", "fp_double");
rz_structured_data_map_add_double(operand, "value", op->dimm);
break;
#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS
case M68K_OP_FP_EXTENDED:
rz_structured_data_map_add_string(operand, "type", "fp_extended");
rz_structured_data_map_add_unsigned(operand, "sign_exp", op->fp_extended.sign_exp, true);
rz_structured_data_map_add_unsigned(operand, "reserved", op->fp_extended.reserved, true);
rz_structured_data_map_add_unsigned(operand, "significand", op->fp_extended.significand, true);
break;
case M68K_OP_FP_PACKED:
rz_structured_data_map_add_string(operand, "type", "fp_packed");
rz_structured_data_map_add_unsigned(operand, "header", op->fp_packed.header, true);
rz_structured_data_map_add_unsigned(operand, "fraction", op->fp_packed.fraction, true);
break;
#endif
case M68K_OP_REG_BITS:
rz_structured_data_map_add_string(operand, "type", "reg_bits");
rz_structured_data_map_add_unsigned(operand, "value", op->register_bits, true);
@@ -164,8 +159,8 @@ static RzStructuredData *mk68_opex(csh handle, cs_insn *insn) {
rz_structured_data_map_add_string(operand, "base_reg", cs_reg_name(handle, op->mem.base_reg));
}
#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE
if (m68k_mem_operand_is_absolute(op)) {
rz_structured_data_map_add_unsigned(operand, "address", op->mem.address, false);
if (rz_m68k_op_is_absolute_mem(op)) {
rz_structured_data_map_add_unsigned(operand, "address", rz_m68k_op_absolute_mem_address(op), false);
}
#endif
if (op->mem.index_reg != M68K_REG_INVALID) {
@@ -193,6 +188,10 @@ static RzStructuredData *mk68_opex(csh handle, cs_insn *insn) {
break;
}
}
if (rz_m68k_fpu_insn_needs_hidden_dst(insn)) {
RzStructuredData *operand = rz_structured_data_array_add_map(operands);
m68k_opex_add_reg(handle, operand, rz_m68k_fpu_insn_extension_dst_reg(insn));
}
return root;
}
@@ -221,6 +220,10 @@ static inline int m68k_op_memref(const cs_m68k *m68k) {
return 8;
case M68K_FPU_SIZE_EXTENDED:
return 12;
#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS
case M68K_FPU_SIZE_PACKED:
return 12;
#endif
default:
return 0;
}
@@ -257,6 +260,9 @@ static RzAnalysisValue *m68k_value_from_operand(RzAnalysis *a, csh handle, const
return NULL;
}
break;
case M68K_OP_INVALID:
rz_analysis_value_free(value);
return NULL;
case M68K_OP_IMM:
value->type = RZ_ANALYSIS_VAL_IMM;
value->imm = (st64)operand->imm;
@@ -275,9 +281,9 @@ static RzAnalysisValue *m68k_value_from_operand(RzAnalysis *a, csh handle, const
value->regdelta = m68k_reg_get(a, handle, operand->mem.index_reg);
value->mul = operand->mem.scale;
value->delta = operand->mem.disp + operand->mem.in_disp + operand->mem.out_disp;
if (m68k_mem_operand_is_absolute(operand)) {
if (rz_m68k_op_is_absolute_mem(operand)) {
value->absolute = true;
value->base = m68k_mem_operand_absolute_address(operand);
value->base = rz_m68k_op_absolute_mem_address(operand);
value->delta = 0;
} else if (!value->reg && !value->regdelta && value->delta) {
value->absolute = true;
@@ -301,6 +307,21 @@ static RzAnalysisValue *m68k_value_from_operand(RzAnalysis *a, csh handle, const
return value;
}
static RzAnalysisValue *m68k_value_from_reg(RzAnalysis *a, csh handle, m68k_reg reg, RzAnalysisValueAccess access) {
RzAnalysisValue *value = rz_analysis_value_new();
if (!value) {
return NULL;
}
value->access = access;
value->type = RZ_ANALYSIS_VAL_REG;
value->reg = m68k_reg_get(a, handle, reg);
if (!value->reg) {
rz_analysis_value_free(value);
return NULL;
}
return value;
}
static inline void m68k_note_memref(RzAnalysisOp *op, RzAnalysisValue *value) {
if (value && value->type == RZ_ANALYSIS_VAL_MEM && value->memref > 0) {
op->refptr = value->memref;
@@ -349,12 +370,76 @@ static void m68k_set_dst_operand(RzAnalysis *a, RzAnalysisOp *op, csh handle, co
m68k_set_dst_value(op, value);
}
static void m68k_fill_fpu_hidden_dst(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_insn *insn) {
rz_return_if_fail(a && op && insn && insn->detail);
if (!rz_m68k_fpu_insn_needs_hidden_dst(insn)) {
return;
}
const cs_m68k *m68k = &insn->detail->m68k;
for (int i = 0; i < m68k->op_count; i++) {
m68k_add_src_operand(a, op, handle, m68k, i);
}
m68k_reg dst_reg = rz_m68k_fpu_insn_extension_dst_reg(insn);
if ((op->type & RZ_ANALYSIS_OP_TYPE_MASK) == RZ_ANALYSIS_OP_TYPE_CMP) {
m68k_add_src_value(op, m68k_value_from_reg(a, handle, dst_reg, RZ_ANALYSIS_ACC_R));
return;
}
RzAnalysisValueAccess access = RZ_ANALYSIS_ACC_W;
switch (op->type & RZ_ANALYSIS_OP_TYPE_MASK) {
case RZ_ANALYSIS_OP_TYPE_ADD:
case RZ_ANALYSIS_OP_TYPE_SUB:
case RZ_ANALYSIS_OP_TYPE_MUL:
case RZ_ANALYSIS_OP_TYPE_DIV:
case RZ_ANALYSIS_OP_TYPE_MOD:
access |= RZ_ANALYSIS_ACC_R;
break;
default:
break;
}
m68k_set_dst_value(op, m68k_value_from_reg(a, handle, dst_reg, access));
}
static void m68k_fill_fpu_sincos(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_insn *insn) {
rz_return_if_fail(a && op && insn && insn->detail);
const cs_m68k *m68k = &insn->detail->m68k;
if (m68k->op_count > 0) {
m68k_add_src_operand(a, op, handle, m68k, 0);
}
if (m68k->op_count > 1 && m68k->operands[1].type == M68K_OP_REG_PAIR) {
m68k_set_dst_value(op, m68k_value_from_reg(a, handle, m68k->operands[1].reg_pair.reg_1, RZ_ANALYSIS_ACC_W));
return;
}
if (m68k->op_count > 2) {
m68k_set_dst_operand(a, op, handle, m68k, 2, RZ_ANALYSIS_ACC_W);
return;
}
m68k_reg dst_reg = rz_m68k_fpu_insn_extension_dst_reg(insn);
if (dst_reg == M68K_REG_INVALID) {
return;
}
m68k_set_dst_value(op, m68k_value_from_reg(a, handle, dst_reg, RZ_ANALYSIS_ACC_W));
}
static void m68k_fill_srcs_before_dst(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_m68k *m68k, bool dst_is_read) {
if (!m68k || m68k->op_count < 1) {
return;
}
int dst_index = m68k->op_count - 1;
#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS
if (m68k->op_count == 3 && m68k->op_size.type == M68K_SIZE_TYPE_FPU &&
m68k->op_size.fpu_size == M68K_FPU_SIZE_PACKED && m68k->operands[1].type == M68K_OP_MEM) {
dst_index = 1;
m68k_add_src_operand(a, op, handle, m68k, 0);
m68k_add_src_operand(a, op, handle, m68k, 2);
m68k_set_dst_operand(a, op, handle, m68k, dst_index, RZ_ANALYSIS_ACC_W);
return;
}
#endif
for (int i = 0; i < dst_index; i++) {
m68k_add_src_operand(a, op, handle, m68k, i);
}
@@ -405,6 +490,60 @@ static void m68k_fill_indirect_target(RzAnalysis *a, RzAnalysisOp *op, csh handl
m68k_add_src_operand(a, op, handle, m68k, 0);
}
static void m68k_fill_callm(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_m68k *m68k) {
rz_return_if_fail(a && op && m68k);
if (m68k->op_count < 2) {
return;
}
m68k_add_src_operand(a, op, handle, m68k, 0);
m68k_add_src_operand(a, op, handle, m68k, 1);
}
#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE
static void m68k_fill_strldsr(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_m68k *m68k) {
rz_return_if_fail(a && op && m68k);
if (m68k->op_count < 1) {
return;
}
m68k_add_src_operand(a, op, handle, m68k, 0);
m68k_add_src_value(op, m68k_value_from_reg(a, handle, M68K_REG_SR, RZ_ANALYSIS_ACC_R));
m68k_set_dst_value(op, m68k_value_from_reg(a, handle, M68K_REG_SR, RZ_ANALYSIS_ACC_W));
}
static void m68k_fill_coprocessor_transfer(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_m68k *m68k, bool store) {
rz_return_if_fail(a && op && m68k);
if (m68k->op_count < (store ? 2 : 1)) {
return;
}
if (store) {
m68k_set_dst_operand(a, op, handle, m68k, 1, RZ_ANALYSIS_ACC_W);
} else {
m68k_add_src_operand(a, op, handle, m68k, 0);
}
}
#endif
static void m68k_fill_fpu_state_transfer(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_m68k *m68k, bool restore) {
rz_return_if_fail(a && op && m68k);
if (m68k->op_count < 1) {
return;
}
if (restore) {
m68k_add_src_operand(a, op, handle, m68k, 0);
} else {
m68k_set_dst_operand(a, op, handle, m68k, 0, RZ_ANALYSIS_ACC_W);
}
}
static void m68k_fill_scc(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_m68k *m68k) {
rz_return_if_fail(a && op && m68k);
if (m68k->op_count < 1) {
return;
}
m68k_add_src_value(op, m68k_value_from_reg(a, handle, M68K_REG_SR, RZ_ANALYSIS_ACC_R));
m68k_set_dst_operand(a, op, handle, m68k, 0, RZ_ANALYSIS_ACC_W);
}
static void m68k_fill_fpu_unknown(RzAnalysis *a, RzAnalysisOp *op, csh handle, const cs_m68k *m68k) {
if (!m68k || m68k->op_count < 1) {
return;
@@ -422,7 +561,14 @@ static void m68k_set_move_type(RzAnalysisOp *op, const cs_m68k *m68k) {
return;
}
const cs_m68k_op *src = &m68k->operands[0];
const cs_m68k_op *dst = &m68k->operands[m68k->op_count - 1];
int dst_index = m68k->op_count - 1;
#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS
if (m68k->op_count == 3 && m68k->op_size.type == M68K_SIZE_TYPE_FPU &&
m68k->op_size.fpu_size == M68K_FPU_SIZE_PACKED) {
dst_index = 1;
}
#endif
const cs_m68k_op *dst = &m68k->operands[dst_index];
if (dst->type == M68K_OP_MEM) {
op->type = RZ_ANALYSIS_OP_TYPE_STORE;
} else if (src->type == M68K_OP_MEM) {
@@ -471,7 +617,7 @@ static void m68k_set_opdir(RzAnalysisOp *op) {
}
}
static void m68k_handle_fpu_instruction(RzAnalysisOp *op, ut64 addr, cs_m68k *m68k, unsigned int insn_id) {
static void m68k_handle_fpu_instruction(RzAnalysisOp *op, ut64 addr, cs_m68k *m68k, ut32 insn_id) {
op->family = RZ_ANALYSIS_OP_FAMILY_FPU;
switch (insn_id) {
case M68K_INS_FMOVE:
@@ -495,6 +641,7 @@ static void m68k_handle_fpu_instruction(RzAnalysisOp *op, ut64 addr, cs_m68k *m6
case M68K_INS_FSMUL:
case M68K_INS_FDMUL:
case M68K_INS_FSGLMUL:
case M68K_INS_FSCALE:
op->type = RZ_ANALYSIS_OP_TYPE_MUL;
break;
case M68K_INS_FDIV:
@@ -525,6 +672,32 @@ static void m68k_handle_fpu_instruction(RzAnalysisOp *op, ut64 addr, cs_m68k *m6
case M68K_INS_FINTRZ:
op->type = RZ_ANALYSIS_OP_TYPE_CAST;
break;
case M68K_INS_FACOS:
case M68K_INS_FASIN:
case M68K_INS_FATAN:
case M68K_INS_FATANH:
case M68K_INS_FCOS:
case M68K_INS_FCOSH:
case M68K_INS_FETOX:
case M68K_INS_FETOXM1:
case M68K_INS_FGETEXP:
case M68K_INS_FGETMAN:
case M68K_INS_FLOG10:
case M68K_INS_FLOG2:
case M68K_INS_FLOGN:
case M68K_INS_FLOGNP1:
case M68K_INS_FSIN:
case M68K_INS_FSINCOS:
case M68K_INS_FSINH:
case M68K_INS_FSQRT:
case M68K_INS_FSSQRT:
case M68K_INS_FDSQRT:
case M68K_INS_FTAN:
case M68K_INS_FTANH:
case M68K_INS_FTENTOX:
case M68K_INS_FTWOTOX:
op->type = RZ_ANALYSIS_OP_TYPE_MOV;
break;
case M68K_INS_FNOP:
op->type = RZ_ANALYSIS_OP_TYPE_NOP;
break;
@@ -713,11 +886,63 @@ static void op_fillval(RzAnalysis *a, RzAnalysisOp *op, csh handle, cs_insn *ins
case M68K_INS_SATS:
m68k_fill_unary_rw(a, op, handle, m68k);
return;
case M68K_INS_STRLDSR:
m68k_fill_strldsr(a, op, handle, m68k);
return;
case M68K_INS_CP0LD:
case M68K_INS_CP1LD:
m68k_fill_coprocessor_transfer(a, op, handle, m68k, false);
return;
case M68K_INS_CP0ST:
case M68K_INS_CP1ST:
m68k_fill_coprocessor_transfer(a, op, handle, m68k, true);
return;
#endif
case M68K_INS_FSAVE:
m68k_fill_fpu_state_transfer(a, op, handle, m68k, false);
return;
case M68K_INS_FRESTORE:
m68k_fill_fpu_state_transfer(a, op, handle, m68k, true);
return;
case M68K_INS_CALLM:
m68k_fill_callm(a, op, handle, m68k);
return;
case M68K_INS_ST:
case M68K_INS_SF:
case M68K_INS_SHI:
case M68K_INS_SLS:
case M68K_INS_SCC:
case M68K_INS_SHS:
case M68K_INS_SCS:
case M68K_INS_SLO:
case M68K_INS_SNE:
case M68K_INS_SEQ:
case M68K_INS_SVC:
case M68K_INS_SVS:
case M68K_INS_SPL:
case M68K_INS_SMI:
case M68K_INS_SGE:
case M68K_INS_SLT:
case M68K_INS_SGT:
case M68K_INS_SLE:
m68k_fill_scc(a, op, handle, m68k);
return;
case M68K_INS_FSINCOS:
m68k_fill_fpu_sincos(a, op, handle, insn);
return;
default:
break;
}
if (rz_m68k_fpu_insn_needs_hidden_dst(insn)) {
m68k_fill_fpu_hidden_dst(a, op, handle, insn);
return;
}
if (rz_m68k_fpu_insn_has_data_dst(insn->id) && rz_m68k_fpu_insn_single_op_is_complete(insn)) {
m68k_fill_unary_rw(a, op, handle, m68k);
return;
}
switch (op->type & RZ_ANALYSIS_OP_TYPE_MASK) {
case RZ_ANALYSIS_OP_TYPE_LOAD:
case RZ_ANALYSIS_OP_TYPE_MOV:
@@ -756,6 +981,9 @@ static void op_fillval(RzAnalysis *a, RzAnalysisOp *op, csh handle, cs_insn *ins
case RZ_ANALYSIS_OP_TYPE_CMP:
m68k_fill_all_srcs(a, op, handle, m68k);
break;
case RZ_ANALYSIS_OP_TYPE_TRAP:
m68k_fill_all_srcs(a, op, handle, m68k);
break;
case RZ_ANALYSIS_OP_TYPE_UJMP:
case RZ_ANALYSIS_OP_TYPE_UCALL:
m68k_fill_indirect_target(a, op, handle, m68k);
@@ -771,8 +999,9 @@ static void op_fillval(RzAnalysis *a, RzAnalysisOp *op, csh handle, cs_insn *ins
static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, RzAnalysisOpMask mask) {
M68KContext *ctx = (M68KContext *)a->plugin_data;
int n, ret, opsize = -1;
cs_insn *insn;
int opsize = -1;
size_t n = 0;
cs_insn *insn = NULL;
cs_m68k *m68k;
cs_detail *detail;
@@ -784,26 +1013,20 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
ctx->omode = -1;
ctx->obits = a->bits;
}
op->size = 4;
if (len < M68K_MIN_OP_SIZE) {
return -1;
}
if (ctx->handle == 0) {
ret = cs_open(CS_ARCH_M68K, mode, &ctx->handle);
if (ret != CS_ERR_OK) {
if (cs_open(CS_ARCH_M68K, mode, &ctx->handle) != CS_ERR_OK) {
goto fin;
}
ctx->omode = mode;
cs_option(ctx->handle, CS_OPT_DETAIL, CS_OPT_ON);
}
n = cs_disasm(ctx->handle, (ut8 *)buf, len, addr, 1, &insn);
if (n < 1 || insn->size < 1) {
if (n < 1 || !insn || insn->size < 1) {
op->type = RZ_ANALYSIS_OP_TYPE_ILL;
op->size = 2;
opsize = -1;
goto beach;
}
if (!memcmp(buf, "\xff\xff", RZ_MIN(len, 2))) {
op->type = RZ_ANALYSIS_OP_TYPE_ILL;
op->size = 2;
opsize = -1;
opsize = op->size = M68K_MIN_OP_SIZE;
goto beach;
}
detail = insn->detail;
@@ -813,9 +1036,16 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
if (mask & RZ_ANALYSIS_OP_MASK_OPEX) {
op->opex = mk68_opex(ctx->handle, insn);
}
if (mask & RZ_ANALYSIS_OP_MASK_IL) {
op->il_op = rz_m68k_cs_get_il_op(ctx->handle, mode, insn, addr);
}
switch (insn->id) {
case M68K_INS_INVALID:
op->type = RZ_ANALYSIS_OP_TYPE_ILL;
if (mask & RZ_ANALYSIS_OP_MASK_IL) {
rz_il_op_effect_free(op->il_op);
op->il_op = NULL;
}
break;
case M68K_INS_ADD:
case M68K_INS_ADDA:
@@ -832,9 +1062,13 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
op->type = RZ_ANALYSIS_OP_TYPE_SHL;
break;
case M68K_INS_ASR:
op->type = RZ_ANALYSIS_OP_TYPE_SHR;
op->type = RZ_ANALYSIS_OP_TYPE_SAR;
break;
case M68K_INS_ABCD:
op->type = RZ_ANALYSIS_OP_TYPE_ADD;
break;
case M68K_INS_BKPT:
op->type = RZ_ANALYSIS_OP_TYPE_TRAP;
break;
case M68K_INS_BHS:
case M68K_INS_BLO:
@@ -872,14 +1106,20 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
case M68K_INS_BFINS:
case M68K_INS_BFSET:
case M68K_INS_BFTST:
case M68K_INS_BKPT:
case M68K_INS_CALLM:
case M68K_INS_CAS:
case M68K_INS_CAS2:
case M68K_INS_CHK:
case M68K_INS_CHK2:
// TODO:
break;
case M68K_INS_CALLM:
if (m68k->op_count > 1) {
op->type = RZ_ANALYSIS_OP_TYPE_ICALL;
op->fail = make_64bits_address(addr + op->size);
} else {
op->type = RZ_ANALYSIS_OP_TYPE_UCALL;
}
break;
case M68K_INS_CLR:
op->type = RZ_ANALYSIS_OP_TYPE_MOV;
break;
@@ -1125,9 +1365,6 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
case M68K_INS_FTWOTOX:
m68k_handle_fpu_instruction(op, addr, m68k, insn->id);
break;
case M68K_INS_HALT:
op->type = RZ_ANALYSIS_OP_TYPE_NOP;
break;
case M68K_INS_ILLEGAL:
op->type = RZ_ANALYSIS_OP_TYPE_ILL;
break;
@@ -1137,9 +1374,6 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
case M68K_INS_JSR:
handle_jump_instruction(op, addr, m68k, RZ_ANALYSIS_OP_TYPE_CALL);
break;
case M68K_INS_LPSTOP:
op->type = RZ_ANALYSIS_OP_TYPE_NOP;
break;
case M68K_INS_LSL:
op->type = RZ_ANALYSIS_OP_TYPE_SHL;
break;
@@ -1165,6 +1399,11 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
case M68K_INS_MOVE16:
m68k_set_move_type(op, m68k);
break;
case M68K_INS_PMOVE:
case M68K_INS_PMOVEFD:
op->family = RZ_ANALYSIS_OP_FAMILY_PRIV;
m68k_set_move_type(op, m68k);
break;
#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE
case M68K_INS_MOV3Q:
case M68K_INS_MOVCLR:
@@ -1179,7 +1418,11 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
m68k_set_cast_type(op, m68k);
break;
case M68K_INS_MAC:
case M68K_INS_MAAAC:
case M68K_INS_MASAC:
case M68K_INS_MSAAC:
case M68K_INS_MSAC:
case M68K_INS_MSSAC:
op->type = RZ_ANALYSIS_OP_TYPE_MUL;
break;
case M68K_INS_SATS:
@@ -1196,10 +1439,16 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
op->type = RZ_ANALYSIS_OP_TYPE_SYNC;
break;
case M68K_INS_STRLDSR:
op->stackop = RZ_ANALYSIS_STACK_INC;
op->stackptr = -4;
op->type = RZ_ANALYSIS_OP_TYPE_MOV;
break;
case M68K_INS_WDDATA:
case M68K_INS_WDEBUG:
op->type = RZ_ANALYSIS_OP_TYPE_MOV;
break;
#endif
#ifdef RZ_CAPSTONE_HAS_M68K_CPU32
case M68K_INS_TBLS:
case M68K_INS_TBLU:
case M68K_INS_TBLSN:
@@ -1207,6 +1456,10 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
m68k_set_move_type(op, m68k);
break;
case M68K_INS_BGND:
op->type = RZ_ANALYSIS_OP_TYPE_TRAP;
break;
#endif
#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE
case M68K_INS_TPF:
op->type = RZ_ANALYSIS_OP_TYPE_TRAP;
break;
@@ -1255,10 +1508,9 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
case M68K_INS_PLOADW:
case M68K_INS_PLPAR:
case M68K_INS_PLPAW:
case M68K_INS_PMOVE:
case M68K_INS_PMOVEFD:
case M68K_INS_PTESTR:
case M68K_INS_PTESTW:
case M68K_INS_HALT:
case M68K_INS_PULSE:
case M68K_INS_RESET:
break;
@@ -1283,6 +1535,8 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
op->type = RZ_ANALYSIS_OP_TYPE_RET;
break;
case M68K_INS_SBCD:
op->type = RZ_ANALYSIS_OP_TYPE_SUB;
break;
case M68K_INS_ST:
case M68K_INS_SF:
case M68K_INS_SHI:
@@ -1301,6 +1555,9 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
case M68K_INS_SLT:
case M68K_INS_SGT:
case M68K_INS_SLE:
op->type = RZ_ANALYSIS_OP_TYPE_CMOV;
break;
case M68K_INS_LPSTOP:
case M68K_INS_STOP:
break;
case M68K_INS_SUB:
@@ -1314,6 +1571,7 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
op->type = RZ_ANALYSIS_OP_TYPE_MOV;
break;
case M68K_INS_TAS:
op->type = RZ_ANALYSIS_OP_TYPE_OR;
break;
case M68K_INS_TRAP:
case M68K_INS_TRAPV:
@@ -1355,7 +1613,9 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
op_fillval(a, op, ctx->handle, insn);
}
beach:
cs_free(insn, n);
if (insn) {
cs_free(insn, n);
}
// cs_close (&handle);
fin:
return opsize;
@@ -1391,21 +1651,12 @@ static char *m68k_get_reg_profile(RzAnalysis *analysis) {
"gpr a7 .32 60 0\n"
"gpr pc .32 72 0\n"
"gpr ccr .8 71 0\n" // subset of the SR, available from any mode
"gpr fp0 .32 80 0\n" // FPU register 0, 96bits to write and read max
"gpr fp1 .32 84 0\n" // FPU register 1, 96bits to write and read max
"gpr fp2 .32 88 0\n" // FPU register 2, 96bits to write and read max
"gpr fp3 .32 92 0\n" // FPU register 3, 96bits to write and read max
"gpr fp4 .32 96 0\n" // FPU register 4, 96bits to write and read max
"gpr fp5 .32 100 0\n" // FPU register 5, 96bits to write and read max
"gpr fp6 .32 104 0\n" // FPU register 6, 96bits to write and read max
"gpr fp7 .32 108 0\n" // FPU register 7, 96bits to write and read max
"gpr fpcr .32 112 0\n"
"gpr fpsr .32 116 0\n"
"gpr fpiar .32 120 0\n"
"gpr sr .16 70 0\n" // only available for read and write access during supervisor mode
"gpr sfc .32 124 0\n" // source function code register
"gpr dfc .32 128 0\n" // destination function code register
"gpr usp .32 60 0\n" // user stack point this is an shadow register of A7 user mode, SR bit 0xD is 0
"gpr vbr .32 132 0\n" // vector base register, this is a Address pointer
"gpr cacr .32 136 0\n" // cache control register, implementation specific
"gpr caar .32 140 0\n" // cache address register, 68020, 68EC020, 68030 and 68EC030 only.
@@ -1418,19 +1669,29 @@ static char *m68k_get_reg_profile(RzAnalysis *analysis) {
"gpr dtt1 .32 168 0\n" // in 68EC040 this is DACR1
"gpr mmusr .32 172 0\n"
"gpr urp .32 176 0\n"
"gpr srp .32 180 0\n"
"gpr tt0 .32 184 0\n"
"gpr tt1 .32 188 0\n"
"gpr crp .32 192 0\n"
"gpr acc .32 196 0\n"
"gpr acc0 .32 200 0\n"
"gpr acc1 .32 204 0\n"
"gpr acc2 .32 208 0\n"
"gpr acc3 .32 212 0\n"
"gpr accext01 .32 216 0\n"
"gpr accext23 .32 220 0\n"
"gpr macsr .32 224 0\n"
"gpr mask .32 228 0\n";
"gpr srp .64 180 0\n"
"gpr tt0 .32 188 0\n"
"gpr tt1 .32 192 0\n"
"gpr crp .64 196 0\n"
"gpr acc .32 204 0\n"
"gpr acc0 .32 208 0\n"
"gpr acc1 .32 212 0\n"
"gpr acc2 .32 216 0\n"
"gpr acc3 .32 220 0\n"
"gpr accext01 .32 224 0\n"
"gpr accext23 .32 228 0\n"
"gpr macsr .32 232 0\n"
"gpr mask .32 236 0\n"
"gpr usp .32 240 0\n" // user stack point this is an shadow register of A7 user mode, SR bit 0xD is 0
"fpu fp0 .80 244 0\n" // FPU data register 0, 80-bit extended precision
"fpu fp1 .80 254 0\n" // FPU data register 1, 80-bit extended precision
"fpu fp2 .80 264 0\n" // FPU data register 2, 80-bit extended precision
"fpu fp3 .80 274 0\n" // FPU data register 3, 80-bit extended precision
"fpu fp4 .80 284 0\n" // FPU data register 4, 80-bit extended precision
"fpu fp5 .80 294 0\n" // FPU data register 5, 80-bit extended precision
"fpu fp6 .80 304 0\n" // FPU data register 6, 80-bit extended precision
"fpu fp7 .80 314 0\n" // FPU data register 7, 80-bit extended precision
"gpr cp_external_data .32 324 0\n";
return rz_str_dup(p);
}
@@ -1446,9 +1707,9 @@ static bool m68k_fini(void *user) {
static int m68k_archinfo(RzAnalysis *a, RzAnalysisInfoType query) {
switch (query) {
case RZ_ANALYSIS_ARCHINFO_MIN_OP_SIZE:
return 2;
return M68K_MIN_OP_SIZE;
case RZ_ANALYSIS_ARCHINFO_MAX_OP_SIZE:
return M68K_LONGEST_INSTRUCTION;
return M68K_MAX_OP_SIZE;
case RZ_ANALYSIS_ARCHINFO_TEXT_ALIGN:
return 2;
case RZ_ANALYSIS_ARCHINFO_DATA_ALIGN:
@@ -1472,6 +1733,7 @@ RzAnalysisPlugin rz_analysis_plugin_m68k_cs = {
.init = m68k_init,
.fini = m68k_fini,
.archinfo = m68k_archinfo,
.il_config = rz_m68k_cs_il_config,
};
#else
librz/arch/p/asm/asm_m68k_cs.c
+32 -40
View File
@@ -11,28 +11,34 @@
CAPSTONE_DEFINE_PLUGIN_FUNCTIONS(m68k_asm);
static int m68k_set_invalid(RzAsmOp *op, int size) {
op->size = size;
rz_asm_op_set_asm(op, "invalid");
return size;
}
static int m68k_disassemble(const RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) {
if (!buf) {
if (!buf || !op) {
return -1;
}
CapstoneContext *ctx = (CapstoneContext *)a->plugin_data;
char *buf_asm = NULL;
cs_insn *insn = NULL;
int ret = 0, n = 0;
size_t count = 0;
int op_size = -1;
cs_mode mode = rz_m68k_cs_mode(a->cpu);
if (op) {
op->size = 4;
}
if (mode != ctx->omode) {
cs_close(&ctx->handle);
ctx->handle = 0;
ctx->omode = -1;
}
if (len < M68K_MIN_OP_SIZE) {
goto beach;
}
if (!ctx->handle) {
ret = cs_open(CS_ARCH_M68K, mode, &ctx->handle);
if (ret) {
ret = -1;
if (cs_open(CS_ARCH_M68K, mode, &ctx->handle) != CS_ERR_OK) {
goto beach;
}
ctx->omode = mode;
@@ -43,44 +49,30 @@ static int m68k_disassemble(const RzAsm *a, RzAsmOp *op, const ut8 *buf, int len
cs_option(ctx->handle, CS_OPT_DETAIL, CS_OPT_OFF);
}
if (len > M68K_LONGEST_INSTRUCTION) {
len = M68K_LONGEST_INSTRUCTION;
}
n = cs_disasm(ctx->handle, buf, len, a->pc, 1, &insn);
if (n < 1) {
ret = -1;
count = cs_disasm(ctx->handle, buf, len, a->pc, 1, &insn);
if (count < 1 || !insn) {
op_size = m68k_set_invalid(op, M68K_MIN_OP_SIZE);
goto beach;
}
if (op) {
op->size = 0;
}
if (insn->size < 1) {
ret = -1;
if (insn->id == M68K_INS_INVALID || insn->size < 1) {
op_size = m68k_set_invalid(op, insn->size > 0 ? insn->size : M68K_MIN_OP_SIZE);
goto beach;
}
if (op && !op->size) {
op->size = insn->size;
buf_asm = rz_str_newf("%s%s%s", insn->mnemonic, insn->op_str[0] ? " " : "", insn->op_str);
}
if (op && buf_asm) {
buf_asm = rz_str_replace(buf_asm, "$", "0x", true);
if (buf_asm) {
rz_str_replace_char(buf_asm, '#', 0);
rz_asm_op_set_asm(op, buf_asm);
}
}
cs_free(insn, n);
beach:
if (op && buf_asm) {
if (!strncmp(buf_asm, "dc.w", 4)) {
rz_asm_op_set_asm(op, "invalid");
}
ret = op->size;
op_size = insn->size;
buf_asm = rz_str_newf("%s%s%s", insn->mnemonic, insn->op_str[0] ? " " : "", insn->op_str);
if (!buf_asm) {
goto beach;
}
buf_asm = rz_str_replace(buf_asm, "$", "0x", true);
rz_str_replace_char(buf_asm, '#', '\0');
rz_asm_op_set_asm(op, buf_asm);
free(buf_asm);
return ret;
beach:
op->size = op_size;
if (insn) {
cs_free(insn, count);
}
return op_size;
}
static char **m68k_cpu_descriptions() {
librz/core/cfile.c
+9
View File
@@ -103,6 +103,12 @@ static void loadGP(RzCore *core) {
}
}
static void sync_m68k_core_usp(RzCore *core, RzReg *reg) {
if (rz_asm_is_arch(core->rasm, "m68k")) {
rz_reg_setv(reg, "usp", rz_reg_getv(reg, "a7"));
}
}
static RZ_OWN RzPVector /*<RzBinSection *>*/ *__save_old_sections(RzCore *core) {
RzBinObject *obj = rz_bin_cur_object(core->bin);
const RzPVector *sections = obj ? rz_bin_object_get_sections_all(obj) : NULL;
@@ -1161,12 +1167,15 @@ RZ_API bool rz_core_bin_load(RZ_NONNULL RzCore *r, RZ_NULLABLE const char *filen
if (rz_reg_arena_set_bytes(rreg, binfile->o->regstate)) {
RZ_LOG_WARN("Setting up coredump: Problem while setting the registers\n");
} else {
sync_m68k_core_usp(r, rreg);
RZ_LOG_INFO("Setting up coredump: Registers have been set\n");
}
if (!RZ_STR_ISEMPTY(rreg->reg_profile_str)) {
rz_reg_set_profile_string(r->dbg->reg, rreg->reg_profile_str);
if (binfile->o->regstate && rz_reg_arena_set_bytes(r->dbg->reg, binfile->o->regstate)) {
RZ_LOG_WARN("Setting up coredump: Problem while setting debug registers\n");
} else {
sync_m68k_core_usp(r, r->dbg->reg);
}
}
}
meson.build
+20
View File
@@ -245,6 +245,26 @@ if has_capstone_m68k_coldfire
add_project_arguments(['-DRZ_CAPSTONE_HAS_M68K_COLDFIRE'], language: 'c')
endif
has_capstone_m68k_fp_formats = cc.compiles('''
#include <capstone/capstone.h>
#include <capstone/m68k.h>
int main(void) {
m68k_op_fp_extended extended = { 0 };
m68k_op_fp_packed packed = { 0 };
m68k_op_type extended_type = M68K_OP_FP_EXTENDED;
m68k_op_type packed_type = M68K_OP_FP_PACKED;
m68k_fpu_size packed_size = M68K_FPU_SIZE_PACKED;
return extended.sign_exp + packed.header + extended_type + packed_type + packed_size;
}
''',
dependencies: capstone_check_deps,
include_directories: capstone_check_includes,
name: 'Capstone has M68K extended and packed FP operand formats'
)
if has_capstone_m68k_fp_formats
add_project_arguments(['-DRZ_CAPSTONE_HAS_M68K_FP_FORMATS'], language: 'c')
endif
# Handle PCRE2
cpu_jit_supported = [ 'aarch64', 'arm', 'mips', 'mips64', 'ppc', 'ppc64', 'riscv32', 'riscv64', 's390x', 'x86', 'x86_64' ]
pcre2_jit_supported = target_machine.cpu_family() in cpu_jit_supported and cc.get_id() != 'tcc' and target_machine.system() not in ['darwin', 'serenity']
test/db/analysis/m68k
+790 -1587
View File
File diff suppressed because it is too large Load Diff
test/db/asm/m68k_68000_32
+1989 -4
View File
File diff suppressed because one or more lines are too long
test/db/asm/m68k_68010_32
+127
View File
@@ -0,0 +1,127 @@
d "ori.w 0x0, d0" 00400000 0x0 (seq (set src (bv 16 0x0)) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "andi.w 0x0, d0" 02400000 0x0 (seq (set src (bv 16 0x0)) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "subi.w 0x0, d0" 04400000 0x0 (seq (set src (bv 16 0x0)) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false)))))))
d "addi.w 0x0, d0" 06400000 0x0 (seq (set src (bv 16 0x0)) (set dst (cast 16 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false)))))))
d "btst.b 0x0, 0x5(pc)" 083a00000001 0x0 (seq (set bit (bv 8 0x0)) (set dst (loadw 0 8 (bv 32 0x5))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))))
d "btst.b 0x0, 0x5(pc, d0.w)" 083b00000001 0x0 (seq (set bit (bv 8 0x0)) (set dst (loadw 0 8 (+ (bv 32 0x5) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (& (cast 8 false (var sr)) (bv 8 0xfb)) (bv 8 0xfb)) (<< (ite (! (! (is_zero (& (var dst) (<< (bv 8 0x1) (cast 8 false (mod (cast 8 false (var bit)) (bv 8 0x8))) false))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)))))))
d "eori.w 0x0, d0" 0a400000 0x0 (seq (set src (bv 16 0x0)) (set dst (cast 16 false (var d0))) (set res (^ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "cmpi.b 0x0, 0x5(pc)" 0c3a00000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (bv 32 0x5))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "cmpi.b 0x0, 0x5(pc, d0.w)" 0c3b00000001 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (bv 32 0x5) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "cmpi.b 0xff, 0x4(pc, d0.w)" 0c3b00ff0100 0x0 (seq (set src (bv 8 0xff)) (set dst_addr (cast 32 false (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "cmpi.b 0x0, ([0x1800203, pc], 0x8000fff)" 0c3b0100017f018001ff08000fff 0x0 (seq (set src (bv 8 0x0)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x1800201))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 8 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "cmpi.w 0x0, d0" 0c400000 0x0 (seq (set src (bv 16 0x0)) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "cmpi.w 0x0, 0x5(pc)" 0c7a00000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (bv 32 0x5))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "cmpi.w 0x0, 0x5(pc, d0.w)" 0c7b00000001 0x0 (seq (set src (bv 16 0x0)) (set dst_addr (cast 32 false (+ (bv 32 0x5) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "cmpi.w 0xff, 0x4(pc, d0.w)" 0c7b00ff0100 0x0 (seq (set src (bv 16 0xff)) (set dst_addr (cast 32 false (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "cmpi.w 0x100, ([0x1800203, pc], 0x8000fff)" 0c7b0100017f018001ff08000fff 0x0 (seq (set src (bv 16 0x100)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x1800201))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 16 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "cmpi.l 0x1, 0x16(pc)" 0cba000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (bv 32 0x16))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "cmpi.l 0x1, 0x16(pc, d0.w)" 0cbb000000010010 0x0 (seq (set src (bv 32 0x1)) (set dst_addr (cast 32 false (+ (bv 32 0x16) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "cmpi.l 0x8000ff, 0x6(pc, d0.w)" 0cbb008000ff0100 0x0 (seq (set src (bv 32 0x8000ff)) (set dst_addr (cast 32 false (+ (bv 32 0x6) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "cmpi.l 0xff0100, ([0x1800205, pc], 0x8000fff)" 0cbb00ff0100017f018001ff08000fff 0x0 (seq (set src (bv 32 0xff0100)) (set dst_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x1800203))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set dst (loadw 0 32 (var dst_addr))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "moves.b (a0), d0" 0e100000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 8 (cast 32 false (var a0)))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.b d0, (a0)" 0e100800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 8 false (var d0))) (storew 0 (cast 32 false (var a0)) (cast 8 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.b (a0)+, d0" 0e180000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 8 (cast 32 false (var a0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.b d0, (a0)+" 0e180800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 8 false (var d0))) (storew 0 (cast 32 false (var a0)) (cast 8 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.b -(a0), d0" 0e200000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (cast 32 false (var a0)))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.b d0, -(a0)" 0e200800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 8 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (storew 0 (cast 32 false (var a0)) (cast 8 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.b 0x1(a0), d0" 0e2800000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 8 (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1)))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.b d0, 0xfff(a0)" 0e2808000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 8 false (var d0))) (storew 0 (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xfff)))) (cast 8 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.b 0x1(a0, d0.w), d0" 0e3000000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 8 (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.b d0, ([0x10001fff], 0x20002fff)" 0e3008000fff10001fff20002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 8 false (var d0))) (storew 0 (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff))) (cast 8 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.b ([0x20002fff], 0x30003fff), d1" 0e3010001fff20002fff30003fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 8 (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20002fff))) (bv 32 0x0)) (bv 32 0x30003fff))))) (set d1 (| (& (var d1) (bv 32 0xffffff00)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.b (a0, a0.w), a0" 0e3080008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 8 (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))))))) (set a0 (cast 32 false (cast 32 (msb (var src)) (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.b 0x1.w, d0" 0e3800000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 8 (cast 32 false (bv 32 0x1)))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.b d0, 0xfff.w" 0e3808000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 8 false (var d0))) (storew 0 (cast 32 false (bv 32 0xfff)) (cast 8 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.b 0x10010.l, d0" 0e39000000010010 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 8 (cast 32 false (bv 32 0x10010)))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.b d0, 0xfff1000.l" 0e3908000fff1000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 8 false (var d0))) (storew 0 (cast 32 false (bv 32 0xfff1000)) (cast 8 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.w (a0), d0" 0e500000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 16 (cast 32 false (var a0)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.w d0, (a0)" 0e500800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 16 false (var d0))) (storew 0 (cast 32 false (var a0)) (cast 16 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.w (a0)+, d0" 0e580000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 16 (cast 32 false (var a0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.w d0, (a0)+" 0e580800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 16 false (var d0))) (storew 0 (cast 32 false (var a0)) (cast 16 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.w -(a0), d0" 0e600000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (cast 32 false (var a0)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.w d0, -(a0)" 0e600800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 16 false (var d0))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (storew 0 (cast 32 false (var a0)) (cast 16 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.w 0x1(a0), d0" 0e6800000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 16 (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1)))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.w d0, 0xfff(a0)" 0e6808000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 16 false (var d0))) (storew 0 (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xfff)))) (cast 16 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.w 0x1(a0, d0.w), d0" 0e7000000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 16 (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.w d0, ([0x10001fff], 0x20002fff)" 0e7008000fff10001fff20002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 16 false (var d0))) (storew 0 (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff))) (cast 16 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.w ([0x20002fff], 0x30003fff), d1" 0e7010001fff20002fff30003fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 16 (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20002fff))) (bv 32 0x0)) (bv 32 0x30003fff))))) (set d1 (| (& (var d1) (bv 32 0xffff0000)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.w (a0, a0.w), a0" 0e7080008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 16 (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))))))) (set a0 (cast 32 false (cast 32 (msb (var src)) (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.w 0x1.w, d0" 0e7800000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 16 (cast 32 false (bv 32 0x1)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.w d0, 0xfff.w" 0e7808000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 16 false (var d0))) (storew 0 (cast 32 false (bv 32 0xfff)) (cast 16 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.w 0x10010.l, d0" 0e79000000010010 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 16 (cast 32 false (bv 32 0x10010)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var src))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.w d0, 0xfff1000.l" 0e7908000fff1000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 16 false (var d0))) (storew 0 (cast 32 false (bv 32 0xfff1000)) (cast 16 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.l (a0), d0" 0e900000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 32 (cast 32 false (var a0)))) (set d0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.l d0, (a0)" 0e900800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var d0)) (storew 0 (cast 32 false (var a0)) (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.l (a0)+, d0" 0e980000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 32 (cast 32 false (var a0)))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set d0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.l d0, (a0)+" 0e980800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var d0)) (storew 0 (cast 32 false (var a0)) (cast 32 false (var src))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4))))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.l -(a0), d0" 0ea00000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (cast 32 false (var a0)))) (set d0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.l d0, -(a0)" 0ea00800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var d0)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (storew 0 (cast 32 false (var a0)) (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.l 0x1(a0), d0" 0ea800000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 32 (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1)))))) (set d0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.l d0, 0xfff(a0)" 0ea808000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var d0)) (storew 0 (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xfff)))) (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.l 0x1(a0, d0.w), d0" 0eb000000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 32 (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))))))) (set d0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.l d0, ([0x10001fff], 0x20002fff)" 0eb008000fff10001fff20002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var d0)) (storew 0 (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff))) (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.l ([0x20002fff], 0x30003fff), d1" 0eb010001fff20002fff30003fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 32 (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20002fff))) (bv 32 0x0)) (bv 32 0x30003fff))))) (set d1 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.l (a0, a0.w), a0" 0eb080008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 32 (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0))))))) (set a0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.l 0x1.w, d0" 0eb800000001 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 32 (cast 32 false (bv 32 0x1)))) (set d0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.l d0, 0xfff.w" 0eb808000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var d0)) (storew 0 (cast 32 false (bv 32 0xfff)) (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.l 0x10010.l, d0" 0eb9000000010010 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (loadw 0 32 (cast 32 false (bv 32 0x10010)))) (set d0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "moves.l d0, 0xfff1000.l" 0eb908000fff1000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var d0)) (storew 0 (cast 32 false (bv 32 0xfff1000)) (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "move.l 0x1.l, d0" 203900000001 0x0 (seq (set src (loadw 0 32 (bv 32 0x1))) (set d0 (cast 32 false (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var src))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "lea.l 0x0(a0), a0" 41e80000 0x0 (set a0 (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0)))))
d "bkpt 0x0" 4848 0x0 (seq (set trap_op (bv 32 0x1)) (set trap_arg (bv 32 0x0)) (goto m68k_trap))
d "pea.l 0x0(a0)" 48680000 0x0 (seq (set push_value (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0)))) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))))
d "link.w a0, 0x0" 4e500000 0x0 (seq (set push_value (var a0)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (set a0 (cast 32 false (var a7))) (set new_sp (+ (var a7) (bv 32 0x0))) (set a7 (cast 32 false (var new_sp))))
d "unlk a0" 4e58 0x0 (seq (set a7 (cast 32 false (var a0))) (set old (loadw 0 32 (var a7))) (set a7 (cast 32 false (+ (var a7) (bv 32 0x4)))) (set a0 (cast 32 false (var old))))
d "rtd 0x0" 4e740000 0x0 (seq (set target (loadw 0 32 (var a7))) (set a7 (cast 32 false (+ (var a7) (bv 32 0x4)))) (jmp (var target)))
d "movec sfc, d0" 4e7a0000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (set d0 (cast 32 false (var sfc))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "jsr 0x1.l" 4eb900000001 0x0 (seq (set target (bv 32 0x1)) (set push_value (bv 32 0x6)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (var target)))
d "addq.w 0x8, d0" 5040 0x0 (seq (set src (bv 16 0x8)) (set dst (cast 16 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false)))))))
d "dbt d0, 0x2" 50c80000 0x0 (branch true empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty)))
d "subq.w 0x8, d0" 5140 0x0 (seq (set src (bv 16 0x8)) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false)))))))
d "dbra d0, 0x2" 51c80000 0x0 (branch false empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty)))
d "dbhi d0, 0x2" 52c80000 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty)))
d "dbls d0, 0x2" 53c80000 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty)))
d "dbcc d0, 0x2" 54c80000 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty)))
d "dbcs d0, 0x2" 55c80000 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty)))
d "dbne d0, 0x2" 56c80000 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty)))
d "dbeq d0, 0x2" 57c80000 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty)))
d "dbvc d0, 0x2" 58c80000 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty)))
d "dbvs d0, 0x2" 59c80000 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty)))
d "dbpl d0, 0x2" 5ac80000 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty)))
d "dbmi d0, 0x2" 5bc80000 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty)))
d "dbge d0, 0x2" 5cc80000 0x0 (branch (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty)))
d "dblt d0, 0x2" 5dc80000 0x0 (branch (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty)))
d "dbgt d0, 0x2" 5ec80000 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty)))
d "dble d0, 0x2" 5fc80000 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))))) empty (seq (set dec (- (cast 16 false (var d0)) (bv 16 0x1))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var dec)))) (branch (! (== (var dec) (bv 16 0xffff))) (jmp (bv 32 0x2)) empty)))
d "bra.b 0x3" 6001 0x0 (jmp (bv 32 0x3))
d "bsr.b 0x3" 6101 0x0 (seq (set push_value (bv 32 0x2)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (bv 32 0x3)))
d "bhi.b 0x3" 6201 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))))) (jmp (bv 32 0x3)) empty)
d "bls.b 0x3" 6301 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (jmp (bv 32 0x3)) empty)
d "bcc.b 0x3" 6401 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1))))) (jmp (bv 32 0x3)) empty)
d "bcs.b 0x3" 6501 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x1)))) (jmp (bv 32 0x3)) empty)
d "bne.b 0x3" 6601 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (jmp (bv 32 0x3)) empty)
d "beq.b 0x3" 6701 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (jmp (bv 32 0x3)) empty)
d "bvc.b 0x3" 6801 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2))))) (jmp (bv 32 0x3)) empty)
d "bvs.b 0x3" 6901 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (jmp (bv 32 0x3)) empty)
d "bpl.b 0x3" 6a01 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8))))) (jmp (bv 32 0x3)) empty)
d "bmi.b 0x3" 6b01 0x0 (branch (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (jmp (bv 32 0x3)) empty)
d "bge.b 0x3" 6c01 0x0 (branch (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))) (jmp (bv 32 0x3)) empty)
d "blt.b 0x3" 6d01 0x0 (branch (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (jmp (bv 32 0x3)) empty)
d "bgt.b 0x3" 6e01 0x0 (branch (&& (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0)))) (jmp (bv 32 0x3)) empty)
d "ble.b 0x3" 6f01 0x0 (branch (|| (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4)))) (! (== (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x8)))) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (bv 1 0x1) (bv 1 0x0))))) (jmp (bv 32 0x3)) empty)
d "moveq 0x0, d0" 7000 0x0 (seq (set res (bv 32 0x0)) (set d0 (cast 32 false (bv 32 0x0))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "or.w d0, d0" 8040 0x0 (seq (set src (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set res (| (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "sub.w d0, d0" 9040 0x0 (seq (set src (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false)))))))
d "cmp.w d0, d0" b040 0x0 (seq (set src (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set res (- (var dst) (var src))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "eor.w d0, d0" b140 0x0 (seq (set src (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set res (^ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "and.w d0, d0" c040 0x0 (seq (set src (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set res (& (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mulu.w d0, d0" c0c0 0x0 (seq (set src (cast 16 false (var d0))) (set res (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src)))) (set d0 (cast 32 false (* (cast 32 false (cast 16 false (var d0))) (cast 32 false (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "muls.w d0, d0" c1c0 0x0 (seq (set src (cast 16 false (var d0))) (set res (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src)))) (set d0 (cast 32 false (* (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0))) (cast 32 (msb (var src)) (var src))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "add.w d0, d0" d040 0x0 (seq (set src (cast 16 false (var d0))) (set dst (cast 16 false (var d0))) (set res (+ (var dst) (var src))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false)))))))
d "asr.w 0x8, d0" e040 0x0 (seq (set count (bv 16 0x8)) (set dst (cast 16 false (var d0))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) (msb (var dst)))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (|| (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (msb (var dst))) (&& (&& (ule (var count8) (bv 8 0x10)) (! (== (var count8) (bv 8 0x10)))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false)))))))
d "lsr.w 0x8, d0" e048 0x0 (seq (set count (bv 16 0x8)) (set dst (cast 16 false (var d0))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (>> (var dst) (var count8) false)) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (var count8) (bv 8 0x1)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false)))))))
d "asl.w 0x8, d0" e140 0x0 (seq (set count (bv 16 0x8)) (set dst (cast 16 false (var d0))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (<< (var dst) (var count8) false)) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| (|| false (&& (|| (! (ule (var count8) (bv 8 0x1))) (== (var count8) (bv 8 0x1))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0xe) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x2))) (== (var count8) (bv 8 0x2))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0xd) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x3))) (== (var count8) (bv 8 0x3))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0xc) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x4))) (== (var count8) (bv 8 0x4))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0xb) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x5))) (== (var count8) (bv 8 0x5))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0xa) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x6))) (== (var count8) (bv 8 0x6))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x9) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x7))) (== (var count8) (bv 8 0x7))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x8) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x8))) (== (var count8) (bv 8 0x8))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x7) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x9))) (== (var count8) (bv 8 0x9))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x6) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xa))) (== (var count8) (bv 8 0xa))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x5) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xb))) (== (var count8) (bv 8 0xb))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x4) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xc))) (== (var count8) (bv 8 0xc))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x3) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xd))) (== (var count8) (bv 8 0xd))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x2) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xe))) (== (var count8) (bv 8 0xe))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x1) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0xf))) (== (var count8) (bv 8 0xf))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (! (is_zero (& (>> (var dst) (bv 8 0x0) false) (bv 16 0x1)))) (bv 1 0x1) (bv 1 0x0)))))) (&& (|| (! (ule (var count8) (bv 8 0x10))) (== (var count8) (bv 8 0x10))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite false (bv 1 0x1) (bv 1 0x0)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false)))))))
d "lsl.w 0x8, d0" e148 0x0 (seq (set count (bv 16 0x8)) (set dst (cast 16 false (var d0))) (set count8 (& (cast 8 false (var count)) (bv 8 0x3f))) (set res (<< (var dst) (var count8) false)) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (|| (&& (is_zero (var count8)) (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x10))))) (&& (! (is_zero (var count8))) (! (is_zero (& (>> (var dst) (- (bv 8 0x10) (var count8)) false) (bv 16 0x1)))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false)))))))
d "rte" 4e73 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set rte_state (bv 8 0x1)) (set target (bv 32 0x0)) (repeat (== (var rte_state) (bv 8 0x1)) (seq (set frame (var a7)) (set new_sr (loadw 0 16 (var frame))) (set target (loadw 0 32 (+ (var frame) (bv 32 0x2)))) (set format (>> (loadw 0 16 (+ (var frame) (bv 32 0x6))) (bv 8 0xc) false)) (set frame_size (ite (== (var format) (bv 16 0x0)) (bv 32 0x8) (ite (== (var format) (bv 16 0x1)) (bv 32 0x8) (ite (== (var format) (bv 16 0x2)) (bv 32 0xc) (ite (== (var format) (bv 16 0x3)) (bv 32 0xc) (ite (== (var format) (bv 16 0x4)) (bv 32 0x10) (ite (== (var format) (bv 16 0x7)) (bv 32 0x3c) (ite (== (var format) (bv 16 0x8)) (bv 32 0x3a) (ite (== (var format) (bv 16 0x9)) (bv 32 0x14) (ite (== (var format) (bv 16 0xa)) (bv 32 0x20) (bv 32 0x5c))))))))))) (branch (|| (== (var format) (bv 16 0x0)) (== (var format) (bv 16 0x8))) (seq (set a7 (cast 32 false (+ (var frame) (var frame_size)))) (set sr_write_value (cast 16 false (var new_sr))) (branch (! (== (ite (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))) (ite (is_zero (& (var sr_write_value) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))))) (seq (branch (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (set usp (cast 32 false (var a7))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (set msp (cast 32 false (var a7))) (set isp (cast 32 false (var a7))))) (branch (is_zero (& (var sr_write_value) (bv 16 0x2000))) (set a7 (cast 32 false (var usp))) (branch (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (set a7 (cast 32 false (var msp))) (set a7 (cast 32 false (var isp)))))) empty) (set sr (var sr_write_value)) (set rte_state (ite (== (var format) (bv 16 0x1)) (bv 8 0x1) (bv 8 0x0)))) (set rte_state (bv 8 0x2))))) (branch (== (var rte_state) (bv 8 0x0)) (jmp (var target)) (seq (set trap_op (bv 32 0xa)) (set trap_vector (bv 32 0xe)) (goto m68k_trap)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "movem.l a0, -(a0)" 48e00080 0x0 (seq (set addr (var a0)) (set addr (- (var addr) (bv 32 0x4))) (storew 0 (var addr) (cast 32 false (var a0))) (set a0 (cast 32 false (var addr))))
d "rtd 0x4" 4e740004 0x0 (seq (set target (loadw 0 32 (var a7))) (set a7 (cast 32 false (+ (var a7) (bv 32 0x8)))) (jmp (var target)))
test/db/asm/m68k_68020_32
+653 -3
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test/db/asm/m68k_68030_32
+77 -13
View File
@@ -1,13 +1,77 @@
d "pmove (a0), tc" f0104000
d "pmove tc, (a0)" f0104200
d "pmove (a1), srp" f0114800
d "pmove (a2), crp" f0124c00
d "pmove (a0), mmusr" f0106000
d "pmove (a0), tt0" f0100800
d "pmove (a0), tt1" f0100c00
d "pflush sfc, 0x0, (a0)" f0103800
d "pflusha" f0002400
d "ploadw sfc, (a0)" f0102000
d "ploadr sfc, (a0)" f0102200
d "ptestw sfc, (a0), 0x7" f0109c00
d "ptestr sfc, (a0), 0x7" f0109e00
d "bftst 0x1.w{0:32}" e8f800000001 0x0 (seq (set offset (bv 32 0x0)) (set width (bv 32 0x20)) (set base (cast 32 false (bv 32 0x1))) (set byte_offset (div (var offset) (bv 32 0x8))) (set bit_offset (mod (var offset) (bv 32 0x8))) (set bf_addr (+ (var base) (var byte_offset))) (set byte_count (div (+ (+ (var bit_offset) (var width)) (bv 32 0x7)) (bv 32 0x8))) (set container (bv 64 0x0)) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (var bf_addr))) (bv 8 0x38) false))) (branch (! (ule (var byte_count) (bv 32 0x1))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x1)))) (bv 8 0x30) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x2))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x2)))) (bv 8 0x28) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x3))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x3)))) (bv 8 0x20) false))) empty) (branch (! (ule (var byte_count) (bv 32 0x4))) (set container (| (var container) (<< (cast 64 false (loadw 0 8 (+ (var bf_addr) (bv 32 0x4)))) (bv 8 0x18) false))) empty) (set field (& (cast 32 false (>> (var container) (- (bv 8 0x40) (cast 8 false (+ (var bit_offset) (var width)))) false)) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (! (is_zero (& (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1)))) (<< (bv 32 0x1) (cast 8 false (- (var width) (bv 32 0x1))) false)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (& (var field) (cast 32 false (- (<< (bv 64 0x1) (cast 8 false (var width)) false) (bv 64 0x1))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "pmove d0, tt0" f0000800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var d0)) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ploadw sfc, d0" f0002000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var d0))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflusha" f0002400 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_flush_all (bv 32 0x1)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush sfc, 0x0, d0" f0003000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var d0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush 0xf, 0x7, d0" f0003fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var d0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmove a0, tt0" f0080800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var a0)) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ploadw sfc, a0" f0082000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush sfc, 0x0, a0" f0083000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush 0xf, 0x7, a0" f0083fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ptestw sfc, a0, 0x0" f0088000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmove (a0), tt0" f0100800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 32 (var mmu_addr))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmove (a0), tt1" f0100c00 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 32 (var mmu_addr))) (set tt1 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ploadw sfc, (a0)" f0102000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ploadr sfc, (a0)" f0102200 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x0)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush sfc, 0x0, (a0)" f0103800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush 0xf, 0x7, (a0)" f0103fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmove (a0), tc" f0104000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 32 (var mmu_addr))) (set tc (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmovefd (a0), tc" f0104100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 32 (var mmu_addr))) (set tc (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmove tc, (a0)" f0104200 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (var tc)) (storew 0 (var mmu_addr) (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmovefd tc, (a0)" f0104300 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (var tc)) (storew 0 (var mmu_addr) (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmovefd (a0), srp" f0104900 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 64 (var mmu_addr))) (set srp (cast 64 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmovefd srp, (a0)" f0104b00 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (var srp)) (storew 0 (var mmu_addr) (cast 64 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmovefd (a0), crp" f0104d00 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 64 (var mmu_addr))) (set crp (cast 64 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmovefd crp, (a0)" f0104f00 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (var crp)) (storew 0 (var mmu_addr) (cast 64 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmove (a0), mmusr" f0106000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 16 (var mmu_addr))) (set mmusr (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ptestw sfc, (a0), 0x7" f0109c00 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ptestr sfc, (a0), 0x7" f0109e00 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmove (a1), srp" f0114800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a1))) (set src (loadw 0 64 (var mmu_addr))) (set srp (cast 64 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmove (a2), crp" f0124c00 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a2))) (set src (loadw 0 64 (var mmu_addr))) (set crp (cast 64 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmove (a0)+, tt0" f0180800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 32 (var mmu_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ploadw sfc, (a0)+" f0182000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush sfc, 0x0, (a0)+" f0183000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush 0xf, 0x7, (a0)+" f0183fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ptestw sfc, (a0)+, 0x0" f0188000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmove -(a0), tt0" f0200800 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mmu_addr (cast 32 false (var a0))) (set src (loadw 0 32 (var mmu_addr))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ploadw sfc, -(a0)" f0202000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush sfc, 0x0, -(a0)" f0203000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush 0xf, 0x7, -(a0)" f0203fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ptestw sfc, -(a0), 0x0" f0208000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmove 0xfff(a0), tt0" f02808000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xfff))))) (set src (loadw 0 32 (var mmu_addr))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ploadw sfc, 0x2fff(a0)" f02820002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x2fff))))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush sfc, 0x0, 0x3fff(a0)" f02830003fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x3fff))))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush 0xf, 0x7, 0x4000(a0)" f0283fff4000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x4000))))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ptestw sfc, -0x7f00(a0), 0x0" f02880008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmove ([0x10001fff], 0x20002fff), tt0" f03008000fff10001fff20002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10001fff))) (bv 32 0x0)) (bv 32 0x20002fff)))) (set src (loadw 0 32 (var mmu_addr))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ploadw sfc, ([0x30003fff], 0x40004fff)" f03020002fff30003fff40004fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x30003fff))) (bv 32 0x0)) (bv 32 0x40004fff)))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush sfc, 0x0, ([0x40004fff], 0x50005fff)" f03030003fff40004fff50005fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x40004fff))) (bv 32 0x0)) (bv 32 0x50005fff)))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush 0xf, 0x7, 0x0(a0, d4.w)" f0303fff4000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4)))))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ptestw sfc, (a0, a0.w), 0x0" f03080008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0)))))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmove 0xfff.w, tt0" f03808000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0xfff))) (set src (loadw 0 32 (var mmu_addr))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ploadw sfc, 0x2fff.w" f03820002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x2fff))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush sfc, 0x0, 0x3fff.w" f03830003fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x3fff))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush 0xf, 0x7, 0x4000.w" f0383fff4000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x4000))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ptestw sfc, 0x8100.w, 0x0" f03880008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0xffff8100))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmove 0xfff1000.l, tt0" f03908000fff1000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0xfff1000))) (set src (loadw 0 32 (var mmu_addr))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ploadw sfc, 0x2fff3000.l" f03920002fff3000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x2fff3000))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush sfc, 0x0, 0x3fff4000.l" f03930003fff4000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x3fff4000))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush 0xf, 0x7, 0x40004fff.l" f0393fff40004fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x40004fff))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ptestw sfc, 0x81008170.l, 0x0" f039800081008170 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x81008170))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmove 0x1003(pc), tt0" f03a08000fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x1003))) (set src (loadw 0 32 (var mmu_addr))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ploadw sfc, 0x3003(pc)" f03a20002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x3003))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush sfc, 0x0, 0x4003(pc)" f03a30003fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x4003))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush 0xf, 0x7, 0x4004(pc)" f03a3fff4000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0x4004))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ptestw sfc, 0xffff8104(pc), 0x0" f03a80008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (bv 32 0xffff8104))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmove ([0x10002003], 0x20002fff), tt0" f03b08000fff10001fff20002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x10002001))) (bv 32 0x0)) (bv 32 0x20002fff)))) (set src (loadw 0 32 (var mmu_addr))) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ploadw sfc, ([0x30004003], 0x40004fff)" f03b20002fff30003fff40004fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x30004001))) (bv 32 0x0)) (bv 32 0x40004fff)))) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush sfc, 0x0, ([0x40005003], 0x50005fff)" f03b30003fff40004fff50005fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x40005001))) (bv 32 0x0)) (bv 32 0x50005fff)))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush 0xf, 0x7, 0x4(pc, d4.w)" f03b3fff4000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var d4))) (cast 16 false (var d4)))))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ptestw sfc, 0x4(pc, a0.w), 0x0" f03b80008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (+ (bv 32 0x4) (cast 32 (msb (cast 16 false (var a0))) (cast 16 false (var a0)))))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pmove 0xfff1000, tt0" f03c08000fff1000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (bv 32 0xfff1000)) (set tt0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ploadw sfc, 0xff" f03c20002fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (bv 32 0xff)) (set mmu_op (bv 32 0x0)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush sfc, 0x0, 0xff" f03c30003fff 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (bv 32 0xff)) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (var sfc)) (set mmu_mask (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush 0xf, 0x7, 0x0" f03c3fff4000 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (bv 32 0x0)) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_fc (bv 32 0xf)) (set mmu_mask (bv 32 0x7)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ptestw sfc, 0x0, 0x0" f03c80008100 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (bv 32 0x0)) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (set mmu_fc (var sfc)) (set mmu_level (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "rte" 4e73 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set rte_state (bv 8 0x1)) (set target (bv 32 0x0)) (repeat (== (var rte_state) (bv 8 0x1)) (seq (set frame (var a7)) (set new_sr (loadw 0 16 (var frame))) (set target (loadw 0 32 (+ (var frame) (bv 32 0x2)))) (set format (>> (loadw 0 16 (+ (var frame) (bv 32 0x6))) (bv 8 0xc) false)) (set frame_size (ite (== (var format) (bv 16 0x0)) (bv 32 0x8) (ite (== (var format) (bv 16 0x1)) (bv 32 0x8) (ite (== (var format) (bv 16 0x2)) (bv 32 0xc) (ite (== (var format) (bv 16 0x3)) (bv 32 0xc) (ite (== (var format) (bv 16 0x4)) (bv 32 0x10) (ite (== (var format) (bv 16 0x7)) (bv 32 0x3c) (ite (== (var format) (bv 16 0x8)) (bv 32 0x3a) (ite (== (var format) (bv 16 0x9)) (bv 32 0x14) (ite (== (var format) (bv 16 0xa)) (bv 32 0x20) (bv 32 0x5c))))))))))) (branch (|| (&& (ule (var format) (bv 16 0x3)) (! (== (var format) (bv 16 0x3)))) (&& (|| (! (ule (var format) (bv 16 0x9))) (== (var format) (bv 16 0x9))) (&& (ule (var format) (bv 16 0xc)) (! (== (var format) (bv 16 0xc)))))) (seq (set a7 (cast 32 false (+ (var frame) (var frame_size)))) (set sr_write_value (cast 16 false (var new_sr))) (branch (! (== (ite (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x1000)))) (bv 8 0x2) (bv 8 0x1))) (ite (is_zero (& (var sr_write_value) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (var sr_write_value) (bv 16 0x1000)))) (bv 8 0x2) (bv 8 0x1))))) (seq (branch (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (set usp (cast 32 false (var a7))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x1000)))) (set msp (cast 32 false (var a7))) (set isp (cast 32 false (var a7))))) (branch (is_zero (& (var sr_write_value) (bv 16 0x2000))) (set a7 (cast 32 false (var usp))) (branch (! (is_zero (& (var sr_write_value) (bv 16 0x1000)))) (set a7 (cast 32 false (var msp))) (set a7 (cast 32 false (var isp)))))) empty) (set sr (var sr_write_value)) (set rte_state (ite (== (var format) (bv 16 0x1)) (bv 8 0x1) (bv 8 0x0)))) (set rte_state (bv 8 0x2))))) (branch (== (var rte_state) (bv 8 0x0)) (jmp (var target)) (seq (set trap_op (bv 32 0xa)) (set trap_vector (bv 32 0xe)) (goto m68k_trap)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "movem.l a0, -(a0)" 48e00080 0x0 (seq (set addr (var a0)) (set addr (- (var addr) (bv 32 0x4))) (storew 0 (var addr) (cast 32 false (cast 32 false (- (var a0) (bv 32 0x4))))) (set a0 (cast 32 false (var addr))))
test/db/asm/m68k_68040_32
+44
View File
@@ -0,0 +1,44 @@
d "add fp0" f200007f
d "add fp0, fp1" f20000ff
d "fsmove fp1, fp2" f2000540
d "fssqrt fp1, fp2" f2000541
d "fdmove fp1, fp2" f2000544
d "fdsqrt fp1, fp2" f2000545
d "fsabs fp1, fp2" f2000558
d "fsneg fp1, fp2" f200055a
d "fdabs fp1, fp2" f200055c
d "fdneg fp1, fp2" f200055e
d "fsdiv fp1, fp2" f2000560
d "fsadd fp1, fp2" f2000562
d "fsmul fp1, fp2" f2000563
d "fddiv fp1, fp2" f2000564
d "fdadd fp1, fp2" f2000566
d "fdmul fp1, fp2" f2000567
d "fssub fp1, fp2" f2000568
d "fdsub fp1, fp2" f200056c
d "cinvl nc, (a0)" f408 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set cache_addr (cast 32 false (var a0))) (set cache_op (bv 32 0x1)) (set cache_selector (bv 32 0x0)) (goto m68k_cache)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "cinvp nc, (a0)" f410 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set cache_addr (cast 32 false (var a0))) (set cache_op (bv 32 0x1)) (set cache_selector (bv 32 0x0)) (goto m68k_cache)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "cinva nc" f418 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set cache_op (bv 32 0x1)) (set cache_selector (bv 32 0x0)) (set cache_all (bv 32 0x1)) (goto m68k_cache)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "cpushp nc, (a0)" f430 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set cache_addr (cast 32 false (var a0))) (set cache_op (bv 32 0x2)) (set cache_selector (bv 32 0x0)) (goto m68k_cache)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "cpusha nc" f438 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set cache_op (bv 32 0x2)) (set cache_selector (bv 32 0x0)) (set cache_all (bv 32 0x1)) (goto m68k_cache)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "cpushl dc, (a0)" f468 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set cache_addr (cast 32 false (var a0))) (set cache_op (bv 32 0x2)) (set cache_selector (bv 32 0x1)) (goto m68k_cache)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflushn (a0)" f500 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x1)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflush (a0)" f508 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflushan" f510 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x1)) (set mmu_flush_all (bv 32 0x1)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pflusha" f518 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_op (bv 32 0x1)) (set mmu_flush_non_global (bv 32 0x0)) (set mmu_flush_all (bv 32 0x1)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ptestw (a0)" f548 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x1)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "ptestr (a0)" f568 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x2)) (set mmu_rw (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "move16 (a0)+, 0x1.l" f60000000001 0x0 (seq (set src_addr (var a0)) (set dst_addr (cast 32 false (bv 32 0x1))) (set src_line (& (var src_addr) (bv 32 0xfffffff0))) (set dst_line (& (var dst_addr) (bv 32 0xfffffff0))) (set word0 (loadw 0 32 (var src_line))) (set word1 (loadw 0 32 (+ (var src_line) (bv 32 0x4)))) (set word2 (loadw 0 32 (+ (var src_line) (bv 32 0x8)))) (set word3 (loadw 0 32 (+ (var src_line) (bv 32 0xc)))) (storew 0 (var dst_line) (cast 32 false (var word0))) (storew 0 (+ (var dst_line) (bv 32 0x4)) (cast 32 false (var word1))) (storew 0 (+ (var dst_line) (bv 32 0x8)) (cast 32 false (var word2))) (storew 0 (+ (var dst_line) (bv 32 0xc)) (cast 32 false (var word3))) (set a0 (cast 32 false (+ (var src_addr) (bv 32 0x10)))))
d "move16 0x1.l, (a0)+" f60800000001 0x0 (seq (set src_addr (cast 32 false (bv 32 0x1))) (set dst_addr (var a0)) (set src_line (& (var src_addr) (bv 32 0xfffffff0))) (set dst_line (& (var dst_addr) (bv 32 0xfffffff0))) (set word0 (loadw 0 32 (var src_line))) (set word1 (loadw 0 32 (+ (var src_line) (bv 32 0x4)))) (set word2 (loadw 0 32 (+ (var src_line) (bv 32 0x8)))) (set word3 (loadw 0 32 (+ (var src_line) (bv 32 0xc)))) (storew 0 (var dst_line) (cast 32 false (var word0))) (storew 0 (+ (var dst_line) (bv 32 0x4)) (cast 32 false (var word1))) (storew 0 (+ (var dst_line) (bv 32 0x8)) (cast 32 false (var word2))) (storew 0 (+ (var dst_line) (bv 32 0xc)) (cast 32 false (var word3))) (set a0 (cast 32 false (+ (var dst_addr) (bv 32 0x10)))))
d "move16 (a0), 0x1.l" f61000000001 0x0 (seq (set src_addr (cast 32 false (var a0))) (set dst_addr (cast 32 false (bv 32 0x1))) (set src_line (& (var src_addr) (bv 32 0xfffffff0))) (set dst_line (& (var dst_addr) (bv 32 0xfffffff0))) (set word0 (loadw 0 32 (var src_line))) (set word1 (loadw 0 32 (+ (var src_line) (bv 32 0x4)))) (set word2 (loadw 0 32 (+ (var src_line) (bv 32 0x8)))) (set word3 (loadw 0 32 (+ (var src_line) (bv 32 0xc)))) (storew 0 (var dst_line) (cast 32 false (var word0))) (storew 0 (+ (var dst_line) (bv 32 0x4)) (cast 32 false (var word1))) (storew 0 (+ (var dst_line) (bv 32 0x8)) (cast 32 false (var word2))) (storew 0 (+ (var dst_line) (bv 32 0xc)) (cast 32 false (var word3))))
d "move16 0x1.l, (a0)" f61800000001 0x0 (seq (set src_addr (cast 32 false (bv 32 0x1))) (set dst_addr (cast 32 false (var a0))) (set src_line (& (var src_addr) (bv 32 0xfffffff0))) (set dst_line (& (var dst_addr) (bv 32 0xfffffff0))) (set word0 (loadw 0 32 (var src_line))) (set word1 (loadw 0 32 (+ (var src_line) (bv 32 0x4)))) (set word2 (loadw 0 32 (+ (var src_line) (bv 32 0x8)))) (set word3 (loadw 0 32 (+ (var src_line) (bv 32 0xc)))) (storew 0 (var dst_line) (cast 32 false (var word0))) (storew 0 (+ (var dst_line) (bv 32 0x4)) (cast 32 false (var word1))) (storew 0 (+ (var dst_line) (bv 32 0x8)) (cast 32 false (var word2))) (storew 0 (+ (var dst_line) (bv 32 0xc)) (cast 32 false (var word3))))
d "move16 (a0)+, (a0)+" f6208000 0x0 (seq (set src_addr (var a0)) (set dst_addr (var a0)) (set src_line (& (var src_addr) (bv 32 0xfffffff0))) (set dst_line (& (var dst_addr) (bv 32 0xfffffff0))) (set word0 (loadw 0 32 (var src_line))) (set word1 (loadw 0 32 (+ (var src_line) (bv 32 0x4)))) (set word2 (loadw 0 32 (+ (var src_line) (bv 32 0x8)))) (set word3 (loadw 0 32 (+ (var src_line) (bv 32 0xc)))) (storew 0 (var dst_line) (cast 32 false (var word0))) (storew 0 (+ (var dst_line) (bv 32 0x4)) (cast 32 false (var word1))) (storew 0 (+ (var dst_line) (bv 32 0x8)) (cast 32 false (var word2))) (storew 0 (+ (var dst_line) (bv 32 0xc)) (cast 32 false (var word3))) (set a0 (cast 32 false (+ (var src_addr) (bv 32 0x10)))))
d "rte" 4e73 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set rte_state (bv 8 0x1)) (set target (bv 32 0x0)) (repeat (== (var rte_state) (bv 8 0x1)) (seq (set frame (var a7)) (set new_sr (loadw 0 16 (var frame))) (set target (loadw 0 32 (+ (var frame) (bv 32 0x2)))) (set format (>> (loadw 0 16 (+ (var frame) (bv 32 0x6))) (bv 8 0xc) false)) (set frame_size (ite (== (var format) (bv 16 0x0)) (bv 32 0x8) (ite (== (var format) (bv 16 0x1)) (bv 32 0x8) (ite (== (var format) (bv 16 0x2)) (bv 32 0xc) (ite (== (var format) (bv 16 0x3)) (bv 32 0xc) (ite (== (var format) (bv 16 0x4)) (bv 32 0x10) (ite (== (var format) (bv 16 0x7)) (bv 32 0x3c) (ite (== (var format) (bv 16 0x8)) (bv 32 0x3a) (ite (== (var format) (bv 16 0x9)) (bv 32 0x14) (ite (== (var format) (bv 16 0xa)) (bv 32 0x20) (bv 32 0x5c))))))))))) (branch (|| (&& (ule (var format) (bv 16 0x5)) (! (== (var format) (bv 16 0x5)))) (== (var format) (bv 16 0x7))) (seq (set a7 (cast 32 false (+ (var frame) (var frame_size)))) (set sr_write_value (cast 16 false (var new_sr))) (branch (! (== (ite (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x1000)))) (bv 8 0x2) (bv 8 0x1))) (ite (is_zero (& (var sr_write_value) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (var sr_write_value) (bv 16 0x1000)))) (bv 8 0x2) (bv 8 0x1))))) (seq (branch (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (set usp (cast 32 false (var a7))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x1000)))) (set msp (cast 32 false (var a7))) (set isp (cast 32 false (var a7))))) (branch (is_zero (& (var sr_write_value) (bv 16 0x2000))) (set a7 (cast 32 false (var usp))) (branch (! (is_zero (& (var sr_write_value) (bv 16 0x1000)))) (set a7 (cast 32 false (var msp))) (set a7 (cast 32 false (var isp)))))) empty) (set sr (var sr_write_value)) (set rte_state (ite (== (var format) (bv 16 0x1)) (bv 8 0x1) (bv 8 0x0)))) (set rte_state (bv 8 0x2))))) (branch (== (var rte_state) (bv 8 0x0)) (jmp (var target)) (seq (set trap_op (bv 32 0xa)) (set trap_vector (bv 32 0xe)) (goto m68k_trap)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "movem.l a0, -(a0)" 48e00080 0x0 (seq (set addr (var a0)) (set addr (- (var addr) (bv 32 0x4))) (storew 0 (var addr) (cast 32 false (cast 32 false (- (var a0) (bv 32 0x4))))) (set a0 (cast 32 false (var addr))))
d "fmove.x 0e1, fp0" f23c48003fff00008000000000000000
d "fmove.p 0e1.2345678901234567e+025, fp0" f23c4c00002500012345678901234567
d "fmove.p (a0), fp0" f2104c00
d "fmove.p fp0, (a1){-5}" f2116c7b
d "fmove.p fp2, (a2){d3}" f2127d30
d "fmove.p (a0)+, fp0" f2184c00
d "fmove.p fp0, -(a0){17}" f2206c11
test/db/asm/m68k_68060_32
+8 -8
View File
@@ -1,8 +1,8 @@
d "move16 (a0)+, (a1)+" f6209000
d "halt" 4ac8
d "pflushn (a0)" f500
d "pflush (a0)" f508
d "pflushan" f510
d "pflusha" f518
d "plpaw (a0)" f588
d "plpar (a0)" f5c8
d "halt" 4ac8 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set system_op (bv 32 0x3)) (goto m68k_system)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "pulse" 4acc 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set system_op (bv 32 0x4)) (goto m68k_system)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "plpaw (a0)" f588 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x4)) (set mmu_rw (bv 32 0x1)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "plpar (a0)" f5c8 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set mmu_addr (cast 32 false (var a0))) (set mmu_op (bv 32 0x4)) (set mmu_rw (bv 32 0x0)) (goto m68k_mmu)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "move16 (a0)+, (a1)+" f6209000 0x0 (seq (set src_addr (var a0)) (set dst_addr (var a1)) (set src_line (& (var src_addr) (bv 32 0xfffffff0))) (set dst_line (& (var dst_addr) (bv 32 0xfffffff0))) (set word0 (loadw 0 32 (var src_line))) (set word1 (loadw 0 32 (+ (var src_line) (bv 32 0x4)))) (set word2 (loadw 0 32 (+ (var src_line) (bv 32 0x8)))) (set word3 (loadw 0 32 (+ (var src_line) (bv 32 0xc)))) (storew 0 (var dst_line) (cast 32 false (var word0))) (storew 0 (+ (var dst_line) (bv 32 0x4)) (cast 32 false (var word1))) (storew 0 (+ (var dst_line) (bv 32 0x8)) (cast 32 false (var word2))) (storew 0 (+ (var dst_line) (bv 32 0xc)) (cast 32 false (var word3))) (set a0 (cast 32 false (+ (var src_addr) (bv 32 0x10)))) (set a1 (cast 32 false (+ (var dst_addr) (bv 32 0x10)))))
d "lpstop 0x0" f80001c00000 0x0 (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))
d "rte" 4e73 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set rte_state (bv 8 0x1)) (set target (bv 32 0x0)) (repeat (== (var rte_state) (bv 8 0x1)) (seq (set frame (var a7)) (set new_sr (loadw 0 16 (var frame))) (set target (loadw 0 32 (+ (var frame) (bv 32 0x2)))) (set format (>> (loadw 0 16 (+ (var frame) (bv 32 0x6))) (bv 8 0xc) false)) (set frame_size (ite (== (var format) (bv 16 0x0)) (bv 32 0x8) (ite (== (var format) (bv 16 0x1)) (bv 32 0x8) (ite (== (var format) (bv 16 0x2)) (bv 32 0xc) (ite (== (var format) (bv 16 0x3)) (bv 32 0xc) (ite (== (var format) (bv 16 0x4)) (bv 32 0x10) (ite (== (var format) (bv 16 0x7)) (bv 32 0x3c) (ite (== (var format) (bv 16 0x8)) (bv 32 0x3a) (ite (== (var format) (bv 16 0x9)) (bv 32 0x14) (ite (== (var format) (bv 16 0xa)) (bv 32 0x20) (bv 32 0x5c))))))))))) (branch (&& (&& (ule (var format) (bv 16 0x5)) (! (== (var format) (bv 16 0x5)))) (! (== (var format) (bv 16 0x1)))) (seq (set a7 (cast 32 false (+ (var frame) (var frame_size)))) (set sr_write_value (cast 16 false (var new_sr))) (branch (! (== (ite (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))) (ite (is_zero (& (var sr_write_value) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))))) (seq (branch (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (set usp (cast 32 false (var a7))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (set msp (cast 32 false (var a7))) (set isp (cast 32 false (var a7))))) (branch (is_zero (& (var sr_write_value) (bv 16 0x2000))) (set a7 (cast 32 false (var usp))) (branch (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (set a7 (cast 32 false (var msp))) (set a7 (cast 32 false (var isp)))))) empty) (set sr (var sr_write_value)) (set rte_state (ite (== (var format) (bv 16 0x1)) (bv 8 0x1) (bv 8 0x0)))) (set rte_state (bv 8 0x2))))) (branch (== (var rte_state) (bv 8 0x0)) (jmp (var target)) (seq (set trap_op (bv 32 0xa)) (set trap_vector (bv 32 0xe)) (goto m68k_trap)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "movem.l a0, -(a0)" 48e00080 0x0 (seq (set addr (var a0)) (set addr (- (var addr) (bv 32 0x4))) (storew 0 (var addr) (cast 32 false (cast 32 false (- (var a0) (bv 32 0x4))))) (set a0 (cast 32 false (var addr))))
test/db/asm/m68k_cfv1_32
+276 -105
View File
@@ -1,105 +1,276 @@
d "mov3q.l 0x2, (a4)" a554
d "mvs.b d0, d0" 7100
d "mvs.w d0, d0" 7140
d "mvz.b d0, d0" 7180
d "mvz.w d0, d0" 71c0
d "mvs.b d0, d1" 7300
d "mov3q.l 0xffffffff, d0" a140
d "mvs.b (a0), d1" 7310
d "mvz.w (a0), d1" 73d0
d "move.l d0, d0" 2000
d "movea.l d0, a0" 2040
d "moveq 0x1, d0" 7001
d "movem.l d0-d1, (a0)" 48d00003
d "lea.l (a0), a0" 41d0
d "link.w a0, 0x4" 4e500004
d "pea.l (a0)" 4850
d "unlk a0" 4e58
d "tpf" 51fc
d "tpf.w 0x1234" 51fa1234
d "tpf.l 0x12345678" 51fb12345678
d "bra.l 0x12" 60ff00000010
d "bsr.l 0x12" 61ff00000010
d "bne.l 0x12" 66ff00000010
d "st.b d0" 50c0
d "jmp (a0)" 4ed0
d "jsr (a0)" 4e90
d "nop" 4e71
d "rts" 4e75
d "tas.b d0" 4ac0
d "tst.l d0" 4a80
d "sats.l d0" 4c80
d "add.l d0, d0" d080
d "adda.l d0, a0" d1c0
d "addi.l 0x1, d0" 068000000001
d "addq.l 0x1, d0" 5280
d "addx.l d0, d0" d180
d "clr.l d0" 4280
d "cmp.l d0, d0" b080
d "cmpa.l d0, a0" b1c0
d "cmpi.l 0x1, d0" 0c8000000001
d "ext.l d0" 48c0
d "extb.l d0" 49c0
d "muls.w d0, d0" c1c0
d "mulu.w d0, d0" c0c0
d "neg.l d0" 4480
d "negx.l d0" 4080
d "sub.l d0, d0" 9080
d "suba.l d0, a0" 91c0
d "subi.l 0x1, d0" 048000000001
d "subq.l 0x1, d0" 5380
d "subx.l d0, d0" 9180
d "and.l d0, d0" c080
d "andi.l 0x1, d0" 028000000001
d "eor.l d0, d0" b180
d "eori.l 0x1, d0" 0a8000000001
d "not.l d0" 4680
d "or.l d0, d0" 8080
d "ori.l 0x1, d0" 008000000001
d "asl.l 0x8, d0" e180
d "asr.l 0x8, d0" e080
d "lsl.l 0x8, d0" e188
d "lsr.l 0x8, d0" e088
d "swap d0" 4840
d "bitrev d0" 00c0
d "byterev d1" 02c1
d "ff1 d2" 04c2
d "bchg.b d0, d0" 0140
d "bclr.b d0, d0" 0180
d "bset.b d0, d0" 01c0
d "btst.b d0, d0" 0100
d "halt" 4ac8
d "strldsr.w 0x4d2" 40e746fc04d2
d "wddata.b (a0)" fb10
d "wdebug.l (a0)" fbd00003
d "move.w ccr, d3" 42c3
d "move usp, a0" 4e68
d "move a0, usp" 4e60
d "pulse" 4acc
d "movec d0, cacr" 4e7b0002
d "movec cacr, d1" 4e7a1002
d "wddata.w (a0)" fb50
d "wddata.l (a0)" fb90
d "move.w d0, ccr" 44c0
d "move.w sr, d0" 40c0
d "move.w d0, sr" 46c0
d "illegal 0x4afc" 4afc
d "rte" 4e73
d "stop 0x2700" 4e722700
d "trap 0x0" 4e40
d "intouch (a0)" f428
d "cpushl bc, (a0)" f4e8
d "cp0bcbusy 0x52" fcc00050
d "cp0ld.l d0, d2, 0x1, 0x123" fc802123
d "cp0ld.w (a0), a2, 0x3, 0x1" fc50a401
d "cp0ld.b (a0)+, a2, 0x6, 0x1" fc18aa01
d "cp0ld.l 0x10(a0), a2, 0x8, 0x1" fca8ae010010
d "cp0st.l d2, d0, 0x1, 0x123" fd802123
d "cp0st.w a2, (a0), 0x3, 0x1" fd50a401
d "cp0nop 0x8" fc000e00
d "cp0nop 0x3" fc800400
d "cp0ld.l d0, d1, 0x3, 0x0" fc801400
d "cp1bcbusy 0x52" fec00050
d "cp1ld.l d0, d2, 0x1, 0x123" fe802123
d "cp1st.l d2, d0, 0x1, 0x123" ff802123
d "cp1nop 0x8" fe000e00
d "bitrev d0" 00c0 0x0 (seq (set src (var d0)) (set res (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (| (bv 32 0x0) (<< (& (>> (var src) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x1f) false)) (<< (& (>> (var src) (bv 32 0x1) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x1e) false)) (<< (& (>> (var src) (bv 32 0x2) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x1d) false)) (<< (& (>> (var src) (bv 32 0x3) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x1c) false)) (<< (& (>> (var src) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x1b) false)) (<< (& (>> (var src) (bv 32 0x5) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x1a) false)) (<< (& (>> (var src) (bv 32 0x6) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x19) false)) (<< (& (>> (var src) (bv 32 0x7) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x18) false)) (<< (& (>> (var src) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x17) false)) (<< (& (>> (var src) (bv 32 0x9) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x16) false)) (<< (& (>> (var src) (bv 32 0xa) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x15) false)) (<< (& (>> (var src) (bv 32 0xb) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x14) false)) (<< (& (>> (var src) (bv 32 0xc) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x13) false)) (<< (& (>> (var src) (bv 32 0xd) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x12) false)) (<< (& (>> (var src) (bv 32 0xe) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x11) false)) (<< (& (>> (var src) (bv 32 0xf) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x10) false)) (<< (& (>> (var src) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0xf) false)) (<< (& (>> (var src) (bv 32 0x11) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0xe) false)) (<< (& (>> (var src) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0xd) false)) (<< (& (>> (var src) (bv 32 0x13) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0xc) false)) (<< (& (>> (var src) (bv 32 0x14) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0xb) false)) (<< (& (>> (var src) (bv 32 0x15) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0xa) false)) (<< (& (>> (var src) (bv 32 0x16) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x9) false)) (<< (& (>> (var src) (bv 32 0x17) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x8) false)) (<< (& (>> (var src) (bv 32 0x18) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x7) false)) (<< (& (>> (var src) (bv 32 0x19) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x6) false)) (<< (& (>> (var src) (bv 32 0x1a) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x5) false)) (<< (& (>> (var src) (bv 32 0x1b) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x4) false)) (<< (& (>> (var src) (bv 32 0x1c) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x3) false)) (<< (& (>> (var src) (bv 32 0x1d) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x2) false)) (<< (& (>> (var src) (bv 32 0x1e) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (bv 8 0x1) false)) (& (>> (var src) (bv 32 0x1f) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (set d0 (cast 32 false (var res))))
d "byterev d1" 02c1 0x0 (seq (set src (var d1)) (set res (| (| (<< (& (var src) (bv 32 0xff)) (bv 8 0x18) false) (<< (& (var src) (bv 32 0xff00)) (bv 8 0x8) false)) (| (& (>> (var src) (bv 8 0x8) false) (bv 32 0xff00)) (>> (var src) (bv 8 0x18) false)))) (set d1 (cast 32 false (var res))))
d "ff1 d2" 04c2 0x0 (seq (set src (var d2)) (set res (ite (! (is_zero (& (>> (var src) (bv 32 0x1f) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x0) (ite (! (is_zero (& (>> (var src) (bv 32 0x1e) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x1) (ite (! (is_zero (& (>> (var src) (bv 32 0x1d) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x2) (ite (! (is_zero (& (>> (var src) (bv 32 0x1c) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x3) (ite (! (is_zero (& (>> (var src) (bv 32 0x1b) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x4) (ite (! (is_zero (& (>> (var src) (bv 32 0x1a) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x5) (ite (! (is_zero (& (>> (var src) (bv 32 0x19) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x6) (ite (! (is_zero (& (>> (var src) (bv 32 0x18) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x7) (ite (! (is_zero (& (>> (var src) (bv 32 0x17) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x8) (ite (! (is_zero (& (>> (var src) (bv 32 0x16) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x9) (ite (! (is_zero (& (>> (var src) (bv 32 0x15) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0xa) (ite (! (is_zero (& (>> (var src) (bv 32 0x14) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0xb) (ite (! (is_zero (& (>> (var src) (bv 32 0x13) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0xc) (ite (! (is_zero (& (>> (var src) (bv 32 0x12) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0xd) (ite (! (is_zero (& (>> (var src) (bv 32 0x11) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0xe) (ite (! (is_zero (& (>> (var src) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0xf) (ite (! (is_zero (& (>> (var src) (bv 32 0xf) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x10) (ite (! (is_zero (& (>> (var src) (bv 32 0xe) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x11) (ite (! (is_zero (& (>> (var src) (bv 32 0xd) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x12) (ite (! (is_zero (& (>> (var src) (bv 32 0xc) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x13) (ite (! (is_zero (& (>> (var src) (bv 32 0xb) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x14) (ite (! (is_zero (& (>> (var src) (bv 32 0xa) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x15) (ite (! (is_zero (& (>> (var src) (bv 32 0x9) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x16) (ite (! (is_zero (& (>> (var src) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x17) (ite (! (is_zero (& (>> (var src) (bv 32 0x7) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x18) (ite (! (is_zero (& (>> (var src) (bv 32 0x6) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x19) (ite (! (is_zero (& (>> (var src) (bv 32 0x5) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x1a) (ite (! (is_zero (& (>> (var src) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x1b) (ite (! (is_zero (& (>> (var src) (bv 32 0x3) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x1c) (ite (! (is_zero (& (>> (var src) (bv 32 0x2) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x1d) (ite (! (is_zero (& (>> (var src) (bv 32 0x1) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x1e) (ite (! (is_zero (& (>> (var src) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)))) (bv 32 0x1f) (bv 32 0x20)))))))))))))))))))))))))))))))))) (set d2 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (var src)) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (var src)) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "strldsr.w 0x4d2" 40e746fc04d2 0x0 (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))
d "strldsr.w 0x24d2" 40e746fc24d2 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set push_value (cast 32 false (var sr))) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (set sr_write_value (cast 16 false (bv 16 0x24d2))) (branch (! (== (ite (&& (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (bv 8 0x1) (bv 8 0x0)) (ite (&& (! (is_zero (& (cast 16 false (var sr_write_value)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (bv 8 0x1) (bv 8 0x0)))) (seq (branch (&& (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (set isp (cast 32 false (var a7))) (set usp (cast 32 false (var a7)))) (branch (&& (! (is_zero (& (cast 16 false (var sr_write_value)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (set a7 (cast 32 false (var isp))) (set a7 (cast 32 false (var usp))))) empty) (set sr (var sr_write_value))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "move.w ccr, d3" 42c3 0x0 (seq (set src (cast 16 false (cast 8 false (var sr)))) (set d3 (| (& (var d3) (bv 32 0xffff0000)) (cast 32 false (var src)))))
d "move.w d0, sr" 46c0 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (cast 16 false (var d0))) (set sr_write_value (cast 16 false (var src))) (branch (! (== (ite (&& (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (bv 8 0x1) (bv 8 0x0)) (ite (&& (! (is_zero (& (cast 16 false (var sr_write_value)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (bv 8 0x1) (bv 8 0x0)))) (seq (branch (&& (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (set isp (cast 32 false (var a7))) (set usp (cast 32 false (var a7)))) (branch (&& (! (is_zero (& (cast 16 false (var sr_write_value)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (set a7 (cast 32 false (var isp))) (set a7 (cast 32 false (var usp))))) empty) (set sr (var sr_write_value))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "movem.l d0-d1, (a0)" 48d00003 0x0 (seq (set addr (cast 32 false (var a0))) (storew 0 (var addr) (cast 32 false (var d0))) (storew 0 (+ (var addr) (bv 32 0x4)) (cast 32 false (var d1))))
d "sats.l d0" 4c80 0x0 (seq (set src (var d0)) (set res (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (ite (msb (var src)) (bv 32 0x7fffffff) (bv 32 0x80000000)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "link.w a0, 0x4" 4e500004 0x0 (seq (set push_value (var a0)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (set a0 (cast 32 false (var a7))) (set new_sp (+ (var a7) (bv 32 0x4))) (set a7 (cast 32 false (var new_sp))))
d "move usp, a0" 4e68 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set src (var usp)) (set a0 (cast 32 false (var src)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "stop 0x2700" 4e722700 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set system_op (bv 32 0x1)) (set system_sr (bv 32 0x2700)) (set sr_write_value (cast 16 false (bv 16 0x2700))) (branch (! (== (ite (&& (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (bv 8 0x1) (bv 8 0x0)) (ite (&& (! (is_zero (& (cast 16 false (var sr_write_value)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (bv 8 0x1) (bv 8 0x0)))) (seq (branch (&& (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (set isp (cast 32 false (var a7))) (set usp (cast 32 false (var a7)))) (branch (&& (! (is_zero (& (cast 16 false (var sr_write_value)) (bv 16 0x2000)))) (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10))))) (set a7 (cast 32 false (var isp))) (set a7 (cast 32 false (var usp))))) empty) (set sr (var sr_write_value)) (goto m68k_system)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "movec cacr, d1" 4e7a1002 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (set d1 (cast 32 false (var cacr))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "movec d0, cacr" 4e7b0002 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set cacr_write_value (cast 32 false (var d0))) (branch (&& (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (^^ (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10)))) (! (is_zero (& (cast 32 false (var cacr_write_value)) (bv 32 0x10)))))) (branch (! (is_zero (& (cast 32 false (var cacr)) (bv 32 0x10)))) (seq (set isp (cast 32 false (var a7))) (set a7 (cast 32 false (var usp)))) (seq (set usp (cast 32 false (var a7))) (set a7 (cast 32 false (var isp))))) empty) (set cacr (var cacr_write_value))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "tpf.w 0x1234" 51fa1234 0x0 nop
d "tpf.l 0x12345678" 51fb12345678 0x0 nop
d "tpf" 51fc 0x0 nop
d "addq.l 0x1, d0" 5280 0x0 (seq (set src (bv 32 0x1)) (set dst (var d0)) (set res (+ (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var res) (var dst)) (! (== (var res) (var dst)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false)))))))
d "subq.l 0x1, d0" 5380 0x0 (seq (set src (bv 32 0x1)) (set dst (var d0)) (set res (- (var dst) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (& (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite (&& (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var src)) (bv 1 0x1) (bv 1 0x0)))) (! (== (ite (msb (var dst)) (bv 1 0x1) (bv 1 0x0)) (ite (msb (var res)) (bv 1 0x1) (bv 1 0x0))))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (bv 8 0xef)) (<< (ite (&& (ule (var dst) (var src)) (! (== (var dst) (var src)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x4) false)))))))
d "bra.l 0x12" 60ff00000010 0x0 (jmp (bv 32 0x12))
d "bsr.l 0x12" 61ff00000010 0x0 (seq (set push_value (bv 32 0x6)) (set a7 (cast 32 false (- (var a7) (bv 32 0x4)))) (storew 0 (var a7) (cast 32 false (var push_value))) (jmp (bv 32 0x12)))
d "bne.l 0x12" 66ff00000010 0x0 (branch (! (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x4))))) (jmp (bv 32 0x12)) empty)
d "mvs.b d0, d0" 7100 0x0 (seq (set src (cast 8 false (var d0))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.b (a0)+, d0" 7118 0x0 (seq (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.b -(a0), d0" 7120 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.b 0x0(a0), d0" 71280000 0x0 (seq (set src (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.b 0x0(a0, d0.w), d0" 71300000 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.b (a0, d0.w), d0" 71300100 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.b ([0x18001ff, a0], 0x8000fff), d0" 7130017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.b 0x0.w, d0" 71380000 0x0 (seq (set src (loadw 0 8 (bv 32 0x0))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.b 0x1.l, d0" 713900000001 0x0 (seq (set src (loadw 0 8 (bv 32 0x1))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.b 0x2(pc), d0" 713a0000 0x0 (seq (set src (loadw 0 8 (bv 32 0x2))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.b 0x2(pc, d0.w), d0" 713b0000 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.b ([0x1800201, pc], 0x8000fff), d0" 713b017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.b 0x0, d0" 713c0000 0x0 (seq (set src (bv 8 0x0)) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.w d0, d0" 7140 0x0 (seq (set src (cast 16 false (var d0))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.w a0, d0" 7148 0x0 (seq (set src (cast 16 false (var a0))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.w (a0), d0" 7150 0x0 (seq (set src (loadw 0 16 (var a0))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.w (a0)+, d0" 7158 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.w -(a0), d0" 7160 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.w 0x0(a0), d0" 71680000 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.w 0x0(a0, d0.w), d0" 71700000 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.w (a0, d0.w), d0" 71700100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.w ([0x18001ff, a0], 0x8000fff), d0" 7170017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.w 0x0.w, d0" 71780000 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.w 0x1.l, d0" 717900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.w 0x2(pc), d0" 717a0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.w 0x2(pc, d0.w), d0" 717b0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.w ([0x1800201, pc], 0x8000fff), d0" 717b017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.w 0x0, d0" 717c0000 0x0 (seq (set src (bv 16 0x0)) (set res (cast 32 (msb (var src)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.b d0, d0" 7180 0x0 (seq (set src (cast 8 false (var d0))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.b (a0), d0" 7190 0x0 (seq (set src (loadw 0 8 (var a0))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.b (a0)+, d0" 7198 0x0 (seq (set src (loadw 0 8 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.b -(a0), d0" 71a0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set src (loadw 0 8 (var a0))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.b 0x0(a0), d0" 71a80000 0x0 (seq (set src (loadw 0 8 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.b 0x0(a0, d0.w), d0" 71b00000 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.b (a0, d0.w), d0" 71b00100 0x0 (seq (set src (loadw 0 8 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.b ([0x18001ff, a0], 0x8000fff), d0" 71b0017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.b 0x0.w, d0" 71b80000 0x0 (seq (set src (loadw 0 8 (bv 32 0x0))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.b 0x1.l, d0" 71b900000001 0x0 (seq (set src (loadw 0 8 (bv 32 0x1))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.b 0x2(pc), d0" 71ba0000 0x0 (seq (set src (loadw 0 8 (bv 32 0x2))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.b 0x2(pc, d0.w), d0" 71bb0000 0x0 (seq (set src (loadw 0 8 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.b ([0x1800201, pc], 0x8000fff), d0" 71bb017f018001ff08000fff 0x0 (seq (set src (loadw 0 8 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.b 0x0, d0" 71bc0000 0x0 (seq (set src (bv 8 0x0)) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.w d0, d0" 71c0 0x0 (seq (set src (cast 16 false (var d0))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.w a0, d0" 71c8 0x0 (seq (set src (cast 16 false (var a0))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.w (a0)+, d0" 71d8 0x0 (seq (set src (loadw 0 16 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.w -(a0), d0" 71e0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set src (loadw 0 16 (var a0))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.w 0x0(a0), d0" 71e80000 0x0 (seq (set src (loadw 0 16 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.w 0x0(a0, d0.w), d0" 71f00000 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.w (a0, d0.w), d0" 71f00100 0x0 (seq (set src (loadw 0 16 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.w ([0x18001ff, a0], 0x8000fff), d0" 71f0017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.w 0x0.w, d0" 71f80000 0x0 (seq (set src (loadw 0 16 (bv 32 0x0))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.w 0x1.l, d0" 71f900000001 0x0 (seq (set src (loadw 0 16 (bv 32 0x1))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.w 0x2(pc), d0" 71fa0000 0x0 (seq (set src (loadw 0 16 (bv 32 0x2))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.w 0x2(pc, d0.w), d0" 71fb0000 0x0 (seq (set src (loadw 0 16 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.w ([0x1800201, pc], 0x8000fff), d0" 71fb017f018001ff08000fff 0x0 (seq (set src (loadw 0 16 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.w 0x0, d0" 71fc0000 0x0 (seq (set src (bv 16 0x0)) (set res (cast 32 false (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.b d0, d1" 7300 0x0 (seq (set src (cast 8 false (var d0))) (set res (cast 32 (msb (var src)) (var src))) (set d1 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvs.b (a0), d1" 7310 0x0 (seq (set src (loadw 0 8 (var a0))) (set res (cast 32 (msb (var src)) (var src))) (set d1 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mvz.w (a0), d1" 73d0 0x0 (seq (set src (loadw 0 16 (var a0))) (set res (cast 32 false (var src))) (set d1 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mov3q.l 0xffffffff, d0" a140 0x0 (seq (set res (bv 32 0xffffffff)) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mov3q.l 0xffffffff, a0" a148 0x0 (seq (set res (bv 32 0xffffffff)) (set a0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mov3q.l 0xffffffff, (a0)+" a158 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (var a0) (cast 32 false (var res))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mov3q.l 0xffffffff, -(a0)" a160 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set res (bv 32 0xffffffff)) (storew 0 (var a0) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mov3q.l 0xffffffff, 0x0(a0)" a1680000 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mov3q.l 0xffffffff, 0x0(a0, d0.w)" a1700000 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mov3q.l 0xffffffff, (a0, d0.w)" a1700100 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mov3q.l 0xffffffff, ([0x18001ff, a0], 0x8000fff)" a170017f018001ff08000fff 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mov3q.l 0xffffffff, 0x0.w" a1780000 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (bv 32 0x0) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mov3q.l 0xffffffff, 0x1.l" a17900000001 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (bv 32 0x1) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mov3q.l 0xffffffff, 0x2(pc)" a17a0000 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (bv 32 0x2) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mov3q.l 0xffffffff, 0x2(pc, d0.w)" a17b0000 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mov3q.l 0xffffffff, ([0x1800201, pc], 0x8000fff)" a17b017f018001ff08000fff 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mov3q.l 0xffffffff, 0x1" a17c00000001 0x0 (seq (set res (bv 32 0xffffffff)) (storew 0 (bv 32 0x1) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "mov3q.l 0x2, (a4)" a554 0x0 (seq (set res (bv 32 0x2)) (storew 0 (var a4) (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "intouch (a0)" f428 0x0 (seq (set cache_addr (cast 32 false (var a0))) (set cache_op (bv 32 0x0)) (goto m68k_cache))
d "cpushl bc, (a0)" f4e8 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set cache_addr (cast 32 false (var a0))) (set cache_op (bv 32 0x2)) (set cache_selector (bv 32 0x3)) (goto m68k_cache)) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "wddata.b (a0)" fb10 0x0 (seq (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 8 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug))
d "wddata.b (a0)+" fb18 0x0 (seq (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 8 (var debug_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug))
d "wddata.b -(a0)" fb20 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 8 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug))
d "wddata.b 0x0(a0)" fb280000 0x0 (seq (set debug_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set debug_data (loadw 0 8 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug))
d "wddata.b 0x0(a0, d0.w)" fb300000 0x0 (seq (set debug_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set debug_data (loadw 0 8 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug))
d "wddata.b (a0, d0.w)" fb300100 0x0 (seq (set debug_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set debug_data (loadw 0 8 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug))
d "wddata.b ([0x18001ff, a0], 0x8000fff)" fb30017f018001ff08000fff 0x0 (seq (set debug_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set debug_data (loadw 0 8 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug))
d "wddata.b 0x0.w" fb380000 0x0 (seq (set debug_addr (cast 32 false (bv 32 0x0))) (set debug_data (loadw 0 8 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug))
d "wddata.b 0x1.l" fb3900000001 0x0 (seq (set debug_addr (cast 32 false (bv 32 0x1))) (set debug_data (loadw 0 8 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x8)) (goto m68k_debug))
d "wddata.w (a0)" fb50 0x0 (seq (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 16 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug))
d "wddata.w (a0)+" fb58 0x0 (seq (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 16 (var debug_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug))
d "wddata.w -(a0)" fb60 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 16 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug))
d "wddata.w 0x0(a0)" fb680000 0x0 (seq (set debug_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set debug_data (loadw 0 16 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug))
d "wddata.w 0x0(a0, d0.w)" fb700000 0x0 (seq (set debug_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set debug_data (loadw 0 16 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug))
d "wddata.w (a0, d0.w)" fb700100 0x0 (seq (set debug_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set debug_data (loadw 0 16 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug))
d "wddata.w ([0x18001ff, a0], 0x8000fff)" fb70017f018001ff08000fff 0x0 (seq (set debug_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set debug_data (loadw 0 16 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug))
d "wddata.w 0x0.w" fb780000 0x0 (seq (set debug_addr (cast 32 false (bv 32 0x0))) (set debug_data (loadw 0 16 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug))
d "wddata.w 0x1.l" fb7900000001 0x0 (seq (set debug_addr (cast 32 false (bv 32 0x1))) (set debug_data (loadw 0 16 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x10)) (goto m68k_debug))
d "wddata.l (a0)" fb90 0x0 (seq (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug))
d "wddata.l (a0)+" fb98 0x0 (seq (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 32 (var debug_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug))
d "wddata.l -(a0)" fba0 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug))
d "wddata.l 0x0(a0)" fba80000 0x0 (seq (set debug_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug))
d "wddata.l 0x0(a0, d0.w)" fbb00000 0x0 (seq (set debug_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug))
d "wddata.l (a0, d0.w)" fbb00100 0x0 (seq (set debug_addr (cast 32 false (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug))
d "wddata.l ([0x18001ff, a0], 0x8000fff)" fbb0017f018001ff08000fff 0x0 (seq (set debug_addr (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug))
d "wddata.l 0x0.w" fbb80000 0x0 (seq (set debug_addr (cast 32 false (bv 32 0x0))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug))
d "wddata.l 0x1.l" fbb900000001 0x0 (seq (set debug_addr (cast 32 false (bv 32 0x1))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x0)) (set debug_bits (bv 32 0x20)) (goto m68k_debug))
d "wdebug.l (a0)" fbd00003 0x0 (seq (set debug_addr (cast 32 false (var a0))) (set debug_data (loadw 0 32 (var debug_addr))) (set debug_op (bv 32 0x1)) (set debug_bits (bv 32 0x20)) (goto m68k_debug))
d "cp0ld.b d0, d0, 0x1, 0x1" fc000001 0x0 (seq (set cp_data (cast 8 false (var d0))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x1)) (goto m68k_coprocessor))
d "cp0nop 0x8" fc000e00 0x0 (seq (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x0)) (set cp_extension (bv 32 0x8)) (goto m68k_coprocessor))
d "cp0ld.b d0, a0, 0x1, 0x0" fc008000 0x0 (seq (set cp_data (cast 8 false (var d0))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.b a0, d0, 0x1, 0x0" fc080000 0x0 (seq (set cp_data (cast 8 false (var a0))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.b a0, a0, 0x1, 0x0" fc088000 0x0 (seq (set cp_data (cast 8 false (var a0))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.b (a0), d0, 0x1, 0x0" fc100000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.b (a0), a0, 0x1, 0x0" fc108000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.b (a0)+, d0, 0x1, 0x0" fc180000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.b (a0)+, a2, 0x6, 0x1" fc18aa01 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x6)) (set cp_extension (bv 32 0x1)) (goto m68k_coprocessor))
d "cp0ld.b -(a0), d0, 0x1, 0x0" fc200000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.b -(a0), a0, 0x1, 0x0" fc208000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.b 0x1(a0), d0, 0x1, 0x0" fc2800000001 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.b -0x7f00(a0), a0, 0x1, 0x0" fc2880008100 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.w d0, d0, 0x1, 0x1" fc400001 0x0 (seq (set cp_data (cast 16 false (var d0))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x1)) (goto m68k_coprocessor))
d "cp0ld.w d0, a0, 0x1, 0x0" fc408000 0x0 (seq (set cp_data (cast 16 false (var d0))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.w a0, d0, 0x1, 0x0" fc480000 0x0 (seq (set cp_data (cast 16 false (var a0))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.w a0, a0, 0x1, 0x0" fc488000 0x0 (seq (set cp_data (cast 16 false (var a0))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.w (a0), d0, 0x1, 0x0" fc500000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.w (a0), a2, 0x3, 0x1" fc50a401 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x3)) (set cp_extension (bv 32 0x1)) (goto m68k_coprocessor))
d "cp0ld.w (a0)+, d0, 0x1, 0x0" fc580000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.w (a0)+, a0, 0x1, 0x0" fc588000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.w -(a0), d0, 0x1, 0x0" fc600000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.w -(a0), a0, 0x1, 0x0" fc608000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.w 0x1(a0), d0, 0x1, 0x0" fc6800000001 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.w -0x7f00(a0), a0, 0x1, 0x0" fc6880008100 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0nop 0x3" fc800400 0x0 (seq (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x0)) (set cp_extension (bv 32 0x3)) (goto m68k_coprocessor))
d "cp0ld.l d0, d1, 0x3, 0x0" fc801400 0x0 (seq (set cp_data (var d0)) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x3)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.l d0, d2, 0x1, 0x123" fc802123 0x0 (seq (set cp_data (var d0)) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x123)) (goto m68k_coprocessor))
d "cp0ld.l d0, a0, 0x1, 0x0" fc808000 0x0 (seq (set cp_data (var d0)) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.l a0, d0, 0x1, 0x0" fc880000 0x0 (seq (set cp_data (var a0)) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.l a0, a0, 0x1, 0x0" fc888000 0x0 (seq (set cp_data (var a0)) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.l (a0), d0, 0x1, 0x0" fc900000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.l (a0), a0, 0x1, 0x0" fc908000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.l (a0)+, d0, 0x1, 0x0" fc980000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.l (a0)+, a0, 0x1, 0x0" fc988000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.l -(a0), d0, 0x1, 0x0" fca00000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.l -(a0), a0, 0x1, 0x0" fca08000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.l 0x1(a0), d0, 0x1, 0x0" fca800000001 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0ld.l 0x10(a0), a2, 0x8, 0x1" fca8ae010010 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x8)) (set cp_extension (bv 32 0x1)) (goto m68k_coprocessor))
d "cp0bcbusy 0x52" fcc00050 0x0 (seq (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x1)) (set cp_branch (bv 32 0x52)) (goto m68k_coprocessor))
d "cp0st.b d0, d0, 0x1, 0x0" fd000000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var cp_data)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.b a0, d0, 0x1, 0x0" fd008000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var cp_data)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.b d0, a0, 0x1, 0x0" fd080000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set a0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.b a0, a0, 0x1, 0x0" fd088000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set a0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.b d0, (a0), 0x1, 0x0" fd100000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.b a0, (a0), 0x1, 0x0" fd108000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.b d0, (a0)+, 0x1, 0x0" fd180000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.b a0, (a0)+, 0x1, 0x0" fd188000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.b d0, -(a0), 0x1, 0x0" fd200000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.b a0, -(a0), 0x1, 0x0" fd208000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.b d0, 0x1(a0), 0x1, 0x0" fd2800000001 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.b a0, -0x7f00(a0), 0x1, 0x0" fd2880008100 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.w d0, d0, 0x1, 0x0" fd400000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var cp_data)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.w a0, d0, 0x1, 0x0" fd408000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var cp_data)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.w d0, a0, 0x1, 0x0" fd480000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set a0 (cast 32 (msb (var cp_data)) (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.w a0, a0, 0x1, 0x0" fd488000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set a0 (cast 32 (msb (var cp_data)) (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.w d0, (a0), 0x1, 0x0" fd500000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.w a2, (a0), 0x3, 0x1" fd50a401 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x3)) (set cp_extension (bv 32 0x1)) (goto m68k_coprocessor))
d "cp0st.w d0, (a0)+, 0x1, 0x0" fd580000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.w a0, (a0)+, 0x1, 0x0" fd588000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.w d0, -(a0), 0x1, 0x0" fd600000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.w a0, -(a0), 0x1, 0x0" fd608000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.w d0, 0x1(a0), 0x1, 0x0" fd6800000001 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.w a0, -0x7f00(a0), 0x1, 0x0" fd6880008100 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.l d2, d0, 0x1, 0x123" fd802123 0x0 (seq (set cp_data (var cp_external_data)) (set d0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x123)) (goto m68k_coprocessor))
d "cp0st.l a0, d0, 0x1, 0x0" fd808000 0x0 (seq (set cp_data (var cp_external_data)) (set d0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.l d0, a0, 0x1, 0x0" fd880000 0x0 (seq (set cp_data (var cp_external_data)) (set a0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.l a0, a0, 0x1, 0x0" fd888000 0x0 (seq (set cp_data (var cp_external_data)) (set a0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.l d0, (a0), 0x1, 0x0" fd900000 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.l a0, (a0), 0x1, 0x0" fd908000 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.l d0, (a0)+, 0x1, 0x0" fd980000 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.l a0, (a0)+, 0x1, 0x0" fd988000 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.l d0, -(a0), 0x1, 0x0" fda00000 0x0 (seq (set cp_data (var cp_external_data)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.l a0, -(a0), 0x1, 0x0" fda08000 0x0 (seq (set cp_data (var cp_external_data)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.l d0, 0x1(a0), 0x1, 0x0" fda800000001 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp0st.l a0, -0x7f00(a0), 0x1, 0x0" fda880008100 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x0)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.b d0, d0, 0x1, 0x1" fe000001 0x0 (seq (set cp_data (cast 8 false (var d0))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x1)) (goto m68k_coprocessor))
d "cp1nop 0x8" fe000e00 0x0 (seq (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x0)) (set cp_extension (bv 32 0x8)) (goto m68k_coprocessor))
d "cp1ld.b d0, a0, 0x1, 0x0" fe008000 0x0 (seq (set cp_data (cast 8 false (var d0))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.b a0, d0, 0x1, 0x0" fe080000 0x0 (seq (set cp_data (cast 8 false (var a0))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.b a0, a0, 0x1, 0x0" fe088000 0x0 (seq (set cp_data (cast 8 false (var a0))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.b (a0), d0, 0x1, 0x0" fe100000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.b (a0), a0, 0x1, 0x0" fe108000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.b (a0)+, d0, 0x1, 0x0" fe180000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.b (a0)+, a0, 0x1, 0x0" fe188000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.b -(a0), d0, 0x1, 0x0" fe200000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.b -(a0), a0, 0x1, 0x0" fe208000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.b 0x1(a0), d0, 0x1, 0x0" fe2800000001 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.b -0x7f00(a0), a0, 0x1, 0x0" fe2880008100 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (set cp_data (loadw 0 8 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.w d0, d0, 0x1, 0x1" fe400001 0x0 (seq (set cp_data (cast 16 false (var d0))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x1)) (goto m68k_coprocessor))
d "cp1ld.w d0, a0, 0x1, 0x0" fe408000 0x0 (seq (set cp_data (cast 16 false (var d0))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.w a0, d0, 0x1, 0x0" fe480000 0x0 (seq (set cp_data (cast 16 false (var a0))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.w a0, a0, 0x1, 0x0" fe488000 0x0 (seq (set cp_data (cast 16 false (var a0))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.w (a0), d0, 0x1, 0x0" fe500000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.w (a0), a0, 0x1, 0x0" fe508000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.w (a0)+, d0, 0x1, 0x0" fe580000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.w (a0)+, a0, 0x1, 0x0" fe588000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.w -(a0), d0, 0x1, 0x0" fe600000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.w -(a0), a0, 0x1, 0x0" fe608000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.w 0x1(a0), d0, 0x1, 0x0" fe6800000001 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.w -0x7f00(a0), a0, 0x1, 0x0" fe6880008100 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (set cp_data (loadw 0 16 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.l d0, d2, 0x1, 0x123" fe802123 0x0 (seq (set cp_data (var d0)) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x123)) (goto m68k_coprocessor))
d "cp1ld.l d0, a0, 0x1, 0x0" fe808000 0x0 (seq (set cp_data (var d0)) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.l a0, d0, 0x1, 0x0" fe880000 0x0 (seq (set cp_data (var a0)) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.l a0, a0, 0x1, 0x0" fe888000 0x0 (seq (set cp_data (var a0)) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.l (a0), d0, 0x1, 0x0" fe900000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.l (a0), a0, 0x1, 0x0" fe908000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.l (a0)+, d0, 0x1, 0x0" fe980000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.l (a0)+, a0, 0x1, 0x0" fe988000 0x0 (seq (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.l -(a0), d0, 0x1, 0x0" fea00000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.l -(a0), a0, 0x1, 0x0" fea08000 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set cp_addr (cast 32 false (var a0))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.l 0x1(a0), d0, 0x1, 0x0" fea800000001 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1ld.l -0x7f00(a0), a0, 0x1, 0x0" fea880008100 0x0 (seq (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (set cp_data (loadw 0 32 (var cp_addr))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x2)) (set cp_store (bv 32 0x0)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1bcbusy 0x52" fec00050 0x0 (seq (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x1)) (set cp_branch (bv 32 0x52)) (goto m68k_coprocessor))
d "cp1st.b d0, d0, 0x1, 0x0" ff000000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var cp_data)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.b a0, d0, 0x1, 0x0" ff008000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var cp_data)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.b d0, a0, 0x1, 0x0" ff080000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set a0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.b a0, a0, 0x1, 0x0" ff088000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set a0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.b d0, (a0), 0x1, 0x0" ff100000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.b a0, (a0), 0x1, 0x0" ff108000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.b d0, (a0)+, 0x1, 0x0" ff180000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.b a0, (a0)+, 0x1, 0x0" ff188000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.b d0, -(a0), 0x1, 0x0" ff200000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.b a0, -(a0), 0x1, 0x0" ff208000 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.b d0, 0x1(a0), 0x1, 0x0" ff2800000001 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.b a0, -0x7f00(a0), 0x1, 0x0" ff2880008100 0x0 (seq (set cp_data (cast 8 false (var cp_external_data))) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (storew 0 (var cp_addr) (cast 8 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x8)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.w d0, d0, 0x1, 0x0" ff400000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var cp_data)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.w a0, d0, 0x1, 0x0" ff408000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var cp_data)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.w d0, a0, 0x1, 0x0" ff480000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set a0 (cast 32 (msb (var cp_data)) (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.w a0, a0, 0x1, 0x0" ff488000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set a0 (cast 32 (msb (var cp_data)) (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.w d0, (a0), 0x1, 0x0" ff500000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.w a0, (a0), 0x1, 0x0" ff508000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.w d0, (a0)+, 0x1, 0x0" ff580000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.w a0, (a0)+, 0x1, 0x0" ff588000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.w d0, -(a0), 0x1, 0x0" ff600000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.w a0, -(a0), 0x1, 0x0" ff608000 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.w d0, 0x1(a0), 0x1, 0x0" ff6800000001 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.w a0, -0x7f00(a0), 0x1, 0x0" ff6880008100 0x0 (seq (set cp_data (cast 16 false (var cp_external_data))) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (storew 0 (var cp_addr) (cast 16 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x10)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.l d2, d0, 0x1, 0x123" ff802123 0x0 (seq (set cp_data (var cp_external_data)) (set d0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x123)) (goto m68k_coprocessor))
d "cp1st.l a0, d0, 0x1, 0x0" ff808000 0x0 (seq (set cp_data (var cp_external_data)) (set d0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.l d0, a0, 0x1, 0x0" ff880000 0x0 (seq (set cp_data (var cp_external_data)) (set a0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.l a0, a0, 0x1, 0x0" ff888000 0x0 (seq (set cp_data (var cp_external_data)) (set a0 (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.l d0, (a0), 0x1, 0x0" ff900000 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.l a0, (a0), 0x1, 0x0" ff908000 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.l d0, (a0)+, 0x1, 0x0" ff980000 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.l a0, (a0)+, 0x1, 0x0" ff988000 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.l d0, -(a0), 0x1, 0x0" ffa00000 0x0 (seq (set cp_data (var cp_external_data)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.l a0, -(a0), 0x1, 0x0" ffa08000 0x0 (seq (set cp_data (var cp_external_data)) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set cp_addr (cast 32 false (var a0))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.l d0, 0x1(a0), 0x1, 0x0" ffa800000001 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1))))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
d "cp1st.l a0, -0x7f00(a0), 0x1, 0x0" ffa880008100 0x0 (seq (set cp_data (var cp_external_data)) (set cp_addr (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0xffff8100))))) (storew 0 (var cp_addr) (cast 32 false (var cp_data))) (set cp_num (bv 32 0x1)) (set cp_op (bv 32 0x3)) (set cp_store (bv 32 0x1)) (set cp_bits (bv 32 0x20)) (set cp_selector (bv 32 0x1)) (set cp_extension (bv 32 0x0)) (goto m68k_coprocessor))
test/db/asm/m68k_cfv2_32
+14 -90
View File
@@ -1,90 +1,14 @@
d "move.l d0, d0" 2000
d "movea.l d0, a0" 2040
d "moveq 0x1, d0" 7001
d "movem.l d0-d1, (a0)" 48d00003
d "lea.l (a0), a0" 41d0
d "link.w a0, 0x4" 4e500004
d "pea.l (a0)" 4850
d "unlk a0" 4e58
d "tpf" 51fc
d "tpf.w 0x1234" 51fa1234
d "tpf.l 0x12345678" 51fb12345678
d "st.b d0" 50c0
d "jmp (a0)" 4ed0
d "jsr (a0)" 4e90
d "nop" 4e71
d "rts" 4e75
d "tas.b d0" 4ac0
d "tst.l d0" 4a80
d "divs.l d0, d2" 4c402802
d "divu.l d0, d1:d2" 4c402401
d "divs.l d0, d1:d2" 4c402c01
d "add.l d0, d0" d080
d "adda.l d0, a0" d1c0
d "addi.l 0x1, d0" 068000000001
d "addq.l 0x1, d0" 5280
d "addx.l d0, d0" d180
d "clr.l d0" 4280
d "cmp.l d0, d0" b080
d "cmpa.l d0, a0" b1c0
d "cmpi.l 0x1, d0" 0c8000000001
d "ext.l d0" 48c0
d "extb.l d0" 49c0
d "muls.w d0, d0" c1c0
d "mulu.w d0, d0" c0c0
d "neg.l d0" 4480
d "negx.l d0" 4080
d "remu.l d0, d1:d2" 4c402001
d "rems.l d0, d1:d2" 4c402801
d "sub.l d0, d0" 9080
d "suba.l d0, a0" 91c0
d "subi.l 0x1, d0" 048000000001
d "subq.l 0x1, d0" 5380
d "subx.l d0, d0" 9180
d "and.l d0, d0" c080
d "andi.l 0x1, d0" 028000000001
d "eor.l d0, d0" b180
d "eori.l 0x1, d0" 0a8000000001
d "not.l d0" 4680
d "or.l d0, d0" 8080
d "ori.l 0x1, d0" 008000000001
d "asl.l 0x8, d0" e180
d "asr.l 0x8, d0" e080
d "lsl.l 0x8, d0" e188
d "lsr.l 0x8, d0" e088
d "swap d0" 4840
d "bchg.b d0, d0" 0140
d "bclr.b d0, d0" 0180
d "bset.b d0, d0" 01c0
d "btst.b d0, d0" 0100
d "halt" 4ac8
d "wddata.b (a0)" fb10
d "wdebug.l (a0)" fbd00003
d "move.w ccr, d3" 42c3
d "pulse" 4acc
d "movec d0, cacr" 4e7b0002
d "movec cacr, d1" 4e7a1002
d "wddata.w (a0)" fb50
d "wddata.l (a0)" fb90
d "move.w d0, ccr" 44c0
d "move.w sr, d0" 40c0
d "move.w d0, sr" 46c0
d "illegal 0x4afc" 4afc
d "rte" 4e73
d "stop 0x2700" 4e722700
d "trap 0x0" 4e40
d "cpushl bc, (a0)" f4e8
d "cp0bcbusy 0x52" fcc00050
d "cp0ld.l d0, d2, 0x1, 0x123" fc802123
d "cp0ld.w (a0), a2, 0x3, 0x1" fc50a401
d "cp0ld.b (a0)+, a2, 0x6, 0x1" fc18aa01
d "cp0ld.l 0x10(a0), a2, 0x8, 0x1" fca8ae010010
d "cp0st.l d2, d0, 0x1, 0x123" fd802123
d "cp0st.w a2, (a0), 0x3, 0x1" fd50a401
d "cp0nop 0x8" fc000e00
d "cp0nop 0x3" fc800400
d "cp0ld.l d0, d1, 0x3, 0x0" fc801400
d "cp1bcbusy 0x52" fec00050
d "cp1ld.l d0, d2, 0x1, 0x123" fe802123
d "cp1st.l d2, d0, 0x1, 0x123" ff802123
d "cp1nop 0x8" fe000e00
d "remu.l d0, d1:d2" 4c402001 0x0 (seq (set src (var d0)) (set dst (var d2)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))))))
d "rems.l d0, d1:d2" 4c402801 0x0 (seq (set src (var d0)) (set dst (var d2)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (&& (== (var dst) (bv 32 0x80000000)) (== (var src) (bv 32 0xffffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (sdiv (cast 64 (msb (var dst)) (var dst)) (cast 64 (msb (var src)) (var src)))) (set rem (- (cast 64 (msb (var dst)) (var dst)) (* (var quot) (cast 64 (msb (var src)) (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))))))
d "remu.l (a0), d1:d0" 4c500001 0x0 (seq (set src (loadw 0 32 (var a0))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))))))
d "remu.l (a0)+, d1:d0" 4c580001 0x0 (seq (set src (loadw 0 32 (var a0))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))))))
d "remu.l -(a0), d1:d0" 4c600001 0x0 (seq (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set src (loadw 0 32 (var a0))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))))))
d "remu.l 0x10(a0), d1:d0" 4c6800010010 0x0 (seq (set src (loadw 0 32 (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))))))
d "remu.l 0x10(a0, d0.w), d1:d0" 4c7000010010 0x0 (seq (set src (loadw 0 32 (+ (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x10))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))))))
d "remu.l ([0x20002fff], 0x30003fff), d0:d1" 4c7010001fff20002fff30003fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20002fff))) (bv 32 0x0)) (bv 32 0x30003fff)))) (set dst (var d1)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))))))
d "remu.l 0x10.w, d1:d0" 4c7800010010 0x0 (seq (set src (loadw 0 32 (bv 32 0x10))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))))))
d "remu.l 0x10007f.l, d1:d0" 4c7900010010007f 0x0 (seq (set src (loadw 0 32 (bv 32 0x10007f))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))))))
d "remu.l 0x14(pc), d1:d0" 4c7a00010010 0x0 (seq (set src (loadw 0 32 (bv 32 0x14))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))))))
d "remu.l 0x14(pc, d0.w), d1:d0" 4c7b00010010 0x0 (seq (set src (loadw 0 32 (+ (bv 32 0x14) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))))))
d "remu.l ([0x20003003], 0x30003fff), d0:d1" 4c7b10001fff20002fff30003fff 0x0 (seq (set src (loadw 0 32 (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x20003001))) (bv 32 0x0)) (bv 32 0x30003fff)))) (set dst (var d1)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d0 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))))))
d "remu.l 0x10007f, d1:d0" 4c7c00010010007f 0x0 (seq (set src (bv 32 0x10007f)) (set dst (var d0)) (branch (is_zero (var src)) (seq (set trap_op (bv 32 0x6)) (set trap_vector (bv 32 0x5)) (goto m68k_trap)) (branch (! (ule (div (cast 64 false (var dst)) (cast 64 false (var src))) (bv 64 0x7fffffff))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! true) (msb (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! true) (is_zero (cast 32 false (bv 32 0x0)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite true (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))) (seq (set quot (div (cast 64 false (var dst)) (cast 64 false (var src)))) (set rem (- (cast 64 false (var dst)) (* (var quot) (cast 64 false (var src))))) (set d1 (cast 32 false (cast 32 false (var rem)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (&& (! false) (msb (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (&& (! false) (is_zero (cast 32 false (var quot)))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10)))))))))))
test/db/asm/m68k_cfv3_32
+1 -90
View File
@@ -1,90 +1 @@
d "move.l d0, d0" 2000
d "movea.l d0, a0" 2040
d "moveq 0x1, d0" 7001
d "movem.l d0-d1, (a0)" 48d00003
d "lea.l (a0), a0" 41d0
d "link.w a0, 0x4" 4e500004
d "pea.l (a0)" 4850
d "unlk a0" 4e58
d "tpf" 51fc
d "tpf.w 0x1234" 51fa1234
d "tpf.l 0x12345678" 51fb12345678
d "st.b d0" 50c0
d "jmp (a0)" 4ed0
d "jsr (a0)" 4e90
d "nop" 4e71
d "rts" 4e75
d "tas.b d0" 4ac0
d "tst.l d0" 4a80
d "divs.l d0, d2" 4c402802
d "divu.l d0, d1:d2" 4c402401
d "divs.l d0, d1:d2" 4c402c01
d "add.l d0, d0" d080
d "adda.l d0, a0" d1c0
d "addi.l 0x1, d0" 068000000001
d "addq.l 0x1, d0" 5280
d "addx.l d0, d0" d180
d "clr.l d0" 4280
d "cmp.l d0, d0" b080
d "cmpa.l d0, a0" b1c0
d "cmpi.l 0x1, d0" 0c8000000001
d "ext.l d0" 48c0
d "extb.l d0" 49c0
d "muls.w d0, d0" c1c0
d "mulu.w d0, d0" c0c0
d "neg.l d0" 4480
d "negx.l d0" 4080
d "remu.l d0, d1:d2" 4c402001
d "rems.l d0, d1:d2" 4c402801
d "sub.l d0, d0" 9080
d "suba.l d0, a0" 91c0
d "subi.l 0x1, d0" 048000000001
d "subq.l 0x1, d0" 5380
d "subx.l d0, d0" 9180
d "and.l d0, d0" c080
d "andi.l 0x1, d0" 028000000001
d "eor.l d0, d0" b180
d "eori.l 0x1, d0" 0a8000000001
d "not.l d0" 4680
d "or.l d0, d0" 8080
d "ori.l 0x1, d0" 008000000001
d "asl.l 0x8, d0" e180
d "asr.l 0x8, d0" e080
d "lsl.l 0x8, d0" e188
d "lsr.l 0x8, d0" e088
d "swap d0" 4840
d "bchg.b d0, d0" 0140
d "bclr.b d0, d0" 0180
d "bset.b d0, d0" 01c0
d "btst.b d0, d0" 0100
d "halt" 4ac8
d "wddata.b (a0)" fb10
d "wdebug.l (a0)" fbd00003
d "move.w ccr, d3" 42c3
d "pulse" 4acc
d "movec d0, cacr" 4e7b0002
d "movec cacr, d1" 4e7a1002
d "wddata.w (a0)" fb50
d "wddata.l (a0)" fb90
d "move.w d0, ccr" 44c0
d "move.w sr, d0" 40c0
d "move.w d0, sr" 46c0
d "illegal 0x4afc" 4afc
d "rte" 4e73
d "stop 0x2700" 4e722700
d "trap 0x0" 4e40
d "cpushl bc, (a0)" f4e8
d "cp0bcbusy 0x52" fcc00050
d "cp0ld.l d0, d2, 0x1, 0x123" fc802123
d "cp0ld.w (a0), a2, 0x3, 0x1" fc50a401
d "cp0ld.b (a0)+, a2, 0x6, 0x1" fc18aa01
d "cp0ld.l 0x10(a0), a2, 0x8, 0x1" fca8ae010010
d "cp0st.l d2, d0, 0x1, 0x123" fd802123
d "cp0st.w a2, (a0), 0x3, 0x1" fd50a401
d "cp0nop 0x8" fc000e00
d "cp0nop 0x3" fc800400
d "cp0ld.l d0, d1, 0x3, 0x0" fc801400
d "cp1bcbusy 0x52" fec00050
d "cp1ld.l d0, d2, 0x1, 0x123" fe802123
d "cp1st.l d2, d0, 0x1, 0x123" ff802123
d "cp1nop 0x8" fe000e00
d "moveq 0x1, d0" 7001 0x0 (seq (set res (bv 32 0x1)) (set d0 (cast 32 false (bv 32 0x1))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
test/db/asm/m68k_cfv4_32
+1 -108
View File
@@ -1,108 +1 @@
d "mov3q.l 0x2, (a4)" a554
d "mvs.b d0, d0" 7100
d "mvs.w d0, d0" 7140
d "mvz.b d0, d0" 7180
d "mvz.w d0, d0" 71c0
d "mvs.b d0, d1" 7300
d "mov3q.l 0xffffffff, d0" a140
d "mvs.b (a0), d1" 7310
d "mvz.w (a0), d1" 73d0
d "move.l d0, d0" 2000
d "movea.l d0, a0" 2040
d "moveq 0x1, d0" 7001
d "movem.l d0-d1, (a0)" 48d00003
d "lea.l (a0), a0" 41d0
d "link.w a0, 0x4" 4e500004
d "pea.l (a0)" 4850
d "unlk a0" 4e58
d "tpf" 51fc
d "tpf.w 0x1234" 51fa1234
d "tpf.l 0x12345678" 51fb12345678
d "bra.l 0x12" 60ff00000010
d "bsr.l 0x12" 61ff00000010
d "bne.l 0x12" 66ff00000010
d "st.b d0" 50c0
d "jmp (a0)" 4ed0
d "jsr (a0)" 4e90
d "nop" 4e71
d "rts" 4e75
d "tas.b d0" 4ac0
d "tst.l d0" 4a80
d "sats.l d0" 4c80
d "divs.l d0, d2" 4c402802
d "divu.l d0, d1:d2" 4c402401
d "divs.l d0, d1:d2" 4c402c01
d "add.l d0, d0" d080
d "adda.l d0, a0" d1c0
d "addi.l 0x1, d0" 068000000001
d "addq.l 0x1, d0" 5280
d "addx.l d0, d0" d180
d "clr.l d0" 4280
d "cmp.l d0, d0" b080
d "cmpa.l d0, a0" b1c0
d "cmpi.l 0x1, d0" 0c8000000001
d "ext.l d0" 48c0
d "extb.l d0" 49c0
d "muls.w d0, d0" c1c0
d "mulu.w d0, d0" c0c0
d "neg.l d0" 4480
d "negx.l d0" 4080
d "remu.l d0, d1:d2" 4c402001
d "rems.l d0, d1:d2" 4c402801
d "sub.l d0, d0" 9080
d "suba.l d0, a0" 91c0
d "subi.l 0x1, d0" 048000000001
d "subq.l 0x1, d0" 5380
d "subx.l d0, d0" 9180
d "and.l d0, d0" c080
d "andi.l 0x1, d0" 028000000001
d "eor.l d0, d0" b180
d "eori.l 0x1, d0" 0a8000000001
d "not.l d0" 4680
d "or.l d0, d0" 8080
d "ori.l 0x1, d0" 008000000001
d "asl.l 0x8, d0" e180
d "asr.l 0x8, d0" e080
d "lsl.l 0x8, d0" e188
d "lsr.l 0x8, d0" e088
d "swap d0" 4840
d "bitrev d0" 00c0
d "byterev d1" 02c1
d "ff1 d2" 04c2
d "bchg.b d0, d0" 0140
d "bclr.b d0, d0" 0180
d "bset.b d0, d0" 01c0
d "btst.b d0, d0" 0100
d "halt" 4ac8
d "strldsr.w 0x4d2" 40e746fc04d2
d "wddata.b (a0)" fb10
d "wdebug.l (a0)" fbd00003
d "move.w ccr, d3" 42c3
d "pulse" 4acc
d "movec d0, cacr" 4e7b0002
d "movec cacr, d1" 4e7a1002
d "wddata.w (a0)" fb50
d "wddata.l (a0)" fb90
d "move.w d0, ccr" 44c0
d "move.w sr, d0" 40c0
d "move.w d0, sr" 46c0
d "illegal 0x4afc" 4afc
d "rte" 4e73
d "stop 0x2700" 4e722700
d "trap 0x0" 4e40
d "intouch (a0)" f428
d "cpushl bc, (a0)" f4e8
d "cp0bcbusy 0x52" fcc00050
d "cp0ld.l d0, d2, 0x1, 0x123" fc802123
d "cp0ld.w (a0), a2, 0x3, 0x1" fc50a401
d "cp0ld.b (a0)+, a2, 0x6, 0x1" fc18aa01
d "cp0ld.l 0x10(a0), a2, 0x8, 0x1" fca8ae010010
d "cp0st.l d2, d0, 0x1, 0x123" fd802123
d "cp0st.w a2, (a0), 0x3, 0x1" fd50a401
d "cp0nop 0x8" fc000e00
d "cp0nop 0x3" fc800400
d "cp0ld.l d0, d1, 0x3, 0x0" fc801400
d "cp1bcbusy 0x52" fec00050
d "cp1ld.l d0, d2, 0x1, 0x123" fe802123
d "cp1st.l d2, d0, 0x1, 0x123" ff802123
d "cp1nop 0x8" fe000e00
d "sats.l d0" 4c80 0x0 (seq (set src (var d0)) (set res (ite (! (is_zero (& (cast 8 false (var sr)) (bv 8 0x2)))) (ite (msb (var src)) (bv 32 0x7fffffff) (bv 32 0x80000000)) (var src))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
test/db/asm/m68k_cfv4e_32
+148 -209
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test/db/asm/m68k_cfv5_32
+9 -137
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test/db/asm/m68k_coldfire_32
+1 -211
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@@ -1,211 +1 @@
d "mov3q.l 0x2, (a4)" a554
d "mvs.b d0, d0" 7100
d "mvs.w d0, d0" 7140
d "mvz.b d0, d0" 7180
d "mvz.w d0, d0" 71c0
d "mvs.b d0, d1" 7300
d "fsmove fp1, fp2" f2000540
d "fdmove fp1, fp2" f2000544
d "mov3q.l 0xffffffff, d0" a140
d "mvs.b (a0), d1" 7310
d "mvz.w (a0), d1" 73d0
d "move.l d0, acc0" a100
d "move.l acc0, d0" a180
d "move.l 0x12345678, acc0" a13c12345678
d "move.l d0, macsr" a900
d "move.l macsr, d0" a980
d "move.l 0x7, macsr" a93c00000007
d "move.l d0, mask" ad00
d "move.l mask, d0" ad80
d "move.l 0x7, mask" ad3c00000007
d "movclr.l acc0, d0" a1c0
d "move.l d0, accext01" ab00
d "move.l accext01, d0" ab80
d "move.l 0x7, accext01" ab3c00000007
d "move.l d0, accext23" af00
d "fmove.l d0, fp0" f2004000
d "fmove.l fp0, d0" f2006000
d "fmove.s 1.000000, fp1" f23c44803f800000
d "fmove.d 3.141593, fp1" f23c5480400921fb54442d18
d "fmove.w (a0), fp0" f2105000
d "fmove.s fp0, (a0)" f2106400
d "fmovecr 0xf, fp6" f2005f0f
d "fmove.l d0, fpcr" f2009000
d "fmove.l fpcr, d0" f200b000
d "fmove.l d0, fpsr" f2008800
d "fmove.l fpiar, d0" f200a400
d "fmovem (a0)+, fp6-fp7" f218d003
d "fmovem fp0-fp1, -(a0)" f220e003
d "move.l d0, d0" 2000
d "movea.l d0, a0" 2040
d "moveq 0x1, d0" 7001
d "movem.l d0-d1, (a0)" 48d00003
d "lea.l (a0), a0" 41d0
d "link.w a0, 0x4" 4e500004
d "pea.l (a0)" 4850
d "unlk a0" 4e58
d "tpf" 51fc
d "tpf.w 0x1234" 51fa1234
d "tpf.l 0x12345678" 51fb12345678
d "bra.l 0x12" 60ff00000010
d "bsr.l 0x12" 61ff00000010
d "bne.l 0x12" 66ff00000010
d "fnop" f2800000
d "fbf.w 0x12" f2800010
d "fbf.l 0x12" f2c000000010
d "fdbf d0, 0x14" f24800000010
d "fsf.b (a0)" f2500000
d "ftrapf" f27c0000
d "ftrapf.w 0x1234" f27a00001234
d "ftrapf.l 0x12345678" f27b000012345678
d "ftst fp1, fp2" f200053a
d "st.b d0" 50c0
d "jmp (a0)" 4ed0
d "jsr (a0)" 4e90
d "nop" 4e71
d "rts" 4e75
d "tas.b d0" 4ac0
d "tst.l d0" 4a80
d "sats.l d0" 4c80
d "mac.w d1l, d0l, acc0" a0010000
d "mac.w d1l, d0u, <<, acc0" a0010280
d "mac.l d2, d3, acc0" a6020800
d "mac.w a1l, a2u, (a3), d1, acc0" a293a089
d "mac.w a1l, a2u, (a3)&, d1, acc0" a293a0a9
d "mac.w a1l, a2u, <<, (a3), d1, acc0" a293a289
d "divs.l d0, d2" 4c402802
d "mac.l d2, d3, acc1" a6820800
d "divu.l d0, d1:d2" 4c402401
d "divs.l d0, d1:d2" 4c402c01
d "msac.w d1l, d0l, acc0" a0010100
d "msac.l d2, d3, acc0" a6020900
d "mac.w d2l, d0l, >>, acc0" a0020600
d "msac.w a1l, a2u, <<, (a3), d1, acc0" a293a389
d "mac.w a1l, a2u, >>, (a3), d1, acc0" a293a489
d "add.l d0, d0" d080
d "adda.l d0, a0" d1c0
d "addi.l 0x1, d0" 068000000001
d "addq.l 0x1, d0" 5280
d "addx.l d0, d0" d180
d "clr.l d0" 4280
d "cmp.l d0, d0" b080
d "cmpa.l d0, a0" b1c0
d "cmpi.l 0x1, d0" 0c8000000001
d "ext.l d0" 48c0
d "extb.l d0" 49c0
d "muls.w d0, d0" c1c0
d "mulu.w d0, d0" c0c0
d "neg.l d0" 4480
d "negx.l d0" 4080
d "remu.l d0, d1:d2" 4c402001
d "rems.l d0, d1:d2" 4c402801
d "sub.l d0, d0" 9080
d "suba.l d0, a0" 91c0
d "subi.l 0x1, d0" 048000000001
d "subq.l 0x1, d0" 5380
d "subx.l d0, d0" 9180
d "fsub fp2, fp4" f2000a28
d "fsadd fp1, fp2" f2000562
d "fdadd fp1, fp2" f2000566
d "fssub fp1, fp2" f2000568
d "fdsub fp1, fp2" f200056c
d "fsmul fp1, fp2" f2000563
d "fdmul fp1, fp2" f2000567
d "fsdiv fp1, fp2" f2000560
d "fddiv fp1, fp2" f2000564
d "fsneg fp1, fp2" f200055a
d "fdneg fp1, fp2" f200055e
d "fsabs fp1, fp2" f2000558
d "fdabs fp1, fp2" f200055c
d "fssqrt fp1, fp2" f2000541
d "fdsqrt fp1, fp2" f2000545
d "fint fp1, fp2" f2000501
d "fsinh fp1, fp2" f2000502
d "fintrz fp1, fp2" f2000503
d "fsqrt fp1, fp2" f2000504
d "flognp1 fp1, fp2" f2000506
d "fetoxm1 fp1, fp2" f2000508
d "fatanh fp1, fp2" f2000509
d "fatan fp1, fp2" f200050a
d "fasin fp1, fp2" f200050c
d "fsin fp1, fp2" f200050e
d "ftan fp1, fp2" f200050f
d "fetox fp1, fp2" f2000510
d "ftwotox fp1, fp2" f2000511
d "ftentox fp1, fp2" f2000512
d "flogn fp1, fp2" f2000514
d "flog10 fp1, fp2" f2000515
d "flog2 fp1, fp2" f2000516
d "fcosh fp1, fp2" f2000519
d "facos fp1, fp2" f200051c
d "fcos fp1, fp2" f200051d
d "fgetexp fp1, fp2" f200051e
d "fgetman fp1, fp2" f200051f
d "fdiv fp1, fp2" f2000520
d "fmod fp1, fp2" f2000521
d "fadd fp1, fp2" f2000522
d "fmul fp1, fp2" f2000523
d "fsgldiv fp1, fp2" f2000524
d "frem fp1, fp2" f2000525
d "fscale fp1, fp2" f2000526
d "fsglmul fp1, fp2" f2000527
d "fcmp fp1, fp2" f2000538
d "fabs fp1, fp2" f2000518
d "fneg fp1, fp2" f200051a
d "and.l d0, d0" c080
d "andi.l 0x1, d0" 028000000001
d "eor.l d0, d0" b180
d "eori.l 0x1, d0" 0a8000000001
d "not.l d0" 4680
d "or.l d0, d0" 8080
d "ori.l 0x1, d0" 008000000001
d "asl.l 0x8, d0" e180
d "asr.l 0x8, d0" e080
d "lsl.l 0x8, d0" e188
d "lsr.l 0x8, d0" e088
d "swap d0" 4840
d "bitrev d0" 00c0
d "byterev d1" 02c1
d "ff1 d2" 04c2
d "bchg.b d0, d0" 0140
d "bclr.b d0, d0" 0180
d "bset.b d0, d0" 01c0
d "btst.b d0, d0" 0100
d "move.l macsr, ccr" a9c0
d "halt" 4ac8
d "strldsr.w 0x4d2" 40e746fc04d2
d "wddata.b (a0)" fb10
d "wdebug.l (a0)" fbd00003
d "move.w ccr, d3" 42c3
d "move usp, a0" 4e68
d "move a0, usp" 4e60
d "pulse" 4acc
d "movec d0, cacr" 4e7b0002
d "movec cacr, d1" 4e7a1002
d "wddata.w (a0)" fb50
d "wddata.l (a0)" fb90
d "fsave (a0)" f310
d "frestore (a0)" f350
d "move.w d0, ccr" 44c0
d "move.w sr, d0" 40c0
d "move.w d0, sr" 46c0
d "illegal 0x4afc" 4afc
d "rte" 4e73
d "stop 0x2700" 4e722700
d "trap 0x0" 4e40
d "intouch (a0)" f428
d "cpushl bc, (a0)" f4e8
d "cp0bcbusy 0x52" fcc00050
d "cp0ld.l d0, d2, 0x1, 0x123" fc802123
d "cp0ld.w (a0), a2, 0x3, 0x1" fc50a401
d "cp0ld.b (a0)+, a2, 0x6, 0x1" fc18aa01
d "cp0ld.l 0x10(a0), a2, 0x8, 0x1" fca8ae010010
d "cp0st.l d2, d0, 0x1, 0x123" fd802123
d "cp0st.w a2, (a0), 0x3, 0x1" fd50a401
d "cp0nop 0x8" fc000e00
d "cp0nop 0x3" fc800400
d "cp0ld.l d0, d1, 0x3, 0x0" fc801400
d "cp1bcbusy 0x52" fec00050
d "cp1ld.l d0, d2, 0x1, 0x123" fe802123
d "cp1st.l d2, d0, 0x1, 0x123" ff802123
d "cp1nop 0x8" fe000e00
d "move.l accext01, d0" ab80 0x0 (seq (set src (var accext01)) (set d0 (cast 32 false (var src))))
test/db/asm/m68k_cpu32_32
+73 -7
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@@ -1,7 +1,73 @@
d "bgnd" 4afa
d "tblu.w (a0), d0" f8100140
d "tbls.l (a2), d3" f8123980
d "tblun.b (a1), d2" f8112500
d "tblsn.w (a4), d5" f8145d40
d "tblu.w d1:d2, d3" f8013042
d "tbls.b d4:d5, d6" f8046805
d "bgnd" 4afa 0x0 (seq (set trap_op (bv 32 0x5)) (goto m68k_trap))
d "lpstop 0x0" f80001c00000 0x0 (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege))
d "fbf.w 0x3" f2800001
d "fbeq.w 0x2" f2810000
d "fbogt.w 0x2" f2820000
d "fboge.w 0x2" f2830000
d "fbolt.w 0x2" f2840000
d "fbole.w 0x2" f2850000
d "fbogl.w 0x2" f2860000
d "fbor.w 0x2" f2870000
d "fbun.w 0x2" f2880000
d "fbueq.w 0x2" f2890000
d "fbugt.w 0x2" f28a0000
d "fbuge.w 0x2" f28b0000
d "fbult.w 0x2" f28c0000
d "fbule.w 0x2" f28d0000
d "fbne.w 0x2" f28e0000
d "fbt.w 0x2" f28f0000
d "fbf.l 0x3" f2c000000001
d "fbeq.l 0x3" f2c100000001
d "fbogt.l 0x3" f2c200000001
d "fboge.l 0x3" f2c300000001
d "fbolt.l 0x3" f2c400000001
d "fbole.l 0x3" f2c500000001
d "fbogl.l 0x3" f2c600000001
d "fbor.l 0x3" f2c700000001
d "fbun.l 0x3" f2c800000001
d "fbueq.l 0x3" f2c900000001
d "fbugt.l 0x3" f2ca00000001
d "fbuge.l 0x3" f2cb00000001
d "fbult.l 0x3" f2cc00000001
d "fbule.l 0x3" f2cd00000001
d "fbne.l 0x3" f2ce00000001
d "fbt.l 0x3" f2cf00000001
d "tblu.b d0:d0, d0" f8000000 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set entry0 (cast 64 false (cast 8 false (var d0)))) (set entry1 (cast 64 false (cast 8 false (var d0)))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.l d0:d0, d0" f8000080 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set entry0 (cast 64 false (var d0))) (set entry1 (cast 64 false (var d0))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.w d1:d2, d3" f8013042 0x0 (seq (set x (cast 16 false (var d3))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set entry0 (cast 64 false (cast 16 false (var d1)))) (set entry1 (cast 64 false (cast 16 false (var d2)))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d3 (| (& (var d3) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tbls.b d4:d5, d6" f8046805 0x0 (seq (set x (cast 16 false (var d6))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set entry0 (cast 64 (msb (cast 8 false (var d4))) (cast 8 false (var d4)))) (set entry1 (cast 64 (msb (cast 8 false (var d5))) (cast 8 false (var d5)))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d6 (| (& (var d6) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.b (a0), d0" f8100100 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.w (a0), d0" f8100140 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.l (a0), d0" f8100180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblun.b (a1), d2" f8112500 0x0 (seq (set x (cast 16 false (var d2))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a1))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set fixed (+ (<< (var entry0) (bv 8 0x8) false) (var prod))) (set res (cast 32 false (cast 16 false (var fixed)))) (set d2 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tbls.l (a2), d3" f8123980 0x0 (seq (set x (cast 16 false (var d3))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a2))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 (msb (loadw 0 32 (var entry_addr))) (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 (msb (loadw 0 32 (+ (var entry_addr) (bv 32 0x4)))) (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d3 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblsn.w (a4), d5" f8145d40 0x0 (seq (set x (cast 16 false (var d5))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a4))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 (msb (loadw 0 16 (var entry_addr))) (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 (msb (loadw 0 16 (+ (var entry_addr) (bv 32 0x2)))) (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set fixed (+ (<< (var entry0) (bv 8 0x8) false) (var prod))) (set res (cast 32 (msb (cast 24 false (var fixed))) (cast 24 false (var fixed)))) (set d5 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.b (a0)+, d0" f8180100 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x1)))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.w (a0)+, d0" f818017f 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x2)))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.l (a0)+, d0" f8180180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set a0 (cast 32 false (+ (var a0) (bv 32 0x4)))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.b -(a0), d0" f8200100 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x1)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.w -(a0), d0" f820017f 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x2)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.l -(a0), d0" f8200180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set a0 (cast 32 false (- (var a0) (bv 32 0x4)))) (set base (cast 32 false (var a0))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.b 0x17f(a0), d0" f8280100017f 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x17f))))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.w 0x180(a0), d0" f828017f0180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x180))))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.l 0x1ff(a0), d0" f828018001ff 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (cast 32 false (var a0)) (cast 32 false (bv 32 0x1ff))))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.b ([0x18001ff, a0], 0x8000fff), d0" f8300100017f018001ff08000fff 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (var a0) (bv 32 0x18001ff))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.w (d0.w), d0" f830017f0180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (+ (cast 32 false (bv 32 0x0)) (cast 32 false (bv 32 0x0))) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.l ([0x8000fff], 0x10001fff), d0" f830018001ff08000fff10001fff 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x8000fff))) (bv 32 0x0)) (bv 32 0x10001fff)))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.b 0x17f.w, d0" f8380100017f 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x17f))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.w 0x180.w, d0" f838017f0180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x180))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.l 0x1ff.w, d0" f838018001ff 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x1ff))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.b 0x17f0180.l, d0" f8390100017f0180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x17f0180))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.w 0x18001ff.l, d0" f839017f018001ff 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x18001ff))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.l 0x1ff0800.l, d0" f839018001ff0800 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x1ff0800))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.b 0x183(pc), d0" f83a0100017f 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x183))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.w 0x184(pc), d0" f83a017f0180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x184))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.l 0x203(pc), d0" f83a018001ff 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (bv 32 0x203))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.b ([0x1800203, pc], 0x8000fff), d0" f83b0100017f018001ff08000fff 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x2) (bv 32 0x1800201))) (bv 32 0x0)) (bv 32 0x8000fff)))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.w 0x4(pc, d0.w), d0" f83b017f0180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (bv 32 0x2) (cast 32 (msb (cast 16 false (var d0))) (cast 16 false (var d0)))))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.l ([0x8001003], 0x10001fff), d0" f83b018001ff08000fff10001fff 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (cast 32 false (+ (+ (loadw 0 32 (+ (bv 32 0x0) (bv 32 0x8001001))) (bv 32 0x0)) (bv 32 0x10001fff)))) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.b 0x7f, d0" f83c0100017f 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (bv 32 0x5)) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x1)))) (set entry0 (cast 64 false (loadw 0 8 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 8 (+ (var entry_addr) (bv 32 0x1))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 8 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffffff00)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 8 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.w 0x180, d0" f83c017f0180 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (bv 32 0x4)) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x2)))) (set entry0 (cast 64 false (loadw 0 16 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 16 (+ (var entry_addr) (bv 32 0x2))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 16 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (| (& (var d0) (bv 32 0xffff0000)) (cast 32 false (var res)))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 16 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "tblu.l 0x1ff0800, d0" f83c018001ff0800 0x0 (seq (set x (cast 16 false (var d0))) (set frac (cast 64 false (& (var x) (bv 16 0xff)))) (set base (bv 32 0x4)) (set index (cast 32 false (>> (& (var x) (bv 16 0xff00)) (bv 8 0x8) false))) (set entry_addr (+ (var base) (* (var index) (bv 32 0x4)))) (set entry0 (cast 64 false (loadw 0 32 (var entry_addr)))) (set entry1 (cast 64 false (loadw 0 32 (+ (var entry_addr) (bv 32 0x4))))) (set diff (- (var entry1) (var entry0))) (set prod (* (var diff) (var frac))) (set res (cast 32 false (+ (var entry0) (sdiv (ite (msb (var prod)) (- (var prod) (bv 64 0x80)) (+ (var prod) (bv 64 0x80))) (bv 64 0x100))))) (set d0 (cast 32 false (var res))) (set sr (| (& (var sr) (bv 16 0xff00)) (cast 16 false (cast 8 false (| (| (& (| (& (| (& (| (& (& (cast 8 false (var sr)) (bv 8 0xe0)) (bv 8 0xf7)) (<< (ite (msb (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x3) false)) (bv 8 0xfb)) (<< (ite (is_zero (cast 32 false (var res))) (bv 8 0x1) (bv 8 0x0)) (bv 8 0x2) false)) (bv 8 0xfd)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x1) false)) (bv 8 0xfe)) (<< (ite false (bv 8 0x1) (bv 8 0x0)) (bv 8 0x0) false)) (& (cast 8 false (var sr)) (bv 8 0x10))))))))
d "rte" 4e73 0x0 (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000)))) (seq (set rte_state (bv 8 0x1)) (set target (bv 32 0x0)) (repeat (== (var rte_state) (bv 8 0x1)) (seq (set frame (var a7)) (set new_sr (loadw 0 16 (var frame))) (set target (loadw 0 32 (+ (var frame) (bv 32 0x2)))) (set format (>> (loadw 0 16 (+ (var frame) (bv 32 0x6))) (bv 8 0xc) false)) (set frame_size (ite (== (var format) (bv 16 0xc)) (bv 32 0x18) (ite (== (var format) (bv 16 0x0)) (bv 32 0x8) (ite (== (var format) (bv 16 0x1)) (bv 32 0x8) (ite (== (var format) (bv 16 0x2)) (bv 32 0xc) (ite (== (var format) (bv 16 0x3)) (bv 32 0xc) (ite (== (var format) (bv 16 0x4)) (bv 32 0x10) (ite (== (var format) (bv 16 0x7)) (bv 32 0x3c) (ite (== (var format) (bv 16 0x8)) (bv 32 0x3a) (ite (== (var format) (bv 16 0x9)) (bv 32 0x14) (ite (== (var format) (bv 16 0xa)) (bv 32 0x20) (bv 32 0x5c)))))))))))) (branch (|| (&& (ule (var format) (bv 16 0x3)) (! (== (var format) (bv 16 0x3)))) (== (var format) (bv 16 0xc))) (seq (set a7 (cast 32 false (+ (var frame) (var frame_size)))) (set sr_write_value (cast 16 false (var new_sr))) (branch (! (== (ite (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))) (ite (is_zero (& (var sr_write_value) (bv 16 0x2000))) (bv 8 0x0) (ite (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (bv 8 0x2) (bv 8 0x1))))) (seq (branch (is_zero (& (cast 16 false (var sr)) (bv 16 0x2000))) (set usp (cast 32 false (var a7))) (branch (! (is_zero (& (cast 16 false (var sr)) (bv 16 0x0)))) (set msp (cast 32 false (var a7))) (set isp (cast 32 false (var a7))))) (branch (is_zero (& (var sr_write_value) (bv 16 0x2000))) (set a7 (cast 32 false (var usp))) (branch (! (is_zero (& (var sr_write_value) (bv 16 0x0)))) (set a7 (cast 32 false (var msp))) (set a7 (cast 32 false (var isp)))))) empty) (set sr (var sr_write_value)) (set rte_state (ite (== (var format) (bv 16 0x1)) (bv 8 0x1) (bv 8 0x0)))) (set rte_state (bv 8 0x2))))) (branch (== (var rte_state) (bv 8 0x0)) (jmp (var target)) (seq (set trap_op (bv 32 0xa)) (set trap_vector (bv 32 0xe)) (goto m68k_trap)))) (seq (set trap_op (bv 32 0x9)) (set trap_vector (bv 32 0x8)) (goto m68k_privilege)))
d "movem.l a0, -(a0)" 48e00080 0x0 (seq (set addr (var a0)) (set addr (- (var addr) (bv 32 0x4))) (storew 0 (var addr) (cast 32 false (cast 32 false (- (var a0) (bv 32 0x4))))) (set a0 (cast 32 false (var addr))))
test/db/cmd/cmd_aL
+1 -1
View File
@@ -35,7 +35,7 @@ _d___ 32 lm32 BSD Lattice Micro 32 ISA disassembler (by Felix
_dA__ 32 64 loongarch LGPL3 Loongson LoongArch disassembler
adA__ 32 luac LGPL3 Lua bytecode (LUAC) disassembler
_dA__ 8 32 m680x BSD Motorola 680X Capstone-based disassembler
_dA__ 32 m68k BSD Motorola 68K Capstone-based disassembler
_dA_I 32 m68k BSD Motorola 68K Capstone-based disassembler
_dA__ 32 malbolge LGPL3 Malbolge Ternary VM bytecode disassembler (by condret)
_dA__ 32 mcore LGPL3 Motorola MCORE disassembler
_dA__ 16 mcs96 LGPL3 Intel MCS-96 disassembler (by condret)
test/db/cmd/cmd_list
+6 -5
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File diff suppressed because one or more lines are too long
test/db/cmd/m68k
-31
View File
@@ -1,31 +0,0 @@
NAME="m68k: m68k filter"
FILE==
CMDS=<<EOF
e asm.arch=m68k
e asm.bits=32
wx 33fc010000a10000
pi 1
f foo.bar @ 0xa10000
pi 1
EOF
EXPECT=<<EOF
move.w 0x100, 0xa10000.l
move.w 0x100, foo.bar
EOF
RUN
NAME="m68k: m68k filter2"
FILE==
CMDS=<<EOF
e asm.arch=m68k
e asm.bits=32
wx 33fc010000a10000
pi 1
f foo.bar @ 0x100
pi 1
EOF
EXPECT=<<EOF
move.w 0x100, 0xa10000.l
move.w foo.bar, 0xa10000.l
EOF
RUN
test/db/formats/elf/core
+20 -11
View File
@@ -1116,6 +1116,14 @@ NAME=core regs linux m68k
FILE=bins/elf/core/core-linux-m68k
CMDS=<<EOF
ar
ar fp0
ar fp1
ar fp2
ar fp3
ar fp4
ar fp5
ar fp6
ar fp7
ar ccr
EOF
EXPECT=<<EOF
@@ -1136,21 +1144,12 @@ a5 = 0xc01ab150
a6 = 0xef903514
a7 = 0xef903508
pc = 0x800005b2
fp0 = 0x00000000
fp1 = 0x00000000
fp2 = 0x00000000
fp3 = 0x00000000
fp4 = 0x00000000
fp5 = 0x00000000
fp6 = 0x00000000
fp7 = 0x00000000
fpcr = 0x00000000
fpsr = 0x00000000
fpiar = 0x00000000
sr = 0x0000
sfc = 0x00000000
dfc = 0x00000000
usp = 0xef903508
vbr = 0x00000000
cacr = 0x00000000
caar = 0x00000000
@@ -1163,10 +1162,10 @@ dtt0 = 0x00000000
dtt1 = 0x00000000
mmusr = 0x00000000
urp = 0x00000000
srp = 0x00000000
srp = 0x0000000000000000
tt0 = 0x00000000
tt1 = 0x00000000
crp = 0x00000000
crp = 0x0000000000000000
acc = 0x00000000
acc0 = 0x00000000
acc1 = 0x00000000
@@ -1176,6 +1175,16 @@ accext01 = 0x00000000
accext23 = 0x00000000
macsr = 0x00000000
mask = 0x00000000
usp = 0xef903508
cp_external_data = 0x00000000
fp0 = 0x00000000000000000000
fp1 = 0x00000000000000000000
fp2 = 0x00000000000000000000
fp3 = 0x00000000000000000000
fp4 = 0x00000000000000000000
fp5 = 0x00000000000000000000
fp6 = 0x00000000000000000000
fp7 = 0x00000000000000000000
ccr = 0x00
EOF
RUN
test/db/rzil/m68k
+3448
View File
File diff suppressed because it is too large Load Diff
test/unit/meson.build
+1 -1
View File
@@ -150,7 +150,7 @@ if get_option('enable_tests')
]
if capstone_dep.type_name() == 'internal'
tests += 'analysis_op'
tests += ['analysis_op', 'analysis_m68k']
endif
unit_test_env = environment()
test/unit/test_analysis_m68k.c
+682
View File
@@ -0,0 +1,682 @@
// SPDX-FileCopyrightText: 2026 RizinOrg <[email protected]>
// SPDX-License-Identifier: LGPL-3.0-only
#include <rz_analysis.h>
#include <rz_core.h>
#include "minunit.h"
/* Expected states follow M68000PRM, sections 4 and 5, and CFPRM, sections 3
* and 4. Test real encodings through the plugin, including its VAL and OPEX
* interfaces; IL snapshots alone do not check these values or execution. */
static RzCore *m68k_core_new(const char *cpu) {
rz_return_val_if_fail(cpu, NULL);
RzCore *core = rz_core_new();
if (!core) {
return NULL;
}
if (!rz_core_arch_configure(core, "m68k", 32, cpu, NULL, NULL) ||
!rz_io_open_at(core->io, "malloc://0x1000", RZ_PERM_RWX, 0, 0, NULL)) {
rz_core_free(core);
return NULL;
}
rz_config_set_b(core->config, "cfg.bigendian", true);
return core;
}
static bool m68k_decode(RzCore *core, RzAnalysisOp *op, const char *hex) {
rz_return_val_if_fail(core && op && hex, false);
ut8 bytes[32];
int size = rz_hex_str2bin(hex, bytes);
rz_analysis_op_init(op);
return size > 0 && rz_analysis_op(core->analysis, op, 0x100, bytes, size, RZ_ANALYSIS_OP_MASK_VAL | RZ_ANALYSIS_OP_MASK_OPEX) == size;
}
static bool m68k_value_reg(const RzAnalysisValue *value, const char *name, RzAnalysisValueAccess access) {
rz_return_val_if_fail(name, false);
mu_assert_notnull(value, "register value exists");
mu_assert_eq(value->type, RZ_ANALYSIS_VAL_REG, "register value type");
mu_assert_notnull(value->reg, "register exists");
mu_assert_streq(value->reg->name, name, "register name");
mu_assert_eq(value->access, access, "register access");
return true;
}
#if defined(RZ_CAPSTONE_HAS_M68K_FP_FORMATS) || defined(RZ_CAPSTONE_HAS_M68K_COLDFIRE)
static bool m68k_value_mem(const RzAnalysisValue *value, const char *base, int size, RzAnalysisValueAccess access) {
rz_return_val_if_fail(base, false);
mu_assert_notnull(value, "memory value exists");
mu_assert_eq(value->type, RZ_ANALYSIS_VAL_MEM, "memory value type");
mu_assert_notnull(value->reg, "base register exists");
mu_assert_streq(value->reg->name, base, "base register");
mu_assert_eq(value->memref, size, "memory access size");
mu_assert_eq(value->access, access, "memory access direction");
return true;
}
#endif
static bool m68k_opex_is(const RzAnalysisOp *op, const char *expected) {
rz_return_val_if_fail(op && expected, false);
mu_assert_notnull(op->opex, "operand metadata exists");
char *json = rz_structured_data_to_json(op->opex);
mu_assert_notnull(json, "operand metadata JSON");
bool equal = rz_json_string_eq(json, expected);
if (!equal) {
fprintf(stderr, "OPEX: %s\nExpected: %s\n", json, expected);
}
free(json);
return equal;
}
static bool test_m68k_hidden_fpu_destination(void) {
RzCore *core = m68k_core_new("68020");
mu_assert_notnull(core, "M68K core");
const char *encodings[] = {
"f2000025", "f2001fa5", /* frem fp0 / fp7 */
"f2000026", "f2001fa6", /* fscale fp0 / fp7 */
"f2000027", "f2001fa7", /* fsglmul fp0 / fp7 */
};
for (size_t i = 0; i < RZ_ARRAY_SIZE(encodings); i++) {
RzAnalysisOp op;
mu_assert_true(m68k_decode(core, &op, encodings[i]), "decode collapsed FPU instruction");
const char *reg = i % 2 ? "fp7" : "fp0";
mu_assert_eq(op.family, RZ_ANALYSIS_OP_FAMILY_FPU, "FPU family");
mu_assert_true(m68k_value_reg(op.src[0], reg, RZ_ANALYSIS_ACC_R), "collapsed source");
mu_assert_null(op.src[1], "one source");
mu_assert_true(m68k_value_reg(op.dst, reg, RZ_ANALYSIS_ACC_R | RZ_ANALYSIS_ACC_W), "hidden destination is read/write");
char *expected = rz_str_newf("{\"opex\":{\"operands\":[{\"type\":\"reg\",\"value\":\"%s\"},{\"type\":\"reg\",\"value\":\"%s\"}]}}", reg, reg);
mu_assert_notnull(expected, "expected operand metadata");
bool matches = m68k_opex_is(&op, expected);
free(expected);
mu_assert_true(matches, "materialized destination in OPEX");
rz_analysis_op_fini(&op);
}
RzAnalysisOp op;
mu_assert_true(m68k_decode(core, &op, "f2000522"), "fadd fp1, fp2");
mu_assert_true(m68k_value_reg(op.src[0], "fp1", RZ_ANALYSIS_ACC_R), "explicit source");
mu_assert_null(op.src[1], "no invented source");
mu_assert_true(m68k_value_reg(op.dst, "fp2", RZ_ANALYSIS_ACC_R | RZ_ANALYSIS_ACC_W), "explicit destination");
rz_analysis_op_fini(&op);
mu_assert_true(m68k_decode(core, &op, "f2000538"), "fcmp fp1, fp2");
mu_assert_true(m68k_value_reg(op.src[0], "fp1", RZ_ANALYSIS_ACC_R), "comparison first source");
mu_assert_true(m68k_value_reg(op.src[1], "fp2", RZ_ANALYSIS_ACC_R), "comparison second source");
mu_assert_null(op.src[2], "two comparison sources");
mu_assert_null(op.dst, "comparison does not write a data register");
rz_analysis_op_fini(&op);
const char *unary[] = { "f2000018", "f200003a" }; /* fabs fp0, ftst fp0 */
for (size_t i = 0; i < RZ_ARRAY_SIZE(unary); i++) {
mu_assert_true(m68k_decode(core, &op, unary[i]), "complete unary FPU instruction");
mu_assert_true(m68k_value_reg(op.src[0], "fp0", RZ_ANALYSIS_ACC_R), "unary source");
mu_assert_null(op.src[1], "no synthetic unary source");
if (i == 0) {
mu_assert_true(m68k_value_reg(op.dst, "fp0", RZ_ANALYSIS_ACC_R | RZ_ANALYSIS_ACC_W), "unary destination");
} else {
mu_assert_null(op.dst, "ftst has no destination");
}
mu_assert_true(m68k_opex_is(&op, "{\"opex\":{\"operands\":[{\"type\":\"reg\",\"value\":\"fp0\"}]}}"), "complete unary operand is not duplicated");
rz_analysis_op_fini(&op);
}
rz_core_free(core);
mu_end;
}
#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS
static bool test_m68k_fp_formats(void) {
RzCore *core = m68k_core_new("68040");
mu_assert_notnull(core, "M68K core");
RzAnalysisOp op;
mu_assert_true(m68k_decode(core, &op, "f23c48003fff00008000000000000000"), "extended immediate");
mu_assert_eq(op.family, RZ_ANALYSIS_OP_FAMILY_FPU, "extended FPU family");
mu_assert_true(m68k_value_reg(op.dst, "fp0", RZ_ANALYSIS_ACC_W), "extended destination");
mu_assert_true(m68k_opex_is(&op, "{\"opex\":{\"operands\":[{\"type\":\"fp_extended\",\"sign_exp\":16383,\"reserved\":0,\"significand\":9223372036854775808},{\"type\":\"reg\",\"value\":\"fp0\"}]}}"), "extended bits are retained");
rz_analysis_op_fini(&op);
mu_assert_true(m68k_decode(core, &op, "f23c4c00002500012345678901234567"), "packed immediate");
mu_assert_eq(op.family, RZ_ANALYSIS_OP_FAMILY_FPU, "packed FPU family");
mu_assert_true(m68k_value_reg(op.dst, "fp0", RZ_ANALYSIS_ACC_W), "packed destination");
mu_assert_true(m68k_opex_is(&op, "{\"opex\":{\"operands\":[{\"type\":\"fp_packed\",\"header\":2424833,\"fraction\":2541551402847782247},{\"type\":\"reg\",\"value\":\"fp0\"}]}}"), "packed bits are retained");
rz_analysis_op_fini(&op);
const char *loads[] = { "f2104800", "f2104c00" }; /* fmove.x/p (a0), fp0 */
for (size_t i = 0; i < RZ_ARRAY_SIZE(loads); i++) {
mu_assert_true(m68k_decode(core, &op, loads[i]), "extended/packed load");
mu_assert_eq(op.type, RZ_ANALYSIS_OP_TYPE_LOAD, "FP load type");
mu_assert_eq(op.direction, RZ_ANALYSIS_OP_DIR_READ, "FP load direction");
mu_assert_eq(op.refptr, 12, "FP memory representation occupies 12 bytes");
mu_assert_true(m68k_value_mem(op.src[0], "a0", 12, RZ_ANALYSIS_ACC_R), "FP load source");
mu_assert_true(m68k_value_reg(op.dst, "fp0", RZ_ANALYSIS_ACC_W), "FP load destination");
rz_analysis_op_fini(&op);
}
const char *stores[] = { "f2116c7b", "f2127d30" }; /* static -5 / dynamic d3 k-factor */
for (size_t i = 0; i < RZ_ARRAY_SIZE(stores); i++) {
mu_assert_true(m68k_decode(core, &op, stores[i]), "packed store");
mu_assert_eq(op.type, RZ_ANALYSIS_OP_TYPE_STORE, "k-factor is not the destination");
mu_assert_eq(op.direction, RZ_ANALYSIS_OP_DIR_WRITE, "packed store direction");
mu_assert_eq(op.refptr, 12, "packed store width");
mu_assert_true(m68k_value_reg(op.src[0], i ? "fp2" : "fp0", RZ_ANALYSIS_ACC_R), "packed source");
if (i) {
mu_assert_true(m68k_value_reg(op.src[1], "d3", RZ_ANALYSIS_ACC_R), "dynamic k-factor");
} else {
mu_assert_notnull(op.src[1], "static k-factor");
mu_assert_eq(op.src[1]->type, RZ_ANALYSIS_VAL_IMM, "static k-factor type");
mu_assert_eq(op.src[1]->imm, -5, "signed static k-factor");
mu_assert_eq(op.src[1]->access, RZ_ANALYSIS_ACC_R, "static k-factor access");
}
mu_assert_null(op.src[2], "only FP value and k-factor are sources");
mu_assert_true(m68k_value_mem(op.dst, i ? "a2" : "a1", 12, RZ_ANALYSIS_ACC_W), "packed memory destination");
rz_analysis_op_fini(&op);
}
rz_core_free(core);
mu_end;
}
#endif
static void m68k_reset(RzCore *core, ut32 d0, ut32 d1, ut16 sr) {
rz_return_if_fail(core);
RzReg *reg = rz_analysis_get_reg(core->analysis);
rz_reg_setv(reg, "pc", 0x100);
rz_reg_setv(reg, "d0", d0);
rz_reg_setv(reg, "d1", d1);
rz_reg_setv(reg, "a0", 0x400);
rz_reg_setv(reg, "a1", 0x500);
rz_reg_setv(reg, "a7", 0x800);
rz_reg_setv(reg, "sr", sr);
}
static bool m68k_step(RzCore *core, const char *hex) {
rz_return_val_if_fail(core && hex, false);
ut8 bytes[32];
int size = rz_hex_str2bin(hex, bytes);
ut64 pc = rz_reg_getv(rz_analysis_get_reg(core->analysis), "pc");
if (size <= 0 || !rz_io_write_at(core->io, pc, bytes, size)) {
return false;
}
RzAnalysisILVM *vm = rz_analysis_il_vm_new(core->analysis, rz_analysis_get_reg(core->analysis));
if (!vm) {
return false;
}
RzAnalysisILStepResult result = rz_analysis_il_vm_step(core->analysis, vm, rz_analysis_get_reg(core->analysis));
rz_analysis_il_vm_free(vm);
if (result != RZ_ANALYSIS_IL_STEP_RESULT_SUCCESS) {
fprintf(stderr, "M68K step %s at 0x%" PFMT64x ": result %d\n", hex, pc, result);
return false;
}
return true;
}
/* Bit n gives the condition's value for NZVC == n (M68000PRM table 3-19).
* This truth table is independent of the lifter's Boolean expressions. */
static const ut16 condition_truth[] = {
0xffff, 0x0000, 0x0505, 0xfafa, 0x5555, 0xaaaa, 0x0f0f, 0xf0f0,
0x3333, 0xcccc, 0x00ff, 0xff00, 0xcc33, 0x33cc, 0x0c03, 0xf3fc
};
static bool test_m68k_bcc_conditions(void) {
RzCore *core = m68k_core_new("68020");
mu_assert_notnull(core, "M68K core");
for (ut8 condition = 2; condition < 16; condition++) {
char hex[5];
snprintf(hex, sizeof(hex), "%02x10", 0x60 | condition);
for (ut8 flags = 0; flags < 16; flags++) {
m68k_reset(core, 0x12345678, 0, 0x2010 | flags);
mu_assert_true(m68k_step(core, hex), "Bcc executes");
bool taken = (condition_truth[condition] >> flags) & 1;
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "pc"), taken ? 0x112 : 0x102, "Bcc target or fallthrough");
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "sr"), 0x2010 | flags, "Bcc preserves SR");
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "d0"), 0x12345678, "Bcc preserves data register");
}
}
rz_core_free(core);
mu_end;
}
static bool test_m68k_scc_conditions(void) {
RzCore *core = m68k_core_new("68020");
mu_assert_notnull(core, "M68K core");
for (ut8 condition = 0; condition < 16; condition++) {
for (ut8 flags = 0; flags < 16; flags++) {
ut8 expected = (condition_truth[condition] >> flags) & 1 ? 0xff : 0;
for (int memory = 0; memory < 2; memory++) {
char hex[5];
snprintf(hex, sizeof(hex), "%02x%02x", 0x50 | condition, memory ? 0xd0 : 0xc0);
m68k_reset(core, 0x12345678, 0, 0x2010 | flags);
ut8 bytes[] = { 0xaa, 0x55 };
mu_assert_true(rz_io_write_at(core->io, 0x400, bytes, sizeof(bytes)), "initialize Scc memory");
mu_assert_true(m68k_step(core, hex), "Scc executes");
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "pc"), 0x102, "Scc advances PC");
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "sr"), 0x2010 | flags, "Scc preserves SR");
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "d0"), memory ? 0x12345678 : 0x12345600 | expected, "Scc only changes destination byte");
mu_assert_eq(rz_io_nread_at(core->io, 0x400, bytes, sizeof(bytes)), sizeof(bytes), "read Scc memory");
mu_assert_eq(bytes[0], memory ? expected : 0xaa, "Scc memory byte");
mu_assert_eq(bytes[1], 0x55, "Scc preserves adjacent memory");
}
}
}
rz_core_free(core);
mu_end;
}
static bool test_m68k_dbcc_conditions(void) {
RzCore *core = m68k_core_new("68020");
mu_assert_notnull(core, "M68K core");
for (ut8 condition = 0; condition < 16; condition++) {
char hex[9];
snprintf(hex, sizeof(hex), "%02xc8fffc", 0x50 | condition);
for (ut8 flags = 0; flags < 16; flags++) {
for (ut32 counter = 0; counter <= 2; counter += 2) {
m68k_reset(core, 0x12340000 | counter, 0, 0x2010 | flags);
mu_assert_true(m68k_step(core, hex), "DBcc executes");
bool satisfied = (condition_truth[condition] >> flags) & 1;
ut32 expected = satisfied ? counter : (ut16)(counter - 1);
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "d0"), 0x12340000 | expected, "DBcc decrements only the low word when false");
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "pc"), !satisfied && counter ? 0xfe : 0x104, "DBcc branch, expiry, or condition-true fallthrough");
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "sr"), 0x2010 | flags, "DBcc preserves SR");
}
}
}
rz_core_free(core);
mu_end;
}
static bool test_m68k_branch_widths_and_calls(void) {
const struct {
const char *cpu;
const char *hex;
ut32 target;
bool call;
} cases[] = {
{ "68000", "6010", 0x112, false },
{ "68000", "60f0", 0xf2, false },
{ "68000", "60000020", 0x122, false },
{ "68000", "6000ffe0", 0xe2, false },
{ "68020", "60ff00000040", 0x142, false },
{ "68020", "60ffffffffc0", 0xc2, false },
{ "68000", "6110", 0x112, true },
{ "68000", "61f0", 0xf2, true },
{ "68000", "61000020", 0x122, true },
{ "68000", "6100ffe0", 0xe2, true },
{ "68020", "61ff00000040", 0x142, true },
{ "68020", "61ffffffffc0", 0xc2, true },
{ "68000", "4ed0", 0x400, false }, /* jmp (a0) */
{ "68000", "4ef900000420", 0x420, false },
{ "68000", "4e90", 0x400, true }, /* jsr (a0) */
{ "68000", "4eb900000420", 0x420, true },
{ "68000", "4ebafffc", 0xfe, true }, /* PC-relative jsr */
{ "68000", "4eaf0004", 0x804, true }, /* target must use A7 before pushing */
#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE
{ "cfv4e", "6010", 0x112, false },
{ "cfv4e", "61ff00000040", 0x142, true },
{ "cfv1", "4e90", 0x400, true },
#endif
};
for (size_t i = 0; i < RZ_ARRAY_SIZE(cases); i++) {
RzCore *core = m68k_core_new(cases[i].cpu);
mu_assert_notnull(core, "M68K core");
m68k_reset(core, 0, 0, 0x201f);
mu_assert_true(m68k_step(core, cases[i].hex), "branch/call executes");
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "pc"), cases[i].target, "branch/call target");
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "sr"), 0x201f, "branch/call preserves SR");
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "a7"), cases[i].call ? 0x7fc : 0x800, "call pushes one longword");
if (cases[i].call) {
ut8 bytes[4];
ut32 next = 0x100 + strlen(cases[i].hex) / 2;
mu_assert_eq(rz_io_nread_at(core->io, 0x7fc, bytes, sizeof(bytes)), sizeof(bytes), "read return address");
mu_assert_eq(rz_read_be32(bytes), next, "big-endian return address follows the full instruction");
mu_assert_true(m68k_step(core, "4e75"), "RTS executes at call target");
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "pc"), next, "RTS returns to caller");
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "a7"), 0x800, "RTS restores stack pointer");
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "sr"), 0x201f, "RTS preserves SR");
}
rz_core_free(core);
}
mu_end;
}
static bool test_m68k_integer_results_and_flags(void) {
const struct {
const char *instruction;
const char *hex;
ut32 d0, d1;
ut16 sr;
ut32 result;
ut16 flags;
ut16 mask; /* Zero checks all SR bits; omit architecturally undefined flags. */
} cases[] = {
{ "move.b d1,d0", "1001", 0x12345678, 0x80, 0x201f, 0x12345680, 0x2018, 0 },
{ "move.w d1,d0", "3001", 0x12345678, 0, 0x201f, 0x12340000, 0x2014, 0 },
{ "move.l d1,d0", "2001", 0, 0x87654321, 0x201f, 0x87654321, 0x2018, 0 },
{ "moveq -1,d0", "70ff", 0, 0, 0x201f, 0xffffffff, 0x2018, 0 },
{ "add.b d1,d0 carry", "d001", 0x123400ff, 1, 0x2000, 0x12340000, 0x2015, 0 },
{ "add.w d1,d0 overflow", "d041", 0x12347fff, 1, 0x2010, 0x12348000, 0x200a, 0 },
{ "add.l d1,d0 carry", "d081", 0xffffffff, 1, 0x2000, 0, 0x2015, 0 },
{ "addi.w 1,d0", "06400001", 0x1234ffff, 0, 0x2000, 0x12340000, 0x2015, 0 },
{ "addq.l 1,d0", "5280", 0x7fffffff, 0, 0x2010, 0x80000000, 0x200a, 0 },
{ "sub.b d1,d0 borrow", "9001", 0x12340000, 1, 0x2000, 0x123400ff, 0x2019, 0 },
{ "sub.w d1,d0 overflow", "9041", 0x12348000, 1, 0x2010, 0x12347fff, 0x2002, 0 },
{ "sub.l d1,d0 zero", "9081", 1, 1, 0x201f, 0, 0x2004, 0 },
{ "subi.w 1,d0", "04400001", 0x12340000, 0, 0x2000, 0x1234ffff, 0x2019, 0 },
{ "subq.l 1,d0", "5380", 0, 0, 0x2000, 0xffffffff, 0x2019, 0 },
{ "cmp.w d1,d0 borrow", "b041", 1, 2, 0x2010, 1, 0x2019, 0 },
{ "cmp.w d1,d0 equal", "b041", 2, 2, 0x2010, 2, 0x2014, 0 },
{ "tst.b d0", "4a00", 0x12340000, 0, 0x201f, 0x12340000, 0x2014, 0 },
{ "and.l d1,d0", "c081", 0xf000000f, 0x0ffffff0, 0x201f, 0, 0x2014, 0 },
{ "or.l d1,d0", "8081", 0x80000000, 1, 0x201f, 0x80000001, 0x2018, 0 },
{ "eor.l d1,d0", "b380", 0x80000001, 0x80000000, 0x201f, 1, 0x2010, 0 },
{ "clr.b d0", "4200", 0x123456ff, 0, 0x201f, 0x12345600, 0x2014, 0 },
{ "neg.b d0 overflow", "4400", 0x12345680, 0, 0x2000, 0x12345680, 0x201b, 0 },
{ "neg.l d0 zero", "4480", 0, 0, 0x201f, 0, 0x2004, 0 },
{ "not.b d0", "4600", 0x123456ff, 0, 0x201f, 0x12345600, 0x2014, 0 },
{ "ext.w d0", "4880", 0x12340080, 0, 0x201f, 0x1234ff80, 0x2018, 0 },
{ "swap d0", "4840", 0x12345678, 0, 0x201f, 0x56781234, 0x2010, 0 },
{ "asl.w 1,d0 overflow", "e340", 0x12344000, 0, 0x2010, 0x12348000, 0x200a, 0 },
{ "lsl.w 1,d0 carry", "e348", 0x12348000, 0, 0x2000, 0x12340000, 0x2015, 0 },
{ "asr.w 1,d0", "e240", 0x12348001, 0, 0x2000, 0x1234c000, 0x2019, 0 },
{ "lsr.w 1,d0", "e248", 0x12348001, 0, 0x2000, 0x12344000, 0x2011, 0 },
{ "rol.w 1,d0", "e358", 0x12348000, 0, 0x2010, 0x12340001, 0x2011, 0 },
{ "ror.w 1,d0", "e258", 0x12340001, 0, 0x2010, 0x12348000, 0x2019, 0 },
{ "roxl.w 1,d0", "e350", 0x12340000, 0, 0x2010, 0x12340001, 0x2000, 0 },
{ "roxr.w 1,d0", "e250", 0x12340001, 0, 0x2000, 0x12340000, 0x2015, 0 },
{ "muls.w d1,d0", "c1c1", 0x1234fffe, 3, 0x201f, 0xfffffffa, 0x2018, 0 },
{ "mulu.w d1,d0", "c0c1", 0xffff, 2, 0x201f, 0x1fffe, 0x2010, 0 },
{ "divs.w d1,d0", "81c1", 0xfffffff9, 2, 0x201f, 0xfffffffd, 0x2018, 0 },
{ "divu.w d1,d0", "80c1", 7, 2, 0x201f, 0x00010003, 0x2010, 0 },
{ "divu.w quotient overflow", "80c1", 0x10000, 1, 0x2010, 0x10000, 0x2012, 0xfff3 },
};
RzCore *core = m68k_core_new("68020");
mu_assert_notnull(core, "M68K core");
for (size_t i = 0; i < RZ_ARRAY_SIZE(cases); i++) {
m68k_reset(core, cases[i].d0, cases[i].d1, cases[i].sr);
mu_assert_true(m68k_step(core, cases[i].hex), cases[i].instruction);
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "d0"), cases[i].result, cases[i].instruction);
ut16 mask = cases[i].mask ? cases[i].mask : UT16_MAX;
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "sr") & mask, cases[i].flags & mask, cases[i].instruction);
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "d1"), cases[i].d1, "source register is preserved");
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "pc"), 0x100 + strlen(cases[i].hex) / 2, "integer instruction advances PC");
}
rz_core_free(core);
mu_end;
}
static bool test_m68k_data_transfers(void) {
RzCore *core = m68k_core_new("68020");
mu_assert_notnull(core, "M68K core");
RzReg *reg = rz_analysis_get_reg(core->analysis);
m68k_reset(core, 0x8000, 0, 0x201f);
mu_assert_true(m68k_step(core, "3040"), "movea.w d0,a0");
mu_assert_eq(rz_reg_getv(reg, "a0"), 0xffff8000, "MOVEA sign extends a word");
mu_assert_eq(rz_reg_getv(reg, "sr"), 0x201f, "MOVEA preserves SR");
m68k_reset(core, 0, 0, 0x201f);
mu_assert_true(m68k_step(core, "41e8fffc"), "lea -4(a0),a0");
mu_assert_eq(rz_reg_getv(reg, "a0"), 0x3fc, "LEA computes address without loading memory");
mu_assert_eq(rz_reg_getv(reg, "sr"), 0x201f, "LEA preserves SR");
m68k_reset(core, 0x12345678, 0, 0x201f);
mu_assert_true(m68k_step(core, "20c0"), "move.l d0,(a0)+");
ut8 bytes[4];
mu_assert_eq(rz_io_nread_at(core->io, 0x400, bytes, sizeof(bytes)), sizeof(bytes), "read stored longword");
mu_assert_eq(rz_read_be32(bytes), 0x12345678, "MOVE stores big endian");
mu_assert_eq(rz_reg_getv(reg, "a0"), 0x404, "MOVE postincrement");
mu_assert_eq(rz_reg_getv(reg, "sr"), 0x2010, "MOVE store flags");
mu_assert_true(m68k_step(core, "2220"), "move.l -(a0),d1");
mu_assert_eq(rz_reg_getv(reg, "d1"), 0x12345678, "MOVE loads big endian");
mu_assert_eq(rz_reg_getv(reg, "a0"), 0x400, "MOVE predecrement");
m68k_reset(core, 0, 0, 0x201f);
mu_assert_true(m68k_step(core, "4850"), "pea (a0)");
mu_assert_eq(rz_reg_getv(reg, "a7"), 0x7fc, "PEA stack delta");
mu_assert_eq(rz_io_nread_at(core->io, 0x7fc, bytes, sizeof(bytes)), sizeof(bytes), "read pushed effective address");
mu_assert_eq(rz_read_be32(bytes), 0x400, "PEA pushes address");
mu_assert_eq(rz_reg_getv(reg, "sr"), 0x201f, "PEA preserves SR");
m68k_reset(core, 0, 0, 0x201f);
mu_assert_true(m68k_step(core, "4e50fff8"), "link a0,-8");
mu_assert_eq(rz_reg_getv(reg, "a0"), 0x7fc, "LINK frame pointer");
mu_assert_eq(rz_reg_getv(reg, "a7"), 0x7f4, "LINK reserves stack space");
mu_assert_true(m68k_step(core, "4e58"), "unlk a0");
mu_assert_eq(rz_reg_getv(reg, "a0"), 0x400, "UNLK restores frame pointer");
mu_assert_eq(rz_reg_getv(reg, "a7"), 0x800, "UNLK restores stack");
mu_assert_eq(rz_reg_getv(reg, "sr"), 0x201f, "LINK/UNLK preserve SR");
rz_core_free(core);
mu_end;
}
#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE
static bool m68k_opex_field(const RzAnalysisOp *op, size_t index, const char *key, const char *expected) {
rz_return_val_if_fail(op && key && expected, false);
mu_assert_notnull(op->opex, "operand metadata exists");
char *text = rz_structured_data_to_json(op->opex);
char *expected_text = rz_str_dup(expected);
mu_assert_notnull(text, "operand JSON");
mu_assert_notnull(expected_text, "expected JSON");
RzJson *json = rz_json_parse(text);
RzJson *expected_json = rz_json_parse(expected_text);
const RzJson *opex = json ? rz_json_get(json, "opex") : NULL;
const RzJson *operands = opex ? rz_json_get(opex, "operands") : NULL;
const RzJson *operand = operands ? rz_json_item(operands, index) : NULL;
const RzJson *field = operand ? operand->children.first : NULL;
while (field && (!field->key || strcmp(field->key, key))) {
field = field->next;
}
bool matches = field && expected_json && rz_json_eq(field, expected_json);
if (!matches) {
fprintf(stderr, "operand %zu %s: expected %s\n", index, key, expected);
}
rz_json_free(expected_json);
rz_json_free(json);
free(expected_text);
free(text);
return matches;
}
static bool test_m68k_coldfire_profiles(void) {
RzCore *core = m68k_core_new("68020");
mu_assert_notnull(core, "M68K core");
const RzAsmPlugin *plugin = rz_asm_plugin_current(core->rasm);
mu_assert_notnull(plugin, "M68K assembler plugin");
mu_assert_notnull(plugin->get_cpu_desc, "CPU descriptions callback");
char **descriptions = plugin->get_cpu_desc();
const char *cpus[] = { "cfv1", "cfv2", "cfv3", "cfv4", "cfv4e", "cfv5", "coldfire" };
for (size_t i = 0; i < RZ_ARRAY_SIZE(cpus); i++) {
bool listed = false;
for (size_t j = 0; descriptions[j]; j += 2) {
if (!strcmp(descriptions[j], cpus[i])) {
listed = descriptions[j + 1] && *descriptions[j + 1];
break;
}
}
mu_assert_true(listed, "ColdFire profile has a description");
mu_assert_true(rz_core_arch_configure(core, "m68k", 32, cpus[i], NULL, NULL), "select ColdFire profile");
RzAnalysisOp op;
mu_assert_true(m68k_decode(core, &op, "101f"), "MOVE.B (A7)+,D0 on ColdFire");
mu_assert_true(m68k_value_mem(op.src[0], "a7", 1, RZ_ANALYSIS_ACC_R), "byte load source");
rz_analysis_op_fini(&op);
m68k_reset(core, 0, 0, 0x2010);
mu_assert_true(m68k_step(core, "101f"), "byte load executes on selected CPU");
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "a7"), 0x801, "ColdFire A7 byte increment");
mu_assert_true(rz_core_arch_configure(core, "m68k", 32, "68020", NULL, NULL), "switch back to classic M68K");
m68k_reset(core, 0, 0, 0x2010);
mu_assert_true(m68k_step(core, "101f"), "byte load executes on classic CPU");
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "a7"), 0x802, "ColdFire mode does not leak into classic execution");
}
rz_core_free(core);
mu_end;
}
static bool test_m68k_coldfire_acc_copy(void) {
const char *cpus[] = { "coldfire", "cfv4e", "cfv5" };
/* Signed integer, unsigned integer, and fractional MACSR modes. */
const ut32 modes[] = { 0, 0x40, 0x20 };
for (size_t cpu = 0; cpu < RZ_ARRAY_SIZE(cpus); cpu++) {
RzCore *core = m68k_core_new(cpus[cpu]);
mu_assert_notnull(core, "ColdFire core");
RzReg *reg = rz_analysis_get_reg(core->analysis);
for (size_t mode = 0; mode < RZ_ARRAY_SIZE(modes); mode++) {
for (ut32 ev = 0; ev <= 1; ev++) {
m68k_reset(core, 0, 0, 0x201f);
rz_reg_setv(reg, "acc0", 0x12345678);
rz_reg_setv(reg, "acc1", 0);
rz_reg_setv(reg, "accext01", 1);
rz_reg_setv(reg, "macsr", 0x100 | modes[mode] | ev);
mu_assert_true(m68k_step(core, "a310"), "MOVE ACC0,ACC1 executes and releases its IL tree");
mu_assert_eq(rz_reg_getv(reg, "acc0"), 0x12345678, "source accumulator is preserved");
mu_assert_eq(rz_reg_getv(reg, "acc1"), 0x12345678, "destination accumulator is copied");
mu_assert_eq(rz_reg_getv(reg, "accext01"), 0x00010001, "accumulator extension is copied");
/* The value overflows 32-bit integer storage but fits fractional
* storage. EMAC recomputes EV; original MAC preserves it. PAV0
* remains set and is copied to PAV1 and V; N and Z are clear. */
ut32 expected_ev = cpu == 0 ? ev : (mode == 2 ? 0 : 1);
mu_assert_eq(rz_reg_getv(reg, "macsr"), 0x302 | modes[mode] | expected_ev, "MACSR after accumulator copy");
mu_assert_eq(rz_reg_getv(reg, "sr"), 0x201f, "accumulator copy preserves SR");
mu_assert_eq(rz_reg_getv(reg, "pc"), 0x102, "accumulator copy advances PC");
}
}
rz_core_free(core);
}
mu_end;
}
static bool test_m68k_coldfire_values(void) {
RzCore *core = m68k_core_new("cfv1");
mu_assert_notnull(core, "ColdFire core");
RzAnalysisOp op;
mu_assert_true(m68k_decode(core, &op, "a140"), "MOV3Q on CFv1");
mu_assert_eq(op.type, RZ_ANALYSIS_OP_TYPE_MOV, "MOV3Q type");
mu_assert_notnull(op.src[0], "MOV3Q immediate");
mu_assert_eq(op.src[0]->imm, UT32_MAX, "MOV3Q encodes minus one");
mu_assert_true(m68k_value_reg(op.dst, "d0", RZ_ANALYSIS_ACC_W), "MOV3Q destination");
rz_analysis_op_fini(&op);
const char *unary[] = { "00c0", "02c0", "04c0", "4c80" }; /* BITREV, BYTEREV, FF1, SATS */
for (size_t i = 0; i < RZ_ARRAY_SIZE(unary); i++) {
mu_assert_true(m68k_decode(core, &op, unary[i]), "ColdFire unary operation");
mu_assert_true(m68k_value_reg(op.src[0], "d0", RZ_ANALYSIS_ACC_R), "unary source");
mu_assert_true(m68k_value_reg(op.dst, "d0", RZ_ANALYSIS_ACC_R | RZ_ANALYSIS_ACC_W), "unary destination");
rz_analysis_op_fini(&op);
}
const char *casts[] = { "7100", "7180", "7110", "7190" }; /* MVS/MVZ from D0/(A0) */
for (size_t i = 0; i < RZ_ARRAY_SIZE(casts); i++) {
mu_assert_true(m68k_decode(core, &op, casts[i]), "ColdFire sign/zero extension");
mu_assert_eq(op.type, i < 2 ? RZ_ANALYSIS_OP_TYPE_CAST : RZ_ANALYSIS_OP_TYPE_LOAD, "cast or load type");
mu_assert_eq(op.sign, !(i % 2), "MVS is signed; MVZ is unsigned");
if (i < 2) {
mu_assert_true(m68k_value_reg(op.src[0], "d0", RZ_ANALYSIS_ACC_R), "cast source");
} else {
mu_assert_true(m68k_value_mem(op.src[0], "a0", 1, RZ_ANALYSIS_ACC_R), "cast memory source");
}
mu_assert_true(m68k_value_reg(op.dst, "d0", RZ_ANALYSIS_ACC_W), "cast destination");
rz_analysis_op_fini(&op);
}
mu_assert_true(m68k_decode(core, &op, "40e746fc24d2"), "STRLDSR");
mu_assert_eq(op.stackptr, -4, "STRLDSR stack delta");
mu_assert_notnull(op.src[0], "STRLDSR immediate");
mu_assert_eq(op.src[0]->imm, 0x24d2, "STRLDSR new SR");
mu_assert_true(m68k_value_reg(op.src[1], "sr", RZ_ANALYSIS_ACC_R), "STRLDSR reads old SR");
mu_assert_true(m68k_value_reg(op.dst, "sr", RZ_ANALYSIS_ACC_W), "STRLDSR writes SR");
rz_analysis_op_fini(&op);
const char *transfers[] = { "fc900000", "fd900000", "fe900000", "ff900000" };
for (size_t i = 0; i < RZ_ARRAY_SIZE(transfers); i++) {
mu_assert_true(m68k_decode(core, &op, transfers[i]), "coprocessor memory transfer");
if (i % 2) {
mu_assert_eq(op.type, RZ_ANALYSIS_OP_TYPE_STORE, "coprocessor store");
mu_assert_true(m68k_value_mem(op.dst, "a0", 4, RZ_ANALYSIS_ACC_W), "coprocessor store destination");
mu_assert_null(op.src[0], "coprocessor store has no CPU source");
} else {
mu_assert_eq(op.type, RZ_ANALYSIS_OP_TYPE_LOAD, "coprocessor load");
mu_assert_true(m68k_value_mem(op.src[0], "a0", 4, RZ_ANALYSIS_ACC_R), "coprocessor load source");
mu_assert_null(op.dst, "coprocessor load has no CPU destination");
}
rz_analysis_op_fini(&op);
}
mu_assert_true(rz_core_arch_configure(core, "m68k", 32, "cfv4e", NULL, NULL), "select EMAC");
mu_assert_true(m68k_decode(core, &op, "a1c0"), "MOVCLR");
mu_assert_true(m68k_value_reg(op.src[0], "acc0", RZ_ANALYSIS_ACC_R), "MOVCLR accumulator source");
mu_assert_true(m68k_value_reg(op.dst, "d0", RZ_ANALYSIS_ACC_W), "MOVCLR destination");
rz_analysis_op_fini(&op);
/* The flags are part of OPEX's numeric interface: lower=1, upper=2,
* left=4, right=8, masked memory=16. */
const char *macs[] = { "a293a2a9", "a293a4a9" };
for (size_t i = 0; i < RZ_ARRAY_SIZE(macs); i++) {
mu_assert_true(m68k_decode(core, &op, macs[i]), "MAC with register halves, shift, and masked load");
mu_assert_true(m68k_opex_field(&op, 0, "value", "\"a1\""), "MAC first register");
mu_assert_true(m68k_opex_field(&op, 0, "flags", "1"), "MAC lower half");
mu_assert_true(m68k_opex_field(&op, 1, "flags", "2"), "MAC upper half");
mu_assert_true(m68k_opex_field(&op, 2, "type", "\"shift\""), "MAC shift operand");
mu_assert_true(m68k_opex_field(&op, 2, "flags", i ? "8" : "4"), "MAC shift direction");
mu_assert_true(m68k_opex_field(&op, 3, "flags", "16"), "MAC masked memory");
mu_assert_true(m68k_value_reg(op.dst, "acc0", RZ_ANALYSIS_ACC_R | RZ_ANALYSIS_ACC_W), "MAC accumulator destination");
rz_analysis_op_fini(&op);
}
rz_core_free(core);
mu_end;
}
#endif
static bool test_m68k_address_metadata(void) {
RzCore *core = m68k_core_new("68020");
mu_assert_notnull(core, "M68K core");
const char *hex[] = { "20380000", "20387fff", "20388000", "2038fffc", "203912345678" };
const ut32 address[] = { 0, 0x7fff, 0xffff8000, 0xfffffffc, 0x12345678 };
for (size_t i = 0; i < RZ_ARRAY_SIZE(hex); i++) {
RzAnalysisOp op;
mu_assert_true(m68k_decode(core, &op, hex[i]), "absolute MOVE");
mu_assert_notnull(op.src[0], "absolute memory source");
mu_assert_true(op.src[0]->absolute, "absolute address");
mu_assert_eq(op.src[0]->base, address[i], "absolute address value");
mu_assert_eq(op.src[0]->delta, 0, "absolute address is not counted twice");
mu_assert_eq(op.src[0]->memref, 4, "absolute memory width");
#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE
char expected[16];
snprintf(expected, sizeof(expected), "%" PFMT32u, address[i]);
mu_assert_true(m68k_opex_field(&op, 0, "address", expected), "absolute address in OPEX");
#endif
rz_analysis_op_fini(&op);
}
const char *jumps[] = { "4ef8fffc", "4eb8fffc" }; /* JMP/JSR absolute short */
for (size_t i = 0; i < RZ_ARRAY_SIZE(jumps); i++) {
RzAnalysisOp op;
mu_assert_true(m68k_decode(core, &op, jumps[i]), "absolute-short jump/call");
mu_assert_eq(op.jump, 0xfffffffc, "analysis jump target is sign-extended");
rz_analysis_op_fini(&op);
m68k_reset(core, 0, 0, 0x2010);
mu_assert_true(m68k_step(core, jumps[i]), "absolute-short jump/call executes");
mu_assert_eq(rz_reg_getv(rz_analysis_get_reg(core->analysis), "pc"), 0xfffffffc, "analysis agrees with execution");
}
#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE
const char *indexed[] = { "20300122fff0ffe0", "20300133fffffff0ffffffe0" };
for (size_t i = 0; i < RZ_ARRAY_SIZE(indexed); i++) {
RzAnalysisOp op;
mu_assert_true(m68k_decode(core, &op, indexed[i]), "full-format preindexed MOVE");
mu_assert_true(m68k_value_mem(op.src[0], "a0", 4, RZ_ANALYSIS_ACC_R), "indexed memory source");
mu_assert_true(m68k_opex_field(&op, 0, "in_disp", "-16"), "signed base displacement");
mu_assert_true(m68k_opex_field(&op, 0, "out_disp", "-32"), "signed outer displacement");
/* Capstone's displacement-size metadata uses 0 for word, 1 for long. */
mu_assert_true(m68k_opex_field(&op, 0, "in_disp_size", i ? "1" : "0"), "base displacement size");
mu_assert_true(m68k_opex_field(&op, 0, "out_disp_size", i ? "1" : "0"), "outer displacement size");
rz_analysis_op_fini(&op);
}
#endif
rz_core_free(core);
mu_end;
}
int all_tests(void) {
mu_run_test(test_m68k_hidden_fpu_destination);
#ifdef RZ_CAPSTONE_HAS_M68K_FP_FORMATS
mu_run_test(test_m68k_fp_formats);
#endif
mu_run_test(test_m68k_bcc_conditions);
mu_run_test(test_m68k_scc_conditions);
mu_run_test(test_m68k_dbcc_conditions);
mu_run_test(test_m68k_branch_widths_and_calls);
mu_run_test(test_m68k_integer_results_and_flags);
mu_run_test(test_m68k_data_transfers);
#ifdef RZ_CAPSTONE_HAS_M68K_COLDFIRE
mu_run_test(test_m68k_coldfire_profiles);
mu_run_test(test_m68k_coldfire_acc_copy);
mu_run_test(test_m68k_coldfire_values);
#endif
mu_run_test(test_m68k_address_metadata);
return tests_passed != tests_run;
}
mu_main(all_tests)