The `RzFloat` changes fix or improve:
- binary80 explicit-integer-bit, pseudo-value, infinity, and NaN handling;
- binary16 conversions;
- gradual underflow and directed rounding;
- overflow, underflow, invalid-operation, and inexact exception reporting;
- exception propagation through nested conversions and arithmetic operations;
- binary80 fused multiply-add rounding, including reduced-precision and double-rounding edge cases;
- thread-local SoftFloat state, preventing rounding state from leaking between threads.
The `RzIL` changes add scoped binary80 precision support through `RzFloatRPrecision` and `FWITH_RPREC`. The supported precisions are 32, 64, and 80. Precision scopes restore the
previous thread-local SoftFloat state after successful evaluation and evaluation failures.
Runtime rounding modes are represented explicitly by dedicated pure opcodes:
- `FCONVERT_WITH_RMODE`
- `FROUND_WITH_RMODE`
- `FSQRT_WITH_RMODE`
- `FADD_WITH_RMODE`
- `FSUB_WITH_RMODE`
- `FMUL_WITH_RMODE`
- `FDIV_WITH_RMODE`
- `FMOD_WITH_RMODE`
Their rounding-mode operand is a 32-bit IL bitvector whose values correspond to `RzFloatRMode`: RNE, RNA, RTP, RTN, and RTZ. Invalid operand widths are rejected by validation,
while invalid runtime values cause evaluation to fail with an error.
Dedicated opcodes keep runtime-controlled floating-point expressions compact. This is useful for architectures whose rounding mode is selected from register state and avoids the
expression duplication caused by expanding every operation into nested `ITE` branches.
The new operations are supported by:
- construction, duplication, and destruction;
- type and operand validation;
- VM evaluation;
- plain, Unicode, and JSON exporters;
- graph output and opcode stringification.
`FEXCEPT` now emits a VM event only when the queried exception is present, while preserving exceptions raised by nested conversions and arithmetic operations.
* Update Capstone and add m68k ColdFire support
* Fix test 'core regs linux m68k'
* Add M68K ColdFire integration coverage
* Update Capstone v6 to version 6.0.0-Alpha9
* Refactor CPU mode detection to use case-insensitive string comparison
* Update Capstone next revision to 3df6ff0
* fix: memory leak rz_analysis_op_fini op->src
* fix: memory leak, replaced `rz_type_clone` with `rz_type_clone_shallow` to resolve the memory leak in `rz_type_free(type.callable)`
* fix: memory leak in try_create_var_global
* fix: memory leak in dwarf
* fix: remove redundant memset calls and add documentation for rz_type_clone_shallow
* Update librz/arch/op.c
Co-authored-by: Giovanni <[email protected]>
* fix: set free and free_user to NULL in vector copy when item_cpy is not provided
---------
Co-authored-by: Giovanni <[email protected]>
* refactor h8300 register handling and improve operand definitions
h8500: add h8500h/l support
* Fix operand references in H8300 assembly instructions and update operand width handling
* Add support for H8300 instruction formats with 32-bit immediate values
* Refactor H8300 instruction decoding and operand handling for improved clarity and maintainability
* Refactor H8300 instruction decoding to enhance CPU type handling and improve code clarity
* Add H8300L specific instruction decoding for MOVFPE and MOVTPE
* Refactor stack pointer handling for H8300 instruction set to support CPU type differentiation
* Add H8300H specific register profile to enhance CPU differentiation
* Refactor H8300 instruction handling to improve CPU type differentiation and clarity
* Enhance H8300 instruction handling for CPU type differentiation in post-increment and pre-decrement operations
* h8300: add explicit `inline` mark
* fix: format with clang-format-20
* fix: fix clang-format linter with rewrite '^#define.*/\*.*\\$'
* fix: update clang-format to version 20 in workflows and documentation
* fix: add SPDX license information to .git-blame-ignore-revs
* add h8/500 plugin stub
* refactor h8500 instruction parsing and disassembly logic
* fix: remove debug print statement from h8500 EA parsing
fix: correct plugin name from h8300 to h8500
add: new test case for h8500 disassembly
* refactor: improve operand parsing and disassembly logic for h8500
* refactor: update operand representation in h8500 EA parsing
* refactor: enhance operand definitions and add test cases for h8500 instructions
* fix: add h8500 disassembly plugin to command lists
* refactor: enhance H8500 instruction and operand structures for better parsing
* refactor: update H8500 instruction set with size suffixes and enhance operand handling
* Apply suggestion from @Copilot
Co-authored-by: Copilot <[email protected]>
* Apply suggestion from @Copilot
Co-authored-by: Copilot <[email protected]>
* refactor: update H8500 operand handling and address mode definitions for consistency
* refactor: update H8500 addressing flags and operand handling for consistency
* refactor: update H8500 immediate operand syntax to use '#' prefix for consistency
* refactor: update H8500 addressing modes and mnemonics for consistency
* refactor: add new H8500 instructions BNOT, BSET, BSR, and BTST with operand handling
* refactor: update H8500 opcode definitions and add new CLR and CMP instructions
* refactor: add DADD instruction to H8500 opcode definitions and update related tests
* fix: correct memory copy size in h8500_instruction_parse function
* refactor: add DIVXU, EXTS, and EXTU instructions to H8500 opcode definitions and update tests
* refactor: add JMP instruction to H8500 opcode definitions and update tests
* refactor: add JSR instruction to H8500 opcode definitions and update tests
* refactor: add LDC, LDM, and LINK instructions to H8500 opcode definitions and update tests
* Update librz/arch/isa/h8500/h8500.c
Co-authored-by: Copilot <[email protected]>
* Apply suggestion from @Copilot
Co-authored-by: Copilot <[email protected]>
* Apply suggestion from @Copilot
Co-authored-by: Copilot <[email protected]>
* refactor: update H8500 addressing mode and operand flags to use ut64 type
* refactor: update H8500 addressing modes and add MOV instruction test cases
* feat: add MOVFPE, MOVTPE, and MULXU instructions to H8500 opcode and assembly
* feat: add NEG, NOT, and NOP instructions to H8500 opcode and assembly
* feat: enhance H8500 opcode with new instructions and EA flags
* fix: change enum to typedef enum for addressing mode definition
* pjmp
* pjsr | prts
* rot*
* rt*
* scb
* sh*
* sleep | stc | stm
* sub*
* swap
* tas | trapa | trap/vs | tst
* fin disas
* fix header
* add h8500_reg_name function to retrieve register names
* implement H8500 instruction analysis and operand value extraction
* refactor H8500 addressing modes and operand definitions for clarity
* fix msvc 2017 build
* fmt
* fix: update description for H8500 disassembler plugin
* fix: cmd test
* fix: coff h8500 support
* add author and cpus
* fix: test cmd
* feat: add instruction operand string retrieval and new instruction test
* fix: change operand length type from size_t to int in h8500 instruction parsing functions
* feat: add dsub instruction and update operand syntax in h8500 assembly files
* feat: update h8500 opcode descriptions and add new branch instructions
* Fix coff permissions when rz_coff_perms_from_section_flags returns 0
* Fix missing op->size
* refactor: update addressing mode macros and improve operand handling in h8500
* Refactor assembly syntax for H8500 instructions
- Added spaces for better readability in the assembly instruction definitions.
- Updated the formatting of operand lists to include spaces around commas.
- Ensured consistency in the formatting of immediate values and register references.
- Adjusted the assembly test cases to reflect the new formatting style.
* fix: correct permissions for .drectve sections in COFF format
* feat: add initial test cases for h8500 registers and analysis
* fix: add comment to clarify H8300 machine definition in COFF specs
* fix: correct typo in expected output for h8500 analysis
* fix: update data type and constants for H8500 pattern checks
* fix: apply suggestion
* fix: update H8500 instruction encoding and address modes
* fix: add cmp.b and cmp.w instructions for H8500
* fix: refactor H8500 analysis for improved address mode handling
* fix: enhance H8500 analysis for improved operand handling and stack operations
* fix: improve operand handling in H8500 analysis for better instruction processing
* fix: update PJSR instruction format for H8500 and enhance CMP instruction handling
* fix: enhance H8500 function analysis with additional metadata for varfunc and leaffunc
* fix: add documentation and clarify PC-relative mode handling in H8500 instruction parsing
* fix: correct PJMP instruction format to include address dereferencing
* Update librz/arch/isa/h8500/h8500.c
Co-authored-by: Giovanni <[email protected]>
---------
Co-authored-by: Copilot <[email protected]>
Co-authored-by: wargio <[email protected]>
Co-authored-by: Giovanni <[email protected]>
* Add xtensa arch capstone plugin
* Remove xtensa-gnu
* fix: `asm.cpu` is not set correctly, when there is no “,” in asm plugin -> cpus
* fix core_disassembly when n_bytes==0
* fix xtensa_analyze_op_esil
* fix xtensa esil pc mod
* fix xtensa esil l32r
* fix xtensa esil call0
* fix xtensa esil extui
* fix xtensa esil store
* fix xtensa stack inc and ret
* keep `asm.cpu` when valid in cb_asmarch
* fix cb_asmarch
* fix max op size
* xtensa: add cpu select
* xtensa: mark PUSH POP
* xtensa: set src dst
* xtensa: set dir
* xtensa: fix stackframe
* bump capstone next f6f967961b913cf4fc1c6233f6cf42194a0938ca
* fix: tricore il and test
* Fix code scanning alert no. 1874: Multiplication result converted to larger type
* DWARF: Fix ANSI Escape Sequence Injection vulns via DWARF
* DWARF: Reduce one memory copy in rz_bin_dwarf_attr_string
* DWARF: move Doxygen of `rz_bin_dwarf_attr_string` from the header to the implementation
* Support for .zdebug_*
* Simplify macro.inc
* Fix ranges and loc, because it was using the wrong bigendian.
* - DW_TAG_ptr_to_member_type as Ptr type
- DW_TAG_unspecified_type as base type
* Fix union in struct
- `RZ_PROJECT_VERSION` 14
- Add `RzCallable`.has_unspecified_parameters
- Add `RzAnalysis`.debug_info
- Add `RzAnalysisVarStorageType` composite and `eval` `pending`
- Support for parse DWARF section "debug_loclists", "debug_ranges", "debug_rnglists"
- Partial support for eval DWARF expr_loc
- Support for anonymous Type, function variable, struct member
- Cache all DWARF information in `RzAnalysisDebugInfo` and remove `SDB` based caching.
- Add arm32, arm64, TriCore DWARF register name
- Fix same name basetype
billow