Implement V_LSHR_B64 (#3961)

This commit is contained in:
Marcin Mikołajczyk
2026-01-27 11:27:56 +01:00
committed by GitHub
parent 4ba0e62670
commit 1e059cac04
2 changed files with 9 additions and 0 deletions

View File

@@ -259,6 +259,7 @@ public:
void V_CVT_PK_I16_I32(const GcnInst& inst);
void V_CVT_PK_U8_F32(const GcnInst& inst);
void V_LSHL_B64(const GcnInst& inst);
void V_LSHR_B64(const GcnInst& inst);
void V_ALIGNBIT_B32(const GcnInst& inst);
void V_ALIGNBYTE_B32(const GcnInst& inst);
void V_MUL_F64(const GcnInst& inst);

View File

@@ -394,6 +394,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
return V_CVT_PK_U8_F32(inst);
case Opcode::V_LSHL_B64:
return V_LSHL_B64(inst);
case Opcode::V_LSHR_B64:
return V_LSHR_B64(inst);
case Opcode::V_ADD_F64:
return V_ADD_F64(inst);
case Opcode::V_ALIGNBIT_B32:
@@ -1357,6 +1359,12 @@ void Translator::V_LSHL_B64(const GcnInst& inst) {
SetDst64(inst.dst[0], ir.ShiftLeftLogical(src0, ir.BitwiseAnd(src1, ir.Imm64(u64(0x3F)))));
}
void Translator::V_LSHR_B64(const GcnInst& inst) {
const IR::U64 src0{GetSrc64(inst.src[0])};
const IR::U64 src1{GetSrc64(inst.src[1])};
SetDst64(inst.dst[0], ir.ShiftRightLogical(src0, ir.BitwiseAnd(src1, ir.Imm64(u64(0x3F)))));
}
void Translator::V_ALIGNBIT_B32(const GcnInst& inst) {
const IR::U32 src0{GetSrc(inst.src[0])};
const IR::U32 src1{GetSrc(inst.src[1])};