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Implement V_LSHR_B64 (#3961)
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1e059cac04
@@ -259,6 +259,7 @@ public:
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void V_CVT_PK_I16_I32(const GcnInst& inst);
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void V_CVT_PK_U8_F32(const GcnInst& inst);
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void V_LSHL_B64(const GcnInst& inst);
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void V_LSHR_B64(const GcnInst& inst);
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void V_ALIGNBIT_B32(const GcnInst& inst);
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void V_ALIGNBYTE_B32(const GcnInst& inst);
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void V_MUL_F64(const GcnInst& inst);
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@@ -394,6 +394,8 @@ void Translator::EmitVectorAlu(const GcnInst& inst) {
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return V_CVT_PK_U8_F32(inst);
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case Opcode::V_LSHL_B64:
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return V_LSHL_B64(inst);
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case Opcode::V_LSHR_B64:
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return V_LSHR_B64(inst);
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case Opcode::V_ADD_F64:
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return V_ADD_F64(inst);
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case Opcode::V_ALIGNBIT_B32:
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@@ -1357,6 +1359,12 @@ void Translator::V_LSHL_B64(const GcnInst& inst) {
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SetDst64(inst.dst[0], ir.ShiftLeftLogical(src0, ir.BitwiseAnd(src1, ir.Imm64(u64(0x3F)))));
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}
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void Translator::V_LSHR_B64(const GcnInst& inst) {
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const IR::U64 src0{GetSrc64(inst.src[0])};
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const IR::U64 src1{GetSrc64(inst.src[1])};
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SetDst64(inst.dst[0], ir.ShiftRightLogical(src0, ir.BitwiseAnd(src1, ir.Imm64(u64(0x3F)))));
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}
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void Translator::V_ALIGNBIT_B32(const GcnInst& inst) {
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const IR::U32 src0{GetSrc(inst.src[0])};
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const IR::U32 src1{GetSrc(inst.src[1])};
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