target/avr: Add instruction translation - Arithmetic and Logic Instructions
This includes:
- ADD, ADC, ADIW
- SBIW, SUB, SUBI, SBC, SBCI
- AND, ANDI
- OR, ORI, EOR
- COM, NEG
- INC, DEC
- MUL, MULS, MULSU
- FMUL, FMULS, FMULSU
- DES
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-12-huth@tuxfamily.org>
[PMD: Added qemu_log_mask(LOG_UNIMP) in trans_DES()]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-01-24 00:51:10 +00:00
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#
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# AVR instruction decode definitions.
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#
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# Copyright (c) 2019-2020 Michael Rolnik <mrolnik@gmail.com>
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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#
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# regs_16_31_by_one = [16 .. 31]
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# regs_16_23_by_one = [16 .. 23]
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# regs_24_30_by_two = [24, 26, 28, 30]
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# regs_00_30_by_two = [0, 2, 4, 6, 8, .. 30]
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%rd 4:5
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%rr 9:1 0:4
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%rd_a 4:4 !function=to_regs_16_31_by_one
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%rd_b 4:3 !function=to_regs_16_23_by_one
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%rd_c 4:2 !function=to_regs_24_30_by_two
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%rr_a 0:4 !function=to_regs_16_31_by_one
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%rr_b 0:3 !function=to_regs_16_23_by_one
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%imm6 6:2 0:4
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%imm8 8:4 0:4
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%io_imm 9:2 0:4
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%ldst_d_imm 13:1 10:2 0:3
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&rd_rr rd rr
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&rd_imm rd imm
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@op_rd_rr .... .. . ..... .... &rd_rr rd=%rd rr=%rr
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@op_rd_imm6 .... .... .. .. .... &rd_imm rd=%rd_c imm=%imm6
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@op_rd_imm8 .... .... .... .... &rd_imm rd=%rd_a imm=%imm8
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@fmul .... .... . ... . ... &rd_rr rd=%rd_b rr=%rr_b
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#
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# Arithmetic Instructions
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#
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ADD 0000 11 . ..... .... @op_rd_rr
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ADC 0001 11 . ..... .... @op_rd_rr
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ADIW 1001 0110 .. .. .... @op_rd_imm6
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SUB 0001 10 . ..... .... @op_rd_rr
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SUBI 0101 .... .... .... @op_rd_imm8
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SBC 0000 10 . ..... .... @op_rd_rr
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SBCI 0100 .... .... .... @op_rd_imm8
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SBIW 1001 0111 .. .. .... @op_rd_imm6
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AND 0010 00 . ..... .... @op_rd_rr
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ANDI 0111 .... .... .... @op_rd_imm8
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OR 0010 10 . ..... .... @op_rd_rr
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ORI 0110 .... .... .... @op_rd_imm8
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EOR 0010 01 . ..... .... @op_rd_rr
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COM 1001 010 rd:5 0000
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NEG 1001 010 rd:5 0001
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INC 1001 010 rd:5 0011
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DEC 1001 010 rd:5 1010
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MUL 1001 11 . ..... .... @op_rd_rr
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MULS 0000 0010 .... .... &rd_rr rd=%rd_a rr=%rr_a
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MULSU 0000 0011 0 ... 0 ... @fmul
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FMUL 0000 0011 0 ... 1 ... @fmul
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FMULS 0000 0011 1 ... 0 ... @fmul
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FMULSU 0000 0011 1 ... 1 ... @fmul
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DES 1001 0100 imm:4 1011
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target/avr: Add instruction translation - Branch Instructions
This includes:
- RJMP, IJMP, EIJMP, JMP
- RCALL, ICALL, EICALL, CALL
- RET, RETI
- CPSE, CP, CPC, CPI
- SBRC, SBRS, SBIC, SBIS
- BRBC, BRBS
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-13-huth@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-01-24 00:51:11 +00:00
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#
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# Branch Instructions
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#
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# The 22-bit immediate is partially in the opcode word,
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# and partially in the next. Use append_16 to build the
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# complete 22-bit value.
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%imm_call 4:5 0:1 !function=append_16
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@op_bit .... .... . bit:3 ....
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@op_bit_imm .... .. imm:s7 bit:3
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RJMP 1100 imm:s12
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IJMP 1001 0100 0000 1001
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EIJMP 1001 0100 0001 1001
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JMP 1001 010 ..... 110 . imm=%imm_call
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RCALL 1101 imm:s12
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ICALL 1001 0101 0000 1001
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EICALL 1001 0101 0001 1001
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CALL 1001 010 ..... 111 . imm=%imm_call
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RET 1001 0101 0000 1000
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RETI 1001 0101 0001 1000
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CPSE 0001 00 . ..... .... @op_rd_rr
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CP 0001 01 . ..... .... @op_rd_rr
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CPC 0000 01 . ..... .... @op_rd_rr
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CPI 0011 .... .... .... @op_rd_imm8
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SBRC 1111 110 rr:5 0 bit:3
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SBRS 1111 111 rr:5 0 bit:3
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SBIC 1001 1001 reg:5 bit:3
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SBIS 1001 1011 reg:5 bit:3
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BRBS 1111 00 ....... ... @op_bit_imm
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BRBC 1111 01 ....... ... @op_bit_imm
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target/avr: Add instruction translation - Data Transfer Instructions
This includes:
- MOV, MOVW
- LDI, LDS LDX LDY LDZ
- LDDY, LDDZ
- STS, STX STY STZ
- STDY, STDZ
- LPM, LPMX
- ELPM, ELPMX
- SPM, SPMX
- IN, OUT
- PUSH, POP
- XCH
- LAS, LAC LAT
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-14-huth@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2020-01-24 00:51:12 +00:00
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#
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# Data Transfer Instructions
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#
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%rd_d 4:4 !function=to_regs_00_30_by_two
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%rr_d 0:4 !function=to_regs_00_30_by_two
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@io_rd_imm .... . .. ..... .... &rd_imm rd=%rd imm=%io_imm
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@ldst_d .. . . .. . rd:5 . ... &rd_imm imm=%ldst_d_imm
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# The 16-bit immediate is completely in the next word.
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# Fields cannot be defined with no bits, so we cannot play
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# the same trick and append to a zero-bit value.
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# Defer reading the immediate until trans_{LDS,STS}.
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@ldst_s .... ... rd:5 .... imm=0
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MOV 0010 11 . ..... .... @op_rd_rr
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MOVW 0000 0001 .... .... &rd_rr rd=%rd_d rr=%rr_d
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LDI 1110 .... .... .... @op_rd_imm8
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LDS 1001 000 ..... 0000 @ldst_s
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LDX1 1001 000 rd:5 1100
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LDX2 1001 000 rd:5 1101
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LDX3 1001 000 rd:5 1110
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LDY2 1001 000 rd:5 1001
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LDY3 1001 000 rd:5 1010
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LDZ2 1001 000 rd:5 0001
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LDZ3 1001 000 rd:5 0010
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LDDY 10 . 0 .. 0 ..... 1 ... @ldst_d
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LDDZ 10 . 0 .. 0 ..... 0 ... @ldst_d
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STS 1001 001 ..... 0000 @ldst_s
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STX1 1001 001 rr:5 1100
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STX2 1001 001 rr:5 1101
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STX3 1001 001 rr:5 1110
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STY2 1001 001 rd:5 1001
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STY3 1001 001 rd:5 1010
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STZ2 1001 001 rd:5 0001
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STZ3 1001 001 rd:5 0010
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STDY 10 . 0 .. 1 ..... 1 ... @ldst_d
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STDZ 10 . 0 .. 1 ..... 0 ... @ldst_d
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LPM1 1001 0101 1100 1000
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LPM2 1001 000 rd:5 0100
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LPMX 1001 000 rd:5 0101
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ELPM1 1001 0101 1101 1000
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ELPM2 1001 000 rd:5 0110
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ELPMX 1001 000 rd:5 0111
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SPM 1001 0101 1110 1000
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SPMX 1001 0101 1111 1000
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IN 1011 0 .. ..... .... @io_rd_imm
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OUT 1011 1 .. ..... .... @io_rd_imm
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PUSH 1001 001 rd:5 1111
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POP 1001 000 rd:5 1111
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XCH 1001 001 rd:5 0100
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LAC 1001 001 rd:5 0110
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LAS 1001 001 rd:5 0101
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LAT 1001 001 rd:5 0111
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2020-01-24 00:51:13 +00:00
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#
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# Bit and Bit-test Instructions
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#
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LSR 1001 010 rd:5 0110
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ROR 1001 010 rd:5 0111
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ASR 1001 010 rd:5 0101
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SWAP 1001 010 rd:5 0010
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SBI 1001 1010 reg:5 bit:3
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CBI 1001 1000 reg:5 bit:3
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BST 1111 101 rd:5 0 bit:3
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BLD 1111 100 rd:5 0 bit:3
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BSET 1001 0100 0 bit:3 1000
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BCLR 1001 0100 1 bit:3 1000
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2020-01-24 00:51:14 +00:00
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#
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# MCU Control Instructions
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#
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BREAK 1001 0101 1001 1000
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NOP 0000 0000 0000 0000
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SLEEP 1001 0101 1000 1000
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WDR 1001 0101 1010 1000
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