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25,620 Commits 70 Branches 122 Tags 688 MiB
280f7fec39
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Author SHA1 Message Date
LunaMoo
280f7fec39 Fix VS2019 builds and remove _xp dependency 
(drops Win XP support, allows latest SDK etc.)
 2019-04-25 23:56:55 +02:00
Henrik Rydgård
d15a6cf6bf
Merge pull request #11990 from m4xw/master 
Band-Aid for libretro Savestate load
 2019-04-24 11:00:47 +02:00
M4xw
00bf914ce4 Band-Aid for libretro Savestate load 
Proper would be using PPSSPP's Queue.
This will need frontend extensions to do it sanely.
Fixes #11429 (mitigate for now)
 2019-04-23 17:35:24 +02:00
Henrik Rydgård
f6fe917615 Update gradle stuff again 2019-04-21 11:10:31 +02:00
Henrik Rydgård
091c475fec
Merge pull request #11970 from itstake/master 
Added IO Timing Method option for RetroArch PPSSPP Core.
 2019-04-20 17:22:31 +02:00
ITSTAKE
f7aed9a754
Fix typo again 2019-04-20 18:02:09 +09:00
Unknown W. Brackets
8d4ab57b46 Oops, got these backwards. 
Surprising this didn't break as much as expected.  Mostly broke the 60 FPS
limit hack.
 2019-04-16 17:36:29 -07:00
Henrik Rydgård
40f1542798 Update ffmpeg and lang submodules 2019-04-16 21:21:52 +02:00
Henrik Rydgård
dcd2ff03b0
Merge pull request #11971 from unknownbrackets/power 
Correct cpu/pll/bus hz update and rescheduling
 2019-04-16 09:41:43 +02:00
ITSTAKE
5ee7d73be8
Fix typo 2019-04-15 14:07:19 +00:00
Henrik Rydgård
057e720b28
Merge pull request #11972 from m4xw/aarch64_masking 
Masked PSP Memory support for the AArch64 Dynarec
 2019-04-15 12:43:40 +02:00
M4xw
b9352354c9 Masked PSP Memory support for the AArch64 Dynarec 2019-04-15 12:07:57 +02:00
Unknown W. Brackets
ad299ca92d Power: Match reschedule timing better. 2019-04-14 15:06:32 -07:00
Unknown W. Brackets
bc4a203fcf Power: Correct hz on update and improve resched. 
It only reschedules when the PLL changes, which changes in steps.  This
also reads back much more accurate Mhz for each of PLL, CPU, and bus.
 2019-04-14 14:51:35 -07:00
ITSTAKE
f038573d48
Added IO Timing Method option. 2019-04-13 19:31:10 +09:00
Henrik Rydgård
54e102cfad
Merge pull request #11965 from psyberpunk/master 
Update controller data base ps3 clone controller
 2019-04-10 21:06:02 +02:00
psyberpunk
d79d829a1d
Update controller data base ps3 clone controller 
Update controller data base ps3 clone controller
 2019-04-10 08:51:47 -05:00
Henrik Rydgård
b56c66e889
Merge pull request #11964 from unknownbrackets/gpu-stencil-blend 
GPU: Improve non dual source stencil replace
 2019-04-08 01:06:54 +02:00
Unknown W. Brackets
00d088ab58 GPU: Improve non dual source stencil replace. 
If we're replacing with a constant FF, we can make it work more often.
Fixes #11249.
 2019-04-07 15:20:56 -07:00
Henrik Rydgård
b5db387bfb
Merge pull request #11948 from unknownbrackets/vfpu 
Make vfad/vavg/vtfm ops more accurate
 2019-04-04 09:31:20 +02:00
Unknown W. Brackets
ec7cffa847 interp: Handle vtfm/vhtfm prefixes properly. 2019-04-02 18:46:39 -07:00
Unknown W. Brackets
442d6450bb interp: Correct prefixes on vfad and vavg. 
Including write mask, which didn't work before.
 2019-04-02 18:46:39 -07:00
Henrik Rydgård
4d580c32c4
Merge pull request #11959 from unknownbrackets/vfpu-chunk8 
Improve prefixes for vwbn/vlgb/vmin/vmax/vqmul/vcrsp and 2 ops
 2019-04-02 23:45:02 +02:00
Unknown W. Brackets
5414c12a15 interp: Cleanup prefix/size in vcrsp/vqmul. 2019-04-02 07:12:34 -07:00
Unknown W. Brackets
58573cd4b4 interp: Handle invalid swizzle for vmin/vmax. 2019-04-02 07:08:33 -07:00
Unknown W. Brackets
e8c060bb5f interp: Correct vwbn and vlgb size behavior. 2019-04-02 07:08:20 -07:00
Unknown W. Brackets
89dbfd7d5b interp: Better prefixes for vdiv/similar ops. 
Turns out it does work, just uses the wrong slot like S/T after all.
These other ops must go through the a similar process.
 2019-04-02 07:07:53 -07:00
Henrik Rydgård
24cfad87d1
Merge pull request #11955 from unknownbrackets/vfpu-chunk6 
Correct prefixes for several swizzled ops, use zero for invalid
 2019-04-01 17:13:34 +02:00
Henrik Rydgård
b346142df8
Merge pull request #11954 from unknownbrackets/vfpu-chunk5 
Fix prefix and size handling for vsbx, vsocp, and integer conv ops
 2019-04-01 17:12:03 +02:00
Henrik Rydgård
3eaead8af1
Merge pull request #11956 from unknownbrackets/vfpu-chunk7 
Correct vmfvc/vmtvc decoding, prefixes on vsgn, vdot, vhdp, and matrix init
 2019-04-01 17:09:46 +02:00
Henrik Rydgård
8434ac037c
Merge pull request #11952 from unknownbrackets/vfpu-chunk4 
Fix vmfvc, vfim -nan, and improve size/swizzle on vh2f/vf2h/vrnds/vdiv
 2019-04-01 14:14:28 +02:00
Unknown W. Brackets
6f87987e7b interp: Correct prefixes on vdot/vhdp. 2019-03-31 17:12:21 -07:00
Unknown W. Brackets
b24f84d1a2 interp: Handle prefixes on matrix init ops. 2019-03-31 17:11:24 -07:00
Unknown W. Brackets
59905de719 interp: Correct vsgn out of swizzle bounds. 2019-03-31 17:10:51 -07:00
Unknown W. Brackets
85ff32eed1 interp: Handle vsgn prefixing. 
One could compare against 3 using this, it just generates zeros to compare
with.
 2019-03-31 17:10:51 -07:00
Unknown W. Brackets
a5214d0b1a Jit: Ignore high bit in vmfvc/vmtvc. 2019-03-31 17:09:55 -07:00
Unknown W. Brackets
b881a689c4 interp: Ignore high bit in vmfvc/vmtvc. 
Both 0 and 128 read/write the S prefix, for example.
 2019-03-31 17:09:55 -07:00
Unknown W. Brackets
dffa238611 interp: Handle invalid swizzle in vsge/vslt. 2019-03-31 15:05:43 -07:00
Unknown W. Brackets
dfd8094f21 interp: Implement vcrs prefixes and sizes. 
It only makes sense as triple, but it can be used as quad/single/etc. and
has consistent and sane results.
 2019-03-31 15:05:15 -07:00
Unknown W. Brackets
fa7ac7bc64 interp: Correct simple vmov variant prefixing. 2019-03-31 15:01:28 -07:00
Unknown W. Brackets
01aebe54b9 interp: Correct vdet prefix handling. 2019-03-31 15:01:11 -07:00
Unknown W. Brackets
cc58d0d3a3 interp: Correct prefixes in vsrt ops. 2019-03-31 15:00:12 -07:00
Unknown W. Brackets
f2be0cb083 interp: Correct prefixes for vsbn/vsbz. 2019-03-31 13:52:59 -07:00
Unknown W. Brackets
175ceef583 interp: Cleanup vsocp size handling. 2019-03-31 13:52:07 -07:00
Unknown W. Brackets
4a2f8a74dc interp: Correct size handling for vi2x ops. 2019-03-31 13:51:12 -07:00
Unknown W. Brackets
b75690787e interp: Correct swizzle on vx2i ops. 2019-03-31 13:51:12 -07:00
Unknown W. Brackets
68cdcba6c5 interp: Don't write lane 2 on single colorconv. 
Not that it's valid to use the op with that size anyway.
 2019-03-31 13:51:12 -07:00
Unknown W. Brackets
5736b1be2a interp: Correct some negative invalid zero cases. 
In these cases, the input value wires to +0.  Also, transposed the values
in a comment (oops.)
 2019-03-31 13:45:37 -07:00
Unknown W. Brackets
aa998b815c interp: Force vscmp result of invalid to zero. 
Some other ops do this, but mostly only that do plus or minus.
 2019-03-31 13:41:48 -07:00
Unknown W. Brackets
c7e83cd4fa interp: Correct vfim for -inf and similar. 
Was dropping the sign bit before for inf and nan.
 2019-03-31 13:41:48 -07:00