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20,556 Commits 70 Branches 122 Tags 688 MiB
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1829 Commits

Author SHA1 Message Date
Henrik Rydgård
c6d4966067 Make really sure we're not using the IRBlock copy constructor other than on Symbian. 
Turns out it ended up being used on Mac, and our asserts just debugprint and don't actually assert...
 2016-07-09 09:32:41 +02:00
Henrik Rydgard
e0845b876f Fix some bugs in the IRJit. Hopefully helps #8848 2016-07-08 00:05:44 +02:00
Henrik Rydgård
1091fd2dc0 Merge pull request #8840 from unknownbrackets/ir-vfpu 
Minor IR cleanup in the VFPU
 2016-07-04 10:02:52 +02:00
Unknown W. Brackets
1de4943632 jit-ir: Avoid crash in stack walk. 
This can happen if something is data, I suppose, and not a valid block.
 2016-07-02 20:51:06 -07:00
Unknown W. Brackets
4578c3cb54 jit-ir: Implement memory breakpoints. 
These generally work, but likely delay slots will make downcount slightly
off, and won't resume when you hit run again without manually stepping
through them.
 2016-07-02 16:38:30 -07:00
Unknown W. Brackets
7cd666c351 jit-ir: Decrease downcount after delayslot. 
Except for likely delay slots.  This makes breakpoints work more
correctly when they trigger within a delay slot.
 2016-07-02 16:35:56 -07:00
Unknown W. Brackets
1df08518ae jit-ir: Implement basic icache clear. 2016-07-01 17:27:24 -07:00
Unknown W. Brackets
6fb34d0bee jit-ir: Add initial breakpoint support. 
No memory breakpoints yet, and cache isn't cleared yet so these don't work
exactly the way you might expect...
 2016-07-01 17:15:57 -07:00
Unknown W. Brackets
8fab3dc91b jit-ir: Allow 3x3 and 2x2 vmmov in IR. 
While this will generate a lot of FMovs, it should still be better than
bailing to interp.
 2016-07-01 14:08:32 -07:00
Unknown W. Brackets
65394f1dba jit-ir: Fix vbfy with overlap. 2016-07-01 14:08:31 -07:00
Unknown W. Brackets
4761c0aa3f jit-ir: Allow SIMD on vabs/vneg. 2016-07-01 14:08:31 -07:00
Unknown W. Brackets
f4a06cd79a Remove an impossible assert condition. 2016-05-31 11:56:23 -07:00
Unknown W. Brackets
6ee770bd80 Add some missing overrides to declarations. 2016-05-31 11:55:45 -07:00
Unknown W. Brackets
25136eb019 Remove an unused function. 2016-05-31 11:40:39 -07:00
Unknown W. Brackets
419b960403 x86jit: Fix params in Replace_fabsf. 2016-05-31 10:40:14 -07:00
Unknown W. Brackets
a450a79f52 jit-ir: Optimize loads to transfers if possible. 
These (especially float <-> gpr) happen in all games, but gpr->gpr is
especially common in some minis.  Good to reduce bloat.
 2016-05-29 18:34:41 -07:00
Unknown W. Brackets
5b7bd8155d Special case specific sin/cos result values. 
Fixes #7737, thanks go to gid15 from Jpcsp for finding and daniel229 for
reporting.
 2016-05-29 08:51:38 -07:00
Unknown W. Brackets
4113fd940c Add ugly invalidation workaround for SGS7s. 
Otherwise they just crash, and crash often.  Special thanks to Jaaan for
numerous trials to try to find the best way to solve the crashes.
 2016-05-23 21:35:28 -07:00
Unknown W. Brackets
e65e794f28 x86jit: Fix vmmul of matrix with itself. 
Was not SIMDing correctly.  Probably rare in practice.
 2016-05-21 23:02:29 -07:00
Henrik Rydgård
bb7dd908ba Merge pull request #8760 from unknownbrackets/warnings 
Warning fixes + more ccache
 2016-05-21 18:35:29 +02:00
Unknown W. Brackets
b09c2b1f75 Add some missing override definitions. 2016-05-21 09:29:03 -07:00
Unknown W. Brackets
f0cc975865 Hook some funcs in Me and My Katamari. 
One is a very hardcoded screenshot download / vfpu convert to 565, and the
other is some very weird check to make sure render is clear or has
happened or something.

The screenshot func detects downloads for the "Royal Album".  The render
check detects downloads for post-rename (no idea why it checks here.)

Fixes #7695.
 2016-05-20 22:30:25 -07:00
Henrik Rydgård
306f7423e7 Merge pull request #8755 from unknownbrackets/cpu-div 
Handle divide by zero more accurately in jit
 2016-05-19 09:30:25 +02:00
Unknown W. Brackets
2d3df5c621 armjit: Handle divide by zero more accurately. 
Turns out, some games may depend on this behavior.
 2016-05-19 00:07:41 -07:00
Unknown W. Brackets
5105e1947f x86jit: Set HI/LO properly on divide by zero. 2016-05-19 00:06:53 -07:00
Henrik Rydgard
3cae60b320 Revert potentially dangerous optimization that may have caused #8754, though not sure how. 2016-05-18 21:22:08 +02:00
Unknown W. Brackets
ee31f09b67 Buildfix. 2016-05-18 07:12:21 -07:00
Unknown W. Brackets
5534fba72c jit-ir: Add load/store reorder and merge passes. 
Can do more in merge, potentially.  Maybe it's not useful...
 2016-05-17 21:24:13 -07:00
Unknown W. Brackets
a9cdf7651e jit-ir: Mark prefixes unknown in mtv. 2016-05-17 21:22:57 -07:00
Unknown W. Brackets
b1c7f3dd3f jit-ir: Correct vx2i with partial overlap. 2016-05-17 21:22:23 -07:00
Henrik Rydgard
fff898b526 Log the block when "uneaten prefix" happens 2016-05-16 00:05:03 +02:00
Henrik Rydgard
dc772e6f3a Add missing cases to simplify pass 2016-05-15 23:39:42 +02:00
Henrik Rydgard
f544364c4a Fix bug in vus2i (thanks unknown), recognize vectors in IR disasm 2016-05-15 23:35:33 +02:00
Unknown W. Brackets
e960158490 jit-ir: Add notes and report about vrot prefixes. 2016-05-15 14:08:59 -07:00
Unknown W. Brackets
ab1461faca Add prefix handling to vfpu color conv per tests. 2016-05-15 13:16:03 -07:00
Unknown W. Brackets
3f0fc2d851 jit-ir: Fix FSat0_1 behavior on -0.0f. 2016-05-15 13:10:49 -07:00
Unknown W. Brackets
fa61deae3d Remove unused value. 2016-05-15 12:43:35 -07:00
Unknown W. Brackets
6bf1390603 Fix timing drift on CoreTiming::ForceCheck(). 
Since -1 -(-1) = 0, we'll never think we moved forward this way.
 2016-05-15 12:43:34 -07:00
Henrik Rydgard
d6c2b6e9ae Most of vi2x 2016-05-15 11:46:01 +02:00
Henrik Rydgard
905af75925 vx2i, vbfy, vsgn 2016-05-15 10:57:43 +02:00
Henrik Rydgard
7046f960e5 IR: Add vrot 2016-05-15 10:36:18 +02:00
Henrik Rydgård
168573e711 Merge pull request #8740 from unknownbrackets/ir-vfpu 
More VFPU comments, implement vmscl
 2016-05-15 10:08:22 +02:00
Unknown W. Brackets
e140d36818 ir-jit: Oops, fix matrix scale + tranpose. 2016-05-15 00:59:17 -07:00
Henrik Rydgård
205419a72e Merge pull request #8741 from unknownbrackets/ir-alu 
IR the remaining ALU ops, correct div by zero
 2016-05-15 09:43:41 +02:00
Unknown W. Brackets
c606f64f71 jit-ir: Add div/divu instructions. 2016-05-14 19:23:52 -07:00
Unknown W. Brackets
6413b44434 jit-ir: Enable IR for madd(u)/msub(u). 2016-05-14 19:23:51 -07:00
Unknown W. Brackets
a05ae2a0a6 Correct divide by zero HI/LO values a bit. 
Interpreter is now correct, but it's probably not all that important to
get right in jit.
 2016-05-14 19:23:50 -07:00
Unknown W. Brackets
4ac773e8b4 jit-ir: Implement bit reverse instruction. 2016-05-14 18:21:42 -07:00
Unknown W. Brackets
8a3dce3b8b jit-ir: Comment most of the vfpu ops. 2016-05-14 17:35:04 -07:00
Unknown W. Brackets
e1dbcd724e jit-ir: Oops, correct vtfm for transposed case. 
The ones that are aligned are here in this case.  Fixes crash in Crisis
Core.
 2016-05-14 16:20:39 -07:00