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Author SHA1 Message Date
Henrik Rydgård
deba52487b
Merge pull request #17819 from hrydgard/devscreens-collapsible-header 
Experiment with the collapsible header thingy, increase ItemHeader font size
 2023-07-31 13:30:02 +02:00
Henrik Rydgård
3861e97a94 Experiment with the collapsible header thingy. Slightly increase the font size of headers. 2023-07-31 11:48:50 +02:00
Henrik Rydgård
434aab9e69
Merge pull request #17817 from unknownbrackets/riscv-disas 
riscv: Add bitmanip ops to disasm
 2023-07-31 07:50:12 +02:00
Unknown W. Brackets
0d0029fc9d riscv: Add bitmanip ops to disasm. 2023-07-30 17:45:36 -07:00
Henrik Rydgård
50ac61f362
Merge pull request #17816 from unknownbrackets/riscv-android 
Build: Fix link issue for rv64 disasm
 2023-07-31 01:32:21 +02:00
Unknown W. Brackets
c24dca12bb Build: Fix link issue for rv64 disasm. 2023-07-30 16:06:55 -07:00
Unknown W. Brackets
b03398a46c
Merge pull request #17815 from unknownbrackets/riscv-jit 
riscv: Spill registers more intelligently
 2023-07-30 14:49:37 -07:00
Henrik Rydgård
fa2b831dbc
Merge pull request #17814 from unknownbrackets/riscv-jit-debug 
riscv: Implement block debug interface
 2023-07-30 23:42:14 +02:00
Henrik Rydgård
fa558b5b71
Merge pull request #17813 from unknownbrackets/riscv-jit-fixes 
Fix some typos and mistakes in RISC-V jit
 2023-07-30 23:41:13 +02:00
Henrik Rydgård
100f7c838e
Merge pull request #17812 from unknownbrackets/irjit-floats 
Cleanup IR cond move flag, fmov to self
 2023-07-30 23:36:37 +02:00
Unknown W. Brackets
f870271011 riscv: Spill registers more intelligently. 2023-07-30 14:24:12 -07:00
Unknown W. Brackets
020706f545 riscv: Implement float saturate clamping. 2023-07-30 14:24:12 -07:00
Unknown W. Brackets
45d44c1d4f riscv: Implement block debug interface. 
This gives us the target disasm in jit compare, bloat, etc.
 2023-07-30 14:21:43 -07:00
Unknown W. Brackets
5ef4b2b5fa riscv: Fix assert when flushing not mapped reg. 2023-07-30 14:19:28 -07:00
Unknown W. Brackets
9f917488c3 riscv: Fix PC in disassembly. 2023-07-30 14:19:28 -07:00
Unknown W. Brackets
e34736fbb2 riscv: Reduce norms in Slt/Sltu overlap cases. 
We can skip an SEXT.W in common cases where the dest and src overlap.
 2023-07-30 14:19:28 -07:00
Unknown W. Brackets
d1dc346899 riscv: Fix pointer add/sub. 2023-07-30 14:19:28 -07:00
Unknown W. Brackets
09f3842a32 riscv: Fix VFPU compare typos. 2023-07-30 14:19:28 -07:00
Unknown W. Brackets
f3240393fa irjit: Use vf for vfpu regs, v0 is a gpr. 2023-07-30 14:16:17 -07:00
Unknown W. Brackets
6819acd29f irjit: Fix flag on float cond move. 2023-07-30 14:16:17 -07:00
Unknown W. Brackets
5db6b11ef2 irjit: Cleanup self-fmovs. 
These were sometimes getting emitted.
 2023-07-30 14:16:17 -07:00
Henrik Rydgård
4c560e44b5
Merge pull request #17810 from hrydgard/bbox-cache-planes 
Cache computed planes used for BBOX culling
 2023-07-30 19:34:00 +02:00
Henrik Rydgård
f0fd9e85aa Try dirtying CULL_PLANES in Execute_BoundingBox in SoftGPU 2023-07-30 18:35:18 +02:00
Henrik Rydgård
fd656c629d More dirtying 2023-07-30 17:45:19 +02:00
Unknown W. Brackets
a28acf2662
Merge pull request #17805 from hch12907/sdl-ttf 
SDL: address comments on #17780
 2023-07-30 07:10:59 -07:00
Henrik Rydgård
061131ec8a Cache planes used for BBOX culling 
This isn't a huge performance boost for the games that use BBOX (like
Tekken), but it'll be more valuable if we start using soft culling more
widely automatically, see #17808
 2023-07-30 14:42:22 +02:00
Henrik Rydgård
36951a0b98
Merge pull request #17806 from hrydgard/update-rcheevos 
Update to the latest version of rcheevos.
 2023-07-30 12:19:40 +02:00
Henrik Rydgård
1c05f71b50 Update to the latest version of rcheevos. 2023-07-30 11:58:55 +02:00
Henrik Rydgård
47bbddad0f
Merge pull request #17807 from hrydgard/re-enable-framebuffer-fetch 
Re-enable framebuffer fetch for blend where available.
 2023-07-30 11:37:20 +02:00
Henrik Rydgård
6da6de8201 Re-enable framebuffer fetch for blend where available. 
Accidentally disabled this in #17575

Helps #17797 but only on OpenGL on mobile. There's more to improve
there.

caps_.framebufferFetchSupported is now always set to false in Vulkan.
 2023-07-30 11:13:42 +02:00
Hoe Hao Cheng
c56f302e51 SDL: address comments on #17780 2023-07-30 16:25:36 +08:00
Henrik Rydgård
c20f508db2
Merge pull request #17804 from unknownbrackets/riscv-jit 
A couple more RISC-V ops
 2023-07-30 10:23:13 +02:00
Unknown W. Brackets
c24e3ef831 riscv: Implement ll/sc. 2023-07-30 00:45:51 -07:00
Unknown W. Brackets
26a527bdf8 riscv: Implement float/int conversion. 2023-07-30 00:45:51 -07:00
Henrik Rydgård
b93275bb35
Merge pull request #17800 from unknownbrackets/riscv-jit 
More RISC-V jit ops
 2023-07-30 09:26:22 +02:00
Henrik Rydgård
c8447ff4b7
Merge pull request #17801 from unknownbrackets/irjit-vminmax 
irjit: Fix vmin/vmax nan handling
 2023-07-30 09:18:25 +02:00
Henrik Rydgård
180bda6f6b
Merge pull request #17799 from unknownbrackets/irjit-lsu 
Add ll/sc to IR and x86jit
 2023-07-30 09:15:55 +02:00
Henrik Rydgård
f5c7e6c937
Merge pull request #17802 from HR1025/win 
some small change
 2023-07-30 09:09:15 +02:00
Henrik Rydgård
52cefeb5c3
Merge pull request #17798 from unknownbrackets/irjit-vf2ix 
irjit: Implement vf2ix
 2023-07-30 09:08:45 +02:00
Henrik Rydgård
88bef1b00f
Merge pull request #17803 from Narugakuruga/patch-24 
Update zh_CN.ini
 2023-07-30 09:06:45 +02:00
Unknown W. Brackets
0036f3c494 riscv: Implement FMin/FMax. 2023-07-30 00:02:10 -07:00
Unknown W. Brackets
8e8081c686 riscv: Implement VFPU compares. 2023-07-30 00:02:10 -07:00
Unknown W. Brackets
9c9330a207 riscv: Implement float conditional move. 2023-07-30 00:02:10 -07:00
Unknown W. Brackets
70ff18a463 riscv: Implement count leading zeros. 2023-07-30 00:02:10 -07:00
Unknown W. Brackets
a5671bc716 riscv: Add simple debug log of missed ops. 2023-07-30 00:02:10 -07:00
Narugakuruga
99d5a90898
Update zh_CN.ini 2023-07-30 14:23:21 +08:00
haorui wang
ec4927069e 1. remove some unused code 
2. add some missing header
3. fix error address offset operation
 2023-07-30 12:31:31 +08:00
Unknown W. Brackets
6aa4b0c5e1 irjit: Fix vmin/vmax nan handling. 
Should be relevant to NFS MW and possibly other game bugs.
 2023-07-29 19:13:12 -07:00
Unknown W. Brackets
6d4fb949c2 riscv: Implement float compare ops. 2023-07-29 19:02:15 -07:00
Unknown W. Brackets
6b632a103d riscv: Implement FSin/similar. 2023-07-29 19:02:15 -07:00