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Author SHA1 Message Date
Tony Wasserka
a6f9c51317 FEXQonfig: Load config from default location on startup 2024-08-21 10:04:35 +02:00
Ryan Houdek
cfa2ad8423
Merge pull request #3986 from alyssarosenzweig/opt/test-x-x 
Optimize test
 2024-08-20 19:20:57 -07:00
Alyssa Rosenzweig
19010491da InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 21:17:08 -04:00
Alyssa Rosenzweig
5d613e8716 OpcodeDispatcher: optimize test x, x 
fewer uops now that we invert carry

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 21:17:08 -04:00
Alyssa Rosenzweig
894aaa980f
Merge pull request #3975 from Sonicadvance1/update_wfe_comment 
SpinWaitLock: Update comment about WFE spurious wakeups
 2024-08-20 20:55:30 -04:00
Ryan Houdek
877b2f4fef
Merge pull request #3955 from alyssarosenzweig/opt/pop-final 
Rearrange SRA to let us coalesce cmpxchg moves
 2024-08-20 17:36:11 -07:00
Ryan Houdek
2a170cfdec
Merge pull request #3985 from alyssarosenzweig/opt/tso 
OpcodeDispatcher: fix tso checks
 2024-08-20 17:18:21 -07:00
Alyssa Rosenzweig
a299d6b1a5 InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 20:17:06 -04:00
Alyssa Rosenzweig
ffb85e6305 ArchHelpers: rearrange SRA layout to coalesce cmpxchg 
linux only for now, arm64ec should do something similar.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 20:14:08 -04:00
Alyssa Rosenzweig
d7a20fa28f OpcodeDispatcher: fix tso checks 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 20:11:06 -04:00
Ryan Houdek
5ac7d5dfcd
Merge pull request #3980 from alyssarosenzweig/opt/avx 
Optimize AVX load/store with ldp/stp
 2024-08-20 16:29:55 -07:00
Alyssa Rosenzweig
75644b33df InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:36:50 -04:00
Alyssa Rosenzweig
4c4c6e7807 OpcodeDispatcher: pair loads on cortex 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:36:50 -04:00
Alyssa Rosenzweig
a8c9c71ce3 OpcodeDispatcher: use loadcontextpair 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:33:41 -04:00
Alyssa Rosenzweig
8a4bd5f22c OpcodeDispatcher: pair avx128 save 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:33:41 -04:00
Alyssa Rosenzweig
138a36c69a OpcodeDispatcher: pair avx128 restore 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:33:41 -04:00
Alyssa Rosenzweig
3400ca5d42 OpcodeDispatcher: pair avx restore 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:33:41 -04:00
Alyssa Rosenzweig
5d8164da4e OpcodeDispatcher: pair restore x87 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:33:41 -04:00
Alyssa Rosenzweig
8b89b30a6f OpcodeDispatcher: pair restore SSE 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:33:41 -04:00
Alyssa Rosenzweig
e66d7cfd6c OpcodeDispatcher: pair mm save 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:33:41 -04:00
Alyssa Rosenzweig
63afa29dae OpcodeDispatcher: pair save AVX 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:33:41 -04:00
Alyssa Rosenzweig
926a9b40e2 OpcodeDispatcher: pair save mxcsr 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:33:41 -04:00
Alyssa Rosenzweig
9bb43264b5 OpcodeDispatcher: pair SSE store 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:33:37 -04:00
Alyssa Rosenzweig
32d6daf558 OpcodeDispatcher: use ldp/stp for AVX load/store 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig
bebcb73c68 OpcodeDispatcher: pair AVX high writes 
reduces instr count with AVX-128

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig
d0e040514f IR: add LoadContextPair 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig
850c027d52 IR: add AllocateFPR 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig
5df90563e2 IR: add LoadMemPair 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig
7a489d18c6 IR: add StoreMemPair 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig
1db092e96f IR: add StoreContextPair 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig
65a4de221b InstructionCountCI: add AddressingLimitations for AVX 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Alyssa Rosenzweig
9c8df79dfb InstructionCountCI: add bytemark stringsort blocks 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 18:31:19 -04:00
Ryan Houdek
689b461d7b
Merge pull request #3984 from Sonicadvance1/atomic_tso_subchecks 
FEXCore: Splits up atomic enablement checks
 2024-08-20 15:16:54 -07:00
Ryan Houdek
92c951c81f
Merge pull request #3983 from Sonicadvance1/direct_sra_correlation 
Arm64: Allow directly correlating an ARM register back to an x86 register
 2024-08-20 15:16:46 -07:00
Ryan Houdek
9c8438f264
FEXCore: Splits up atomic enablement checks 
PR #3980 is adding a feature to merge loadstores in to paired
loadstores, but it was using the incorrect atomic check to determine if
it can safely merge them or not. It was using the GPR atomic check
instead of the vector atomic check. While this would improve performance
on Apple Silicon with its hardware TSO implementation, it would have had
zero impact on Cortex and Oryon.

Instead split out the three config options to live as a boolean check in
the ContextImpl similar to how we disable "AtomicTSOEmulation". Removing
the various configs in the JIT and CPUID so that it queries from the
same context. This makes it clearer that if you are wanting the current
active configuration for memcpy, vector, or general atomic TSO
emulation, you should query one of those three getters.

This also fixes a weird edge case bug in the arm64 JIT where you could
have TSO emulation disable, but still have vector TSO enabled partially.
Just because half a config wasn't checked in {Load,Store}MemTSO for
vectors. If the global "TSOEnabled" option is disabled then TSO should
always be disabled.

Alyssa will be able to pull this in to #3980 once merged and get the
performance uplift on Cortex and Oryon, since our default configuration
is to have vector and memcpy TSO emulation disabled.
 2024-08-20 14:34:34 -07:00
Ryan Houdek
caf7ad53e6
Arm64: Allow directly correlating an ARM register back to an x86 register 
Fixes a bug that is getting introduced in to #3955 when it rearranged
register allocation.
 2024-08-20 14:17:13 -07:00
Tony Wasserka
47f0fec2f2 Add Qt-based config editor 2024-08-20 20:54:34 +02:00
Ryan Houdek
eadb502059
Merge pull request #3978 from bylaws/create 
Windows: Implement CreateDirectoryW CRT function
 2024-08-20 11:39:57 -07:00
Ryan Houdek
8e1695afa3
Merge pull request #3977 from bylaws/wowex 
WOW64: Improve exception handling
 2024-08-20 11:39:22 -07:00
Ryan Houdek
a7138f26b6
Merge pull request #3981 from alyssarosenzweig/opt/btc 
Optimize BTC
 2024-08-20 11:38:43 -07:00
Alyssa Rosenzweig
f2a9ce9d4c InstCountCI: Update 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 09:26:20 -04:00
Alyssa Rosenzweig
84e4960e52 OpcodeDispatcher: optimize btc 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
 2024-08-20 09:24:02 -04:00
Ryan Houdek
99afd876ba
Merge pull request #3976 from alyssarosenzweig/opt/huffman- 
Improvements from bytemark "huffman"
 2024-08-19 16:10:29 -07:00
Ryan Houdek
1caa31c5cb
Merge pull request #3962 from Sonicadvance1/remove_vixl_requirement 
HostFeatures: Removes vixl usage
 2024-08-19 14:31:13 -07:00
Tony Wasserka
d2c82ba707
Merge pull request #3968 from Sonicadvance1/binfmt_misc_systemd 
binfmt_misc: Support systemd binfmt_misc
 2024-08-19 22:33:52 +02:00
Billy Laws
9067f3513a Windows: Implement CreateDirectoryW CRT function 
Used when the .fex-emu config dir doesn't exist. Also fixes up
CreateFile to not leak memory.
 2024-08-19 19:11:17 +00:00
Billy Laws
409d691877 WOW64: Only handle unaligned atomics in JIT code 2024-08-19 19:07:30 +00:00
Billy Laws
1762ff0393 WOW64: Spill EFlags into the FEX state when reconstructing JIT context 2024-08-19 19:07:30 +00:00
Billy Laws
4d26178f25 Windows: Commonise guest exception handling logic and use for WOW64 2024-08-19 19:07:29 +00:00
Ryan Houdek
c6582a1ce5
binfmt_misc: Support systemd binfmt_misc 
Adds support for binfmt_misc through systemd configuration paths. Their
configuration files are basically the raw kernel interface description
in a .conf file, quite a bit more simple than the legacy debian path.

Default enable this path since systemd is the expected default
arrangement these days.

Fixes #2417
 2024-08-19 11:15:18 -07:00