2018-06-19 01:31:50 +00:00
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#!/usr/bin/python
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# Test tool to compare Capstone output with llvm-mc. By Nguyen Anh Quynh, 2014
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import sys
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import os
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from capstone import *
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def test_file(fname):
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print("Test %s" %fname);
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f = open(fname)
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lines = f.readlines()
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f.close()
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if not lines[0].startswith('# '):
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print("ERROR: decoding information is missing")
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return
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# skip '# ' at the front, then split line to get out hexcode
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# Note: option can be '', or 'None'
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#print lines[0]
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#print lines[0][2:].split(', ')
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(arch, mode, option) = lines[0][2:].split(', ')
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mode = mode.replace(' ', '')
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option = option.strip()
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archs = {
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"CS_ARCH_ARM": CS_ARCH_ARM,
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2023-11-15 04:12:14 +00:00
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"CS_ARCH_AARCH64": CS_ARCH_AARCH64,
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2018-06-19 01:31:50 +00:00
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"CS_ARCH_MIPS": CS_ARCH_MIPS,
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"CS_ARCH_PPC": CS_ARCH_PPC,
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"CS_ARCH_SPARC": CS_ARCH_SPARC,
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"CS_ARCH_SYSZ": CS_ARCH_SYSZ,
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"CS_ARCH_X86": CS_ARCH_X86,
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"CS_ARCH_XCORE": CS_ARCH_XCORE,
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RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: https://github.com/porto703/capstone/commit/0db412ce3bed9d963caf598a2cb7dc76b41a5a2b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
2019-03-09 00:41:12 +00:00
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"CS_ARCH_RISCV": CS_ARCH_RISCV,
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2023-03-25 13:12:40 +00:00
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"CS_ARCH_TRICORE": CS_ARCH_TRICORE,
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2023-12-28 02:10:38 +00:00
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"CS_ARCH_ALPHA": CS_ARCH_ALPHA,
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2018-06-19 01:31:50 +00:00
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}
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modes = {
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"CS_MODE_16": CS_MODE_16,
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"CS_MODE_32": CS_MODE_32,
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"CS_MODE_64": CS_MODE_64,
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"CS_MODE_MIPS32": CS_MODE_MIPS32,
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"CS_MODE_MIPS64": CS_MODE_MIPS64,
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"0": CS_MODE_ARM,
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"CS_MODE_ARM": CS_MODE_ARM,
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"CS_MODE_THUMB": CS_MODE_THUMB,
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"CS_MODE_ARM+CS_MODE_V8": CS_MODE_ARM+CS_MODE_V8,
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"CS_MODE_THUMB+CS_MODE_V8": CS_MODE_THUMB+CS_MODE_V8,
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"CS_MODE_THUMB+CS_MODE_MCLASS": CS_MODE_THUMB+CS_MODE_MCLASS,
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2023-07-19 09:56:27 +00:00
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"CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS": CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS,
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2018-06-19 01:31:50 +00:00
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"CS_MODE_LITTLE_ENDIAN": CS_MODE_LITTLE_ENDIAN,
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"CS_MODE_BIG_ENDIAN": CS_MODE_BIG_ENDIAN,
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"CS_MODE_64+CS_MODE_LITTLE_ENDIAN": CS_MODE_64+CS_MODE_LITTLE_ENDIAN,
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"CS_MODE_64+CS_MODE_BIG_ENDIAN": CS_MODE_64+CS_MODE_BIG_ENDIAN,
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"CS_MODE_MIPS32+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO,
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"CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN,
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"CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN,
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"CS_MODE_BIG_ENDIAN+CS_MODE_V9": CS_MODE_BIG_ENDIAN + CS_MODE_V9,
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"CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN,
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"CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN,
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"CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN,
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"CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN,
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RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: https://github.com/porto703/capstone/commit/0db412ce3bed9d963caf598a2cb7dc76b41a5a2b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
2019-03-09 00:41:12 +00:00
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"CS_MODE_RISCV32": CS_MODE_RISCV32,
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"CS_MODE_RISCV64": CS_MODE_RISCV64,
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2023-04-07 20:28:38 +00:00
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"CS_MODE_TRICORE_110": CS_MODE_TRICORE_110,
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"CS_MODE_TRICORE_120": CS_MODE_TRICORE_120,
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"CS_MODE_TRICORE_130": CS_MODE_TRICORE_130,
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"CS_MODE_TRICORE_131": CS_MODE_TRICORE_131,
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"CS_MODE_TRICORE_160": CS_MODE_TRICORE_160,
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"CS_MODE_TRICORE_161": CS_MODE_TRICORE_161,
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"CS_MODE_TRICORE_162": CS_MODE_TRICORE_162,
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2023-09-24 03:09:53 +00:00
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"CS_MODE_BIG_ENDIAN+CS_MODE_QPX": CS_MODE_BIG_ENDIAN+CS_MODE_QPX,
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2018-06-19 01:31:50 +00:00
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}
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mc_modes = {
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("CS_ARCH_X86", "CS_MODE_32"): 0,
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("CS_ARCH_X86", "CS_MODE_64"): 1,
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("CS_ARCH_ARM", "CS_MODE_ARM"): 2,
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("CS_ARCH_ARM", "CS_MODE_THUMB"): 3,
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("CS_ARCH_ARM", "CS_MODE_ARM+CS_MODE_V8"): 4,
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("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8"): 5,
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("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_MCLASS"): 6,
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2023-07-19 09:56:27 +00:00
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("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8+CS_MODE_MCLASS"): 7,
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2023-11-15 04:12:14 +00:00
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("CS_ARCH_AARCH64", "0"): 8,
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2023-07-19 09:56:27 +00:00
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("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN"): 9,
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("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO"): 10,
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("CS_ARCH_MIPS", "CS_MODE_MIPS64"): 11,
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("CS_ARCH_MIPS", "CS_MODE_MIPS32"): 12,
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("CS_ARCH_MIPS", "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN"): 13,
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("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): 14,
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("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): 14,
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("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): 15,
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("CS_ARCH_SPARC", "CS_MODE_BIG_ENDIAN"): 16,
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("CS_ARCH_SPARC", "CS_MODE_BIG_ENDIAN+CS_MODE_V9"): 17,
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("CS_ARCH_SYSZ", "0"): 18,
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("CS_ARCH_XCORE", "0"): 19,
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("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_BIG_ENDIAN"): 20,
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("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): 21,
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("CS_ARCH_MIPS", "CS_MODE_MIPS32R6"): 22,
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("CS_ARCH_MIPS", "CS_MODE_MIPS32R6+CS_MODE_MICRO"): 23,
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("CS_ARCH_M68K", "0"): 24,
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("CS_ARCH_M680X", "CS_MODE_M680X_6809"): 25,
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("CS_ARCH_EVM", "0"): 26,
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("CS_ARCH_BPF", "CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_CLASSIC"): 30,
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("CS_ARCH_BPF", "CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_EXTENDED"): 31,
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("CS_ARCH_BPF", "CS_MODE_BIG_ENDIAN+CS_MODE_BPF_CLASSIC"): 32,
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("CS_ARCH_BPF", "CS_MODE_BIG_ENDIAN+CS_MODE_BPF_EXTENDED"): 33,
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("CS_ARCH_RISCV", "CS_MODE_RISCV32"): 45,
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("CS_ARCH_RISCV", "CS_MODE_RISCV64"): 46,
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2023-04-10 17:18:41 +00:00
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("CS_ARCH_TRICORE", "CS_MODE_TRICORE_110"): 47,
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("CS_ARCH_TRICORE", "CS_MODE_TRICORE_120"): 48,
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("CS_ARCH_TRICORE", "CS_MODE_TRICORE_130"): 49,
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("CS_ARCH_TRICORE", "CS_MODE_TRICORE_131"): 50,
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("CS_ARCH_TRICORE", "CS_MODE_TRICORE_160"): 51,
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("CS_ARCH_TRICORE", "CS_MODE_TRICORE_161"): 52,
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("CS_ARCH_TRICORE", "CS_MODE_TRICORE_162"): 53,
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2023-09-24 03:09:53 +00:00
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("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN+CS_MODE_QPX"): 54,
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2023-12-28 02:10:38 +00:00
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("CS_ARCH_ALPHA", "CS_MODE_LITTLE_ENDIAN"): 55,
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2018-06-19 01:31:50 +00:00
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}
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#if not option in ('', 'None'):
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# print archs[arch], modes[mode], options[option]
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for line in lines[1:]:
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# ignore all the input lines having # in front.
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if line.startswith('#'):
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continue
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2019-02-15 14:45:45 +00:00
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if line.startswith('// '):
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line=line[3:]
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2018-06-19 01:31:50 +00:00
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#print("Check %s" %line)
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code = line.split(' = ')[0]
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if len(code) < 2:
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continue
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2019-02-15 14:45:45 +00:00
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if code.find('//') >= 0:
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continue
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2018-06-19 01:31:50 +00:00
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hex_code = code.replace('0x', '')
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hex_code = hex_code.replace(',', '')
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2023-04-10 17:28:01 +00:00
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hex_code = hex_code.replace(' ', '')
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2019-03-11 05:12:54 +00:00
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try:
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hex_data = hex_code.strip().decode('hex')
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except:
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print "skipping", hex_code
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2018-06-19 01:31:50 +00:00
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fout = open("fuzz/corpus/%s_%s" % (os.path.basename(fname), hex_code), 'w')
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if (arch, mode) not in mc_modes:
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print "fail", arch, mode
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fout.write(unichr(mc_modes[(arch, mode)]))
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fout.write(hex_data)
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fout.close()
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if __name__ == '__main__':
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if len(sys.argv) == 1:
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fnames = sys.stdin.readlines()
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for fname in fnames:
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test_file(fname.strip())
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else:
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#print("Usage: ./test_mc.py <input-file.s.cs>")
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test_file(sys.argv[1])
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