1 ChangeLog 3.0.1 RC1

Nguyen Anh Quynh edited this page 2015-01-20 14:31:37 +08:00

This is the changelog for version 3.0.1-rc1. (Look here for the detailed changelog of v3.0)

NOTE: changes are listed in time order: newer changes are at the top, older changes are at the bottom.

X86:

• Handle undocumented immediates for SSE's (V)CMPPS/PD/SS/SD instructions.
• Print LJUMP/LCALL without * as prefix for Intel syntax.
• Handle REX prefix properly for segment/MMX related instructions (x86_64).
• Instruction with length > 15 is consider invalid.
• Handle some tricky encodings for instructions MOVSXD, FXCH, FCOM, FCOMP, FSTP, FSTPNCE, NOP.
• Handle some tricky code for some X86_64 instructions with REX prefix.
• Add missing operands in detail mode for PUSH , POP , IN/OUT reg, reg
• MOV32ms & MOV32sm should reference word rather than dword.

Arm64

• Print absolute (rather than relative) address for instructions B, BL, CBNZ, ADR.

Arm

• BL & BLX do not read SP, but PC register.
• Alias LDR instruction with operands [sp], 4 to POP.
• Print immediate operand of MVN instruction in positive hexadecimal form.

PPC

• Fix some compilation bugs when DIET mode is enable.
• Populate SLWI/SRWI instruction details with SH operand.

Python

• Fix a NULL memory access issue when SKIPDATA & Detail modes are enable at the same time.
• Fix a memory leaking bug when when we stop enumeration over the disassembled instructions prematurely.
• Export generic operand types & groups (CS_OP_xxx & CS_GRP_xxx).