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Page: ChangeLog since 3.0 rc2
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Binding changes for binding authors version 2.1 Branching Model Capstone 4.0 New API to provide explicit registers ChangeLog 2.0 ChangeLog 2.1.1 ChangeLog 2.1.2 ChangeLog 2.1 ChangeLog 3.0.1 RC1 ChangeLog 3.0.1 RC2 ChangeLog 3.0.1 ChangeLog 3.0.2 ChangeLog 3.0.3 RC1 ChangeLog 3.0.3 ChangeLog 3.0.4 ChangeLog 3.0.5 ChangeLog 3.0 ChangeLog 4.0 alpha1 ChangeLog from 2.1.2 to 3.0 rc1 ChangeLog since 3.0 rc1 ChangeLog since 3.0 rc2 ChangeLog since 3.0 rc3 ChangeLog Changes from "next" to "v3" for binding authors Home Ideas for next version(s) . Feel free to add yours! Installing on Cygwin & Python3 New APIs: cs_disasm_alloc() & cs_disasm_buf() Next branch Release Guide
7 ChangeLog since 3.0 rc2
aquynh edited this page 2014-10-31 00:52:59 -07:00

  • Use common instruction operand types REG, IMM, MEM & FP across all architectures (see commit 21ac056728)

  • Use common instruction group types across all architectures (see commit 3ab509192a)

  • Fix an overflow bug in fill_insn() in cs.c.

  • Mips: properly handle modes MIPS32R6 & MICRO.

  • ARM: instructions B, BL, BX, BLX, BXJ belong to ARM_GRP_JUMP group.

  • X86: remove bogus instructions X86_INS_REP/REPNE/LOCK (x8.h).

  • X86: added prefixed symbols X86_PREFIX_REP/REPNE/LOCK/CS/DS/SS/FS/GS/ES/OPSIZE/ADDRSIZE (x86.h)

  • PPC: add new operand type PPC_OP_CRX.