The MCInstDesc table changed. Bsides this only minor changes were done
and some additional code is emitted now for LLVM.
This commit is the combination of all previous Auto-Sync commits.
The list of commit messages follows:
-----------
Combination of all commits of the refactored tablegen backends.
These are the changes made for LLVM 16.
Refactor Capstone relevant TableGen Emitter backends.
This commit extracts the code which emits generated tables into two printer classes.
The Printer is called whenever actual code is written to a file.
There is the PrinterLLVM which emits tht code as before and
PrinterCapstone which is tailored to or needs (emitting C and generates
more info).
Additionally missing memory access properties were added to ARMs td
files.
Emit a single header for all files.
Captialize Target name for enums.
Add lay metric to emit enum value for Banked and system regs.
Malloc substr
Sort instructions in ascending order.
Free substr after use
Add vanished constrainsts
Fix `regInfoEmitEnums()` and indent
Fix `GenDisassemblerTables.inc#checkDecoderPredicate()`
Fix `TriCoreGenRegisterInfo.inc` | `PrinterCapstone::regInfoEmitRegClasses`
revert changes to NEON instructions
Add instructions with duplicate operands as Matchables.
Add memory load and store info
Correct memory access and out operand info
Set register lists again as read ops due to https://github.com/llvm/llvm-project/issues/62455
Make printAliasInstr and getMnemonic static.
Generate CS instruction enums from actual mnemonic. Not via the flawed AsmMatcher.
Fix typo in InstrInfoEmitter.cpp
Add deprecated QPX feature
Replace + and - with p and m
Add AssemblerPredicates to PPC
Generate RegEncodingTable
Define functions which are called by the Mapper as static.
Necessary because these functions are present in each arch'
Remove set_mem_access().
The cases where this is used to mark access to actual memory operands are
either very rare, or those are neon lane indicies.
Generate correct op type for absolute addresses.
Check for RegisterPointer operands first to prevent mis-categorization.
Add missing Operand types
Generate Instruction formats for PPC.
Add Paired Single instructions.
Partly revert 94e41ce23a7fd863a96288ec05b6c7202c3cfbf1 (introduces accidentially removed code.)
Set correct operand types for PS operands
Add memory read/write attributes
Add missing operand types
Add mayLoad and mayStore information.
Add documentation.
Handle special AArch64 operand
Replace C++ with C code.
Check for duplicate enum instr. names
Check for duplicate defintions of system registers.
Add note about missing target names.
Resolve templates in a single static method and add docs about it.
Revert printing target name in upper case.
Revert partially C++ syntax fixes in .td files.
They break the TemplateCOllector since it searches for exactly those references but can't find any'
Add all SubtargetFeatures to feature enum.
Not just the one used by CGIs.
Pass Decoder
Enable to check specific table fields to determine if reg enum must be emitted.
Allow to add namespace to type name/
Formatting
Rework emitting of tables.
The system operands are now emitted in reg, imm and aliass groups.
Also a bug was fixed which emitted incorrect code..
Check for rename IMPLICIT_IMM operand types
Pass DecodeComplete as pointer not as reference
Print undef when it needs to be printed.
Add namespace ids to all types and functions.
Rework C translation.
Pass MCOp as pointer not as ref
Add missing SysImm type
Fix syntax mistakes
Generate additonal sys immediates and op groups.
Handle edge case for printSVERegOp
Handle default arguments of template functions.
Add two missing op groups
Generate a static RecEncodingTable
Set enum values to encodings of the sys ops
Generate a single Enum value file for system operands.
Replace System operand groups with their operand types
Fix missing braces warning
Emit MCOperand validator.
Emit lookupByName functions for sys operands
Add namespaces for ARM.
Check for Target if default arguments of template functions are resolved.
auto-sync opcode & operand encoding info generation (#14)
* Added operand and opcode info generation
* Wrapped deprecated macro under an intellisense check
Basically intellisense fails, causing multiple errors in other files,
so when intellisense parses the code it will use the different version of the macro
* Fixed a small bug
Used double braces to prevent an old bug
Removed extra new line and fixed a bug regarding move semantics
