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487756 Commits

Author SHA1 Message Date
Rot127
26bc587b01
Alpha Fixups () 
* Fix Alpha architecture with newest TableGen generator assumptions.

The latest TableGen assumes that the operand names match the names
of the definitions in classes. This was not the case for Alpha yet.
It also patches operand printers with addresses for Alpha now.

* Fix up patching of operand printers with multiple lines.
 2025-03-29 11:50:05 +00:00
Rot127
a5c8bdfe84
Mark hvc, smc and svc as call. () 2025-03-25 15:41:18 +00:00
Changqing Jing
93d64ce9ba
Fix wrong version requirement of tricore instructions: () 
crc32.b
crc32b.w
crc32l.w
crcn
popcnt.w
shuffle

Remove invalid instruction:
BISR_rc_v161

Learn up misconfigure of nor and not
 2025-02-06 09:44:28 +00:00
Changqing Jing
159c98411e
Add tricore tc1.8 instructions () 
* Add tricore tc1.8 instructions:
add.df
sub.df
madd.df
msub.df
mul.df
div.df
cmp.df
max.df
min.df
min.f
max.f
dftoi
dftoiz
dftoin
ftoin
dftou
dftouz
dftol
dftoul
dftoulz
abs.f
abs.df
dftolz
neg.df
neg.f
qseed.df
itodf
utodf
ltodf
ultodf
dftof
ftodf

* add tricore tc1.8 instructions:
div64
div64.u
rem64
rem64.u
 2025-01-14 15:14:29 +00:00
Rot127
ee9eebb40a Add Mips, SystemZ, Xtensa 2025-01-13 18:53:33 +00:00
Rot127
b6b6e8825c Add TriCore to CI 
Exclude SysOperand table from TriCore
 2025-01-13 18:53:33 +00:00
R33v0LT
5cd3fa147a Add ARC patterns 2025-01-06 18:53:02 +00:00
R33v0LT
d4b34a1dae Set GPR32Reduced OperandType 2024-12-17 12:32:48 +00:00
R33v0LT
2e8642c70d Add ARC to Capstone Printer 2024-12-17 12:32:48 +00:00
Rot127
f6a22fb898 Tread crbitm as register 2024-12-17 12:32:29 +00:00
Rot127
9f87617a17 Fix LI/LIS are no real instructions. 2024-12-17 12:32:29 +00:00
Rot127
1002f679be Fix priv store/load: Make register pointer like regs 2024-12-17 12:32:29 +00:00
Rot127
b709f9c82c Fix endless loop if ReplaceDot = False 2024-12-17 12:32:29 +00:00
Rot127
52da756484 Clean up normalizeMnemonic a little and allow to pass on removal patterns. 2024-12-17 12:32:29 +00:00
Rot127
e6420b28d3 Set correct printer for PS memory operands 2024-11-21 13:48:01 +00:00
Rot127
7c6840d171 Fix QPX instructions. 
Due to 4b43ef3e5c
the names of the operands were matched.
Because FRT dosn't exist in the XForm_1 class,
the generated tables didn't decoded them.
 2024-11-21 13:48:01 +00:00
Rot127
e57d7e2b55 Don't replace dot in alias mnemonic map 2024-11-21 13:48:01 +00:00
Rot127
a3cc36f886 Remove branching instructions which are actually alias. 2024-11-21 13:48:01 +00:00
Rot127
0162e01063 Move store to correct block so meta info is set correclty. 2024-11-10 11:18:28 +00:00
Rot127
c4f934f472 Add memory access infor to ARM 2024-11-10 11:18:28 +00:00
Rot127
c06b997485 Revert for Capstone: 
We want to know that the instruction is v8.
Because this is how it is defined in the ISA.

Revert "[ARM] Change CRC predicate to just HasCRC"

This reverts commit a82c106e571c6991a95c38a936a466895122d713.
 2024-11-10 11:18:28 +00:00
Rot127
92c98d24a3 Fix printer functions which get Address as argument 2024-11-07 19:09:30 +00:00
Rot127
290cd0784e Fix Xtensa reachable assert. 
The immediate given to decodeImm8_sh8Operand has been already shifted.
Checking if it is an 8bit value fails therefore.
 2024-11-05 17:03:06 +00:00
billow
396ba323c8 Xtensa: Add GenCSInsnFormatsEnum.inc support 2024-11-05 13:25:31 +00:00
billow
7f069f5af9 Add getArchSupplInfoXtensa 2024-11-05 13:25:31 +00:00
billow
8b806d4f41 fix: - in Operand Group Name 2024-11-05 13:25:31 +00:00
billow
8bdb4963c2 fix printInsnAliasEnum 2024-11-05 13:25:31 +00:00
billow
48774db25f tricore: fixes all 2024-10-24 12:26:31 +00:00
billow
a1d54201a3 tricore: try fixes 2024-10-24 12:26:31 +00:00
billow
717740dd49 fix: tricore 2024-10-24 12:26:31 +00:00
billow
4b2ed3ee95 fix: tricore 2024-10-24 12:26:31 +00:00
billow
6d32f27923 Add TriCore td files 2024-10-06 12:47:21 +00:00
billow
c0bc1e2f34 Add InsnBytesAsUint24 and add Xtensa to InsnBytesAsUint24 2024-09-27 06:06:40 +00:00
Rot127
2361b73798 Replace hard asserts with assert macros with different behavior. 2024-09-19 16:12:47 +00:00
Rot127
600a1b3d97 Fix: Src operand is not the out operand 2024-09-19 16:12:47 +00:00
Rot127
139e42930c Revert "Add curly brackets to normalize mnemonic." 
Instead make it dependent on even/odd number of brackets.

This reverts commit ac6fd33f567e20f47fff50606caaacdcb583653a.
 2024-09-19 16:12:47 +00:00
Rot127
26a30270a6 Remove incorrect SP reads. 2024-09-19 16:12:47 +00:00
Rot127
1cc0208738 Add instruction formats for SystemZ 2024-09-03 11:24:32 +00:00
Rot127
ac6fd33f56 Add curly brackets to normalize mnemonic. 2024-09-03 11:24:32 +00:00
Rot127
12424fa530 Fix incorrect parameter 2024-09-03 11:24:32 +00:00
Rot127
830c7a8e6f Replace | char of SystemZ insn enums 2024-09-03 11:24:32 +00:00
Rot127
ca07088b26 Add SystemZ decoder macro. 2024-09-03 11:24:32 +00:00
Giovanni
1496434327
Mips + microMips + nanoMips () 
* Mips + microMips + nanoMips
* Add nanomips tests
 2024-09-01 00:57:34 +08:00
Rot127
029bac0e9b Allow to patch multiple default template arguments for Mips. 2024-08-28 08:36:41 +00:00
Rot127
6464d962f4 Handle MIPS SIMM9 operand 2024-07-28 14:29:13 +00:00
Rot127
584efadbc4 Panic if no decoder was initialized. 2024-07-28 14:29:13 +00:00
Rot127
90b6007454 Clear MCInst when the decode fails, to reset operand counter. 2024-07-28 14:29:13 +00:00
Rot127
dddf0d1faa Simplify name comparison 2024-07-07 03:41:09 +00:00
Rot127
933e2a85cf OP_GROUP enums can't be all upper case currently 2024-07-07 03:41:09 +00:00
Rot127
5f266ccfb9 Fix template patching for AArch64 2024-07-07 03:41:09 +00:00