Rot127
095dff8afe
Add AMX and other Apple proprietary instructions. ( #78 )
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* Add docs how to add a new processor extension.
* Remove { for AArch64 instructions.
* Add Apple proprietary AMX extension.
* Add Mul53 instructions.
* Add missing mayLoad and mayStore flags.
* Add gexit, genter, wkdmd, wkdmc instructions.
* Add sdsb and at_as1elx
2025-05-06 09:12:52 +00:00
Rot127
26bc587b01
Alpha Fixups ( #77 )
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Weekly-LLVM-Release-Update / merge-llvm (push) Has been cancelled
Weekly-LLVM-Release-Update / build-llvm-tblgen (push) Has been cancelled
* Fix Alpha architecture with newest TableGen generator assumptions.
The latest TableGen assumes that the operand names match the names
of the definitions in classes. This was not the case for Alpha yet.
It also patches operand printers with addresses for Alpha now.
* Fix up patching of operand printers with multiple lines.
2025-03-29 11:50:05 +00:00
R33v0LT
5cd3fa147a
Add ARC patterns
LLVM-Tblgen-Build / build-and-test-llvm-tblgen (push) Has been cancelled
2025-01-06 18:53:02 +00:00
R33v0LT
2e8642c70d
Add ARC to Capstone Printer
2024-12-17 12:32:48 +00:00
Rot127
b709f9c82c
Fix endless loop if ReplaceDot = False
2024-12-17 12:32:29 +00:00
Rot127
52da756484
Clean up normalizeMnemonic a little and allow to pass on removal patterns.
2024-12-17 12:32:29 +00:00
Rot127
e57d7e2b55
Don't replace dot in alias mnemonic map
2024-11-21 13:48:01 +00:00
Rot127
c4f934f472
Add memory access infor to ARM
2024-11-10 11:18:28 +00:00
Rot127
92c98d24a3
Fix printer functions which get Address as argument
LLVM-Tblgen-Build / build-and-test-llvm-tblgen (push) Has been cancelled
2024-11-07 19:09:30 +00:00
billow
396ba323c8
Xtensa: Add GenCSInsnFormatsEnum.inc support
2024-11-05 13:25:31 +00:00
billow
7f069f5af9
Add getArchSupplInfoXtensa
2024-11-05 13:25:31 +00:00
billow
8b806d4f41
fix: - in Operand Group Name
2024-11-05 13:25:31 +00:00
billow
8bdb4963c2
fix printInsnAliasEnum
2024-11-05 13:25:31 +00:00
billow
717740dd49
fix: tricore
2024-10-24 12:26:31 +00:00
billow
4b2ed3ee95
fix: tricore
2024-10-24 12:26:31 +00:00
billow
c0bc1e2f34
Add InsnBytesAsUint24 and add Xtensa to InsnBytesAsUint24
LLVM-Tblgen-Build / build-and-test-llvm-tblgen (push) Has been cancelled
2024-09-27 06:06:40 +00:00
Rot127
2361b73798
Replace hard asserts with assert macros with different behavior.
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2024-09-19 16:12:47 +00:00
Rot127
139e42930c
Revert "Add curly brackets to normalize mnemonic."
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Instead make it dependent on even/odd number of brackets.
This reverts commit ac6fd33f567e20f47fff50606caaacdcb583653a.
2024-09-19 16:12:47 +00:00
Rot127
1cc0208738
Add instruction formats for SystemZ
2024-09-03 11:24:32 +00:00
Rot127
ac6fd33f56
Add curly brackets to normalize mnemonic.
2024-09-03 11:24:32 +00:00
Rot127
12424fa530
Fix incorrect parameter
2024-09-03 11:24:32 +00:00
Rot127
830c7a8e6f
Replace | char of SystemZ insn enums
2024-09-03 11:24:32 +00:00
Rot127
ca07088b26
Add SystemZ decoder macro.
2024-09-03 11:24:32 +00:00
Giovanni
1496434327
Mips + microMips + nanoMips ( #56 )
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* Mips + microMips + nanoMips
* Add nanomips tests
2024-09-01 00:57:34 +08:00
Rot127
029bac0e9b
Allow to patch multiple default template arguments for Mips.
2024-08-28 08:36:41 +00:00
Rot127
6464d962f4
Handle MIPS SIMM9 operand
2024-07-28 14:29:13 +00:00
Rot127
584efadbc4
Panic if no decoder was initialized.
2024-07-28 14:29:13 +00:00
Rot127
90b6007454
Clear MCInst when the decode fails, to reset operand counter.
2024-07-28 14:29:13 +00:00
Rot127
dddf0d1faa
Simplify name comparison
2024-07-07 03:41:09 +00:00
Rot127
933e2a85cf
OP_GROUP enums can't be all upper case currently
2024-07-07 03:41:09 +00:00
Rot127
5f266ccfb9
Fix template patching for AArch64
2024-07-07 03:41:09 +00:00
Rot127
a795ea9719
Emit CS enum values in all capital letters
2024-06-24 07:27:52 +00:00
R3v0LT
3c619b615d
Tblgen capstone backends - add Alpha architecture ( #17 )
2024-06-04 12:57:14 +00:00
Jiajie Chen
16baaaf307
Rename CS_AC_READ_WRTE to CS_AC_READ_WRITE
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Following https://github.com/capstone-engine/capstone/pull/2358
2024-05-29 08:31:35 +00:00
Jiajie Chen
5c6d1fa0c9
Emit formats enum and supplemental info for LoongArch
2024-05-29 08:31:35 +00:00
Jiajie Chen
bece35d7fa
Avoid using llvm_unreachable
2024-05-29 08:31:35 +00:00
Jiajie Chen
af1ff9c099
Change RegDiffLists type to MCPhysReg
2024-05-29 08:31:35 +00:00
Jiajie Chen
91da70b398
Handle multiple template arguments in handleDefaultArg
2024-05-29 08:31:35 +00:00
Jiajie Chen
1ac920cc21
Add LoongArch support
2024-05-29 08:31:35 +00:00
Rot127
1f5a51cec8
Generate BOUND flags for SME operands.
2024-05-29 08:31:35 +00:00
Rot127
118ad37dd0
Fix regex pattern to not match operand names between ] and [
2024-05-29 08:31:35 +00:00
Rot127
1312d742a5
Add memory access info as supplementary AArch64 info
2024-05-29 08:31:35 +00:00
Rot127
f5c4f04bd6
Check in patterns for memory operand properties.
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- Determine memory operands by there membership of patterns.
Operands can be defined via patterns. The pattern has a type itself.
Patterns are commonly used to define memory operands
(as a collection of multiple other operands).
Here we check, if the operand is part of a pattern with type iPTR.
Type iPTR indicates a memory operand.
- Search for unspecified instruction patterns and extract memory op info from them.
AArch64 has the case of patterns which are not set in the CGI class.
Instead those patterns are free floating in the record keeper.
With this commit we first collect all such unassigned patterns and save them in a map
(indexed by instruction name they belong to).
When instruction operand details are generated, the operand type is searched in the pattern of the instruction.
If there is an operand with the same type in the pattern, which is also of a iPTR pattern, we treat it as memory operand.
Note that we can not compare the operands of the instruction and the pattern operands by name.
Because they simply are not named the same way.
This is a short coming in the td files and should be addressed in LLVM.
Because it is enormiously hard to get a 1 to 1 mapping from a pattern to an instruction
and its operands.
2024-05-29 08:31:35 +00:00
Rot127
162c1c0002
Initialize DecoderComplete flag in generated decoder function.
2024-05-29 08:31:35 +00:00
Rot127
b025bae5cf
Assign enum value to the raw_val member to prevent compiler warnings.
2024-05-29 08:31:35 +00:00
Rot127
a35941283f
Add AdrLabel and AdrpLable to OP_GROUPS
2024-05-29 08:31:35 +00:00
Rot127
2be2c0fed8
Add MatrixIndex_... to the OP_GROUP list
2024-05-29 08:31:35 +00:00
Rot127
04b82d5399
Fix template function translation
2024-05-29 08:31:35 +00:00
Rot127
86c1c566e6
Fix: Don't return NULL for a struct
2024-05-29 08:31:35 +00:00
Rot127
2e51e2eded
Generate InstDecs tables with references to the OpInfo structs.
2024-05-29 08:31:35 +00:00
