481013 Commits

Author SHA1 Message Date
Philip Reames
233971b475 [RISCV] Fix typo in a test and regen another to reduce test diff 2023-11-16 14:28:16 -08:00
Peiming Liu
ccd923e3cb
[mlir][sparse] code cleanup (remove dead code related to filter loop). (#72573) 2023-11-16 14:26:09 -08:00
Augusto Noronha
46396108de
[lldb] Add interface to check if UserExpression::Parse() is cacheable (#66826)
When setting conditional breakpoints, we currently assume that a call to
UserExpression::Parse() can be cached and resued multiple times. This
may not be true for every user expression. Add a new method so
subclasses of UserExpression can customize if they are parseable or not.
2023-11-16 14:20:14 -08:00
Philip Reames
1aa493f064 [RISCV] Further expand coverage for insert_vector_elt patterns 2023-11-16 14:14:31 -08:00
Jonathan Thackray
066c4524bc
[AArch64] Add support for Cortex-A520, Cortex-A720 and Cortex-X4 CPUs (#72395)
Cortex-A520, Cortex-A720 and Cortex-X4 are Armv9.2 AArch64 CPUs.

Technical Reference Manual for Cortex-A520:
   https://developer.arm.com/documentation/102517/latest/

Technical Reference Manual for Cortex-A720:
   https://developer.arm.com/documentation/102530/latest/

Technical Reference Manual for Cortex-X4:
   https://developer.arm.com/documentation/102484/latest/

Patch co-authored by: Sivan Shani <sivan.shani@arm.com>
2023-11-16 22:08:58 +00:00
Aiden Grossman
add20537cc Reland "[llvm-exegesis] Fix preservation of RDI in subprocess mode (#72458)"
This reverts commit 186db1bcb0096a6af348d7e17866c68fa2004068.

This relands commit 0718c1a8405ac130d72cd3525befed2911618cc7.

The REQUIRES flag in the test that was added only specified that the
machine needed to have the capability to execute the snippet rather than
actually run it with performance counters. This would work with
--dummy-perf-counters, but that is not currently supported in the
subprocess execution mode. So for now, we require the ability to
actually perform measurements to prevent test failures in configurations
that don't have libpfm or access to performance counters.
2023-11-16 14:03:07 -08:00
Jason Molenda
5f64b94076
Clarify error messages on corefiles that no plugin handles (#72559)
These error messages are written in a way that makes sense to an lldb
developer, but not to an end user who asks lldb to run on a compressed
corefile or whatever. Simplfy the messages.
2023-11-16 13:58:07 -08:00
serge-sans-paille
102f7fce8d
[llvm] Reduce memory footprint of Debug metadata nodes (#71227)
Using a combination of reordering fields and using empty SubclassData32
/ SubclassData1, it's possible to improve the size of data structures
used to store debug info in the IR:

Before:

DILexicalBlock: 24
DILexicalBlockFile: 24
DIModule: 24
DITemplateParameter: 24
DICommonBlock: 24
DIMacro: 24
DICompileUnit: 56
DIType: 48
DINamespace: 24
DIVariable: 24
DIGlobalVariable: 32
DILocalVariable: 32
DILabel: 24

After:

DILexicalBlock: 24
DILexicalBlockFile: 16
DIModule: 16
DITemplateParameter: 16
DICommonBlock: 16
DIMacro: 16
DICompileUnit: 48
DIType: 40
DINamespace: 16
DIVariable: 24
DIGlobalVariable: 24
DILocalVariable: 32
DILabel: 16
2023-11-16 21:55:43 +00:00
Fangrui Song
ae623d16d5 [Driver,Gnu] Simplify -static -static-pie -shared -pie handling and suppress -shared -rdynamic warning
These options select different link modes (note: -shared -static can be
used together for musl and mingw). It makes sense to place them
together, which enables some simplification. The relevant ld options
are now consistently placed after -m, similar to GCC.

While here, suppress -Wunused-command-line-argument warning when -shared
-rdynamic are used together (introduced by commit
291f4a00232b5742940d67e2ecf9168631251317). It can be argued either way
whether the warning is justified (in ELF linkers --export-dynamic
functionality is subsumed by -shared), but it is not useful (users can
do -Wl,--export-dynamic, bypassing the driver diagnostic).
2023-11-16 13:48:04 -08:00
David Li
ac3779e92e
Enable Custom Lowering for fabs.v8f16 on AVX (#71730)
[X86]: Enable custom lowering for fabs.v8f16 on AVX

Currently, custom lowering of fabs.v8f16 requires AVX512FP16, which is
too restrictive. For v8f16 fabs lowering, no instructions in AVX512FP16
are needed. Without the fix, horribly inefficient code is generated
without AVX512FP16. Note instcombiner generates calls to intrinsics
@llvm.fabs.v8f16 when simplifyping AND <8 x half> operations.
2023-11-16 13:47:31 -08:00
Philip Reames
73e963379e [RISCV] Add test coverage for partial buildvecs idioms
Test coverage for an upcoming set of changes
2023-11-16 13:33:12 -08:00
Peiming Liu
ff8815e597
[mlir][sparse] code cleanup (remove topSort in CodegenEnv). (#72550) 2023-11-16 13:21:49 -08:00
Florian Hahn
6f3b88baa2
[VPlan] Move trunc ([s|z]ext A) simplifications to simplifyRecipe.
Split off simplification from D149903 as suggested.

This should be effectively NFC until D149903 lands.
2023-11-16 21:17:10 +00:00
PiJoules
b2d62c9a58
[clang] Ensure fixed point conversions work in C++ (#68344) 2023-11-16 13:11:15 -08:00
Aiden Grossman
cdfb51295d
[MLGO] Remove -tfutils-use-simplelogger flag (#72492)
This flag was redundant and the value was not used anywhere, so it
should be removed.
2023-11-16 12:50:46 -08:00
Florian Hahn
10c0166909
[PhaseOrdering] Add tests where early sinking prevents if-conversion. 2023-11-16 20:31:21 +00:00
Alex Langford
a322d50804 [lldb] Add forward declaration for SBWatchpointOptions in SBDefines.h 2023-11-16 12:13:44 -08:00
Louis Dionne
f97a579b74 [runtimes] Add TODO about CXX_STANDARD_REQUIRED being off after review comment 2023-11-16 14:58:52 -05:00
Craig Topper
337f0ededc [RISCV] Fix memory leak in RISCVInstrInfoTest.cpp unittest
We need to make sure the RISCVTargetMachine is also deleted.
2023-11-16 11:48:27 -08:00
androm3da
4e6a9fccaa
Hexagon: Add memw_phys, l2gclean* instructions (#72420) 2023-11-16 13:48:20 -06:00
Maksim Levental
4eaf3a9c12
[mlir][python] reformat transform ext (#71136) 2023-11-16 13:37:52 -06:00
Matthias Braun
a9cc6fc280
LoopVectorize: Set branch_weight for conditional branches (#72450)
Consistently add `branch_weights` metadata in any condition branch
created by `LoopVectorize.cpp`:
- Will only add metadata if the original loop-latch branch had metadata
assigned.
- Most checks should rarely trigger so I am using a 127:1 ratio.
- For the middle block we assume an equal distribution of modulo
results.
2023-11-16 11:33:46 -08:00
Billy Zhu
0ab6b20c36
[MLIR] Add DIExpression to LLVM dialect (#72462)
Add initial support for DIExpression in LLVM dialect.

Similar to LLVM IR, DI Expression is encoded as a list of uint64. The
difference is that LLVM IR has helpers for understanding the expression
(e.g. for verification and pretty printing), whereas the current support
added by this PR treats the expression elements as opaque.
2023-11-16 11:32:02 -08:00
Craig Topper
927f6f1858 [RISCV] Use bset+addi for (not (sll -1, X)).
This is an alternative to #71420 that handles i32 on RV64 safely
by pre-promoting the pattern in DAG combine.
2023-11-16 11:14:53 -08:00
Craig Topper
4eaf986be4 [RISCV] Add test cases for (not (sll -1, X)) for Zbs. NFC
We can use (ADDI (BSET X0, X), -1).
2023-11-16 11:14:53 -08:00
Kazu Hirata
f8e8530f73 [StaticAnalyzer] Fix warnings about missing override
This patch fixes:

  clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp:609:23:
  error: 'describe' overrides a member function but is not marked
  'override' [-Werror,-Winconsistent-missing-override]

  clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp:627:23:
  error: 'describe' overrides a member function but is not marked
  'override' [-Werror,-Winconsistent-missing-override]
2023-11-16 11:06:01 -08:00
Tarun Prabhu
34e4e5eb70
[flang][Driver] Support -rpath, -shared, and -static in the frontend (#66702)
Enable -rpath, -shared, and -static for the flang frontend. This brings
it in line with clang. Fixes issue #65546.
2023-11-16 12:01:17 -07:00
Matthias Braun
cb4627d150
Add setBranchWeigths convenience function. NFC (#72446)
Add `setBranchWeights` convenience function to ProfDataUtils.h and use
it where appropriate.
2023-11-16 10:55:19 -08:00
Aiden Grossman
186db1bcb0 Revert "[llvm-exegesis] Fix preservation of RDI in subprocess mode (#72458)"
This reverts commit 0718c1a8405ac130d72cd3525befed2911618cc7.

The test doesn't have the correct requires string apparently because it
attempts to run on all the buildbots. Reverting until I have time to fix
the test and reland it.
2023-11-16 10:39:53 -08:00
Aiden Grossman
f49bca9b5a
[CMake] Make specifying invalid build type a fatal error (#72021)
This patch makes it so that specifying an invalid value for
CMAKE_BUILD_TYPE is a fatal error. Having this simply as a warning has
caused me (and probably others) a decent amount of headache. The check
was present before, but was proposed to be modified to a warning in
https://github.com/llvm/llvm-project/issues/60975 and changed to a
warning in c75dbeda15c10424910ddc83a9ff7669776c19ac. This patch
reenables that behavior to hopefully reduce frustration for people
building LLVM in the common case while still allowing for alternative
build types to be setup without needing to perform source modification
through the addition of a CMake flag.
2023-11-16 10:32:14 -08:00
Aiden Grossman
0718c1a840
[llvm-exegesis] Fix preservation of RDI in subprocess mode (#72458)
I made a typo at some point while doing the subprocess implementation,
trying to pop RIP from the stack. For whatever reason, this ends up as
popq %rax after being JITed, which means we aren't properly preserving
the value of %rdi.

Regression test added.

This fixes #72188.
2023-11-16 10:27:10 -08:00
Eric
f4e3fb5972
Refactor dockerfile to support Buildkite AND Github Actions (#71954)
This change adds the image used by the self-hosted Github Actions
builders.

In an attempt to make the transition simple, all of the different images
share as much of the same state as possible, including packages, users,
etc... This results in bigger images, but that shouldn't be a problem.
That said, the refactorings caused the buildkite image to shrink by 100
MB.

This change also renames all of the packages for consistency. Bots will
have to be changed to use the new package names eventually.

Again, docker-compose was used as the source of truth for defining
argument.

I have already pushed example images to ghcr.io/libcxx/<name>:testing
2023-11-16 12:52:46 -05:00
Craig Topper
2fbd088524
[InstCombine] Queue Xor for deletion after replacing its uses in freelyInvertAllUsersOf. (#72445)
Fixes #72433
2023-11-16 09:46:34 -08:00
Logikable
3d2527ebe3
[Kaleidoscope] Switch to the new PassManager, revisited. (#72324)
Rollforward of #69032, which was reverted in
[63d19cf](63d19cfd85).

New: implemented changes in
https://github.com/llvm/llvm-project/pull/69032#issuecomment-1809250162.
Given the PassBuilder is how we expect users to register passes, the
tutorial should reflect that.
2023-11-16 09:13:56 -08:00
Momchil Velikov
4ac5b0da8d Revert "[MachineSink][AArch64] Enable sink-and-fold by default (#72132)"
This reverts commit 13fe0386454d2f4c9bad4e20fc59699d1a49b8cf.

May have broken an LLDB test https://lab.llvm.org/buildbot/#/builders/96/builds/48609
2023-11-16 17:07:39 +00:00
Balázs Kéri
699e1019af
[clang][analyzer] Improve 'errno' handling in StdLibraryFunctionsChecker. (#71392)
The checker now displays one combined note tag for errno-related and
"case"-related notes. Previous functions in the errno-modeling part that
were used for construction of note tags are removed. The note tag added
by StdLibraryFunctionsChecker contains the code to display the note tag
for 'errno' (this was done previously by these removed functions).
2023-11-16 18:06:51 +01:00
Antonio Frighetto
ebbb9cdbb3 [SROA] Allow llvm.launder.invariant.group intrinsic to be splittable
Let `llvm.launder.invariant.group` intrinsic as well as instructions
operating on memory addresses, whose invariance may be broken by the
intrinsic, to be rewritten.

Fixes: https://github.com/llvm/llvm-project/issues/72035.
2023-11-16 17:56:34 +01:00
Juergen Ributzka
d3b75c4750
[clang] Make -fvisibility={} and -ftype-visibility={} benign options. (#71985)
Both options do not affect the AST content that is serialized into the PCM. This
commit includes the following changes:
    
1.) Mark `-fvisibility={}` and `-ftype-visibility={}` as benign options.That
     means they are no longer considered part of the module hash, which can
     reduce the number of module variants.
    
2.) Add a test to verify the generated LLVM IR is not affected by the default
     visibiliy mode in the module.

3.) Add a test to clang-scan-deps to ensure only one module is build, even if
      the above mentioned options are used.
    
This fixes rdar://118246054.
2023-11-16 08:41:20 -08:00
Fabian Mora
be9fa9dee5
[flang][NVPTX] Add initial support to the NVPTX target (#71992)
This patch adds initial support to the NVPTX target, enabling `flang` to
produce OpenMP offload code for NVPTX targets.
2023-11-16 11:34:28 -05:00
Alexey Bataev
009002a8cb [SLP][NFC]Unify matching for perfect diamond match between cost and codegen
models, NFC.
2023-11-16 08:11:52 -08:00
Michael Buch
70900ec799
[lldb][DWARFASTParserClang][NFC] Clarify comment around static member variable handling (#72495) 2023-11-16 16:09:47 +00:00
Valery Pykhtin
667ba7f8f3
[AMDGPU] Fix GCNRewritePartialRegUses pass: vector regclass is selected instead of scalar. (#69957)
For the following testcase:

undef %1.sub1:sgpr_96 = COPY undef %0:sgpr_32
%3:vgpr_32 = V_LSHL_ADD_U32_e64 %1.sub1:sgpr_96, ...

GCNRewritePartialRegUses produced:

%4:vgpr_32 = COPY undef %1:sgpr_32
dead %2:vgpr_32 = V_LSHL_ADD_U32_e64 %4, ...

Register class for %4 is incorrect: there should be sgpr_32 instead of
vgpr_32 because the original %1 had scalar regclass. This patch fixes
that.

Note that GCNRewritePartialRegUses pass isn't enabled by default yet.
2023-11-16 16:56:46 +01:00
Alexey Bataev
206799fcf5 [SLP]Fix PR72524: "Out-of-bounds shuffle mask element" failed.
Need to check if we ran into subvector extract pattern before checking
for identity vector to avoid compiler crash.
2023-11-16 07:39:32 -08:00
Lucas Duarte Prates
59b2301508
[AArch64] Introduce the Armv9.5-A architecture version (#72392)
This introduces the Armv9.5-A architecture version, including the
relevant command-line option for -march.

Mode details about the Armv9.5-A architecture version can be found at:
*
https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2023
* https://developer.arm.com/documentation/ddi0602/2023-09/

Patch by Oliver Stannard.
2023-11-16 15:38:32 +00:00
Youngsuk Kim
f432a004c5 [llvm] Remove no-op ptr-to-ptr bitcasts (NFC)
Opaque ptr cleanup effort (NFC).
2023-11-16 09:19:45 -06:00
Alexey Bataev
95703642e3 [SLP]Fix PR72202: wrong mask emission for the first found vector
operand.

Need to copy the submask not to the very first part of the common
extractelements vector mask, but to the proper one to avoid wrong code
emission.
2023-11-16 07:01:05 -08:00
LLVM GN Syncbot
9edc0f592d [gn build] Port 7f28e8ced7ef 2023-11-16 14:50:00 +00:00
Alex Bradbury
42d9232a02
[TargetInstrInfo][NFC] Don't restrict isAddImmediate description to physical registers (#72357)
None of the in-tree implementations have different behaviour for
physical vs virtual registers, and it seems would work equally well if
used with virtual registers. As such, perhaps it's simplest to just drop
that part of the doc comment.
2023-11-16 14:44:11 +00:00
Alex Bradbury
7f28e8ced7
[RISCV] Implement RISCVInstrInfo::isAddImmediate (#72356)
This hook is called by the target-independent implementation of
TargetInstrInfo::describeLoadedValue. I've opted to test it via a C++
unit test, which although fiddly to set up seems the right way to test a
function with such clear intended semantics (rather than testing the
impact indirectly).

isAddImmediate will never recognise ADDIW as an add immediate which I
_think_ is conservatively correct, as the caller may not understand its
semantics vs ADDI.

Note that although the doc comment for isAddImmediate specifies its
behaviour solely in terms of physical registers, none of the current
in-tree implementations (including this one) bail out on virtual
registers (see #72357).
2023-11-16 14:43:31 +00:00
Alexey Bataev
181b2c1b4a [SLP][NFC]Add a test for PR72202 to show a bug in a mask generation for
vectorized extractelements operands.
2023-11-16 06:36:04 -08:00