474868 Commits

Author SHA1 Message Date
Andrzej Warzyński
57cf6896cd
[mlir][vector] Fix vector.broadcast lowering for scalable vectors (#66344)
This patch makes sure that the following case is lowered correctly
("duplication"):
```
  func.func @broadcast_scalable_duplication(%arg0: vector<[32]xf32>) -> vector<1x[32]xf32> {
    %res = vector.broadcast %arg0 : vector<[32]xf32> to vector<1x[32]xf32>
    return %res : vector<1x[32]xf32>
  }
```
2023-09-15 16:35:47 +01:00
Andrzej Warzynski
cadabb58f1 [mlir][linalg][nfc] Fix typo in a file name
Follow-up of D158427
2023-09-15 15:31:36 +00:00
Cyndy Ishida
dc787bc94c [TextAPI] Add missing flag input for <=tbdv3 formats 2023-09-15 08:30:28 -07:00
Jay Foad
fcbdcb13ce
[AMDGPU] Tweak tuple weight calculation. NFC. (#66490)
This just makes it more obvious that GCNRegPressure does not actually
use pressure sets.
2023-09-15 16:30:06 +01:00
Andrzej Warzynski
c92124765e [mlir][Linalg] Move test
To avoid confusion with vectorization-masked.mlir, move

  test/Dialect/Linalg/masked_vectorization.mlir

to:

  test/Dialect/Linalg/transpose-compose-masked-vectorize-and-cleanups.mlir

The updated name better reflects what's being tested.

Differential Revision: https://reviews.llvm.org/D158427
2023-09-15 15:21:32 +00:00
bipmis
530a45c296 Add a or(phi,phi) test without loops 2023-09-15 16:18:25 +01:00
Chris B
b799e9dafa
[DX] Support pipeline state masks (#66425)
The DXContainer pipeline state information encodes a bunch of mask
vectors that are used to track things about the inputs and outputs from
each shader.

This adds support for reading and writing them throught he YAML test
interfaces. The writing logic in MC is extremely primitive and we'll
want to revisit the API for that, but since I'm not sure how we'll want
to generate the mask bits from DXIL during code generation I didn't want
to spend too much time on the API.

Fixes #59479
2023-09-15 10:02:54 -05:00
cor3ntin
1b18e98642
[Github] Improve formating of PR diffs in bot notifications (#66118)
* This avoid pinging folks on all issue when they got pinged on bugzilla
eons ago
* Avoid formatting bugs when there is html in the issue description
* Truncate the list of files and the diff independently of each other.
This avoids truncating cutting a file line in 2 and to cut in the middle
of html markup. This is a fringe case but it does happen when people
accidentally push weird branches conflicting on all the files.
2023-09-15 16:58:05 +02:00
Vladislav Dzhidzhoev
4e970d7bd8
[AArch64][GlobalISel] Select llvm.aarch64.neon.st* intrinsics (#65491)
Similar to llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
2023-09-15 16:35:21 +02:00
vic
87d77d3cfb
[mlir][IR] Insert operations before SingleBlock's terminator (#65959)
Change `SingleBlock::{insert,push_back}` to avoid inserting the argument
operation after the block's terminator. This allows removing
`SingleBlockImplicitTerminator`'s functions with the same name.

Define `Block::hasTerminator` checking whether the block has a
terminator operation.

Signed-off-by: Victor Perez <victor.perez@codeplay.com>
2023-09-15 16:17:35 +02:00
Louis Dionne
b64bf895e5
[libc++] Improve the verbosity of configuration errors when a compiler flag is not supported (#66379)
If an assertion fails during the configuration of the test suite because
the compiler doesn't support a flag (or the compiler configuration is
borked entirely), we will now print additional context to help debug the
issue instead of just saying "The compiler doesn't support the flag" and
bailing.
2023-09-15 10:15:50 -04:00
Louis Dionne
320d4c90fa
[libc++] Update Apple CI jobs to run the C++23 configuration (#66367)
We were running the test suite in C++20 mode, but we should really be
tracking the latest supported version. We can't do C++26 because the
latest stable AppleClang doesn't support it yet.
2023-09-15 10:15:15 -04:00
Louis Dionne
fdf91c768e
[libc++][NFC] Introduce named states in std::call_once (#66289)
This idea is extracted from https://reviews.llvm.org/D112319. It makes
the code easier to read but doesn't otherwise change any functionality.
2023-09-15 10:14:13 -04:00
zhoujing
de6a919f77 [BOLT] Fix deadloop bug in taildup
The intent is clearly to push the tail rather than current BB.

Reviewed By: maksfb

Differential Revision: https://reviews.llvm.org/D159289
2023-09-15 22:12:53 +08:00
Aaron Ballman
e8b1af9a55 Fix clang-tidy sphinx docs
This addresses issues found by:
https://lab.llvm.org/buildbot/#/builders/115/builds/53446
2023-09-15 10:11:10 -04:00
Louis Dionne
69875d59bc
[libc++] Refactor node creation and destruction in list and forward_list (#65614)
This removes a lot of code duplication, makes the code simpler and
prepares the terrain for https://reviews.llvm.org/D101206, which will
fix some UB in the node-based containers.

This also allows removing the dependency of list and forward_list on
unique_ptr by using __allocation_guard instead.
2023-09-15 10:10:26 -04:00
Louis Dionne
4d08eccd63
[libc++] Implement P2538R1 "ADL-proof std::projected" (#65411)
Notice that because Holder<Incomplete> is _possible_ to complete, but
_unsafe_ to complete, that means that Holder<Incomplete>* is basically
not an iterator and it's not even safe to ask if
input_iterator<Holder<Incomplete>*> because that _will_ necessarily
complete the type. So it's totally expected that we still cannot safely
ask e.g.


static_assert(std::indirect_unary_predicate<bool(&)(Holder<Incomplete>&),
Holder<Incomplete>*>);

or even

static_assert(!std::indirect_unary_predicate<int, Holder<Incomplete>*>);

This was originally uploaded as https://reviews.llvm.org/D119029 and I
picked it up here as part of the Github PR transition.

Co-authored-by: Arthur O'Dwyer <arthur.j.odwyer@gmail.com>
2023-09-15 10:09:38 -04:00
Jakub Kuderski
63327fa814
[GitHub] Add teams for ADT and Support (#65519) 2023-09-15 10:09:02 -04:00
LLVM GN Syncbot
75501f5362 [gn build] Port 72d4d4e3b9f6 2023-09-15 13:12:27 +00:00
dingfei
7c9abbd8a4 Reapply [analyzer] Simplify SVal for simple NonLoc->Loc casts
Reapply after fixing the test by enabling the `debug.ExprInspection` checker.

-----

NonLoc symbolic SVal to Loc casts are not supported except for
nonloc::ConcreteInt.

This change simplifies the source SVals so that the more casts can
go through nonloc::ConcreteInt->loc::ConcreteInt path. For example:

  void test_simplified_before_cast_add(long long t1) {
    long long t2 = t1 + 3;
    if (!t2) {
      int *p = (int *) t2;
      clang_analyzer_eval(p == 0); // expected-warning{{TRUE}}
    }
  }

If simplified, 't2' is 0, resulting 'p' is nullptr, otherwise 'p'
is unknown.

Fixes #62232
2023-09-15 15:07:39 +02:00
David Green
b0f0aa852d [AArch64] Guard against a invalid size request in performVecReduceAddCombine
With both +sve and +dotprod, and a scalable vecreduce(sext) we could attempt to
access the number of elements of a scalable vector. Guard against this for now,
until scalable dotprod are properly supported.
2023-09-15 14:04:21 +01:00
Congcong Cai
72d4d4e3b9
[clang-tidy]add new check bugprone-compare-pointer-to-member-virtual-function (#66055) 2023-09-15 20:59:12 +08:00
Nikita Popov
47324cfd7d Reapply [Verifier] Sanity check alloca size against DILocalVariable fragment size
Reapply after fixing a clang bug this exposed in D158972 and
adjusting a number of tests that failed for 32-bit targets.

-----

Add a check that the DILocalVariable fragment size in dbg.declare
does not exceed the size of the alloca.

This would have caught the invalid debuginfo regenerated by rustc
in https://github.com/llvm/llvm-project/issues/64149.

Differential Revision: https://reviews.llvm.org/D158743
2023-09-15 14:51:50 +02:00
Jay Foad
303eb50cf4 [update_mir_test_checks] Fix new test in non-X86 builds 2023-09-15 13:43:00 +01:00
sstwcw
a20f485bb0 [clang-format] Generate the style options
I was in a hurry and I forgot to do it for the last commit.
2023-09-15 12:37:21 +00:00
sstwcw
ae90f689a5
[clang-format] Disable string breaking in JS for now (#66372)
See the discussion

[here](https://github.com/llvm/llvm-project/pull/66168#issuecomment-1719038797).

The functionality is not mature enough.
2023-09-15 12:36:09 +00:00
martinboehme
0069004856
[clang][dataflow] Add a test for context-sensitive analysis on a self-referential class. (#66359)
The test demonstrates that the `this` pointer seen in the constructor
has the
same value as the address of the variable the object is constructed
into.
2023-09-15 14:31:10 +02:00
Nikita Popov
c0a64ec139 [MemoryBuiltins] Use SmallDenseMap for visited map (NFC)
This partially recovers a major compile-time regression introduced
by #65326.
2023-09-15 14:26:59 +02:00
Dhruv Chawla
ff9ae3f49d
[IRSymtab] Replace linear time lookup with DenseSet (#66376)
There is an inefficiency in the IRSymtab Builder where it does a lookup
of PreservedSymbols when calling addSymbol. This lookup is linear in
time, so it tends to be quite slow. Replacing it with DenseSet gives a
0.1% speedup:

https://llvm-compile-time-tracker.com/compare.php?from=02d27eac0f3f470a93635fc98ae990bf2a9809ed&to=62b09786fff4d53aa0c75b64aea48de241e4a856&stat=instructions:u

This change is quite similar to https://reviews.llvm.org/D157951.
2023-09-15 17:49:31 +05:30
Jay Foad
24a082878f
[update_mir_test_checks] Handle multiple defs of vreg (#66483)
When (post-SSA) MIR has multiple defs of the same vreg,
update_mir_test_checks would use different variable names for each def
like this, where DEF and DEF1 both refer to %0:
```
    %0:gr32 = IMPLICIT_DEF
    %0:gr32 = IMPLICIT_DEF
-->
    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:gr32 = IMPLICIT_DEF
```
This should be harmless, but it messed up the way that mangle_vreg
counts the number of names in vreg_map to come up with a new numeric
suffix, such that you could get the same variable name for different
vregs, like this, where DEF2 refers to both %0 and %2:
```
    %0:gr32 = IMPLICIT_DEF
    %1:gr32 = IMPLICIT_DEF
    %0:gr32 = IMPLICIT_DEF
    %2:gr32 = IMPLICIT_DEF
-->
    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:gr32 = IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF2:%[0-9]+]]:gr32 = IMPLICIT_DEF
    ; CHECK-NEXT: [[DEF2:%[0-9]+]]:gr32 = IMPLICIT_DEF
```
Fix this by always using the same variable name for the same vreg.
2023-09-15 13:10:45 +01:00
Jay Foad
e4eb204333
[update_mir_test_checks] Precommit test for multiple defs of vreg (#66482)
XFAIL it until it is fixed by an upcoming commit.
2023-09-15 13:08:56 +01:00
Vladislav Dzhidzhoev
c464896dbe
[AArch64][GlobalISel] Select llvm.aarch64.neon.ld* intrinsics (#65630)
Similar to llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp.
2023-09-15 14:03:48 +02:00
Nikita Popov
0e67a68478 [SCEV] Add tests for PR66066 (NFC) 2023-09-15 13:53:11 +02:00
Nikita Popov
ab6667f844 [ConstantRange] Optimize smul nowrap with constant (NFC)
Don't call makeExactMulNSWRegion() twice with the same value.
2023-09-15 13:50:08 +02:00
Timm Bäder
73371faf05 [clang][Interp][NFC] Remove unused includes 2023-09-15 13:37:35 +02:00
Benjamin Kramer
3454cf67bd Revert "[MachineLICM] Handle Subloops"
This reverts commit 5ec9699c4d1f165364586d825baef434e2c110b4. It
accesses MI after it has been hoisted.
2023-09-15 13:20:31 +02:00
Benjamin Kramer
7af24c765d Disable writing an output file to the source directory in Driver test 2023-09-15 13:19:13 +02:00
Balazs Benics
03693d5b40 Revert "[analyzer] Simplify SVal for simple NonLoc->Loc casts (#66463)"
This reverts commit 3ebf3dd30da219f9f9aee12f42d45d18d55e7580.

I thought "Mergeing" will wait and confirm if the checks pass, and only
merge it if they succeed. Apparently, it's not the case here xD

The test is just broken in x86. See:
https://lab.llvm.org/buildbot/#/builders/109/builds/73686
2023-09-15 13:18:34 +02:00
Nathan Gauër
71d6d81a19
[Github] add spirv backend team (#66075)
This PR adds the paths the SPIR-V backend folks maintains. (Another
distince SPIR-V team exists, but only for the MLIR part (mlir-spirv).

---------

Signed-off-by: Nathan Gauër <brioche@google.com>
2023-09-15 13:17:06 +02:00
Timm Bäder
23c39f9a9e [clang][Interp] Diagnose unknown parameter values
Differential Revision: https://reviews.llvm.org/D156509
2023-09-15 13:10:19 +02:00
Timm Bäder
177f9ab2fb [clang][Interp] Check pointer inc/dec ops for initialization
Differential Revision: https://reviews.llvm.org/D158702
2023-09-15 13:04:04 +02:00
Ding Fei
3ebf3dd30d
[analyzer] Simplify SVal for simple NonLoc->Loc casts (#66463)
NonLoc symbolic SVal to Loc casts are not supported except for
nonloc::ConcreteInt.

This change simplifies the source SVals so that the more casts can go
through nonloc::ConcreteInt->loc::ConcreteInt path. For example:

```c
  void test_simplified_before_cast_add(long long t1) {
    long long t2 = t1 + 3;
    if (!t2) {
      int *p = (int *) t2;
      clang_analyzer_eval(p == 0); // expected-warning{{TRUE}}
    }
  }
```
If simplified, `t2` is 0, resulting `p` is nullptr, otherwise `p` is
unknown.

Fixes #62232
2023-09-15 13:00:32 +02:00
Alexey Bataev
b9ad72ba05 [SLP]Fix PR66176: SLP incorrectly reorders select operands.
On the very first iteration for the reductions, when trying to build
reduction for boolean logic operations, no need to compare LHS/RHS with
the Reduction(VectorizedTree), need to compare with actual parameters of
the reduction operations.
2023-09-15 03:57:36 -07:00
Zhang
5664b56043
[CMake][Z3]Don't attempt to compile / run if cross-compiling (#66355)
Otherwise CMake might throw and error:
CMake Error: try_run() invoked in cross-compiling mode, please set the
following cache variables appropriately:
   Z3_RETURNCODE (advanced)
   Z3_RETURNCODE__TRYRUN_OUTPUT (advanced)
2023-09-15 12:57:33 +02:00
Matthew Devereau
9bbbfbc7fd
[AArch64][SME] Emit Zero instruction for NewZA functions
[The ACLE](https://github.com/ARM-software/acle/pull/268) Demands that
functions with the aarch64_pstate_za_new attribute set all bits of the
ZA register to zero upon entry.
2023-09-15 11:40:30 +01:00
Jay Foad
ceb68eea8c
[AMDGPU] Remove repeated -mtriple options from RUN lines (#66486) 2023-09-15 11:29:24 +01:00
Job Noorman
c5ba61978c [BOLT][RISCV] Add support for linker relaxation
Calls on RISC-V are typically compiled to `auipc`/`jalr` pairs to allow
a maximum target range (32-bit pc-relative). In order to optimize calls
to near targets, linker relaxation may replace those pairs with, for
example, single `jal` instructions.

To allow BOLT to freely reassign function addresses in relaxed binaries,
this patch proposes the following approach:
- Expand all relaxed calls back to `auipc`/`jalr`;
- Rely on JITLink to relax those back to shorter forms where possible.

This is implemented by detecting all possible call instructions and
replacing them with `PseudoCALL` (or `PseudoTAIL`) instructions. The
RISC-V backend then expands those and adds the necessary relocations for
relaxation.

Since BOLT generally ignores pseudo instruction, this patch makes
`MCPlusBuilder::isPseudo` virtual so that `RISCVMCPlusBuilder` can
override it to exclude `PseudoCALL` and `PseudoTAIL`.

To ensure JITLink knows about the correct section addresses while
relaxing, reassignment of addresses has been moved to a post-allocation
pass. Note that this is probably the time it had to be done in the
first place since in `notifyResolved` (where it was done before), all
symbols are supposed to be resolved already.

Depends on D159082

Reviewed By: maksfb

Differential Revision: https://reviews.llvm.org/D159089
2023-09-15 11:57:28 +02:00
Nikita Popov
18e77760ce [GVN] Also remove phi nodes from VN table (PR65447)
Followup to D158849: We also need to remove the phi node from the
VN table, which is not handled by removeInstruction().

Fixes https://github.com/llvm/llvm-project/issues/65447.
2023-09-15 11:50:34 +02:00
Benjamin Maxwell
665995b918 [mlir][Conversion] Allow lowering to fixed arrays of scalable vectors
This allows lowering vector types like: vector<3x[4]> or vector<3x2x[4]>
to LLVM IR, i.e. vectors where the trailing dim is scalable.

This is contingent on:
https://discourse.llvm.org/t/rfc-enable-arrays-of-scalable-vector-types/72935

More tests will be added in later patches, however, some MLIR fixes are
needed first.

Depends on: D158517

Reviewed By: awarzynski

Differential Revision: https://reviews.llvm.org/D158752
2023-09-15 09:33:18 +00:00
Yusuke MINATO
4eafb5f57c
[flang][hlfir] Add hlfir.minval intrinsic (#66306)
Adds a new HLFIR operation for the MINVAL intrinsic according to the
design set out in flang/docs/HighLevelFIR.md.
2023-09-15 18:30:06 +09:00