Commit Graph

459694 Commits

Author SHA1 Message Date
4vtomat
e6ffd42a93 [tests] Add missing REQUIRES: riscv-registered-target to clang test 2023-05-02 09:19:32 -07:00
Shao-Ce SUN
fe558efe71 [RISCV][CodeGen] Support Zfinx codegen
This patch was split from D122918 . Co-Author: @liaolucy @realqhc

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D148874
2023-05-03 00:13:38 +08:00
NAKAMURA Takumi
ea2b79d48d Try to fix CodeGenTypes issues in mlir 2023-05-03 00:58:57 +09:00
Dan McGregor
ea6ecdbfe0 Call printName to get name of Decl
Rather than sending a name directly to the stream, use printName
to preserve any PrintingPolicy. This ensures that names are properly
affected by path remapping.

Fixes: https://github.com/llvm/llvm-project/issues/62192
Differential Revision: https://reviews.llvm.org/D149272
2023-05-02 11:56:23 -04:00
Mark de Wever
d5442761f9 [libc++][ranges] Fixes as_rvalue's linkage.
This was discovered while working on modules. They can't export
declarations with internal linkage.

Reviewed By: #libc, philnik

Differential Revision: https://reviews.llvm.org/D149593
2023-05-02 17:55:16 +02:00
Adrian Prantl
45905b53f0 Add missing include 2023-05-02 08:37:40 -07:00
Spenser Bauman
19109a274e [mlir][tosa] Fix crash when inferring shape of tosa.equal
The tosa-infer-shapes pass crashes when trying to infer the output shape
of tosa.equal when the input shape is unranked.
This is due to tosa-infer-shapes requiring at least information on the
base type of the resulting operation from inferReturnTypeComponents.
This change enhances EqualOp::inferReturnTypeComponents to always supply
the inferred elementType.

Reviewed By: eric-k256

Differential Revision: https://reviews.llvm.org/D149582
2023-05-02 08:18:35 -07:00
NAKAMURA Takumi
631bfdbee5 Switch llvm/CodeGen/MachineValueType.h to the generated one
Prune `SupportTests/MVTTest` since it is no longer needed.

Depends on D148769

Differential Revision: https://reviews.llvm.org/D148770
2023-05-03 00:13:20 +09:00
NAKAMURA Takumi
5d71ec6e44 Split out CodeGenTypes from CodeGen for LLT/MVT
This reduces dependencies on `llvm-tblgen` so much.

`CodeGenTypes` depends on `Support` at the moment.
Be careful to append deps on this, since Targets' tablegens
depend on this.

Depends on D149024

Differential Revision: https://reviews.llvm.org/D148769
2023-05-03 00:13:20 +09:00
NAKAMURA Takumi
c1221251fb Restore CodeGen/MachineValueType.h from Support
This is rework of;

  - rG13e77db2df94 (r328395; MVT)

Since `LowLevelType.h` has been restored to `CodeGen`, `MachinveValueType.h`
can be restored as well.

Depends on D148767

Differential Revision: https://reviews.llvm.org/D149024
2023-05-03 00:13:20 +09:00
NAKAMURA Takumi
9cfeba5b12 Restore CodeGen/LowLevelType from Support
This is rework of;
  - D30046 (LLT)

Since I have introduced `llvm-min-tblgen` as D146352, `llvm-tblgen`
may depend on `CodeGen`.

`LowLevlType.h` originally belonged to `CodeGen`. Almost all userse are
still under `CodeGen` or `Target`. I think `CodeGen` is the right place
to put `LowLevelType.h`.

`MachineValueType.h` may be moved as well. (later, D149024)

I have made many modules depend on `CodeGen`. It is consistent but
inefficient. It will be split out later, D148769

Besides, I had to isolate MVT and LLT in modmap, since
`llvm::PredicateInfo` clashes between `TableGen/CodeGenSchedule.h`
and `Transforms/Utils/PredicateInfo.h`.
(I think better to introduce namespace llvm::TableGen)

Depends on D145937, D146352, and D148768.

Differential Revision: https://reviews.llvm.org/D148767
2023-05-03 00:13:19 +09:00
NAKAMURA Takumi
2df215f7a6 [Bazel] Update for D148308 (riscv-sifive) 2023-05-03 00:13:19 +09:00
Erich Keane
3e850a6eea Revert "[Clang][Sema] Fix comparison of constraint expressions"
This reverts commit e3b1083e00.

This was reverted because it breaks a number of libstdc++ examples, AND
required a workaround that causes hiding of legitimate bugs.
2023-05-02 08:09:35 -07:00
Erich Keane
ad7111495f Revert "[Clang][Sema] Add a temporary workaround in SemaConcept.cpp"
This reverts commit ce861ec782.
2023-05-02 08:09:01 -07:00
Jakub Kuderski
9701c5abd6 [mlir][arith] Add narrowing patterns for max*i and min*i
Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D149583
2023-05-02 10:50:07 -04:00
Teresa Johnson
48f18ecd82 [ThinLTO] Loosen up variable importing correctness checks
After importing variables, we do some checking to ensure that variables
marked read or write only, which have been marked exported (e.g.
because a referencing function has been exported), are on at least one
module's imports list. This is because the read or write only variables
will be internalized, so we need a copy any any module that references
it.

This checking is overly conservative in the case of linkonce_odr or
other linkage types where there can already be a duplicate copy in
existence in the importing module, which therefore wouldn't need to
import it. Loosen up the checking for these linkage types.

Fixes https://github.com/llvm/llvm-project/issues/62468.

Differential Revision: https://reviews.llvm.org/D149630
2023-05-02 07:49:03 -07:00
Jakub Kuderski
46740dd02b [mlir][arith] Add narrowing patterns for subi, divsi, and divui
Each of these ops is compatible with only one extension kind and
produces an extra result bit.

I checked these transformation in Alive2:
1. subi + extsi: https://alive2.llvm.org/ce/z/ipmZZA
2. divsi + extsi: https://alive2.llvm.org/ce/z/fAcqUv
3. divui + extui: https://alive2.llvm.org/ce/z/QZJpFp

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D149531
2023-05-02 10:44:29 -04:00
Cullen Rhodes
707b6e94b8 [mlir][SparseTensor][ArmSVE] Fix missing lli substitutions
The MLIR SVE integration tests are now enabled in the
clang-aarch64-full-2stage buildbot under emulation (QEMU) and two of the
sparse integration tests are failing [1]:

  * mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_sorted_coo.mlir
  * mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_spmm.mlir

The reason for this is the SVE RUN lines use plain 'lli' rather than the
'%lli_host_or_aarch64_cmd' substitution that's necessary to run under
emulation. The CI doesn't support SVE so the tests will SIGILL unless
run under emulation.

I should note the logs don't show a SIGILL, only the non-descript:

  FileCheck error: '<stdin>' is empty.

but I expect this is what's actually happening.

https://lab.llvm.org/buildbot/#/builders/179/builds/6051/steps/12/logs/stdio
2023-05-02 14:43:48 +00:00
Joseph Huber
2353b52eae [libc] Fix some missing features from the hermetic test support
This patch addresses some of the flags and features that are currently
missing from the hermetic test support. This mostly just fixes the
`add_libc_test` option failing to find a few dependencies or missing
arguments from the previous unit test support.

Reviewed By: lntue

Differential Revision: https://reviews.llvm.org/D149629
2023-05-02 09:40:24 -05:00
Job Noorman
d755e10e7a [BOLT] Make sure Mach-O binaries are actually linked
Note that this issue is also solved by D147544.

Reviewed By: alexander-shaposhnikov

Differential Revision: https://reviews.llvm.org/D149244
2023-05-02 16:22:49 +02:00
Job Noorman
f3ea4228fd [BOLT] Make sure all section allocations have deterministic contents
For empty sections, RuntimeDyld always allocates 1 byte but leaves it
uninitialized. This causes the contents of some output sections to be
non-deterministic.

Note that this issue is also solved by D147544.

Fixes #59008

Reviewed By: maksfb

Differential Revision: https://reviews.llvm.org/D149243
2023-05-02 16:18:01 +02:00
Jakub Kuderski
e2f7563d7c [mlir][arith] Add narrowing patterns for addi and muli
These two ops are handled in a very similar way -- the only difference
in the number result bits produced.

I checked these transformation with Alive2:
1.  addi + sext: https://alive2.llvm.org/ce/z/3NSs9T
2.  addi + zext: https://alive2.llvm.org/ce/z/t7XHOT
3.  muli + sext: https://alive2.llvm.org/ce/z/-7sfW9
4.  muli + zext: https://alive2.llvm.org/ce/z/h4yntF

Reviewed By: antiagainst

Differential Revision: https://reviews.llvm.org/D149530
2023-05-02 10:10:10 -04:00
Jay Foad
55678b43b5 [CodeGen] One more use of MachineBasicBlock::phis. NFC. 2023-05-02 14:55:24 +01:00
Joel E. Denny
fa280c1994 [OpenMP] In libomptarget, assume alignment at powers of two
This patch fixes a bug introduced by D142586, which landed as
434992c96e.  The fix was to only look for alignments that are powers
of 2.  See the new test case for details.

Reviewed By: jdoerfert, jhuber6

Differential Revision: https://reviews.llvm.org/D149490
2023-05-02 09:44:58 -04:00
Alexey Lapshin
709bc11266 [DWARFLinker][NFC] Make interfaces to be compatible.
This patch makes interface of AddressManager from DWARFLinker
to be compatible with AddressesMap from DWARFLinkerParallel.
This makes both linkers to be interchangeable.

Differential Revision: https://reviews.llvm.org/D147455
2023-05-02 14:59:23 +02:00
4vtomat
fa43608d16 [RISCV][RISCV][clang] Split out SiFive Vector C intrinsics from riscv_vector.td
Since we don't always need the vendor extension to be in riscv_vector.td,
so it's better to make it be in separated header.

Depends on D148223 and D148680

Differential Revision: https://reviews.llvm.org/D148308
2023-05-02 05:51:51 -07:00
Alexandre Ganea
8efc7de0e6 [llvm][unittests] Silence warning on MSVC after 5b2423183c
Differential revision: https://reviews.llvm.org/D149609
2023-05-02 08:49:47 -04:00
Dmitry Chernenkov
73e15b5edb [lldb] Add cstdio include to fix a595b931f1 2023-05-02 12:47:37 +00:00
4vtomat
4bf846ba40 [RISCV] Split out part of riscv_vector.td to riscv_vector_common.td
This makes other new targets able to reuse predefined classes
in their own *.td files.

Differential Revision: https://reviews.llvm.org/D148680
2023-05-02 05:40:13 -07:00
Nelson Chu
8ed9cf06e9 [SiFive][RISCV][clang] Support C intrinsics for xsfvcp extension.
Depends on D147934 and D147935

Differential Revision: https://reviews.llvm.org/D148223
2023-05-02 05:40:13 -07:00
Jay Foad
4b2381a5f0 [CodeGen] Make use of MachineBasicBlock::phis. NFC. 2023-05-02 13:39:01 +01:00
Shilei Tian
8a11c5522f Revert "[OpenMP] Make libomptarget link against libomp"
This reverts commit dc049a4ea6.

It causes issue of export target.
2023-05-02 08:35:55 -04:00
Mariya Podchishchaeva
7133283835 [clang] Do not attempt to zero-extend _BitInt(1) when not required
`ConvertTypeForMem` doesn't return wider type for _BitInt unless it is
used in a bitfield, so no need to extend when trying to initialize a
global variable.

Fixes https://github.com/llvm/llvm-project/issues/62207

Reviewed By: erichkeane, shafik

Differential Revision: https://reviews.llvm.org/D149436
2023-05-02 08:23:22 -04:00
Zhiyao Ma
1d0ccebcd7 [ARM] Don't allocate memory if free space in segmented stack is just enough
Assuming that the stack grows downwards, it is fine if the stack
pointer is exactly at the stacklet boundary. We should use
less-or-equal condition when deciding whether to skip new memory
allocation.

Differential Revision: https://reviews.llvm.org/D149315
2023-05-02 13:09:49 +01:00
Kiran Chandramohan
39e8e59950 [Flang][OpenMP] Use fir.if instead of scf.if in lastprivate lowering
For finding the last iteration of a loop, or the last section an
if condition is generated. Using scf::if can cause some lowering
issues since the code contained inside it can have branches. Using
fir::if instead ensures that the fir::if is lowered into branches
along with any code contained inside that can generate branches.

Fixes #62458.

Reviewed By: NimishMishra

Differential Revision: https://reviews.llvm.org/D149547
2023-05-02 12:02:04 +00:00
Michael Buch
52882de0e6 [lldb][test] TestCPP20Standard.py: make it a libc++ test
We just want to test whether the language switch works.
This is easier to control for libc++, since for bots building
the tests against libstdc++ we might not have the necessary
`<compare>` header available currently.
2023-05-02 07:38:53 -04:00
LU Hongyi
e15d6b520e [lldb][DWARFExpression] Fix DW_OP_div to use signed division
This patch resolves an issue where a value
is incorrectly displayed if it is represented
by DW_OP_div.

This issue is caused by lldb evaluating
operands of DW_OP_div as unsigned
and performed unintended unsigned
division.

This issue is resolved by creating two
temporary signed scalar and performing
signed division.

(Addresses GH#61727)

Differential Revision: https://reviews.llvm.org/D147370
2023-05-02 07:38:52 -04:00
Samira Bazuzi
2cdb6b84c1 [clang][dataflow] Expose DataflowAnalysisContext from DataflowEnvironment.
This will eliminate the need for more pass-through APIs. Also replace pass-through usages with this exposure.

Reviewed By: ymandel, gribozavr2, xazax.hun

Differential Revision: https://reviews.llvm.org/D149464
2023-05-02 11:32:19 +00:00
Nikita Popov
084ca632ac [EarlyCSE] Only combine metadata for load CSE
There is no need to combine metadata if we're performing store to
load forwarding. In that case we would end up combining metadata
on an unrelated load instruction.
2023-05-02 12:51:56 +02:00
Nikita Popov
a67a21bf41 [EarlyCSE] Add additional metadata preservation test (NFC) 2023-05-02 12:51:55 +02:00
LLVM GN Syncbot
7cf7ebd917 [gn build] Port 852bf52cc9 2023-05-02 10:31:09 +00:00
Balázs Kéri
852bf52cc9 [clang-tidy] Add check bugprone-multiple-new-in-one-expression.
Reviewed By: donat.nagy
Fixed test failures with previous commit.

Differential Revision: https://reviews.llvm.org/D138777
2023-05-02 12:29:17 +02:00
Nikita Popov
5362a0d859 [LCSSA] Remove unused ScalarEvolution argument (NFC)
After D149435, LCSSA formation no longer needs access to
ScalarEvolution, so remove the argument from the utilities.
2023-05-02 12:17:05 +02:00
David Green
41549b5350 [AArch64] Add sign bits handling for vector compare nodes
This adds ComputeNumSignBits for the NEON vector comparison nodes, which all
either return 0 or -1. Also adds sign_extend_inreg from VASHR+VSHL to show it
performing transforms.

Differential Revision: https://reviews.llvm.org/D148624
2023-05-02 11:05:35 +01:00
Simon Pilgrim
da942fee5b Fix MSVC "truncation of constant value" warnings. NFC. 2023-05-02 10:43:28 +01:00
Simon Pilgrim
14390ecb75 Fix MSVC "not all control paths return a value" warnings. NFC. 2023-05-02 10:43:28 +01:00
Vassil Vassilev
87ae746924 [clang-repl] Add a test coverage for nested out-of-line dtor disambiguation.
This came up as a review comment in https://reviews.llvm.org/D148425
2023-05-02 09:39:48 +00:00
Jay Foad
16980c08cb [AMDGPU] Make use of new tablegen operator !range. NFC. 2023-05-02 10:36:15 +01:00
LLVM GN Syncbot
61cfb96fd3 [gn build] Port 7b7a6b641a 2023-05-02 09:28:16 +00:00
Balázs Kéri
7b7a6b641a Revert "[clang-tidy] Add check bugprone-multiple-new-in-one-expression."
This reverts commit 1aa36da153.
2023-05-02 11:23:31 +02:00