Commit Graph

171405 Commits

Author SHA1 Message Date
Thomas Lively
05ca6955a4 [WebAssembly] Update bleeding-edge cpu features
Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, jfb, llvm-commits

Differential Revision: https://reviews.llvm.org/D54362

llvm-svn: 346570
2018-11-10 00:11:14 +00:00
Philip Reames
2de52b53cc [GC] Simplify linking of GC builtin GC strategies
llvm-svn: 346569
2018-11-09 23:56:21 +00:00
Eli Friedman
f70ae59019 [ARM64] [Windows] Handle funclets
This patch adds support for funclets in frame lowering and ISel
lowering. Together with D50288 and D50166, it enables C++ exception
handling.

Patch by Sanjin Sijaric, with some fixes by me.

Differential Revision: https://reviews.llvm.org/D51524

llvm-svn: 346568
2018-11-09 23:33:30 +00:00
Dylan McKay
9f3b55d70a [AVR] Reorder the CHECK lines in directmem.ll to match current trunk
In r346432 ("[DAGCombine] Improve alias analysis for chain of independent stores"),
the order of ldi/sts blocks changed.

The new IR is equivalent to the old IR.

This patch updates the test to fix the test suite.

llvm-svn: 346565
2018-11-09 23:17:59 +00:00
Craig Topper
f2f9d81200 [SelectionDAG] Fix a -Wparentheses warning from gcc in an assert. NFC
gcc wants parentheses around the logical OR since there is a logical AND for the string.

llvm-svn: 346564
2018-11-09 23:11:30 +00:00
Eli Friedman
d24c268544 [ARM] Add MemOperand to LDRcp to enable DCE.
LDRcp should be deleted when the dest register is dead in register
coalescing. Without MemOp, dead LDRcp will cause dead constant pool
value which references to non-existing label.

Patch by Yin Ma.

Differential Revision: https://reviews.llvm.org/D54173

llvm-svn: 346563
2018-11-09 23:09:17 +00:00
Eli Friedman
7bed1aa94c [JumpThreading] Fix exponential time algorithm computing known values.
ComputeValueKnownInPredecessors has a "visited" set to prevent infinite
loops, since a value can be visited more than once.  However, the
implementation didn't prevent the algorithm from taking exponential
time. Instead of removing elements from the RecursionSet one at a time,
we should keep around the whole set until
ComputeValueKnownInPredecessors finishes, then discard it.

The testcase is synthetic because I was having trouble effectively
reducing the original.  But it's basically the same idea.

Instead of failing, we could theoretically cache the result instead.
But I don't think it would help substantially in practice.

Differential Revision: https://reviews.llvm.org/D54239

llvm-svn: 346562
2018-11-09 22:35:26 +00:00
Thomas Lively
40bba35cf8 Revert "Exclude wasm target from Windows packaging due to PR39448"
Summary:
This reverts r346122 now that the failing tests have been
disabled. Depends on D54353.

Reviewers: aheejin, dschuff

Subscribers: fedor.sergeev, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D54354

llvm-svn: 346559
2018-11-09 22:05:51 +00:00
Thomas Lively
565db5808e [WebAssembly] Disable custom NaN payload tests
Summary:
These tests fail on 32-bit builds because NaN payload bits in floating point
immediates are not necessarily preserved through compilation. This is because
the MC layer uses native doubles to store these values. The tests will be
reenabled once this problem has been fixed or deleted if we decide we don't care
about lowering payload bits.

Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D54353

llvm-svn: 346558
2018-11-09 22:04:37 +00:00
Craig Topper
61f669b57b [X86] Move the promotion of v16i16->v16i8 for avx512f but not avx512bw from lowering to isel. Change to use vpmovzx instead of vpmovsx.
With avx512f but not avx512bw we need to extend to v16i32 then truncate that to to v16i8. Previously we emitted both nodes during lowering, but I'm trying to switch to using target independent nodes and with that switched the extend+truncate wou

This patch changes the implementation to what will be necessary with that patch which helps minimize test diffs.

llvm-svn: 346552
2018-11-09 20:09:53 +00:00
James Y Knight
11b6c9c654 Branch/tag all projects with a single commit in release-tagging script.
This change updates the release script to use svnmucc to create all
the branches with one commit.

This will ensure that the git tag won't bounce around if the git
migration runs in-between separate commits creating a branch.

Additionally, update the list of projects to include all of the
projects in the monorepo, plus test-suite.

Differential Revision: https://reviews.llvm.org/D53467

llvm-svn: 346550
2018-11-09 19:45:13 +00:00
Bryan Chan
21e4975915 [AArch64] Support HiSilicon's TSV110 processor
Reviewers: t.p.northover, SjoerdMeijer, kristof.beyls

Reviewed By: kristof.beyls

Subscribers: olista01, javed.absar, kristof.beyls, kristina, llvm-commits

Differential Revision: https://reviews.llvm.org/D53908

llvm-svn: 346546
2018-11-09 19:32:08 +00:00
Andrea Di Biagio
ef186de8c9 [llvm-mca] Account for buffered resources when analyzing "Super" resources.
This was noticed when working on PR3946.
By construction, a group cannot be used as a "Super" resource. That constraint
is enforced by method `SubtargetEmitter::ExpandProcResource()`.

A Super resource S can be part of a group G. However, method
`SubtargetEmitter::ExpandProcResource()` would not update the number of
consumed resource cycles in G based on S.
In practice, this is perfectly fine because the resource usage is correctly
computed for processor resource units. However, llvm-mca should still check if G
is a buffered resource.
Before this patch, llvm-mca didn't correctly check if S was part of a group that
defines a buffer. So, the instruction descriptor was not correctly set.

For now, the semantic change introduced by this patch doesn't affect any of the
upstream scheduling models. However, it will allow to make some progress on PR3946.

llvm-svn: 346545
2018-11-09 19:30:20 +00:00
Nico Weber
abe2a8d7cb [MS demangler] Use a slightly shorter unmangling for mangled strings.
Before: const wchar_t * {L"%"}
Now: L"%"

See also PR39593.
Differential Revision: https://reviews.llvm.org/D54294

llvm-svn: 346544
2018-11-09 19:28:50 +00:00
Fangrui Song
e21ccabb7a [Hexagon] Fix some -Wunused-function with LLVM_DUMP_METHOD and -Wunused-variable
llvm-svn: 346543
2018-11-09 19:24:48 +00:00
Ulrich Weigand
0b20001f6e [SystemZ] Add a couple of missing tests
A few fp128 tests were omitted from test/CodeGen/SystemZ/fp-round-01.ll
since in early days, LLVM couldn't handle implicitly generated library
calls to functions with long double arguments on SystemZ.

This deficiency was actually long since fixed, but those tests are
still missing.  This patch adds the missing tests.  NFC.

llvm-svn: 346541
2018-11-09 19:16:21 +00:00
Paul Robinson
7b233f2012 [DWARFv5] Emit normal type units in .debug_info comdats.
Differential Revision: https://reviews.llvm.org/D54282

llvm-svn: 346540
2018-11-09 19:06:09 +00:00
Craig Topper
8aad56ad3f [X86] Turn X86ISD::VSEXT into X86ISD::VZEXT if the upper bits aren't demanded.
This makes X86ISD::VSEXT more similar to ISD::SIGN_EXTEND and ISD::ZERO_EXTEND.

I'm hoping to replace X86ISD::VSEXT/VZEXT with target independent nodes. Making the target specific nodes similar to the target independent nodes helps minimize test diffs in that patch.

llvm-svn: 346539
2018-11-09 19:05:51 +00:00
Simon Pilgrim
bdefad428b [CostModel][X86] SK_ExtractSubvector is free if the subvector is at the start of the source vector
llvm-svn: 346538
2018-11-09 19:04:27 +00:00
Jordan Rupprecht
780ec70d82 [Hexagon] Fix unused variable warning in release builds
llvm-svn: 346537
2018-11-09 18:54:27 +00:00
Fangrui Song
1d0a9d40b9 [WebAssembly] Hotfix of WebAssemblyInstructionTableSize after rL346465
llvm-svn: 346535
2018-11-09 18:32:20 +00:00
Simon Pilgrim
9f3675acb9 [TTI] Flip vector types in getShuffleCost SK_ExtractSubvector call
For SK_ExtractSubvector, the default 'Ty' type is the source operand type and 'SubTy' is the destination subvector type

I got this the wrong way around when I added rL346510

llvm-svn: 346534
2018-11-09 18:30:59 +00:00
Stanislav Mekhanoshin
276abb911a [AMDGPU] Cleanup optimize-if-exec-masking.mir test. NFC.
llvm-svn: 346533
2018-11-09 18:23:39 +00:00
Brendon Cahoon
1faabfff72 [Hexagon] Implement noreturn optimization
Eliminate the stack frame in functions with the noreturn nounwind
attributes, and when the noreturn-stack-elim target feature is
enabled. This reduces the code and stack space needed for noreturn
functions.

Differential Revision: https://reviews.llvm.org/D54210

llvm-svn: 346532
2018-11-09 18:16:24 +00:00
Greg Clayton
9ebbccbe64 Add total function byte size and inline function byte size to "llvm-dwarfdump --statistics"
Differential Revision: https://reviews.llvm.org/D54217

llvm-svn: 346531
2018-11-09 18:10:02 +00:00
Craig Topper
9e195442a4 [DAGCombiner][X86][Mips] Enable combineShuffleOfScalars to run between vector op legalization and DAG legalization. Fix bad one use check in combineShuffleOfScalars
It's possible for vector op legalization to generate a shuffle. If that happens we should give a chance for DAG combine to combine that with a build_vector input.

I also fixed a bug in combineShuffleOfScalars that was considering the number of uses on a undef input to a shuffle. We don't care how many times undef is used.

Differential Revision: https://reviews.llvm.org/D54283

llvm-svn: 346530
2018-11-09 18:04:34 +00:00
Jordan Rupprecht
6ebaed2a1d [llvm-strings] Fix whitespaces to match strings output.
Summary:
The current implementation prepends a space on every line, making it difficult to compare against GNU strings.

The space appears to have come from handling --radix in rL292707. The space is for making sure there's a space between the radix and the value; however the space is still emitted even when there is no radix. This change fixes that so the space is only emitted when there is a radix.

Reviewers: jhenderson

Reviewed By: jhenderson

Subscribers: llvm-commits, compnerd

Differential Revision: https://reviews.llvm.org/D54238

llvm-svn: 346529
2018-11-09 18:03:21 +00:00
Stanislav Mekhanoshin
23d5825904 [AMDGPU] Always pass TRI into findRegister[Use/Def]OperandIdx
This only covers AMDGPU BE, hopefully all occurrences.

Differential Revision: https://reviews.llvm.org/D54235

llvm-svn: 346528
2018-11-09 17:58:59 +00:00
Krzysztof Parzyszek
2f7314c085 [Hexagon] Place globals with explicit .sdata section in small data
Both -fPIC and -G0 disable placement of globals in small data section,
but if a global has an explicit section assigmnent placing it in small
data, it should go there anyway.

llvm-svn: 346523
2018-11-09 17:31:22 +00:00
Serge Guelton
edff374355 Type safe version of MachinePassRegistry
Previous version used type erasure through a `void* (*)()` pointer,
which triggered gcc warning and implied a lot of reinterpret_cast.

This version should make it harder to hit ourselves in the foot.

Differential revision: https://reviews.llvm.org/D54203

llvm-svn: 346522
2018-11-09 17:19:45 +00:00
Philip Reames
be340eedc1 [docs][statepoints] Reformulate open issues list
Some have been partially resolved, so update that.  And restructure to make it easie to find and search.

llvm-svn: 346518
2018-11-09 17:09:16 +00:00
Fangrui Song
cb661fa4de Fix -Wsign-compare warning
llvm-svn: 346515
2018-11-09 16:45:37 +00:00
Max Moroz
a32a4e3b54 [llvm-cov] Remove "default:" label in the switch covering all enum values.
Summary:
Fixing the build breakage:
http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/27309

Reviewers: vsk, allevato, Dor1s

Reviewed By: Dor1s

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D54323

llvm-svn: 346514
2018-11-09 16:44:36 +00:00
Philip Reames
b5c052fe8f [docs][statepoint] Expand a bit on problems with mixing references and raw pointers since it keeps coming up in discussions
llvm-svn: 346513
2018-11-09 16:40:34 +00:00
Zaara Syeda
f7abaf5af5 [Power9] Allow gpr callee saved spills in prologue to vectors registers
Currently in llvm, CalleeSavedInfo can only assign a callee saved register to
stack frame index to be spilled in the prologue. We would like to enable
spilling gprs to vector registers. This patch adds the capability to spill to
other registers aside from just the stack. It also adds the changes for power9
to spill gprs to volatile vector registers when they are available.
This happens only for leaf functions when using the option
-ppc-enable-pe-vector-spills.

Differential Revision: https://reviews.llvm.org/D39386

llvm-svn: 346512
2018-11-09 16:36:24 +00:00
Simon Pilgrim
ebe3689ac9 [CostModel] Add SK_ExtractSubvector handling to getInstructionThroughput (PR39368)
Add ShuffleVectorInst::isExtractSubvectorMask helper to match shuffle masks.

llvm-svn: 346510
2018-11-09 16:28:19 +00:00
Philip Reames
438c3f8eaf [docs][statepoint] tweak a title
llvm-svn: 346509
2018-11-09 16:27:04 +00:00
Alexey Bataev
336616d4e5 Revert "[DEBUGINFO, NVPTX]DO not emit ',debug' option if no debug info or only debug directives are requested."
This reverts commit r345972. Need to update the description + possibly
to update the patch itself after discussion with Eric Christofer.

llvm-svn: 346508
2018-11-09 16:22:35 +00:00
Max Moroz
60087383d9 [llvm-cov] Add lcov tracefile export format.
Summary:
lcov tracefiles are used by various coverage reporting tools and build
systems (e.g., Bazel). It is a simple text-based format to parse and
more convenient to use than the JSON export format, which needs
additional processing to map regions/segments back to line numbers.

It's a little unfortunate that "text" format is now overloaded to refer
specifically to JSON for export, but I wanted to avoid making any
breaking changes to the UI of the llvm-cov tool at this time.

Patch by Tony Allevato (@allevato).

Reviewers: Dor1s, vsk

Reviewed By: Dor1s, vsk

Subscribers: mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D54266

llvm-svn: 346506
2018-11-09 16:10:44 +00:00
Jonas Paulsson
ec1b2ec29d [SystemZ] Avoid inserting same value after replication
A minor improvement of buildVector() that skips creating an
INSERT_VECTOR_ELT for a Value which has already been used for the
REPLICATE.

Review: Ulrich Weigand
https://reviews.llvm.org/D54315

llvm-svn: 346504
2018-11-09 15:44:28 +00:00
Nicolai Haehnle
b56d4d7977 AMDGPU: Add testcase to demonstrate a condition with pre-existing waitcnt
Relevant for https://reviews.llvm.org/D54226.

llvm-svn: 346501
2018-11-09 15:13:12 +00:00
Sam McCall
0f672de003 Revert "[VFS] Add "expand tilde" argument to getRealPath."
This reverts commit r346453.
This is a complex change to a widely-used interface, and was not reviewed.

llvm-svn: 346500
2018-11-09 15:11:34 +00:00
Sam Parker
dfb73cdc7f [ARM] Don't promote i1 types in ARM CGP
Now that we have mixed type sizes, i1 values need to be explicitly
handled as we want to avoid promoting these values.

Differential Revision: https://reviews.llvm.org/D54308

llvm-svn: 346499
2018-11-09 15:06:33 +00:00
Sanjay Patel
b6cb8a0e20 [x86] try to form broadcast before widening shuffle elements
I noticed that we weren't generating broadcasts as much I thought we would with 
D54271, and this is part of the problem.

Widening the shuffle elements means adding bitcasts and hiding the relationship 
between a splatted scalar and the vector. If we can form a broadcast, do that 
before going through the rest of the shuffle lowering because broadcasts should 
be cheap and can often be load-folded.

Differential Revision: https://reviews.llvm.org/D54280

llvm-svn: 346498
2018-11-09 14:54:58 +00:00
Alex Bradbury
5acae2b123 [RISCV] Avoid unnecessary XOR for seteq/setne 0
Differential Revision: https://reviews.llvm.org/D53492

Patch by James Clarke.

llvm-svn: 346497
2018-11-09 14:47:36 +00:00
Alex Bradbury
9ada2aa2ad [RISCV] Update test/CodeGen/RISCV/calling-conv.ll after rL346432
The DAGCombiner changes led to a different schedule.

llvm-svn: 346496
2018-11-09 14:35:44 +00:00
Petar Avramovic
d6c3df84d0 [MIPS GlobalISel] narrowScalar G_CONSTANT
Legalize s64 G_CONSTANT using narrowScalar on MIPS 32.

Differential Revision: https://reviews.llvm.org/D54255

llvm-svn: 346495
2018-11-09 14:21:16 +00:00
Krzysztof Parzyszek
753f5bbc55 [Hexagon] Handle Hexagon's SHF_HEX_GPREL section flag
llvm-svn: 346494
2018-11-09 14:17:27 +00:00
Clement Courbet
cd4088c8f1 [llvm-exegesis] Fix unit tests on PowerPC/AArch64.
We were comparing char*s and not contents. Introduced in rL346489.

llvm-svn: 346493
2018-11-09 14:08:29 +00:00
Florian Hahn
b0abfd0d17 Revert r346483: [CallSiteSplitting] Only record conditions up to the IDom(call site).
This cause a failure with EXPENSIVE_CHECKS

llvm-svn: 346492
2018-11-09 13:28:58 +00:00