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60 Commits

Author SHA1 Message Date
Owen Anderson
3146968039 Allow the MCDisassembler to return a "soft fail" status code, indicating an instruction that is disassemblable, but invalid. Only used for ARM UNPREDICTABLE instructions at the moment. 
Patch by James Molloy.

llvm-svn: 137830
 2011-08-17 17:44:15 +00:00
Owen Anderson
ffb049d199 Separate out Thumb1 instructions that need an S bit operand from those that do not, for the purposes of decoding them. 
llvm-svn: 137787
 2011-08-16 23:45:44 +00:00
Owen Anderson
2e722e7cd4 Specify a necessary fixed bit for VLD3DUP, and otherwise rearrange the Thumb2 NEON decoding hooks to bring us closer to correctness. 
llvm-svn: 137686
 2011-08-15 23:38:54 +00:00
Owen Anderson
42946000dd Enforce the constraint that Rt must be even on LDRD/STRD instructions in ARM mode. Update tests to reflect this fact. 
Patch by James Molloy.

llvm-svn: 137647
 2011-08-15 20:51:32 +00:00
Owen Anderson
894585de33 Fix problems decoding the to/from-lane NEON memory instructions, and add a comprehensive NEON decoding testcase. 
llvm-svn: 137635
 2011-08-15 18:44:44 +00:00
Owen Anderson
2ea55a0881 Fix some remaining issues with decoding ARM-mode memory instructions, and add another batch of tests. 
llvm-svn: 137502
 2011-08-12 20:36:11 +00:00
Owen Anderson
7b426d97ad Fix decoding of ARM-mode STRH. 
llvm-svn: 137499
 2011-08-12 20:02:50 +00:00
Owen Anderson
322b9ce8bf Fix decoding of pre-indexed stores. 
llvm-svn: 137487
 2011-08-12 18:12:39 +00:00
Owen Anderson
a1df383bae Separate decoding for STREXD and LDREXD to make each work better. 
llvm-svn: 137476
 2011-08-12 17:58:32 +00:00
Jim Grosbach
edefbb31c3 ARM STRT assembly parsing and encoding. 
llvm-svn: 137372
 2011-08-11 22:18:00 +00:00
Owen Anderson
8a55a4d7be Add another accidentally omitted predicate operand. 
llvm-svn: 137370
 2011-08-11 22:08:38 +00:00
Owen Anderson
253a691ae5 Add missing predicate operand on SMLA and friends. 
llvm-svn: 137368
 2011-08-11 22:05:38 +00:00
Owen Anderson
64c500c7dd Fix decoding support for STREXD and LDREXD. 
llvm-svn: 137356
 2011-08-11 21:34:58 +00:00
Owen Anderson
4618d77bcd Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>. 
llvm-svn: 137347
 2011-08-11 20:47:56 +00:00
Owen Anderson
73e7d34732 Continue to tighten decoding by performing more operand validation. 
llvm-svn: 137340
 2011-08-11 20:21:46 +00:00
Jim Grosbach
bfc85134c2 ARM STRBT assembly parsing and encoding. 
llvm-svn: 137337
 2011-08-11 20:04:56 +00:00
Owen Anderson
63ccfdccd1 Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases. 
llvm-svn: 137325
 2011-08-11 19:00:18 +00:00
Owen Anderson
decc5fcced Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC. 
llvm-svn: 137323
 2011-08-11 18:55:42 +00:00
Owen Anderson
8d6b9f063f Improve error checking in the new ARM disassembler. Patch by James Molloy. 
llvm-svn: 137320
 2011-08-11 18:24:51 +00:00
Jim Grosbach
5322f1ea74 ARM LDRT assembly parsing and encoding. 
llvm-svn: 137282
 2011-08-10 23:43:54 +00:00
Owen Anderson
0fde7a84ee Add initial support for decoding NEON instructions in Thumb2 mode. 
llvm-svn: 137236
 2011-08-10 19:01:10 +00:00
Owen Anderson
0819cf208f Cleanups based on Nick Lewycky's feedback. 
llvm-svn: 137224
 2011-08-10 17:36:48 +00:00
Owen Anderson
87b5ce880a Push GPRnopc through a large number of instruction definitions to tighten operand decoding. 
llvm-svn: 137189
 2011-08-10 00:03:03 +00:00
Owen Anderson
b717d71aa1 Tighten operand checking of register-shifted-register operands. 
llvm-svn: 137180
 2011-08-09 23:33:27 +00:00
Owen Anderson
62faf296dd Tighten operand checking on memory barrier instructions. 
llvm-svn: 137176
 2011-08-09 23:25:42 +00:00
Owen Anderson
869ce85500 Tighten operand checking on CPS instructions. 
llvm-svn: 137172
 2011-08-09 23:05:39 +00:00
Owen Anderson
8ad37f68a2 Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI. 
llvm-svn: 137168
 2011-08-09 22:48:45 +00:00
Benjamin Kramer
ca48bdfd5b ARM Disassembler: sign extend branch immediates. 
Not sure about BLXi, but this is what the old disassembler did.

llvm-svn: 137156
 2011-08-09 22:02:50 +00:00
Owen Anderson
4232cf9141 Silence an false-positive warning. 
llvm-svn: 137154
 2011-08-09 21:38:14 +00:00
Owen Anderson
2aa4c7e391 Tighten Thumb1 branch predicate decoding. 
llvm-svn: 137146
 2011-08-09 21:07:45 +00:00
Owen Anderson
ffe1c55752 Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter. 
This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.

llvm-svn: 137144
 2011-08-09 20:55:18 +00:00
Jim Grosbach
767e9d16e6 ARM refactoring assembly parsing of memory address operands. 
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.

The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.

This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.

Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.

llvm-svn: 136845
 2011-08-03 23:50:40 +00:00
Johnny Chen
7ceb5e40b6 Fix typo in the comment. 
llvm-svn: 129837
 2011-04-19 23:58:52 +00:00
Kevin Enderby
6e09a5d065 Adding support for printing operands symbolically to llvm's public 'C' 
disassembler API.  Hooked this up to the ARM target so such tools as Darwin's
otool(1) can now print things like branch targets for example this:
  blx _puts
instead of this:
  blx #-36
And even print the expression encoded in the Mach-O relocation entried for
things like this:
  movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 129284
 2011-04-11 18:08:50 +00:00
Johnny Chen
61713b9c16 Fixed the t2PLD and friends disassembly and add two test cases. 
llvm-svn: 128322
 2011-03-26 01:32:48 +00:00
Johnny Chen
69bc7c288b Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer! 
llvm-svn: 128241
 2011-03-24 21:42:55 +00:00
Benjamin Kramer
a9c4afdeec Plug a leak in the arm disassembler and put the tests back. 
llvm-svn: 128238
 2011-03-24 21:14:28 +00:00
Johnny Chen
b4284e3f90 For ARM Disassembler, start a newline to dump the opcode and friends for an instruction. 
Change inspired by llvm-bug 9530 submitted by Jyun-Yan You.

llvm-svn: 128122
 2011-03-22 23:49:46 +00:00
Johnny Chen
6bf5d7a170 LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT. 
The insufficient encoding information of the combined instruction confuses the decoder wrt
UQADD16.  Add extra logic to recover from that.

Fixed an assert reported by Sean Callanan

llvm-svn: 127354
 2011-03-09 20:01:14 +00:00
Owen Anderson
899a6d74bf Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. 
llvm-svn: 125127
 2011-02-08 22:39:40 +00:00
Owen Anderson
81f8b084e6 Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it. 
llvm-svn: 121082
 2010-12-07 00:45:21 +00:00
Owen Anderson
8802c68592 Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax. 
llvm-svn: 120589
 2010-12-01 19:18:46 +00:00
Owen Anderson
5aff471eb8 Simplify the encoding of reg+/-imm12 values that allow PC-relative encoding. This allows the 
Thumb2 encoding to share code with the ARM encoding, which gets use fixup support for free.
It also allows us to fold away at least one codegen-only pattern.

llvm-svn: 120481
 2010-11-30 22:45:47 +00:00
Evan Cheng
b41703bc2f Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. 
llvm-svn: 118152
 2010-11-03 05:14:24 +00:00
Jim Grosbach
151502662e Detabify and clean up 80 column violations. 
llvm-svn: 116454
 2010-10-13 23:47:11 +00:00
Oscar Fuentes
cd481d2723 Add ARM Disassembler to the CMake build. 
llvm-svn: 114949
 2010-09-28 11:48:19 +00:00
NAKAMURA Takumi
e223d51276 ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to Cygwin-1.5, following up to r113255. 
llvm-svn: 113345
 2010-09-08 04:48:17 +00:00
Johnny Chen
fef1367b50 The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td 
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.

Added a "usat" test case to arm-tests.txt.

llvm-svn: 110894
 2010-08-12 01:40:54 +00:00
Bob Wilson
3582107cf8 Move the ARM SSAT and USAT optional shift amount operand out of the 
instruction opcode.  This also fixes part of PR7792.

llvm-svn: 110875
 2010-08-11 23:10:46 +00:00
Johnny Chen
bd5bf58029 For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111', 
transform the Opcode to the corresponding t2LDR*pci counterpart.

Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
llvm-svn: 101915
 2010-04-20 17:28:50 +00:00