Duncan Sands
3bf2a701a5
In the calling convention logic, ValVT is always a legal type,
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and as such can be represented by an MVT - the more complicated
EVT is not needed. Use MVT for ValVT everywhere.
llvm-svn: 118245
2010-11-04 10:49:57 +00:00
Evan Cheng
165e65f53a
Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immediate rw. There is currently no intrinsic that matches to pli.
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llvm-svn: 118237
2010-11-04 05:19:35 +00:00
Chris Lattner
a55b12911d
partition operand processing between aliases and instructions.
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Right now the code is partitioned but the behavior is the same.
This should be improved in the near future. This removes some
uses of TheOperandList.
llvm-svn: 118232
2010-11-04 02:11:18 +00:00
Chris Lattner
21179e333e
pull name slicing out of BuildInstructionOperandReference so
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it doesn't do any lexical stuff anymore.
llvm-svn: 118230
2010-11-04 01:58:23 +00:00
Chris Lattner
c30032c0c0
cleanups.
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llvm-svn: 118228
2010-11-04 01:55:23 +00:00
Chris Lattner
fcdb263fa4
replace SrcOpNum with SrcOpName, eliminating a numering dependency
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on the incoming operand list. This also makes the code simpler.
llvm-svn: 118225
2010-11-04 01:42:59 +00:00
Daniel Dunbar
06d64897d3
System: Add llvm_execute_on_thread, which does what it says.
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- Primarily useful for running some code with a specified stack size, when
pthreads are available.
llvm-svn: 118222
2010-11-04 01:26:25 +00:00
Jim Grosbach
9766b186b6
Add ARM fixup info for load/store label references. Probably will need a bit of
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tweaking when we start using it for object file emission or JIT, but it's a
start.
llvm-svn: 118221
2010-11-04 01:12:30 +00:00
Bill Wendling
990c247994
Add encoding for VSTR.
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llvm-svn: 118220
2010-11-04 00:59:42 +00:00
Chris Lattner
b0b3157619
strength reduce some code, resolving a fixme.
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llvm-svn: 118219
2010-11-04 00:57:06 +00:00
Chris Lattner
9ae6cce0fe
take a big step to making aliases more general and less of a hack:
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now matchables contain an explicit list of how to populate each
operand in the result instruction instead of having them somehow
magically be correlated to the input inst.
llvm-svn: 118217
2010-11-04 00:43:46 +00:00
Jakob Stoklund Olesen
aa7acbe740
Disable fancy splitting during spilling unless -extra-spiller-splits is given.
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This way, InlineSpiller does the same amount of splitting as the standard
spiller. Splitting should really be guided by the register allocator, and
doesn't belong in the spiller at all.
llvm-svn: 118216
2010-11-04 00:32:32 +00:00
Jim Grosbach
af6104d4bf
Teach ARM Target to use the tblgen support for generating an MC'ized
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CodeEmitter.
llvm-svn: 118209
2010-11-03 23:52:49 +00:00
Jim Grosbach
e89ee5eb80
Add rule to build MC'ized CodeEmitter.
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llvm-svn: 118207
2010-11-03 23:46:01 +00:00
Jim Grosbach
7426448b7c
Support generating an MC'ized CodeEmitter directly. Maintain a reference to the
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Fixups list for the instruction so the operand encoders can add to it as
needed.
llvm-svn: 118206
2010-11-03 23:38:14 +00:00
Owen Anderson
d144bb1ddc
Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization.
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This is both the conceptually correct place for it, as well as allowing it to be more aggressive.
llvm-svn: 118204
2010-11-03 23:15:26 +00:00
Owen Anderson
1a89511e5d
Add support for code generation of the one register with immediate form of vorr.
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We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.
llvm-svn: 118201
2010-11-03 22:44:51 +00:00
Jim Grosbach
6c197e41bf
trailing whitespace
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llvm-svn: 118199
2010-11-03 22:03:20 +00:00
Eric Christopher
3f1ac311ff
Just return undef for invalid masks or elts, and since we're doing that,
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just do it earlier too.
llvm-svn: 118195
2010-11-03 20:44:42 +00:00
Jakob Stoklund Olesen
13bf5713f2
Let RegAllocBasic require MachineDominators - they are already available and
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splitting needs them.
llvm-svn: 118194
2010-11-03 20:39:26 +00:00
Jakob Stoklund Olesen
7dc4b810ed
Tag debug output as regalloc
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llvm-svn: 118193
2010-11-03 20:39:23 +00:00
Eric Christopher
6b586a109e
Optimize generated code for integer materialization a bit.
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llvm-svn: 118192
2010-11-03 20:21:17 +00:00
Chris Lattner
5280a84fef
rename Operand -> AsmOperand for clarity.
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llvm-svn: 118190
2010-11-03 19:47:34 +00:00
Evan Cheng
72718cf345
Fix test.
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llvm-svn: 118187
2010-11-03 18:21:33 +00:00
Owen Anderson
98f9965c89
Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead,
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all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.
llvm-svn: 118183
2010-11-03 18:16:27 +00:00
Dale Johannesen
74ebf1b011
This test assumes SSE is present; that is not the default
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on non-X86 hosts. Hopefully fixes ppc-host buildbot.
llvm-svn: 118182
2010-11-03 18:08:41 +00:00
Bob Wilson
f44e708279
Add codegen patterns for VST1-lane instructions. Radar 8599955.
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llvm-svn: 118176
2010-11-03 16:24:53 +00:00
Bob Wilson
0ec96428ba
Check for extractelement with a variable operand for the element number.
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For NEON we had been assuming this was always an immediate constant.
llvm-svn: 118175
2010-11-03 16:24:50 +00:00
Mikhail Glushenkov
991857f132
Rename FindExecutable to PrependMainExecutablePath.
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Makes it more clear that it is just a path manipulation function.
llvm-svn: 118174
2010-11-03 16:14:16 +00:00
Mikhail Glushenkov
5cbf236c6a
80-col violations, trailing whitespace.
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llvm-svn: 118173
2010-11-03 16:14:07 +00:00
Duncan Sands
1028fd63a0
Rename PointsToLocalMemory to PointsToLocalOrConstantMemory to make
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the code more self-documenting.
llvm-svn: 118171
2010-11-03 14:45:05 +00:00
Duncan Sands
41edf30895
Simplify uses of MVT and EVT. An MVT can be compared directly
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with a SimpleValueType, while an EVT supports equality and
inequality comparisons with SimpleValueType.
llvm-svn: 118169
2010-11-03 12:17:33 +00:00
Duncan Sands
4bbe978c7c
Fix a comment typo.
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llvm-svn: 118168
2010-11-03 11:55:03 +00:00
Duncan Sands
f6e5e02c9b
Inside the calling convention logic LocVT is always a simple
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value type, so there is no point in passing it around using
an EVT. Use the simpler MVT everywhere. Rather than trying
to propagate this information maximally in all the code that
using the calling convention stuff, I chose to do a mainly
low impact change instead.
llvm-svn: 118167
2010-11-03 11:35:31 +00:00
Eric Christopher
719d9d324b
If we have an undef mask our Elt will be -1 for our access, handle
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this by using an undef as a pointer.
Fixes rdar://8625016
llvm-svn: 118164
2010-11-03 09:36:40 +00:00
Duncan Sands
77fde689d9
Fix typo, pointed out by Trevor Harmon.
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llvm-svn: 118163
2010-11-03 08:16:50 +00:00
Evan Cheng
eab7251695
Fix preload instruction isel. Only v7 supports pli, and only v7 with mp extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing.
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llvm-svn: 118160
2010-11-03 06:34:55 +00:00
Evan Cheng
b41703bc2f
Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.
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llvm-svn: 118152
2010-11-03 05:14:24 +00:00
Bill Wendling
3894287c96
Put the PC encoding in the correct bit position.
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llvm-svn: 118151
2010-11-03 04:57:44 +00:00
Eric Christopher
bc79fa1c9e
Invert these branches by default, it makes assembly comparisons a little
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easier to read.
llvm-svn: 118148
2010-11-03 04:29:11 +00:00
Bill Wendling
34599f4aa8
The MC code couldn't handle ARM LDR instructions with negative offsets:
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vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
llvm-svn: 118144
2010-11-03 01:49:29 +00:00
Dan Gohman
8071a75d31
Fix DAGCombiner to avoid going into an infinite loop when it
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encounters (and:i64 (shl:i64 (load:i64), 1), 0xffffffff).
This fixes rdar://8606584.
llvm-svn: 118143
2010-11-03 01:47:46 +00:00
Jim Grosbach
90a084bac2
Remove unused function.
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llvm-svn: 118141
2010-11-03 01:35:15 +00:00
Jim Grosbach
d3213d4048
Remove the no longer used 'Modifier' optional operand to the ARM
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printOperand() asm printer helper functions. rdar://8425198
llvm-svn: 118140
2010-11-03 01:11:15 +00:00
Jim Grosbach
4d6b503b4c
Remove unused function.
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llvm-svn: 118139
2010-11-03 01:07:48 +00:00
Jim Grosbach
c10d3f3d4b
Break ARM addrmode4 (load/store multiple base address) into its constituent
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parts. Represent the operation mode as an optional operand instead.
rdar://8614429
llvm-svn: 118137
2010-11-03 01:01:43 +00:00
Evan Cheng
67db408634
Two sets of changes. Sorry they are intermingled.
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1. Fix pre-ra scheduler so it doesn't try to push instructions above calls to
"optimize for latency". Call instructions don't have the right latency and
this is more likely to use introduce spills.
2. Fix if-converter cost function. For ARM, it should use instruction latencies,
not # of micro-ops since multi-latency instructions is completely executed
even when the predicate is false. Also, some instruction will be "slower"
when they are predicated due to the register def becoming implicit input.
rdar://8598427
llvm-svn: 118135
2010-11-03 00:45:17 +00:00
Evan Cheng
e156473432
Modify scheduling itineraries to correct instruction latencies (not operand
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latencies) of loads.
llvm-svn: 118134
2010-11-03 00:40:22 +00:00
Dan Gohman
67f95d770b
Factor code out of APInt to form a isUIntN helper function.
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llvm-svn: 118133
2010-11-03 00:38:40 +00:00
Chris Lattner
76a122055f
fix typo, patch by Trevor Harmon (PR8537)
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llvm-svn: 118131
2010-11-03 00:30:29 +00:00