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5634 Commits

Author SHA1 Message Date
Chris Lattner
c2977ac665 Adjust to change in TII ctor arguments 
llvm-svn: 11987
 2004-02-29 06:31:44 +00:00
Chris Lattner
b5f0e162c7 Eliminate the distinction between "real" and "unreal" instructions 
llvm-svn: 11986
 2004-02-29 06:31:16 +00:00
Chris Lattner
cfc8f02250 These two virtual methods are never called. 
llvm-svn: 11984
 2004-02-29 05:59:33 +00:00
Chris Lattner
dd752eec34 Remove a TON of flags that noone cares about 
llvm-svn: 11983
 2004-02-29 05:58:30 +00:00
Chris Lattner
d80ff1bdc0 Noone calls these virtual methods 
llvm-svn: 11982
 2004-02-29 05:58:16 +00:00
Chris Lattner
dded7ad224 This is the only file in the system that uses this enum. eliminate it. 
llvm-svn: 11981
 2004-02-29 05:57:59 +00:00
Chris Lattner
7cb71a20ca Implement initial prolog/epilog code insertion methods. 
llvm-svn: 11979
 2004-02-29 05:18:30 +00:00
Chris Lattner
8b7ac81d2e int64_t -> int 
llvm-svn: 11977
 2004-02-29 05:07:02 +00:00
Alkis Evlogimenos
0f96b44e0e Use correct template for ADC instruction with memory operands. 
llvm-svn: 11974
 2004-02-29 02:18:17 +00:00
Chris Lattner
800f720e7b Add an instruction selector capable of selecting 'ret void' 
llvm-svn: 11973
 2004-02-29 00:27:00 +00:00
Alkis Evlogimenos
6815402082 SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename them 
to denote this fact.

llvm-svn: 11972
 2004-02-28 23:46:44 +00:00
Alkis Evlogimenos
e8dac99a43 Floating point loads/stores act on memory operands. Rename them to 
denote this fact.

llvm-svn: 11971
 2004-02-28 23:42:35 +00:00
Alkis Evlogimenos
1d71a15be9 Rename instruction templates to be easier to the human eye to 
parse. The name is now I (operand size)*. For example:

Im32 -> instruction with 32-bit memory operands.

Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate
          operands.

llvm-svn: 11970
 2004-02-28 23:09:03 +00:00
Alkis Evlogimenos
6038a89025 Uncomment instructions that take both an immediate and a memory 
operand but their sizes differ.

llvm-svn: 11969
 2004-02-28 22:06:59 +00:00
Alkis Evlogimenos
f208a0fd81 Each instruction now has both an ImmType and a MemType. This describes 
the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).

llvm-svn: 11967
 2004-02-28 22:02:05 +00:00
Brian Gaeke
d551a8b5fe Fix typo in comment 
llvm-svn: 11966
 2004-02-28 21:55:18 +00:00
Chris Lattner
a854ddd528 Implement switch->br and br->switch folding by ripping out the switch->switch 
and br->br code and generalizing it.  This allows us to compile code like this:

int test(Instruction *I) {
  if (isa<CastInst>(I))
    return foo(7);
  else if (isa<BranchInst>(I))
    return foo(123);
  else if (isa<UnwindInst>(I))
    return foo(1241);
  else if (isa<SetCondInst>(I))
    return foo(1);
  else if (isa<VAArgInst>(I))
    return foo(42);
  return foo(-1);
}

into:

int %_Z4testPN4llvm11InstructionE("struct.llvm::Instruction"* %I) {
entry:
        %tmp.1.i.i.i.i.i.i.i = getelementptr "struct.llvm::Instruction"* %I, long 0, ubyte 4            ; <uint*> [#uses=1]
        %tmp.2.i.i.i.i.i.i.i = load uint* %tmp.1.i.i.i.i.i.i.i          ; <uint> [#uses=2]
        %tmp.2.i.i.i.i.i.i = seteq uint %tmp.2.i.i.i.i.i.i.i, 27                ; <bool> [#uses=0]
        switch uint %tmp.2.i.i.i.i.i.i.i, label %endif.0 [
                 uint 27, label %then.0
                 uint 2, label %then.1
                 uint 5, label %then.2
                 uint 14, label %then.3
                 uint 15, label %then.3
                 uint 16, label %then.3
                 uint 17, label %then.3
                 uint 18, label %then.3
                 uint 19, label %then.3
                 uint 32, label %then.4
        ]
...

As well as handling the cases in 176.gcc and many other programs more effectively.

llvm-svn: 11964
 2004-02-28 21:28:10 +00:00
Chris Lattner
3583890ab7 Change this so that LLC actually tries to run the code generator, though it will 
immediately abort due to lack of an instruction selector. :)

llvm-svn: 11963
 2004-02-28 20:21:45 +00:00
Chris Lattner
529a354ea4 SparcV8 now builds. 
llvm-svn: 11960
 2004-02-28 19:54:00 +00:00
Chris Lattner
5effdb67b7 fine grainify namespacification 
llvm-svn: 11959
 2004-02-28 19:53:18 +00:00
Chris Lattner
3852b0c3b8 Finegrainify namespacification 
llvm-svn: 11958
 2004-02-28 19:52:49 +00:00
Chris Lattner
88268605ec Tab completion is our friend. 
llvm-svn: 11957
 2004-02-28 19:45:39 +00:00
Chris Lattner
013aa47975 Clean up rules 
llvm-svn: 11956
 2004-02-28 19:43:40 +00:00
Chris Lattner
d2bb7e91b0 Bring this directory into "it actually compiles" land 
llvm-svn: 11955
 2004-02-28 19:37:18 +00:00
Chris Lattner
3f70429d28 Fix multiple inclusion problem 
llvm-svn: 11954
 2004-02-28 19:31:32 +00:00
Chris Lattner
69ab9e0840 if there is already a prototype for malloc/free, use it, even if it's incorrect. 
Do not just inject a new prototype.

llvm-svn: 11951
 2004-02-28 18:51:45 +00:00
Alkis Evlogimenos
977dbaadf7 Do not generate instructions with mismatched memory/immediate sized 
operands. The X86 backend doesn't handle them properly right now.

llvm-svn: 11944
 2004-02-28 06:01:43 +00:00
Chris Lattner
7872171767 Rename AddUsesToWorkList -> AddUsersToWorkList, as that is what it does. 
Create a new AddUsesToWorkList method
optimize memmove/set/cpy of zero bytes to a noop.

llvm-svn: 11941
 2004-02-28 05:22:00 +00:00
Chris Lattner
192d8413d3 Turn 'free null' into nothing 
llvm-svn: 11940
 2004-02-28 04:57:37 +00:00
Misha Brukman
0b846ae65c Right, it's really Extractor, not Extraction. 
llvm-svn: 11939
 2004-02-28 03:37:58 +00:00
Misha Brukman
f14fbb1a0b A pass that uses the generic CodeExtractor to rip out *every* loop in every 
function, as long as the loop isn't the only one in that function. This should
help debugging passes easier with BugPoint.

llvm-svn: 11936
 2004-02-28 03:33:01 +00:00
Misha Brukman
26e90f8776 A generic code extractor: given a list of BasicBlocks, it will rip them out into 
a new function, taking care of inputs and outputs.

llvm-svn: 11935
 2004-02-28 03:26:20 +00:00
Alkis Evlogimenos
84f00e93f7 Further comment updates. 
llvm-svn: 11933
 2004-02-28 03:20:31 +00:00
Alkis Evlogimenos
edbe362160 Update comments. 
llvm-svn: 11932
 2004-02-28 03:12:31 +00:00
Alkis Evlogimenos
0f91ce52a0 My previous commit broke the jit. The shift instructions always take 
an 8-bit immediate. So mark the shifts that take immediates as taking
an 8-bit argument. The rest with the implicit use of CL are marked
appropriately.

A bug still exists:

def SHLDmri32  : I2A8 <"shld", 0xA4, MRMDestMem>, TB;           // [mem32] <<= [mem32],R32 imm8

The immediate in the above instruction is 8-bit but the memory
reference is 32-bit. The printer prints this as an 8-bit reference
which confuses the assembler. Same with SHRDmri32.

llvm-svn: 11931
 2004-02-28 02:56:26 +00:00
Brian Gaeke
6afa0813d2 Turn off the SparcV9MachineCodeDestructionPass for now, because it's buggy 
llvm-svn: 11930
 2004-02-27 21:15:40 +00:00
Brian Gaeke
0e74ff91a0 Correct DestroyMachineFunction's getPassName 
llvm-svn: 11929
 2004-02-27 21:01:14 +00:00
Chris Lattner
9e71c09ff5 Only clone global nodes between graphs if both graphs have the global. 
llvm-svn: 11928
 2004-02-27 20:05:15 +00:00
Chris Lattner
138a7dfb62 ADD MORE FUNCTIONS! 
llvm-svn: 11927
 2004-02-27 20:04:48 +00:00
Alkis Evlogimenos
ace6d81654 Fix argument size for SHL, SHR, SAR, SHLD and SHRD families of 
instructions.

llvm-svn: 11923
 2004-02-27 19:46:30 +00:00
Alkis Evlogimenos
839c70f45d Fix encoding of ADD and SUB family of instructions. Also rearrange 
them so that they are consistent with AND, XOR, etc...

llvm-svn: 11922
 2004-02-27 18:57:00 +00:00
Alkis Evlogimenos
56d357aa23 Rename MRMS[0-7]{r,m} to MRM[0-7]{r,m}. 
llvm-svn: 11921
 2004-02-27 18:55:12 +00:00
Chris Lattner
d06b64c941 setcond instructions don't have aliasing implications. 
llvm-svn: 11919
 2004-02-27 18:09:25 +00:00
Chris Lattner
644af802c9 Fix Regression/Assembler/2004-02-27-SelfUseAssertError.ll 
llvm-svn: 11913
 2004-02-27 17:28:25 +00:00
Alkis Evlogimenos
5ac109957f Add memory operand folding support for the SETcc family of 
instructions.

llvm-svn: 11907
 2004-02-27 16:13:37 +00:00
Alkis Evlogimenos
0742b93bb9 Add memory operand folding support for SHLD and SHRD instructions. 
llvm-svn: 11905
 2004-02-27 15:03:18 +00:00
Alkis Evlogimenos
b1f67f6741 Add memory operand folding support for SHL, SHR and SAR, SHLD instructions. 
llvm-svn: 11903
 2004-02-27 09:28:43 +00:00
Alkis Evlogimenos
cf49d13ed2 Rename SHL, SHR, SAR, SHLD and SHLR instructions to make them 
consistent with the rest and also pepare for the addition of their
memory operand variants.

llvm-svn: 11902
 2004-02-27 06:57:05 +00:00
Chris Lattner
ffae67bae8 Implement test/Regression/Transforms/InstCombine/canonicalize_branch.ll 
This is a really minor thing, but might help out the 'switch statement induction'
code in simplifycfg.

llvm-svn: 11900
 2004-02-27 06:27:46 +00:00
Alkis Evlogimenos
ddfd27ff97 Rename member function to be consistent with the rest. 
llvm-svn: 11898
 2004-02-27 06:11:15 +00:00