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Author SHA1 Message Date
Nadav Rotem
4cad811734 If all of the write objects are identified then we can vectorize the loop even if the read objects are unidentified. 
PR14719.

llvm-svn: 171124
 2012-12-26 23:30:53 +00:00
Craig Topper
9e3cb122f1 Fix operands and encoding form for ARPL instruction. Register form had and reversed. Memory form writes memory, but was marked as MRMSrcMem. 
llvm-svn: 171123
 2012-12-26 23:27:57 +00:00
Craig Topper
fe4506dc6c Add hasSideEffects=0 to some atomic instructions. 
llvm-svn: 171122
 2012-12-26 23:08:12 +00:00
Craig Topper
c4205e1d63 Mark the AL/AX/EAX forms of the basic arithmetic operations has never having side effects. 
llvm-svn: 171121
 2012-12-26 22:19:23 +00:00
Nick Lewycky
7f19cf03a6 80 columns. No functionality change. 
llvm-svn: 171120
 2012-12-26 22:00:49 +00:00
Nick Lewycky
3aba2e21ea Remove mid-optimizer warning. This situation should be handled differently, 
such as by a compiler warning, a check in clang -fsanitizer=undefined, being
optimized to unreachable, or a combination of the above. PR14722.

llvm-svn: 171119
 2012-12-26 22:00:35 +00:00
Craig Topper
152bee45fa Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. 
llvm-svn: 171118
 2012-12-26 21:30:22 +00:00
Craig Topper
2b01799bba Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns. 
llvm-svn: 171117
 2012-12-26 21:04:30 +00:00
Nadav Rotem
758e442bb6 Update the docs with the new workload that was added. 
llvm-svn: 171115
 2012-12-26 19:45:00 +00:00
Nadav Rotem
90712b89cc LoopVectorizer: Optimize the vectorization of consecutive memory access when the iteration step is -1 
llvm-svn: 171114
 2012-12-26 19:08:17 +00:00
Eli Bendersky
38abc56548 Fix comment typo 
llvm-svn: 171113
 2012-12-26 18:15:42 +00:00
Evgeniy Stepanov
3c52fb6e43 [msan] Raise alignment of origin stores/loads when possible. 
Origin alignment is as high as the alignment of the corresponding application
location, but never less than 4.

llvm-svn: 171110
 2012-12-26 11:55:09 +00:00
Evgeniy Stepanov
e64939756e [msan] Expand the file comment with track-origins info. 
llvm-svn: 171109
 2012-12-26 10:59:00 +00:00
Benjamin Kramer
6f560e4b24 Fix quoting in configure. Patch by Krzysztof Parzyszek! 
llvm-svn: 171108
 2012-12-26 10:48:49 +00:00
Craig Topper
d3212f7ab5 Merge still more SSE/AVX instruction definitions. 
llvm-svn: 171103
 2012-12-26 07:54:43 +00:00
Craig Topper
e1a7e48937 Merge more SSE/AVX instruction definitions. 
llvm-svn: 171102
 2012-12-26 07:20:35 +00:00
NAKAMURA Takumi
5b4a443c29 TableGen/FixedLenDecoderEmitter.cpp: Fix a potential mask overflow in fieldFromInstruction(). 
Reported by Yang Yongyong, thanks!

llvm-svn: 171101
 2012-12-26 06:43:14 +00:00
Nadav Rotem
034faa077d revert an accidental commit. 
llvm-svn: 171098
 2012-12-26 06:16:03 +00:00
Craig Topper
e11b743aa8 Fix 80 column violation. 
llvm-svn: 171097
 2012-12-26 06:15:53 +00:00
Craig Topper
6bb87eb1c5 Fix class name in comment. 
llvm-svn: 171096
 2012-12-26 06:15:09 +00:00
Craig Topper
6548cfbc58 Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions. 
llvm-svn: 171095
 2012-12-26 06:14:15 +00:00
Nadav Rotem
fec894619f Doc: add fmuladd to the list of vectorizeable functions. Thanks hfinkel. 
llvm-svn: 171094
 2012-12-26 06:03:35 +00:00
Craig Topper
891ef3c0d5 Remove 'v' from mnemonic to fix asm matching failures. 
llvm-svn: 171093
 2012-12-26 06:02:15 +00:00
Craig Topper
0466a426a3 Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions. 
llvm-svn: 171092
 2012-12-26 05:49:15 +00:00
Nadav Rotem
715148a69d Reformat the docs. 
llvm-svn: 171091
 2012-12-26 04:59:20 +00:00
Nadav Rotem
8ab52765bc white space 
llvm-svn: 171090
 2012-12-26 04:58:12 +00:00
Craig Topper
cc9b1f307a Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN 
llvm-svn: 171087
 2012-12-26 04:36:03 +00:00
Craig Topper
aabd76dd28 Merge an AVX/SSE 256-bit and 128-bit multiclass. 
llvm-svn: 171086
 2012-12-26 03:56:47 +00:00
Craig Topper
0b8d42715a Mark VANDNPD/VANDNPDS as not commutable. 
llvm-svn: 171085
 2012-12-26 03:48:10 +00:00
NAKAMURA Takumi
88036873a3 llvm/test/CodeGen/X86: FileCheck-ize two tests in r171083. 
llvm-svn: 171084
 2012-12-26 03:19:30 +00:00
NAKAMURA Takumi
faa91faa15 llvm/test/CodeGen/X86: Disable avx in two tests corresponding to r171082. 
llvm-svn: 171083
 2012-12-26 03:08:55 +00:00
Craig Topper
771f143613 Remove alignment from a bunch more VEX encoded operations in the folding tables. 
llvm-svn: 171082
 2012-12-26 02:44:47 +00:00
Craig Topper
284833f94e Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment... 
llvm-svn: 171081
 2012-12-26 02:14:19 +00:00
Craig Topper
ca9f2be634 Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX. 
llvm-svn: 171080
 2012-12-26 01:47:12 +00:00
Hal Finkel
7cfc448749 BBVectorize: Use VTTI to compute costs for intrinsics vectorization 
For the time being this includes only some dummy test cases. Once the
generic implementation of the intrinsics cost function does something other
than assuming scalarization in all cases, or some target specializes the
interface, some real test cases can be added.

Also, for consistency, I changed the type of IID from unsigned to Intrinsic::ID
in a few other places.

llvm-svn: 171079
 2012-12-26 01:36:57 +00:00
Craig Topper
b5af563b7e Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment. 
llvm-svn: 171078
 2012-12-26 00:35:47 +00:00
Hal Finkel
f9b3cb9121 LoopVectorize: Enable vectorization of the fmuladd intrinsic 
llvm-svn: 171076
 2012-12-25 23:21:29 +00:00
Hal Finkel
8299a9e0b2 BBVectorize: Enable vectorization of the fmuladd intrinsic 
llvm-svn: 171075
 2012-12-25 22:36:08 +00:00
Hal Finkel
62efc81644 Loosen scheduling restrictions on the PPC dcbt intrinsic 
As with the prefetch intrinsic to which it maps, simply have dcbt
marked as reading from and writing to its arguments instead of having
unmodeled side effects. While this might cause unwanted code motion
(because aliasing checks don't really capture cache-line sharing),
it is more important that prefetches in unrolled loops don't block
the scheduler from rearranging the unrolled loop body.

llvm-svn: 171073
 2012-12-25 18:51:18 +00:00
Hal Finkel
6b98f1baa2 Expand PPC64 atomic load and store 
Use of store or load with the atomic specifier on 64-bit types would
cause instruction-selection failures. As with the 32-bit case, these
can use the default expansion in terms of cmp-and-swap.

llvm-svn: 171072
 2012-12-25 17:22:53 +00:00
Evgeniy Stepanov
f41a8d635d [msan] Fix handling of vectors of pointers. 
VectorType::getInteger() can not be used with them, because pointer size
depends on the target.

llvm-svn: 171070
 2012-12-25 16:04:38 +00:00
Evgeniy Stepanov
e7fdcc5fe1 [msan] Fix handling of select with vector condition. 
llvm-svn: 171069
 2012-12-25 14:56:21 +00:00
Benjamin Kramer
8827e5db0d Harden test so it's not affected by changes to compare lowering. 
This only failed on hosts that don't have SSE41.

llvm-svn: 171066
 2012-12-25 13:23:23 +00:00
Benjamin Kramer
e4eabce005 X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use of and commutativity. 
llvm-svn: 171064
 2012-12-25 13:09:08 +00:00
Benjamin Kramer
2e313ba01d X86: Custom lower <2 x i64> eq and ne when SSE41 is not available. 
pcmpeqd, pshufd, pshufd, pand is cheaper than unpack + cmpq, sbbq, cmpq, sbbq + pack.
Small speedup on loop-vectorized viterbi (-march=core2).

llvm-svn: 171063
 2012-12-25 12:54:19 +00:00
Alexey Samsonov
c191ee3e37 ASan: initialize callbacks from ASan module pass in a separate function for consistency 
llvm-svn: 171061
 2012-12-25 12:28:20 +00:00
Alexey Samsonov
42f6219321 ASan: move stack poisoning logic into FunctionStackPoisoner struct 
llvm-svn: 171060
 2012-12-25 12:04:36 +00:00
Nick Lewycky
654d7933b1 Fix whitespace. No functionality change. 
llvm-svn: 171051
 2012-12-25 06:13:25 +00:00
Nadav Rotem
3017e5481d VCVTSS2SD requires a strict alignment. Thanks Elena. 
llvm-svn: 171049
 2012-12-25 03:29:18 +00:00
Bob Wilson
b0b344d1f6 Rename LLVMContext diagnostic handler types and functions. 
These are now generally used for all diagnostics from the backend, not just
for inline assembly, so this drops the "InlineAsm" from the names.  No
functional change.  (I've left aliases for the old names but only for long
enough to let me switch over clang to use the new ones.)

llvm-svn: 171047
 2012-12-25 00:07:12 +00:00