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Author SHA1 Message Date
Devang Patel
6f94a7469d Link NamedMDNode before linking function bodies. 
llvm-svn: 135204
 2011-07-14 22:13:07 +00:00
Jim Grosbach
6122eb0fff ARM diagnostic when 's' suffix on mnemonic that can't set flags. 
For example, "mlss r0, r1, r2, r3".

The MLS instruction does not have a flag-setting variant.

llvm-svn: 135203
 2011-07-14 22:04:21 +00:00
Bill Wendling
ed868b039b * Redo the permutation encoding for frameless stacks to be more like what the 
unwind library expects.
* Comment the permutation encoding for frameless stacks.

llvm-svn: 135202
 2011-07-14 22:01:34 +00:00
Devang Patel
369cd5cef5 Add dump() 
llvm-svn: 135200
 2011-07-14 21:50:04 +00:00
Benjamin Kramer
cae519ebf0 Add OperandTypes for Thumb branch targets. 
llvm-svn: 135199
 2011-07-14 21:47:24 +00:00
Benjamin Kramer
d88f66e018 Port operand types for ARM and X86 over from EDIS to the .td files. 
llvm-svn: 135198
 2011-07-14 21:47:22 +00:00
Benjamin Kramer
25ffda4d8a Add a new field to MCOperandInfo that contains information about the type of the Operand. 
- The actual values are from the MCOI::OperandType enum.
- Teach tblgen to read it from the instruction definition.
- This is a better implementation of the hacks in edis.

llvm-svn: 135197
 2011-07-14 21:47:18 +00:00
Jim Grosbach
7656c6f97e Add some testcases for ARM MLA/MLS instructions. 
llvm-svn: 135196
 2011-07-14 21:43:05 +00:00
Jim Grosbach
2ab898973a ARM MCRR/MCRR2 immediate operand range checking. 
llvm-svn: 135192
 2011-07-14 21:26:42 +00:00
Chris Lattner
77acb69e12 revert r135172 until Devang and I figure out the right answer. 
llvm-svn: 135191
 2011-07-14 21:25:42 +00:00
Jim Grosbach
27ebbba831 ARM MCR/MCR2 assembly parsing operand constraints. 
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.

llvm-svn: 135189
 2011-07-14 21:19:17 +00:00
Nicolas Geoffray
94c6d2fae9 After type-system-rewrite branch update the Cpp backend to not use OpaqueType. 
llvm-svn: 135186
 2011-07-14 21:04:35 +00:00
Jim Grosbach
09b5985799 Enable some tests we now handle correctly. 
llvm-svn: 135185
 2011-07-14 21:02:23 +00:00
Evan Cheng
24257cb9ea Next round of MC refactoring. This patch factor MC table instantiations, MC 
registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184
 2011-07-14 20:59:42 +00:00
Chris Lattner
29bbec539f simplify this logic now that GlobalAlias::isDeclaration is fixed. 
llvm-svn: 135183
 2011-07-14 20:23:05 +00:00
Chris Lattner
0e48b24f81 Fix GlobalValue::isDeclaration() to always consider aliases to be definitions. 
llvm-svn: 135182
 2011-07-14 20:22:18 +00:00
Eric Christopher
ca7ae418a5 Check register class matching instead of width of type matching 
when determining validity of matching constraint. Allow i1
types access to the GR8 reg class for x86.

Fixes PR10352 and rdar://9777108

llvm-svn: 135180
 2011-07-14 20:13:52 +00:00
Jim Grosbach
e18641e454 Reorganize ARM assembler aliases. 
Consolidate the individual declarations together for ease of reference. This
mirrors the organization in X86, as well, so is good for consistency. No
functional change.

llvm-svn: 135179
 2011-07-14 19:47:47 +00:00
Rafael Espindola
e3b7833680 Add LLVMConstNamedStruct to the C api to let its users create constants 
of named struct types.

llvm-svn: 135178
 2011-07-14 19:09:08 +00:00
Chris Lattner
6b60be1975 DebugLoc's don't hide any interesting types for TypeFinder to find. 
llvm-svn: 135174
 2011-07-14 18:58:40 +00:00
Chris Lattner
c7d5a58efc manually copy debugloc over to a new instruction in clone() instead 
of calling getAllMetadata().  This is semantically identical, but doing
it this way avoids unpacking the DebugLoc.

llvm-svn: 135173
 2011-07-14 18:57:51 +00:00
Chris Lattner
f9d3b2a8c3 Stop the ValueMapper from calling getAllMetadata, which unpacks DebugLoc into 
an MDNode.  This saves a bunch of time and memory in the IR linker, e.g. when 
doing LTO of files with debug info.

llvm-svn: 135172
 2011-07-14 18:53:50 +00:00
Bruno Cardoso Lopes
d24f039847 Add 256-bit load/store recognition and matching in several places. 
llvm-svn: 135171
 2011-07-14 18:50:58 +00:00
Benjamin Kramer
8833af7c47 Don't leak operands when putting them into a shift. 
llvm-svn: 135169
 2011-07-14 18:41:22 +00:00
Jim Grosbach
aebb9cdf68 Update ARM Assembly of LDM/STM. 
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.

llvm-svn: 135168
 2011-07-14 18:35:38 +00:00
Chris Lattner
5bf752bcf4 The key of a StringMap can contain nul's in it, so having first() return 
const char* doesn't make sense.  Have it return StringRef instead.

llvm-svn: 135167
 2011-07-14 18:31:43 +00:00
Chris Lattner
b252bb8f86 though it isn't the case here, the key of a StringMap can 
conceptually have nuls in it.

llvm-svn: 135165
 2011-07-14 18:21:58 +00:00
Chris Lattner
5d982469f8 add comments. 
llvm-svn: 135164
 2011-07-14 18:12:44 +00:00
Chris Lattner
b3458315d4 consolidate GlobalValue::isDeclaration into one 
non-virtual function.

llvm-svn: 135163
 2011-07-14 18:10:41 +00:00
Jim Grosbach
ebbd82a248 ARM ISB assembly parsing tests. 
llvm-svn: 135158
 2011-07-14 18:02:25 +00:00
Chris Lattner
41059ff010 code cleanup 
llvm-svn: 135157
 2011-07-14 18:01:49 +00:00
Jim Grosbach
9bbc2007df ARM ISB instruction assembly parsing. 
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.

llvm-svn: 135156
 2011-07-14 18:00:31 +00:00
Benjamin Kramer
a6129829fa Change Intrinsic::getDeclaration and friends to take an ArrayRef. 
llvm-svn: 135154
 2011-07-14 17:45:39 +00:00
Chris Lattner
f98f70f2f2 add a couple more missing C api, patch by Vitaly Lugovskiy! 
llvm-svn: 135151
 2011-07-14 16:20:28 +00:00
Richard Osborne
d73d21c487 Update XCoreRegisterInfo::eliminateFrameIndex() to handle DBG_VALUE 
instructions.

llvm-svn: 135146
 2011-07-14 14:03:48 +00:00
Frits van Bommel
5017656bef Simplify some functions in the C API by using an ArrayRef to directly reference the array passed to them instead of copying it to a std::vector. 
llvm-svn: 135145
 2011-07-14 11:44:09 +00:00
Nadav Rotem
b93249b1e7 [VECTOR-SELECT] 
During type legalization we often use the SIGN_EXTEND_INREG SDNode.
When this SDNode is legalized during the LegalizeVector phase, it is
scalarized because non-simple types are automatically marked to be expanded.
In this patch we add support for lowering SIGN_EXTEND_INREG manually.
This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements'
flag.

llvm-svn: 135144
 2011-07-14 11:11:14 +00:00
Nadav Rotem
1a0334b49c Add assertion for the chain value type 
llvm-svn: 135143
 2011-07-14 10:37:54 +00:00
Jay Foad
471e6f62b4 Mention all API changes I've made since 2.9 was branched. 
llvm-svn: 135142
 2011-07-14 09:19:05 +00:00
Eric Christopher
be21240f6f Add a testcase for r135123. 
Part of rdar://9761830

llvm-svn: 135133
 2011-07-14 06:23:09 +00:00
Chris Lattner
bd1cea5fe4 add C api for hte new type system rewrite API. Patch by Vitaly Lugovskiy! 
llvm-svn: 135132
 2011-07-14 05:53:17 +00:00
Evan Cheng
3d2be55d6c Unfortunately several files in MC are badly violating layering rule by using 
TargetAsmInfo, which in turn pulls in TargetRegisterInfo, etc. :-( There are
other cases of violations, but this is probably the worst.

This patch is but one small step towards fixing this. 500 more steps to go. :-(

llvm-svn: 135131
 2011-07-14 05:43:07 +00:00
Jakob Stoklund Olesen
b0af7bda8d Reapply r135121 with a fixed copy constructor. 
Original commit message:

Count references to interference cache entries.

Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.

This makes it possible to have multiple live cursors examining
interference for different physregs.

The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().

Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.

llvm-svn: 135130
 2011-07-14 05:35:11 +00:00
Devang Patel
39f6e21de3 Simplify. 
llvm-svn: 135127
 2011-07-14 01:52:45 +00:00
Benjamin Kramer
1cab6179ab Don't emit a bit test if there is only one case the test can yield false. A simple SETNE is sufficient. 
llvm-svn: 135126
 2011-07-14 01:38:42 +00:00
Devang Patel
1856a523ea Simplify and delay extracting DebugLoc elements, scope and InlinedAt, as much as possible. 
llvm-svn: 135124
 2011-07-14 01:14:57 +00:00
Eric Christopher
e84fe67d4f Add a dag combine pattern for folding C2-(A+C1) -> (C2-C1)-A 
Fixes rdar://9761830

llvm-svn: 135123
 2011-07-14 01:12:15 +00:00
Jakob Stoklund Olesen
718e76d4dd Revert r135121 which broke a gcc-4.2 builder. 
llvm-svn: 135122
 2011-07-14 00:58:38 +00:00
Jakob Stoklund Olesen
7d17ec883e Count references to interference cache entries. 
Each InterferenceCache::Cursor instance references a cache entry. A
non-zero reference count guarantees that the entry won't be reused for a
new register.

This makes it possible to have multiple live cursors examining
interference for different physregs.

The total number of live cursors into a cache must be kept below
InterferenceCache::getMaxCursors().

Code generation should be unaffected by this change, and it doesn't seem
to affect the cache replacement strategy either.

llvm-svn: 135121
 2011-07-14 00:31:14 +00:00
Eli Friedman
a1db9f2fd5 Fix up assertion in r135018 so it doesn't trigger on 32-bit; when we're in 32-bit, it doesn't matter whether the operation overflows because the computed address is not wider than the immediate. 
llvm-svn: 135120
 2011-07-14 00:22:31 +00:00