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638 Commits

Author SHA1 Message Date
Kevin Qin
b95721d200 [AArch64 NEON]Fix a assertion failure when disassemble SHLL instruction. 
llvm-svn: 195936
 2013-11-29 01:29:16 +00:00
Hao Liu
2f617213ef AArch64: Fix a bug about disassembling post-index load single element to 4 vectors 
llvm-svn: 195903
 2013-11-28 01:07:45 +00:00
Chad Rosier
ca062e81db [AArch64] Add support for NEON scalar floating-point absolute difference. 
llvm-svn: 195803
 2013-11-27 01:45:58 +00:00
Chad Rosier
1337fcc721 [AArch64] Add support for NEON scalar floating-point to integer convert 
instructions.

llvm-svn: 195788
 2013-11-26 22:17:37 +00:00
Hao Liu
66ab312f94 Fixed a bug about disassembling AArch64 post-index load/store single element instructions. 
ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
    echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
will be disassembled into the same instruction st1 {v0b}[0], [x0], x0.

llvm-svn: 195591
 2013-11-25 01:53:26 +00:00
Hao Liu
b26dfe0306 Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post. 
llvm-svn: 195078
 2013-11-19 02:17:05 +00:00
Jiangning Liu
5a9b5605ba Implement AArch64 NEON instruction set AdvSIMD (table). 
llvm-svn: 194648
 2013-11-14 01:57:32 +00:00
Richard Sandiford
1817f8f7b4 [SystemZ] Add the general form of BCR 
At the moment this is just the MC support.

llvm-svn: 194585
 2013-11-13 16:57:53 +00:00
Zoran Jovanovic
feadcc01d7 Support for microMIPS trap instruction with immediate operands. 
llvm-svn: 194569
 2013-11-13 13:15:03 +00:00
Chad Rosier
ba5d2d1be6 [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalar 
copy in MC layer. Added the MC layer tests.  Fixed triple setting in test cases.

Patch by Ana Pazos <apazos@codeaurora.org>.

llvm-svn: 194501
 2013-11-12 19:13:08 +00:00
Artyom Skrobov
7871752687 [ARM] Add support for MVFR2 which is new in ARMv8 
llvm-svn: 194416
 2013-11-11 19:56:13 +00:00
Chad Rosier
4848250116 [AArch64] Add support for NEON scalar floating-point convert to fixed-point instructions. 
llvm-svn: 194394
 2013-11-11 18:04:07 +00:00
Artyom Skrobov
1890ff3a6d [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (Thumb encodings) 
llvm-svn: 194263
 2013-11-08 16:25:50 +00:00
Artyom Skrobov
d49073b56a [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings) 
llvm-svn: 194262
 2013-11-08 16:17:14 +00:00
Artyom Skrobov
ef73b63766 [ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings) 
llvm-svn: 194261
 2013-11-08 16:16:30 +00:00
Zoran Jovanovic
935364b314 Support for microMIPS trap instructions 1. 
llvm-svn: 194205
 2013-11-07 14:35:24 +00:00
Jiangning Liu
9c0eb8e7ba Implement AArch64 Neon instruction set Perm. 
llvm-svn: 194123
 2013-11-06 03:35:27 +00:00
Jiangning Liu
1cdd311f06 Implement AArch64 Neon instruction set Bitwise Extract. 
llvm-svn: 194118
 2013-11-06 02:25:49 +00:00
Hao Liu
386d8dd5a6 Implement AArch64 post-index vector load/store multiple N-element structure class SIMD(lselem-post). 
Including following 14 instructions:
4 ld1 insts: post-index load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: post-index load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: post-index store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: post-index store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 194043
 2013-11-05 03:39:32 +00:00
Zoran Jovanovic
134add2b71 Support for microMIPS branch instructions. 
llvm-svn: 193992
 2013-11-04 14:53:22 +00:00
Chad Rosier
fd7dc7524c [AArch64] Add support for NEON scalar fixed-point convert to floating-point instructions. 
llvm-svn: 193816
 2013-10-31 22:36:59 +00:00
Chad Rosier
aea5ba449f [AArch64] Add support for NEON scalar shift immediate instructions. 
llvm-svn: 193790
 2013-10-31 19:28:44 +00:00
Amara Emerson
ce9bb052e5 [AArch64] Make the use of FP instructions optional, but enabled by default. 
This adds a new subtarget feature called FPARMv8 (implied by NEON), and
predicates the support of the FP instructions and registers on this feature.

llvm-svn: 193739
 2013-10-31 09:32:11 +00:00
Artyom Skrobov
de6ac0d99e [ARM] NEON instructions were erroneously decoded from certain invalid encodings 
llvm-svn: 193705
 2013-10-30 18:10:09 +00:00
Chad Rosier
02e430c891 [AArch64] Add support for NEON scalar floating-point compare instructions. 
llvm-svn: 193691
 2013-10-30 15:19:37 +00:00
Zoran Jovanovic
929213f2ec Support for microMIPS jump instructions 
llvm-svn: 193623
 2013-10-29 16:38:59 +00:00
Artyom Skrobov
2ef42e5c31 Make ARM hint ranges consistent, and add tests for these ranges 
llvm-svn: 193238
 2013-10-23 10:14:40 +00:00
Tim Northover
e4acb9a5a2 ARM: provide diagnostics on more writeback LDM/STM instructions 
The set of circumstances where the writeback register is allowed to be in the
list of registers is rather baroque, but I think this implements them all on
the assembly parsing side.

For disassembly, we still warn about an ARM-mode LDM even if the architecture
revision is < v7 (the required architecture information isn't available). It's
a silly instruction anyway, so hopefully no-one will mind.

rdar://problem/15223374

llvm-svn: 193185
 2013-10-22 19:00:39 +00:00
Richard Barton
cb6c32ac32 Add hint disassembly syntax for 16-bit Thumb hint instructions. 
Patch by Artyom Skrobov

llvm-svn: 192972
 2013-10-18 14:09:49 +00:00
Chad Rosier
163fdd3e73 [AArch64] Add support for NEON scalar extract narrow instructions. 
llvm-svn: 192970
 2013-10-18 14:03:24 +00:00
Chad Rosier
9a6d485c7f [AArch64] Add support for NEON scalar three register different instruction 
class.  The instruction class includes the signed saturating doubling
multiply-add long, signed saturating doubling multiply-subtract long, and
the signed saturating doubling multiply long instructions.

llvm-svn: 192908
 2013-10-17 18:12:29 +00:00
Chad Rosier
3ed3565e0f [AArch64] Add support for NEON scalar negate instruction. 
llvm-svn: 192843
 2013-10-16 21:04:39 +00:00
Chad Rosier
aaa3bb367a [AArch64] Add support for NEON scalar absolute value instruction. 
llvm-svn: 192842
 2013-10-16 21:04:34 +00:00
Chad Rosier
929e07c8ea Update comment. 
llvm-svn: 192806
 2013-10-16 16:30:10 +00:00
Chad Rosier
a195d145b8 [AArch64] Add support for NEON scalar signed saturating accumulated of unsigned 
value and unsigned saturating accumulate of signed value instructions.

llvm-svn: 192800
 2013-10-16 16:09:02 +00:00
Chad Rosier
3e791b2408 [AArch64] Add support for NEON scalar signed saturating absolute value and 
scalar signed saturating negate instructions.

llvm-svn: 192733
 2013-10-15 21:18:44 +00:00
Chad Rosier
40761dc629 [AArch64] Add support for NEON scalar integer compare instructions. 
llvm-svn: 192596
 2013-10-14 14:37:20 +00:00
Craig Topper
ba1540e28a Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding. 
llvm-svn: 192566
 2013-10-14 01:42:32 +00:00
Benjamin Kramer
3e32e13c0b Mips: Disassemble sign-extended 64 bit immediates properly. 
This doesn't change the meaning of the output, but makes look right. PR17539.

llvm-svn: 192483
 2013-10-11 19:05:08 +00:00
Chad Rosier
d30c4af71b [AArch64] Add support for NEON scalar floating-point reciprocal estimate, 
reciprocal exponent, and reciprocal square root estimate instructions.

llvm-svn: 192242
 2013-10-08 22:09:04 +00:00
Chad Rosier
e281a17b84 [AArch64] Add support for NEON scalar signed/unsigned integer to floating-point 
convert instructions.

llvm-svn: 192231
 2013-10-08 20:43:30 +00:00
Craig Topper
aa1a4d51f0 Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. 
llvm-svn: 192171
 2013-10-08 05:53:50 +00:00
Chad Rosier
128d9134e7 [AArch64] Add support for NEON scalar arithmetic instructions: 
SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS.

llvm-svn: 192107
 2013-10-07 16:36:15 +00:00
Joey Gouly
3ecfaf19bb [ARMv8] Add some disassembly tests for Thumb sevl/sevl.w 
llvm-svn: 192106
 2013-10-07 16:13:03 +00:00
Craig Topper
6e389a510f Remove some instructions that seem to only exist to trick the filtering checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. 
llvm-svn: 192090
 2013-10-07 07:19:47 +00:00
Craig Topper
b5918acf04 Add disassembler support for long encodings for INC/DEC in 32-bit mode. 
llvm-svn: 192086
 2013-10-07 04:28:06 +00:00
Craig Topper
6fb0648c41 Add XOP disassembler support. Fixes PR13933. 
llvm-svn: 191874
 2013-10-03 05:17:48 +00:00
Richard Sandiford
8ac2bcbe80 [SystemZ] Add comparisons of high words and memory 
llvm-svn: 191777
 2013-10-01 15:00:44 +00:00
Richard Sandiford
2ed79fb1d7 [SystemZ] Add comparisons of large immediates using high words 
There are no corresponding patterns for small immediates because they would
prevent the use of fused compare-and-branch instructions.

llvm-svn: 191775
 2013-10-01 14:56:23 +00:00
Richard Sandiford
3b7b53e6f4 [SystemZ] Add immediate addition involving high words 
llvm-svn: 191774
 2013-10-01 14:53:46 +00:00