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51252 Commits

Author SHA1 Message Date
Akira Hatanaka
4ff64c3ed4 Do not try to detect DAG combine patterns for integer multiply-add/sub if value 
type is not i32. MIPS does not have 64-bit integer multiply-add/sub
instructions.

llvm-svn: 144373
 2011-11-11 04:18:21 +00:00
Akira Hatanaka
3b1457c21d 64-bit atomic instructions. 
llvm-svn: 144372
 2011-11-11 04:14:30 +00:00
Akira Hatanaka
40d8c440ad Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64. 
llvm-svn: 144371
 2011-11-11 04:11:56 +00:00
Akira Hatanaka
23c5cb5daf Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC. 
llvm-svn: 144370
 2011-11-11 04:06:38 +00:00
Akira Hatanaka
b83d016dd7 64-bit versions of jal, jalr and bal. 
llvm-svn: 144368
 2011-11-11 04:03:54 +00:00
Akira Hatanaka
5f233b2627 Emit Mips64's sequence of instructions that set global register in prologue. 
llvm-svn: 144367
 2011-11-11 04:00:29 +00:00
Akira Hatanaka
e56d824b2e Fix printing of MCSymbolRegExpr. Needs three closing parentheses for 
VK_Mips_GPOFF_HI/LO.

llvm-svn: 144366
 2011-11-11 03:58:36 +00:00
Eli Friedman
285b451941 Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3. 
llvm-svn: 144361
 2011-11-11 03:16:38 +00:00
Eric Christopher
6b4d25e3f1 Initialize variable. 
llvm-svn: 144360
 2011-11-11 03:16:32 +00:00
Chad Rosier
38f07d3f9c When loading a value, treat an i1 as an i8. 
llvm-svn: 144356
 2011-11-11 02:38:59 +00:00
Eric Christopher
8b9a227517 If we have a DIE with an AT_specification use that instead of the normal 
addr DIE when adding to the dwarf accelerator tables.

llvm-svn: 144354
 2011-11-11 01:55:22 +00:00
Eli Friedman
127d98ab35 Get rid of an optimization in SCCP which appears to have many issues. Specifically, it doesn't handle many cases involving undef correctly, and it is missing other checks which 
lead to it trying to re-mark a value marked as a constant with a different value.  It also appears to trigger very rarely.

Fixes PR11357.

llvm-svn: 144352
 2011-11-11 01:16:15 +00:00
Bill Wendling
b26a165225 Reenable compact unwinding now that <rdar://problem/10430076> is fixed. 
llvm-svn: 144351
 2011-11-11 01:03:50 +00:00
Bill Wendling
3c30beb55a If we have to reset the calculation of the compact encoding, then also reset the 
"saved register" index.
<rdar://problem/10430076>

llvm-svn: 144350
 2011-11-11 00:59:14 +00:00
Chad Rosier
ac92994773 Add support for using MVN to materialize negative constants. 
rdar://10412592

llvm-svn: 144348
 2011-11-11 00:36:21 +00:00
Bill Wendling
7f1e8b3b0e Disable compact unwind generation until I can solve the codegen problems. 
llvm-svn: 144346
 2011-11-11 00:28:42 +00:00
Daniel Dunbar
846fb32afc LLVMBuild: Add explicit information on whether targets define an assembly printer, assembly parser, or disassembler. 
llvm-svn: 144344
 2011-11-11 00:23:56 +00:00
Jim Grosbach
ddf85f6be2 Thumb2 ldm/stm updating w/ one register in the list are LDR/STR. 
rdar://10429490

llvm-svn: 144338
 2011-11-10 23:58:34 +00:00
Jim Grosbach
d1d04109ff ARM let processInstruction() tranforms chain. 
llvm-svn: 144337
 2011-11-10 23:42:14 +00:00
Jim Grosbach
bd7df609b7 Thumb2 parsing for push/pop w/ hi registers in the reglist. 
rdar://10130228.

llvm-svn: 144331
 2011-11-10 23:17:11 +00:00
Jim Grosbach
615c824de4 Thumb1 diagnostics for reglist on PUSH/POP fix. 
Was not checking the first register in the register list.

llvm-svn: 144329
 2011-11-10 23:01:27 +00:00
Rafael Espindola
e7024f983a Check in getOrCreateSubprogramDIE if a declaration exists and if so output 
it first.

This is a more general fix to pr11300.

llvm-svn: 144324
 2011-11-10 22:34:29 +00:00
Jim Grosbach
c3651cb620 Thumb MUL assembly parsing for 3-operand form. 
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.

rdar://10428630

llvm-svn: 144322
 2011-11-10 22:10:12 +00:00
Daniel Dunbar
57e8d2b3d0 build/MBlazeDisassembler: Some compilers may generate an MBlaze disassembler 
that depends on MBlazeCodeGen. This is a layering violation that should really
be fixed.

llvm-svn: 144321
 2011-11-10 22:00:37 +00:00
Daniel Dunbar
1061d5f3b3 build/MCDisassembler: Fix required libraries list of MCDisassembler to use 
all-targets instead of an explicit list.

llvm-svn: 144320
 2011-11-10 22:00:34 +00:00
Eric Christopher
204348c454 Make types and namespaces take multiple DIEs for the accelerator tables 
as well.

llvm-svn: 144319
 2011-11-10 21:47:55 +00:00
Chad Rosier
7b7dced006 When in ARM mode, LDRH/STRH require special handling of negative offsets. 
For correctness, disable this for now.
rdar://10418009

llvm-svn: 144316
 2011-11-10 21:09:49 +00:00
Jim Grosbach
614f35bb30 ARM .thumb_func directive for quoted symbol names. 
Use the getIdentifier() method of the token, not getString(), otherwise
we keep the quotes as part of the symbol name, which we don't want.

rdar://10428015

llvm-svn: 144315
 2011-11-10 20:48:53 +00:00
Pete Cooper
93d3c835a0 Fixed bug in DeadStoreElimination commit r144239 
Size of data being pointed to wasn't always being checked so some small writes were killing big writes

Fixes <rdar://problem/10426753>

llvm-svn: 144312
 2011-11-10 20:22:08 +00:00
Eric Christopher
71b5af9cbe Move type handling to make sure we get all created types that aren't 
forward decls and have names into the dwarf accelerator types table.

llvm-svn: 144306
 2011-11-10 19:52:58 +00:00
Eric Christopher
60be243dc5 Rework adding function names to the dwarf accelerator tables, allow 
multiple dies per function and support C++ basenames.

llvm-svn: 144304
 2011-11-10 19:25:34 +00:00
Jim Grosbach
f5943e4c5e ARM assembly parsing for LSR/LSL/ROR(immediate). 
More of rdar://9704684

llvm-svn: 144301
 2011-11-10 19:18:01 +00:00
Jim Grosbach
b66dfc2999 ARM assembly parsing for ASR(immediate). 
Start of rdar://9704684

llvm-svn: 144293
 2011-11-10 16:44:55 +00:00
Daniel Dunbar
710e8f8758 build: Rename CBackend and CppBackend libraries to have CodeGen suffix, for 
consistency with other targets.

llvm-svn: 144292
 2011-11-10 15:35:14 +00:00
Evan Cheng
4760ff0763 Use a bigger hammer to fix PR11314 by disabling the "forcing two-address 
instruction lower optimization" in the pre-RA scheduler.

The optimization, rather the hack, was done before MI use-list was available.
Now we should be able to implement it in a better way, perhaps in the
two-address pass until a MI scheduler is available.

Now that the scheduler has to backtrack to handle call sequences. Adding
artificial scheduling constraints is just not safe. Furthermore, the hack
is not taking all the other scheduling decisions into consideration so it's just
as likely to pessimize code. So I view disabling this optimization goodness
regardless of PR11314.

llvm-svn: 144267
 2011-11-10 07:43:16 +00:00
Nadav Rotem
e3d8f1a069 AVX2: Add variable shift from memory. 
Note: These patterns only works in some cases because
many times the load sd node is bitcasted from a load
node of a different type.

llvm-svn: 144266
 2011-11-10 06:54:20 +00:00
Chad Rosier
69cdae5eb9 For immediate encodings of icmp, zero or sign extend first. Then 
determine if the value is negative and flip the sign accordingly.
rdar://10422026

llvm-svn: 144258
 2011-11-10 01:30:39 +00:00
Daniel Dunbar
138437ad27 build/Make & CMake: Pass the appropriate --native-target and --enable-targets 
options to llvm-build, so the all-targets etc. components are defined properly.

llvm-svn: 144255
 2011-11-10 01:16:48 +00:00
Daniel Dunbar
f0c4aed0ab llvm-build: Add --native-target and --enable-targets options, and add logic to 
handle defining the "magic" target related components (like native,
nativecodegen, and engine).
 - We still require these components to be in the project (currently in
   lib/Target) so that we have a place to document them and hopefully make it
   more obvious that they are "magic".

llvm-svn: 144253
 2011-11-10 00:50:07 +00:00
Daniel Dunbar
ce64a65fea llvm-build: Change CBackend and CppBackend to not use library_name. This will 
change the generated library .a file name once we fully switch over, but
simplifies how we treat these targets without requiring more special casing
(since their library group name and the codegen library name currently map to
the same "llvm-config" style component name).

llvm-svn: 144251
 2011-11-10 00:49:55 +00:00
Daniel Dunbar
c09b47db8f llvm-build: Add an explicit component type to represent targets. 
- Gives us a place to hang target specific metadata (like whether the target has a JIT).

llvm-svn: 144250
 2011-11-10 00:49:51 +00:00
Jakob Stoklund Olesen
bc48cd34b6 Strip old implicit operands after foldMemoryOperand. 
The TII.foldMemoryOperand hook preserves implicit operands from the
original instruction.  This is not what we want when those implicit
operands refer to the register being spilled.

Implicit operands referring to other registers are preserved.

This fixes PR11347.

llvm-svn: 144247
 2011-11-10 00:17:03 +00:00
Jim Grosbach
ee70556a4e Tidy up. 
llvm-svn: 144244
 2011-11-10 00:02:33 +00:00
Jim Grosbach
8591bd2bab Thumb2 assembly parsing STMDB w/ optional .w suffix. 
rdar://10422955

llvm-svn: 144242
 2011-11-09 23:44:23 +00:00
Eli Friedman
c93f8aa514 Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM. 
llvm-svn: 144241
 2011-11-09 23:36:02 +00:00
Pete Cooper
38700a1201 DeadStoreElimination can now trim the size of a store if the end of the store is dead. 
Currently checks alignment and killing stores on a power of 2 boundary as this is likely
to trim the size of the earlier store without breaking large vector stores into scalar ones.

Fixes <rdar://problem/10140300>

llvm-svn: 144239
 2011-11-09 23:07:35 +00:00
Nick Lewycky
bb1e607255 Fix typo in comment. 
llvm-svn: 144236
 2011-11-09 22:45:04 +00:00
Eli Friedman
b01f15653c Add check so we don't try to perform an impossible transformation. Fixes issue from PR11319. 
llvm-svn: 144216
 2011-11-09 22:25:12 +00:00
Chad Rosier
f47b941510 The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12. 
rdar://10418009

llvm-svn: 144213
 2011-11-09 21:30:12 +00:00
Nadav Rotem
ddc6bfa543 AVX2: Add patterns for variable shift operations 
llvm-svn: 144212
 2011-11-09 21:22:13 +00:00