RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-04-15 14:09:57 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
104,947 Commits 6 Branches 6 Tags
Commit Graph

157 Commits

Author SHA1 Message Date
Craig Topper
0f7cdab983 [C++11] More 'nullptr' conversion. In some cases just using a boolean check instead of comparing to nullptr. 
llvm-svn: 206254
 2014-04-15 07:20:03 +00:00
Craig Topper
0fa9073645 [x86] Simplify disassembler code slightly. 
llvm-svn: 202233
 2014-02-26 06:01:21 +00:00
Craig Topper
80c9d78b97 [x86] Switch PAUSE instruction to use XS prefix instead of HasREPPrefix. Remove HasREPPrefix support from disassembler table generator since its now only used by CodeGenOnly instructions. 
llvm-svn: 201767
 2014-02-20 07:59:43 +00:00
Craig Topper
de3c74571e Remove special FP opcode maps and instead add enough MRM_XX formats to handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change. 
llvm-svn: 201649
 2014-02-19 08:25:02 +00:00
Craig Topper
7d159c5e98 Put some of the X86 formats in a more logical order. 
llvm-svn: 201645
 2014-02-19 06:59:13 +00:00
Craig Topper
5b20c52fcc Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables. 
llvm-svn: 201641
 2014-02-19 05:34:21 +00:00
Craig Topper
de78f4304d Add an x86 prefix encoding for instructions that would decode to a different instruction with 0xf2/f3/66 were in front of them, but don't themselves have a prefix. For now this doesn't change any bbehavior, but plan to use it to fix some bugs in the disassembler. 
llvm-svn: 201538
 2014-02-18 00:21:49 +00:00
Craig Topper
882df7af18 Remove filtering concept from X86 disassembler table generation. It's no longer necessary. 
llvm-svn: 201299
 2014-02-13 07:07:16 +00:00
Craig Topper
f39f3fd69a Remove special case filtering for instructions with lock prefix as they are all marked with isCodeGenOnly already. 
llvm-svn: 201216
 2014-02-12 08:09:20 +00:00
Craig Topper
8189467f87 Mark XACQUIRE_PREFIX/XRELEASE_PREFIX as isAsmParserOnly so they'll disappear from the disassembler table build without custom filtering code. 
llvm-svn: 201215
 2014-02-12 08:02:29 +00:00
Craig Topper
5f3cd9c3a9 Recommit r201059 and r201060 with hopefully a fix for its original failure. 
Original commits messages:

Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code.

Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information.

llvm-svn: 201065
 2014-02-10 06:55:41 +00:00
Bob Wilson
3e54e44d03 Revert r201059 and r201060. 
r201059 appears to cause a crash in a bootstrapped build of clang. Craig
isn't available to look at it right now, so I'm reverting it while he
investigates.

llvm-svn: 201064
 2014-02-10 05:28:30 +00:00
Craig Topper
4940698ac0 Simplify a bunch of code by removing the need for the x86 disassembler table builder to know about extended opcodes. The modrm forms are sufficient to convey the information. 
llvm-svn: 201060
 2014-02-10 01:58:12 +00:00
Craig Topper
c4ecc4bda5 Add MRMXr/MRMXm form to X86 for use by instructions which treat the 'reg' field of modrm byte as a don't care value. Will allow for simplification of disassembler code. 
llvm-svn: 201059
 2014-02-10 00:50:34 +00:00
Craig Topper
e916566881 Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. 
llvm-svn: 200626
 2014-02-02 09:25:09 +00:00
Craig Topper
d19193392f Simplify some code since VEX and EVEX instructions never have HasOpSizePrefix. 
llvm-svn: 200625
 2014-02-02 07:46:05 +00:00
Craig Topper
75deac3bc2 Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags. 
llvm-svn: 200624
 2014-02-02 07:08:01 +00:00
Craig Topper
e33ac72bdf Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters. 
llvm-svn: 200522
 2014-01-31 08:47:06 +00:00
Craig Topper
0754fb95c1 Move REP out of the Prefix field of the X86 format. Give it its own bit. It had special handling anyway and this enables a future patch. 
llvm-svn: 200520
 2014-01-31 07:00:55 +00:00
David Woodhouse
4515fd303f ]x86] Allow segment and address-size overrides for CMPS[BWLQ] (PR9385) 
llvm-svn: 199806
 2014-01-22 15:08:36 +00:00
David Woodhouse
59ef208820 [x86] Allow address-size overrides for STOS[BWLQ] (PR9385) 
llvm-svn: 199804
 2014-01-22 15:08:21 +00:00
David Woodhouse
e01fc03be8 [x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385) 
llvm-svn: 199803
 2014-01-22 15:08:08 +00:00
David Woodhouse
d30df6b04f [x86] Fix disassembly of MOV16ao16 et al. 
The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It
also turns out to have been unnecessary. The disassembler handles the
AdSize prefix for itself, and doesn't care about the difference between
(e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and
don't worry about it.

llvm-svn: 199654
 2014-01-20 12:02:53 +00:00
Craig Topper
f63b7bc430 Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. 
llvm-svn: 199364
 2014-01-16 07:36:58 +00:00
Craig Topper
57fa50f4c8 Simplify x86 disassembler table handling of when to use TYPE_Rv/TYPE_R16/TYPE_R32 now that HasOpSizePrefix only means 16-bit instructions. 
llvm-svn: 199295
 2014-01-15 05:02:02 +00:00
Craig Topper
2b2eb7f7cc Remove stray comma in enum to satisfy -Wpedantic. 
llvm-svn: 199194
 2014-01-14 08:07:10 +00:00
Craig Topper
1c1ecbff81 Separate the concept of 16-bit/32-bit operand size controlled by 0x66 prefix and the current mode from the concept of SSE instructions using 0x66 prefix as part of their encoding without being affected by the mode. 
This should allow SSE instructions to be encoded correctly in 16-bit mode which r198586 probably broke.

llvm-svn: 199193
 2014-01-14 07:41:20 +00:00
David Woodhouse
399c563e5e [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand 
It seems there is no separate instruction class for having AdSize *and*
OpSize bits set, which is required in order to disambiguate between all
these instructions. So add that to the disassembler.

Hm, perhaps we do need an AdSize16 bit after all?

llvm-svn: 198759
 2014-01-08 12:58:24 +00:00
Craig Topper
d4c2e3f15e The rest of r198588. Remove SegOvrBits from X86 TSFlags since they weren't being used. 
llvm-svn: 198589
 2014-01-06 06:57:27 +00:00
Craig Topper
60c74a0e11 Use patterns to remove some duplicate instructions. 
llvm-svn: 198550
 2014-01-05 06:55:48 +00:00
Craig Topper
3ff26e1332 Fix encoding for PUSH64i16. Add In64BitMode Predicate. Remove disassembler hack. 
llvm-svn: 198547
 2014-01-05 05:46:38 +00:00
Craig Topper
5601f6ca67 Remove no longer needed x86 disassembler hack. 
llvm-svn: 198546
 2014-01-05 05:10:07 +00:00
Craig Topper
eea372cfa3 Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches. 
llvm-svn: 198545
 2014-01-05 04:55:55 +00:00
Craig Topper
0b1961cfbc Use new ForceDisassemble flag on the 2-byte forms of INC/DEC for 32-bit mode and remove disassmbler table emitter hack. 
llvm-svn: 198544
 2014-01-05 04:32:42 +00:00
Craig Topper
4a48c26e38 Add a new x86 specific instruction flag to force some isCodeGenOnly instructions to go through to the disassembler tables without resorting to string matches. Apply flag to all _REV instructions. 
llvm-svn: 198543
 2014-01-05 04:17:28 +00:00
Craig Topper
83505ed565 Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test. 
llvm-svn: 198530
 2014-01-05 01:35:51 +00:00
Craig Topper
0418d1dd5a Tag x86 move to/from debug/control registers with Not64BitMode/In64BitMode. Remove disassembler hack. 
llvm-svn: 198515
 2014-01-04 22:29:41 +00:00
Craig Topper
4c535886dc Remove JMP64pcrel32 (jmpq ). There are no tests for it. I'm pretty sure it won't be emitted correctly since it was set to NoImm. And I can't prove that gas accepts 'jmpq' with an immediate either. Remove the special case for it from the disassembler table generator. 
llvm-svn: 198475
 2014-01-04 05:09:27 +00:00
Craig Topper
839231f528 Mark REX64_PREFIX as In64BitMode, remove hack from X86RecognizableInstr. 
llvm-svn: 198336
 2014-01-02 19:12:10 +00:00
Craig Topper
c88fd21439 Remove unused HasFROperands field from disassembler. 
llvm-svn: 198332
 2014-01-02 18:44:21 +00:00
Craig Topper
ba17ca1e89 Mark PUSHFS64/PUSHGS64/POPFS64/POPGS64 as In64BitMode and remove the hack from the disassembler table builder. 
llvm-svn: 198327
 2014-01-02 18:20:48 +00:00
Craig Topper
9cf0c703a1 Remove unnecessary stirng comparison from disassembler. 
llvm-svn: 198325
 2014-01-02 17:41:40 +00:00
Craig Topper
57b949fa83 Mark all x86 Int_ and _Int patterns as isCodeGenOnly so the disassembler table builder doesn't need to string match them to exclude them. 
llvm-svn: 198323
 2014-01-02 17:28:14 +00:00
Craig Topper
f98f744453 Remove unused function argument. 
llvm-svn: 198291
 2014-01-02 03:58:45 +00:00
Craig Topper
b3f7e28cb6 Remove modifierType/Base from X86 disassembler tables as they are no longer used. Removes ~11.5K from static tables. 
llvm-svn: 198284
 2014-01-01 21:52:57 +00:00
Craig Topper
9d2e15270b Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits. 
llvm-svn: 198278
 2014-01-01 15:29:32 +00:00
Elena Demikhovsky
7174584583 AVX-512: Added intrinsics for vcvt, vcvtt, vrndscale, vcmp 
Printing rounding control.
Enncoding for EVEX_RC (rounding control).

llvm-svn: 198277
 2014-01-01 15:12:34 +00:00
Craig Topper
4454a2fa93 Second attempt at Removing special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. 
llvm-svn: 198276
 2014-01-01 14:22:37 +00:00
Craig Topper
d0374cb642 Revert r198238 and add FP disassembler tests. It didn't work and I didn't realized we had no FP disassembler test cases. 
llvm-svn: 198265
 2013-12-31 17:21:44 +00:00
Craig Topper
c4a2189f05 Remove special form of AddRegFrm used by FP instructions. These instructions can be handled by MRMXr instead. 
llvm-svn: 198238
 2013-12-30 19:16:48 +00:00