172757 Commits

Author SHA1 Message Date
Zachary Turner
9c59ff4bb6 [MS Demangler] Add a helper function to print a Node as a string.
llvm-svn: 349359
2018-12-17 16:14:50 +00:00
Petar Avramovic
96837a54be [MIPS GlobalISel] Remove switch statement (fix r349346 for MSVC)
Temporarily remove switch statement without any case labels 
in function legalizeCustom in order to fix r349346 for MSVC.

llvm-svn: 349356
2018-12-17 15:12:53 +00:00
Tim Northover
29b969dda5 ARM: use acquire/release instruction variants when available.
These features (fairly) recently got split out into their own feature, so we
should make CodeGen use them when available. The main change here is that the
check used to be based on the triple, but now it's based on CPU features.

llvm-svn: 349355
2018-12-17 15:05:32 +00:00
Andrea Di Biagio
431c9f6d7c [MCA] Add support for BeginGroup/EndGroup.
llvm-svn: 349354
2018-12-17 14:27:33 +00:00
Eric Liu
865841dbe7 Revert "DebugInfo: Assume an absence of ranges or high_pc on a CU means the CU is empty (devoid of code addresses)"
This reverts commit r349333. It caused internal test to fail. I have
sent more information to the author.

llvm-svn: 349353
2018-12-17 14:14:40 +00:00
Andrea Di Biagio
e6ecfd3ed6 [MCA] Don't assume that createMCInstrAnalysis() always returns a valid pointer.
Class InstrBuilder wrongly assumed that llvm targets were always able to return
a non-null pointer when createMCInstrAnalysis() was called on them.
This was causing crashes when simulating executions for targets that don't
provide an MCInstrAnalysis object.
This patch fixes the issue by making MCInstrAnalysis optional.

llvm-svn: 349352
2018-12-17 14:00:37 +00:00
Simon Pilgrim
e9394d5e98 Regenerate test in prep for SimplifyDemandedBits improvements.
llvm-svn: 349350
2018-12-17 12:48:34 +00:00
Sanjay Patel
abc3c3d481 [AggressiveInstCombine] add test for rotate insertion point; NFC
As noted in D55604 - we need a test to make sure that the new intrinsic
is inserted into a valid position.

llvm-svn: 349347
2018-12-17 12:36:35 +00:00
Petar Avramovic
df2c4df13c [MIPS GlobalISel] Lower G_UADDE and narrowScalar G_ADD
Lower G_UADDE and legalize G_ADD using narrowScalar on MIPS32.

Differential Revision: https://reviews.llvm.org/D54580

llvm-svn: 349346
2018-12-17 12:31:07 +00:00
Alexandros Lamprineas
ff2cabbc44 [AArch64] Re-run load/store optimizer after aggressive tail duplication
The Load/Store Optimizer runs before Machine Block Placement. At O3 the
Tail Duplication Threshold is set to 4 instructions and this can create
new opportunities for the Load/Store Optimizer. It seems worthwhile to
run it once again.

llvm-svn: 349338
2018-12-17 10:45:43 +00:00
David Blaikie
87758632ea DebugInfo: Assume an absence of ranges or high_pc on a CU means the CU is empty (devoid of code addresses)
GCC emitted these unconditionally on/before 4.4/March 2012
Clang emitted these unconditionally on/before 3.5/March 2014

This improves performance when parsing CUs (especially those using split
DWARF) that contain no code ranges (such as the mini CUs that may be
created by ThinLTO importing - though generally they should be/are
avoided, especially for Split DWARF because it produces a lot of very
small CUs, which don't scale well in a bunch of other ways too
(including size)).

llvm-svn: 349333
2018-12-17 08:27:19 +00:00
Clement Courbet
9093bbf39e [llvm-mca] Move llvm-mca library to llvm/lib/MCA.
Summary: See PR38731.

Reviewers: andreadb

Subscribers: mgorny, javed.absar, tschuett, gbedwell, andreadb, RKSimon, llvm-commits

Differential Revision: https://reviews.llvm.org/D55557

llvm-svn: 349332
2018-12-17 08:08:31 +00:00
Craig Topper
ee8ca8fe5e [X86] Add test case for PR39968. NFC
llvm-svn: 349331
2018-12-17 07:51:17 +00:00
Craig Topper
39db38f549 [X86] Fix bad operand lookup for cmov introduced in r349315
The CC is operand 2 not operand 3.

llvm-svn: 349330
2018-12-17 06:40:35 +00:00
Kewen Lin
331b9b3223 [Power9][NFC]update vabsd case for better dumping
Appended options -ppc-vsr-nums-as-vr and -ppc-asm-full-reg-names to get the 
more descriptive output. Also removed useless function attributes.

llvm-svn: 349329
2018-12-17 06:32:02 +00:00
Kewen Lin
946331978d [Power9][NFC]Make pre-inc-disable case more robust
With some patch adopted for Power9 vabsd* insns, some CHECKs can't get the expected results.
But it's false alarm, we should update the case more robust.

llvm-svn: 349325
2018-12-17 03:16:12 +00:00
Nico Weber
b8e447f672 [gn build] Add build files for opt and its dependency Transforms/Couroutines
Needed for check-lld.

Differential Revision: https://reviews.llvm.org/D55750

llvm-svn: 349324
2018-12-17 02:33:15 +00:00
Davide Italiano
9414c8db71 [EarlyCSE] If DI can't be salvaged, mark it as unavailable.
Fixes PR39874.

llvm-svn: 349323
2018-12-17 01:42:39 +00:00
Nikita Popov
38e5dd7e13 [InstCombine] Add cttz/ctlz + select non-bitwidth tests; NFC
llvm-svn: 349322
2018-12-16 23:48:18 +00:00
Nikita Popov
b018fd8e94 [InstCombine] Regenerate test checks; NFC
Also drop unnecessary entry blocks and avoid use of anonymous
variables.

llvm-svn: 349321
2018-12-16 23:48:11 +00:00
Simon Pilgrim
be751a7faf [X86] Pull out constant splat rotation detection.
We had 3 different approaches - consistently use getTargetConstantBitsFromNode and allow undef elts.

llvm-svn: 349319
2018-12-16 19:46:04 +00:00
Nikita Popov
eaa6720bf3 [InstCombine] Make cttz/ctlz knownbits tests more robust; NFC
Tests checking for the addition of !range metadata should be
preserved if cttz/ctlz + icmp is optimized.

llvm-svn: 349318
2018-12-16 19:12:08 +00:00
Simon Pilgrim
d1dcd62356 Regenerate test (merges X86+X64 cases). NFCI.
llvm-svn: 349317
2018-12-16 19:07:57 +00:00
Craig Topper
4feb7d218a [X86] Remove truncation handling from EmitTest. Replace it with a DAG combine.
I'd like to try to move a lot of the flag matching out of EmitTest and push it to isel or isel preprocessing. This is a step towards that.

The test-shrink-bug.ll changie is an improvement because we are no longer interfering with test shrink handling in isel.

The pr34137.ll change is a regression, but the IR came from -O0 and was not reduced by InstCombine. So it contains a lot of redundancies like duplicate loads that made it combine poorly.

llvm-svn: 349315
2018-12-16 18:35:55 +00:00
Craig Topper
1e076b5b0e [X86] Autogenerate complete checks. NFC
llvm-svn: 349314
2018-12-16 18:35:54 +00:00
Nikita Popov
fe418b91a7 Revert "[InstCombine] Regenerate test checks; NFC"
This reverts commit r349311.

Didn't check this carefully enough...

llvm-svn: 349312
2018-12-16 18:27:37 +00:00
Nikita Popov
8943e97c43 [InstCombine] Regenerate test checks; NFC
llvm-svn: 349311
2018-12-16 18:22:57 +00:00
Nikita Popov
61417b4b6d [InstCombined] Add more tests for cttz/ctlz + icmp; NFC
Test cases other than icmp with the bitwidth.

llvm-svn: 349310
2018-12-16 17:51:32 +00:00
Nikita Popov
d0b1b3dede [InstCombine] Add additional saturating add/sub + icmp tests; NFC
These test comparisons with saturating add/sub in non-canonical
form.

llvm-svn: 349309
2018-12-16 17:45:25 +00:00
Sanjay Patel
c0a71fd8c3 [InstCombine] regenerate test checks; NFC
llvm-svn: 349307
2018-12-16 16:14:42 +00:00
Sanjay Patel
7152ae4ea3 [InstCombine] add tests for vector widening transforms (PR40032); NFC
llvm-svn: 349306
2018-12-16 15:50:50 +00:00
Sanjay Patel
09930dc43f [x86] increment/decrement constant vector with min/max in vsetcc lowering (PR39859)
This is part of fixing PR39859:
https://bugs.llvm.org/show_bug.cgi?id=39859

We have a crippled vector ISA, so we have to invert a typical fold and create min/max here.

As discussed in the bug report, we can probably do better by using saturating subtract when 
it's available, but we should have this improvement for the min/max patterns regardless.

Alive proofs:
https://rise4fun.com/Alive/zsf
https://rise4fun.com/Alive/Qrl

Differential Revision: https://reviews.llvm.org/D55515

llvm-svn: 349304
2018-12-16 15:05:48 +00:00
Sanjay Patel
55b3136c52 [DAGCombiner] allow hoisting vector bitwise logic ahead of truncates
The transform performs a bitwise logic op in a wider type followed by
truncate when both inputs are truncated from the same source type:
logic_op (truncate x), (truncate y) --> truncate (logic_op x, y)

There are a bunch of other checks that should prevent doing this when 
it might be harmful.

We already do this transform for scalars in this spot. The vector 
limitation was shared with a check for the case when the operands are 
extended. I'm not sure if that limit is needed either, but that would 
be a separate patch.

Differential Revision: https://reviews.llvm.org/D55448

llvm-svn: 349303
2018-12-16 14:57:04 +00:00
Sylvestre Ledru
a9dc6631f3 Update the list of platforms & archs
llvm-svn: 349302
2018-12-16 14:47:16 +00:00
Sylvestre Ledru
5f65a6f63e Use backquotes to avoid a sphinx unexpected error:
Unknown target name: "bootstrap".

llvm-svn: 349301
2018-12-16 14:19:39 +00:00
Sylvestre Ledru
59afa1fde5 Document the usage of BOOTSTRAP_XXX with stage2 builds
llvm-svn: 349299
2018-12-16 14:04:10 +00:00
Simon Pilgrim
a3996e5f78 [SelectionDAG] Add FSHL/FSHR support to computeKnownBits
Also exposes an issue in DAGCombiner::visitFunnelShift where we were assuming the shift amount had the result type (after legalization it'll have the targets shift amount type).

llvm-svn: 349298
2018-12-16 13:33:37 +00:00
Simon Pilgrim
3c38377cf1 [X86] Add computeKnownBits tests for funnel shift intrinsics
llvm-svn: 349297
2018-12-16 12:15:31 +00:00
Nico Weber
ab798a428a [gn build] Merge r349167
llvm-svn: 349291
2018-12-16 02:32:20 +00:00
Nico Weber
0b2496bfd0 [gn build] Add build files for obj2yaml, yaml2obj, and lib/ObjectYAML
The two executables are needed by check-lld.

Differential Revision: https://reviews.llvm.org/D55687

llvm-svn: 349290
2018-12-16 02:29:02 +00:00
Nico Weber
13f5841557 [gn build] Add build files for llvm-as, llvm-dis, llvm-dwarfdump, llvm-mc, FileCheck, count, not
These executables are needed by check-lld.

Differential Revision: https://reviews.llvm.org/D55688

llvm-svn: 349289
2018-12-16 02:27:10 +00:00
Craig Topper
c206b35246 [X86] Autogenerate complete checks. NFC
llvm-svn: 349287
2018-12-15 22:52:57 +00:00
Simon Pilgrim
c9387a674a [X86] Begin cleaning up combineOr -> SHLD/SHRD. NFCI.
In preparation for converting to funnel shifts.

llvm-svn: 349286
2018-12-15 21:11:49 +00:00
Simon Pilgrim
79a641d507 [X86] Lower to SHLD/SHRD on slow machines for optsize
Use consistent rules for when to lower to SHLD/SHRD for slow machines - fixes a weird issue where funnel shift gets expanded but then X86ISelLowering's combineOr sees the optsize and combines to SHLD/SHRD, but now with the modulo amount guard......

llvm-svn: 349285
2018-12-15 19:43:44 +00:00
Simon Pilgrim
4ab16cb47f [X86] Add optsize SHLD/SHRD tests
llvm-svn: 349284
2018-12-15 19:32:26 +00:00
Kamil Rytarowski
4f542b3de4 Add NetBSD support in needsRuntimeRegistrationOfSectionRange.
Use linker script magic to get data/cnts/name start/end.

llvm-svn: 349277
2018-12-15 16:51:35 +00:00
Kamil Rytarowski
151ce022c7 Register kASan shadow offset for NetBSD/amd64
The NetBSD x86_64 kernel uses the 0xdfff900000000000 shadow
offset.

llvm-svn: 349276
2018-12-15 16:32:41 +00:00
Dinar Temirbulatov
f0b82ae07a [CodeGen] Enhance machine PHIs optimization
Summary:
Make machine PHIs optimization to work for single value register taken from
several different copies. This is the first step to fix PR38917. This change
allows to get rid of redundant PHIs (see opt_phis2.mir test) to make
the subsequent optimizations (like CSE) possible and simpler.

For instance, before this patch the code like this:

%b = COPY %z
...
%a = PHI %bb1, %a; %bb2, %b
could be optimized to:

%a = %b
but the code like this:

%c = COPY %z
...
%b = COPY %z
...
%a = PHI %bb1, %a; %bb2, %b; %bb3, %c
would remain unchanged.
With this patch the latter case will be optimized:

%a = %z```.

Committed on behalf of: Anton Afanasyev anton.a.afanasyev@gmail.com

Reviewers: RKSimon, MatzeB

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D54839

llvm-svn: 349271
2018-12-15 14:37:01 +00:00
Simon Pilgrim
bbfa21a09f Regenerate neon copy tests. NFCI.
llvm-svn: 349270
2018-12-15 14:23:18 +00:00
Simon Pilgrim
1fe9c9ab75 Fix -Wunused-variable warning. NFCI.
llvm-svn: 349265
2018-12-15 12:25:22 +00:00