174037 Commits

Author SHA1 Message Date
Kostya Kortchinsky
a0f8859483 [docs] Scudo: document error messages & their potential cause
Summary:
A couple of changes in the Scudo documentation:
- tag the shell code blocks as `console`;
- document error messages that are displayed in some termination conditions,
  the reason they triggered, and potential causes.

Reviewers: eugenis, enh

Reviewed By: eugenis

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D56857

llvm-svn: 351838
2019-01-22 16:43:45 +00:00
Adrian Prantl
a066459576 Add DIGlobalVariableExpression to LangRef
llvm-svn: 351837
2019-01-22 16:40:18 +00:00
Simon Pilgrim
c9e9d0c57b [llvm-mca][X86] Add missing CLWB/CLZERO/FSGSBASE/LWP/MWAITX/RDPID/SHA tests
We're getting pretty close to matching/exceeding test coverage of the test\CodeGen\X86\*-schedule.ll files, which should allow us to get rid of -print-schedule and fix PR37160

llvm-svn: 351836
2019-01-22 16:39:28 +00:00
Simon Pilgrim
2303d55947 [llvm-mca][X86] Add missing enter/leave, invlpg/invlpga, rdmsr/wrmsr, rdpmc and rdtsc/rdtscp tests
llvm-svn: 351835
2019-01-22 16:29:26 +00:00
Sanjay Patel
523c335e22 [x86] add another partial undef vector binop test; NFC
The existing test unintentionally shows that we have prematurely
optimized the shuffle into a vector concat and lost the undef info, 
so it is not affected by a basic improvement to 
SimplifyDemandedVectorElts.

llvm-svn: 351834
2019-01-22 16:26:09 +00:00
Serge Guelton
a92bb26953 Use response file when generating LLVM-C.dll
As discovered in D56774 the command line gets to long, so use a response file to give the script the libs. This change has been tested and is confirmed working for me.

Commited on behalf of Jakob Bornecrantz

Differential Revision: https://reviews.llvm.org/D56781

llvm-svn: 351833
2019-01-22 16:25:17 +00:00
Simon Pilgrim
7dd228c0b5 [llvm-mca][X86] Add missing mfence/pinsrw tests
llvm-svn: 351831
2019-01-22 16:01:08 +00:00
Simon Pilgrim
7cdc324256 [llvm-mca][X86] Add missing monitor/mwait tests
These technically should be under a MONITOR cpuid bit, but we tag them as SSE3 so I've done that here as well.

llvm-svn: 351829
2019-01-22 15:48:16 +00:00
Simon Pilgrim
b236c0b7ae [llvm-mca][X86] Add missing vperm2i128 tests
llvm-svn: 351828
2019-01-22 14:54:24 +00:00
Simon Pilgrim
d46164e1c4 [llvm-mca][X86] Add missing tzcntw tests
llvm-svn: 351827
2019-01-22 14:53:52 +00:00
Sanjay Patel
f53aba3bbd [DAGCombiner] narrow vector binop with 2 insert subvector operands
vecbo (insertsubv undef, X, Z), (insertsubv undef, Y, Z) --> insertsubv VecC, (vecbo X, Y), Z

This is another step in generic vector narrowing. It's also a step towards more horizontal op 
formation specifically for x86 (although we still failed to match those in the affected tests).

The scalarization cases are also not optimal (we should be scalarizing those), but it's still 
an improvement to use a narrower vector op when we know part of the result must be constant 
because both inputs are undef in some vector lanes.

I think a similar match but checking for a constant operand might help some of the cases in 
D51553.

Differential Revision: https://reviews.llvm.org/D56875

llvm-svn: 351825
2019-01-22 14:24:13 +00:00
George Rimar
374bfb8ad3 [llvm-objdump] - Introduce getRelocsMap() helper. NFCI.
Currently disassembleObject() is a ~550 lines length function.
This patch extracts the code that creates a section->their relocation
mapping into a new helper function to simplify/reduce it a bit.

Differential revision: https://reviews.llvm.org/D57019

llvm-svn: 351824
2019-01-22 14:09:37 +00:00
Alex Bradbury
7b809a350f [RISCV][NFC] Change naming scheme for RISC-V specific DAG nodes
Previously we had names like 'Call' or 'Tail'. This potentially clashes with
the naming scheme used elsewhere in RISCVInstrInfo.td. Many other backends
would use names like AArch64call or PPCtail. I prefer the SystemZ approach,
which uses prefixed all-lowercase names. This matches the naming scheme used
for target-independent SelectionDAG nodes.

llvm-svn: 351823
2019-01-22 14:05:11 +00:00
Andrea Di Biagio
477f885ddd [MCA] Add tests for int-to-fpu transfer delays. NFC
llvm-svn: 351822
2019-01-22 13:59:08 +00:00
Serge Guelton
2a0c5337b6 Slight fix for r351820
llvm-svn: 351821
2019-01-22 13:57:29 +00:00
Serge Guelton
1e000b2c69 Fix llvm::is_trivially_copyable portability issues
llvm::is_trivially_copyable portability is verified at compile time using
std::is_trivially_copyable as the reference implementation.

Unfortunately, the latter is not available on all platforms, so introduce
a proper configure check to detect if it is available on the target platform.

In a similar manner, std::is_copy_assignable is not fully supported for gcc4.9.
Provide a portable (?) implementation instead.

Differential Revision: https://reviews.llvm.org/D57018

llvm-svn: 351820
2019-01-22 13:48:55 +00:00
Simon Pilgrim
af41a20065 [X86][SSE] Canonicalize OR(AND(X,C),AND(Y,~C)) -> OR(AND(X,C),ANDNP(C,Y))
For constant bit select patterns, replace one AND with a ANDNP, allowing us to reuse the constant mask. Only do this if the mask has multiple uses (to avoid losing load folding) or if we have XOP as its VPCMOV can handle most folding commutations.

This also requires computeKnownBitsForTargetNode support for X86ISD::ANDNP and X86ISD::FOR to prevent regressions in fabs/fcopysign patterns.

Differential Revision: https://reviews.llvm.org/D55935

llvm-svn: 351819
2019-01-22 13:44:49 +00:00
Simon Pilgrim
4e12ad7a89 [X86][BtVer2] SSE2 vector shifts has local forwarding disabled
Similar to horizontal ops on D56777, the sse2 (but not mmx) bit shift ops has local forwarding disabled, adding +1cy to the use latency for the result.

Differential Revision: https://reviews.llvm.org/D57026

llvm-svn: 351817
2019-01-22 13:27:18 +00:00
Simon Pilgrim
33cb623284 Fix "comparison of unsigned expression >= 0 is always true" warning. NFCI.
llvm-svn: 351816
2019-01-22 13:18:26 +00:00
Simon Pilgrim
68224246f0 [X86][BtVer2] X86ISD::VPERMILPV has local forwarding disabled
Similar to horizontal ops on D56777, the vpermilpd/vpermilps variable mask ops has local forwarding disabled, adding +1cy to the use latency for the result.

Differential Revision: https://reviews.llvm.org/D57022

llvm-svn: 351815
2019-01-22 13:13:57 +00:00
Martin Storsjo
934770da1f Revert "[llvm-objcopy] [COFF] Implement --add-gnu-debuglink"
This reverts commit r351801, as it caused errors on (so far)
ppc64be and aarch64 buildbots - the reason is yet unknown.

llvm-svn: 351811
2019-01-22 12:35:34 +00:00
Simon Pilgrim
66cbe53d7d [CostModel][X86] Add ICMP Predicate specific costs
First step towards PR40376, this patch adds support for getCmpSelInstrCost to use the (optional) Instruction CmpInst predicate to indicate the type of integer comparison we're performing and alter the costs accordingly.

Differential Revision: https://reviews.llvm.org/D57013

llvm-svn: 351810
2019-01-22 12:29:38 +00:00
Simon Pilgrim
e6c016411f [X86][SSE] Add selective commutation support for insertps (PR40340)
When we are inserting 1 "inline" element, and zeroing 2 of the other elements then we can safely commute the insertps source inputs to improve memory folding.

Differential Revision: https://reviews.llvm.org/D56843

llvm-svn: 351807
2019-01-22 12:17:48 +00:00
Alex Bradbury
047632c571 [RISCV] Quick fix for PR40333
Avoid the infinite loop caused by the target DAG combine converting ANYEXT to
SIGNEXT and the target-independent DAG combine logic converting back to
ANYEXT. Do this by not adding the new node to the worklist.

Committing directly as this definitely doesn't make the problem any worse, and
I intend to follow-up with a patch that avoids this custom combiner logic
altogether and just lowers the i32 operations to a target-specific
SelectionDAG node. This should be easier to reason about and improve codegen
quality in some cases (though may miss out on some later DAG combines).

llvm-svn: 351806
2019-01-22 12:11:53 +00:00
Max Kazantsev
daef624965 [LoopPredication] Support guards expressed as branches by widenable condition
This patch adds support of guards expressed as branches by widenable
conditions in Loop Predication.

Differential Revision: https://reviews.llvm.org/D56081
Reviewed By: reames

llvm-svn: 351805
2019-01-22 11:49:06 +00:00
Simon Pilgrim
a25521a255 [X86] Add test for matchAddressRecursively's MUL handling
Noticed in code coverage tests that this isn't tested.

llvm-svn: 351804
2019-01-22 11:39:21 +00:00
Max Kazantsev
03355e4336 [NFC] Add function to parse widenable conditional branches
llvm-svn: 351803
2019-01-22 11:21:32 +00:00
Martin Storsjo
ac45f0ce9d [llvm-objcopy] [COFF] Implement --add-gnu-debuglink
Differential Revision: https://reviews.llvm.org/D57007

llvm-svn: 351801
2019-01-22 10:58:18 +00:00
Martin Storsjo
2151d56b45 [llvm-objcopy] [COFF] Update symbol indices in weak externals
Differential Revision: https://reviews.llvm.org/D57006

llvm-svn: 351800
2019-01-22 10:58:09 +00:00
Martin Storsjo
70751a99e9 [llvm-objcopy] Consistently use createStringError instead of make_error<StringError>
This was requested in the review of D57006.

Also add missing quotes around symbol names in error messages.

Differential Revision: https://reviews.llvm.org/D57014

llvm-svn: 351799
2019-01-22 10:57:59 +00:00
James Henderson
7a925cd03f [NFC][llvm-readobj]Normalise --/- inconsistency in test options
llvm-svn: 351798
2019-01-22 10:57:21 +00:00
Simon Pilgrim
01208cb3d3 [X86] HADDPS/HADDPD scalar lowering was added at rL350421
llvm-svn: 351797
2019-01-22 10:49:41 +00:00
Chandler Carruth
3764443332 Revert r351778: IR: Add fp operations to atomicrmw
This broke the RISCV build, and even with that fixed, one of the RISCV
tests behaves surprisingly differently with asserts than without,
leaving there no clear test pattern to use. Generally it seems bad for
hte IR to differ substantially due to asserts (as in, an alloca is used
with asserts that isn't needed without!) and nothing I did simply would
fix it so I'm reverting back to green.

This also required reverting the RISCV build fix in r351782.

llvm-svn: 351796
2019-01-22 10:29:58 +00:00
James Henderson
23166c2b13 [llvm-symbolizer] Add support for --basenames/-s
This fixes https://bugs.llvm.org/show_bug.cgi?id=40068.

--basenames is a GNU addr2line switch which strips the directory names
from the file path in the output.

Reviewed by: ruiu

Differential Revision: https://reviews.llvm.org/D56919

llvm-svn: 351795
2019-01-22 10:24:32 +00:00
Max Kazantsev
88e4dee44f [NFC] Factor out some reusable logic
llvm-svn: 351794
2019-01-22 10:13:36 +00:00
Max Kazantsev
75db383edd [NFC] Add detector for guards expressed as branch by widenable conditions
This patch adds a function to detect guards expressed in explicit control
flow form as branch by `and` with widenable condition intrinsic call:

    %wc = call i1 @llvm.experimental.widenable.condition()
    %guard_cond = and i1, %some_cond, %wc
    br i1 %guard_cond, label %guarded, label %deopt

  deopt:
    <maybe some non-side-effecting instructions>
    deoptimize()

This form can be used as alternative to implicit control flow guard
representation expressed by `experimental_guard` intrinsic.

Differential Revision: https://reviews.llvm.org/D56074
Reviewed By: reames

llvm-svn: 351791
2019-01-22 09:36:22 +00:00
James Henderson
ac2839a57d [llvm-readelf]Revert --dyn-symbols behaviour to make it GNU compatible, and add new --hash-symbols switch for old behaviour
In r287786, the behaviour of --dyn-symbols in llvm-readelf (but not
llvm-readobj) was changed to print the dynamic symbols as derived from
the hash table, rather than to print the dynamic symbol table contents
directly. The original change was initially submitted without review,
and some comments were made on the commit mailing list implying that the
new behavious is GNU compatible. I argue that it is not:

  1) It does not include a null symbol.
  2) It prints the symbols based on an order derived from the hash
     table.
  3) It prints an extra column indicating which bucket it came from.
     This could break parsers that expect a fixed number of columns,
     with the first column being the symbol index.
  4) If the input happens to have both .hash and .gnu.hash section, it
     prints interpretations of them both, resulting in most symbols
     being printed twice.
  5) There is no way of just printing the raw dynamic symbol table,
     because --symbols also prints the static symbol table.

This patch reverts the --dyn-symbols behaviour back to its old behaviour
of just printing the contents of the dynamic symbol table, similar to
what is printed by --symbols. As the hashed interpretation is still
desirable to validate the hash table, it puts it under a new switch
"--hash-symbols". This is a no-op on all output forms except for GNU
output style for ELF. If there is no hash table, it does nothing,
unlike the previous behaviour which printed the raw dynamic symbol
table, since the raw dynsym is available under --dyn-symbols.

The yaml input for the test is based on that in
test/tools/llvm-readobj/demangle.test, but stripped down to the bare
minimum to provide a valid dynamic symbol.

Note: some LLD tests needed updating. I will commit a separate patch for
those.

Reviewed by: grimar, rupprecht

Differential Revision: https://reviews.llvm.org/D56910

llvm-svn: 351789
2019-01-22 09:35:35 +00:00
Vitaly Buka
316c1b9dc6 Revert "Remove static_assert(value == std::is_trivially_copyable<T>::value)"
Upgraded the bot as workaround.

This reverts commit r351784.

llvm-svn: 351786
2019-01-22 07:22:45 +00:00
Alex Bradbury
b6f0a606cb [RISCV][NFC] Add break to case statement in RISCVDAGToDAGISel::Select
The break isn't strictly needed yet as there is no subsequent entry in the
case. But adding to prevent mistakes further down the road.

llvm-svn: 351785
2019-01-22 07:22:00 +00:00
Vitaly Buka
c9bbd091e7 Remove static_assert(value == std::is_trivially_copyable<T>::value)
This fails to compile with clang ang libstdc++ 4.6

llvm-svn: 351784
2019-01-22 06:26:50 +00:00
Alex Bradbury
757193855d [RISCV] Fix build after r351778
Also add a comment to explain the expansion strategy for atomicrmw
{fadd,fsub}.

llvm-svn: 351782
2019-01-22 05:06:57 +00:00
Matt Arsenault
44582e29c8 IR: Add fp operations to atomicrmw
Add just fadd/fsub for now.

llvm-svn: 351778
2019-01-22 03:32:36 +00:00
Eli Friedman
d2ca493c0b [ARM] Combine ands+lsls to lsls+lsrs for Thumb1.
This patch may seem familiar... but my previous patch handled the
equivalent lsls+and, not this case.  Usually instcombine puts the
"and" after the shift, so this case doesn't come up. However, if the
shift comes out of a GEP, it won't get canonicalized by instcombine,
and DAGCombine doesn't have an equivalent transform.

This also modifies isDesirableToCommuteWithShift to suppress DAGCombine
transforms which would make the overall code worse.

I'm not really happy adding a bunch of code to handle this, but it would
probably be tricky to substantially improve the behavior of DAGCombine
here.

Differential Revision: https://reviews.llvm.org/D56032

llvm-svn: 351776
2019-01-22 01:51:37 +00:00
Philip Reames
22e59f8759 [CVP] Use LVI to constant fold deopt operands
Deopt operands are generally intended to record information about a site in code with minimal perturbation of the surrounding code. Idiomatically, they also tend to appear down rare paths. Putting these together, we have an obvious case for extending CVP w/deopt operand constant folding. Arguably, we should be doing this for all operands on all instructions, but that's definitely a much larger and risky change.

Differential Revision: https://reviews.llvm.org/D55678

llvm-svn: 351774
2019-01-22 01:34:33 +00:00
Eli Friedman
9361d42b5e [LangRef] Clarify semantics of volatile operations.
Specifically, clarify the following:

1. Volatile load and store may access addresses that are not memory.
2. Volatile load and store do not modify arbitrary memory.
3. Volatile load and store do not trap.

Prompted by recent volatile discussion on llvmdev.

Currently, there's sort of a split in the source code about whether
volatile operations are allowed to trap; this resolves that dispute in
favor of not allowing them to trap.

Differential Revision: https://reviews.llvm.org/D53184

llvm-svn: 351772
2019-01-22 00:42:20 +00:00
Matt Arsenault
57bff27c5d GlobalISel: Fix out of bounds crashes in verifier
llvm-svn: 351769
2019-01-22 00:29:37 +00:00
Eli Friedman
1d6f130191 [AArch64] Add patterns for zext/sext of shift amount.
Not sure this is the best fix, but it saves an instruction for certain
constructs involving variable shifts.

Differential Revision: https://reviews.llvm.org/D55572

llvm-svn: 351768
2019-01-22 00:21:35 +00:00
Matt Arsenault
7bd184dc17 AMDGPU/GlobalISel: Legalize more fp<->int conversions
llvm-svn: 351767
2019-01-22 00:20:17 +00:00
JF Bastien
dec3ae0936 Document toolchain update policy
Summary:
Capture the current agreed-upon toolchain update policy based on the following
discussions:

  - LLVM dev meeting 2018 BoF "Migrating to C++14, and beyond!"
    llvm.org/devmtg/2018-10/talk-abstracts.html#bof3
  - A Short Policy Proposal Regarding Host Compilers
    lists.llvm.org/pipermail/llvm-dev/2018-May/123238.html
  - Using C++14 code in LLVM (2018)
    lists.llvm.org/pipermail/llvm-dev/2018-May/123182.html
  - Using C++14 code in LLVM (2017)
    lists.llvm.org/pipermail/llvm-dev/2017-October/118673.html
  - Using C++14 code in LLVM (2016)
    lists.llvm.org/pipermail/llvm-dev/2016-October/105483.html
  - Document and Enforce new Host Compiler Policy
    llvm.org/D47073
  - Require GCC 5.1 and LLVM 3.5 at a minimum
    llvm.org/D46723

Subscribers: jkorous, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D56819

llvm-svn: 351765
2019-01-21 23:53:52 +00:00
Sanjay Patel
6499823747 [x86] add another test for xor with undefs; NFC
llvm-svn: 351764
2019-01-21 22:12:35 +00:00