Commit Graph

60793 Commits

Author SHA1 Message Date
Jim Grosbach
b6cc69c655 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit.
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419
2010-05-22 01:06:18 +00:00
Eric Christopher
189eca1291 This test is darwin only. Make it so(tm).
llvm-svn: 104418
2010-05-22 00:55:55 +00:00
Bob Wilson
b8ebb375b6 Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by
copying VFP subregs.  This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.

llvm-svn: 104415
2010-05-22 00:23:12 +00:00
Eric Christopher
165bcdf8a8 Add full bss data support for darwin tls variables.
llvm-svn: 104414
2010-05-22 00:10:22 +00:00
Devang Patel
e611375617 Collect variable information during endFunction() instead of beginFunction().
llvm-svn: 104412
2010-05-22 00:04:14 +00:00
Eric Christopher
6bd67791da Add a new section and accessor for TLS data.
llvm-svn: 104411
2010-05-22 00:00:58 +00:00
Bob Wilson
3994f42952 Clean up extra whitespace.
llvm-svn: 104410
2010-05-21 23:53:55 +00:00
Eric Christopher
8f296fd844 Make this LookAheadLimit, not the uninitialized LookAheadLeft.
Evan please verify!

llvm-svn: 104408
2010-05-21 23:40:03 +00:00
Chris Lattner
d5c391bba6 add a note
llvm-svn: 104404
2010-05-21 23:16:21 +00:00
Eric Christopher
d250f449cb Expand on comment.
llvm-svn: 104396
2010-05-21 23:03:53 +00:00
Kevin Enderby
1e4a4f5899 Added retl for 32-bit x86 and added retq for 64-bit x86.
llvm-svn: 104394
2010-05-21 23:01:38 +00:00
Eric Christopher
0df4e8b6a5 Fix comment and whitespace.
llvm-svn: 104392
2010-05-21 22:39:11 +00:00
Chris Lattner
d96398e6b4 expand on the llvm ir bitcode dox. Patch by Peter Housel!
llvm-svn: 104391
2010-05-21 22:20:54 +00:00
Evan Cheng
6a0784954a Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs.
llvm-svn: 104385
2010-05-21 21:22:19 +00:00
Eric Christopher
5fc9256574 Fix section attribute name.
llvm-svn: 104381
2010-05-21 21:08:52 +00:00
Bob Wilson
586811b244 Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements
so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.

llvm-svn: 104380
2010-05-21 21:05:32 +00:00
Evan Cheng
3c850aecf6 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.

llvm-svn: 104377
2010-05-21 20:53:24 +00:00
Jakob Stoklund Olesen
0f1087b284 Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction
reads or writes a register.

This takes partial redefines and undef uses into account.

Don't actually use it yet. That caused miscompiles.

llvm-svn: 104372
2010-05-21 20:02:01 +00:00
Devang Patel
e8f686625e Simplify
llvm-svn: 104338
2010-05-21 18:49:09 +00:00
Dale Johannesen
787ace240c Previous commit message should refer to 104308.
llvm-svn: 104337
2010-05-21 18:44:47 +00:00
Dale Johannesen
38109a0b04 Fix two bugs in 104348:
Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.

llvm-svn: 104336
2010-05-21 18:40:15 +00:00
Nathan Jeffords
28b485543b added an assertion to MCObjectWriter::WriteBytes to catch misuse of the ZeroFillSize parameter
If the size of the string is greater than the zero fill size, the function will attempt to write a very large string of zeros to the object file (~4GB on 32 bit platforms). This assertion will catch the scenario and crash the program before the write occurs.

llvm-svn: 104334
2010-05-21 18:23:56 +00:00
Chris Lattner
4c14d2c4a4 now that fp reg kill insertion stuff happens as a separate
pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.

The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes.  Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross.  It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).

Just do the scan on machine phis which is simpler, faster
and more correct.  This fixes PR6828.

llvm-svn: 104333
2010-05-21 18:17:54 +00:00
Chris Lattner
1e1fb36df4 Use less evil form of switch stmt.
llvm-svn: 104331
2010-05-21 18:02:42 +00:00
Chris Lattner
8c562574eb use continue to reduce nesting.
llvm-svn: 104330
2010-05-21 18:01:24 +00:00
Chris Lattner
2077759153 pull a nested loop of this pass out to its own function,
eliminating the gymnastics around the ContainsFPCode var.

llvm-svn: 104328
2010-05-21 17:57:03 +00:00
Chris Lattner
91ffa7a5bf modernize this pass a bit, fit in 80 columns.
llvm-svn: 104326
2010-05-21 17:49:07 +00:00
Chris Lattner
1794093960 constify accessor.
llvm-svn: 104325
2010-05-21 17:47:50 +00:00
Jakob Stoklund Olesen
a3cca88b41 Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read."
This reverts r104322. I think it was causing miscompilations.

llvm-svn: 104323
2010-05-21 17:36:32 +00:00
Jakob Stoklund Olesen
edf8136011 Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.
This correctly handles partial redefines and undef uses.

llvm-svn: 104322
2010-05-21 16:42:30 +00:00
Jakob Stoklund Olesen
924b84cf0f Teach VirtRegRewriter to handle spilling in instructions that have multiple
definitions of the virtual register.

This happens when spilling the registers produced by REG_SEQUENCE:

%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0

The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.

llvm-svn: 104321
2010-05-21 16:36:13 +00:00
Jakob Stoklund Olesen
6c22635216 If the first definition of a virtual register is a partial redef, add an
<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.

llvm-svn: 104320
2010-05-21 16:32:16 +00:00
Matt Fleming
5d40d53cab Currently, createMachOStreamer() is invoked directly in llvm-mc which
isn't ideal if we want to be able to use another object file format.

Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.

llvm-svn: 104318
2010-05-21 12:54:43 +00:00
Matt Fleming
6a5cb8c84a Split out the x86_32 an x86_64 ELF backends as they handle ELF
differently. This will make adding ELF support easier in the long run.

llvm-svn: 104317
2010-05-21 11:39:07 +00:00
Matt Fleming
0ca99c0262 Add support for parsing the ELF .type assembler directive.
llvm-svn: 104316
2010-05-21 11:36:59 +00:00
Lang Hames
b579a16d82 Removed scaleNumbering method declaration from LiveInterval (not defined, not used).
llvm-svn: 104311
2010-05-21 03:04:04 +00:00
Dale Johannesen
d0a5fdb32f Fix i64->f64 conversion, x86-64, -no-sse. A bit
tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.

llvm-svn: 104308
2010-05-21 00:52:33 +00:00
Evan Cheng
6397a77e16 Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
llvm-svn: 104307
2010-05-21 00:43:17 +00:00
Evan Cheng
1faccbd51a Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.
llvm-svn: 104306
2010-05-21 00:42:32 +00:00
Daniel Dunbar
8824824171 Remove dead option.
llvm-svn: 104303
2010-05-21 00:27:55 +00:00
Devang Patel
765d605934 Simplify.
llvm-svn: 104302
2010-05-21 00:10:20 +00:00
Daniel Dunbar
38460e2596 Fix __crashreport_info__ declaration.
llvm-svn: 104300
2010-05-20 23:50:19 +00:00
Evan Cheng
b5de7de4ce Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
llvm-svn: 104293
2010-05-20 23:26:43 +00:00
Dan Gohman
3274120902 DominatorTree.getNode can return null for unreachable blocks.
llvm-svn: 104290
2010-05-20 22:46:54 +00:00
Dan Gohman
b841e5c433 Minor code cleanups.
llvm-svn: 104287
2010-05-20 22:25:20 +00:00
Mikhail Glushenkov
5ead1e50a7 Print a space after the colon.
llvm-svn: 104279
2010-05-20 21:11:37 +00:00
Dan Gohman
06b35689ec Make Solve check its own post-condition, to reduce clutter in the
top-level LSRInstance logic.

llvm-svn: 104278
2010-05-20 20:59:23 +00:00
Dan Gohman
2702e3105d Add comments.
llvm-svn: 104276
2010-05-20 20:52:00 +00:00
Daniel Dunbar
3a0c98ca87 MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
llvm-svn: 104275
2010-05-20 20:36:29 +00:00
Devang Patel
3d4cd812aa Rename variable. add comment.
llvm-svn: 104274
2010-05-20 20:35:24 +00:00