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Author SHA1 Message Date
Warren Ristow
c0dcf88967 [LTO] Account for overriding lib calls via the alias attribute 
Given a library call that is represented as an llvm intrinsic call, but
later transformed to an actual call, if an overriding definition of that
library routine is provided indirectly via an alias, prevent LTO from
eliminating the definition.

This is a fix for PR38547.

Differential Revision: https://reviews.llvm.org/D52836

llvm-svn: 344198
 2018-10-10 22:54:31 +00:00
Nick Desaulniers
a22145584e [MC][ELF] compute entity size for explicit sections 
Summary:
Global variables might declare themselves to be in explicit sections.
Calculate the entity size always to prevent assembler warnings
"entity size for SHF_MERGE not specified" when sections are to be
marked merge-able.

Fixes PR31828.

Reviewers: rnk, echristo

Reviewed By: rnk

Subscribers: llvm-commits, pirama, srhines

Differential Revision: https://reviews.llvm.org/D53056

llvm-svn: 344197
 2018-10-10 22:52:32 +00:00
Craig Topper
36e607a7ef [X86] Prevent non-temporal loads from folding into instructions by blocking them in X86DAGToDAGISel::IsProfitableToFold rather than with a predicate. 
Remove tryFoldVecLoad since tryFoldLoad would call IsProfitableToFold and pick up the new check.

This saves about 5K out of ~600K on the generated isel table.

llvm-svn: 344189
 2018-10-10 21:48:34 +00:00
Chris Bieneman
e17657a758 [CMake] NFC. Updating documentation on options 
The Ninja pool options are only supported with the Ninja generator and
should be called out as such.

llvm-svn: 344188
 2018-10-10 21:36:12 +00:00
Richard Smith
a97728489f Support for remapping profile data when symbols change, for sample-based 
profiling.

Reviewers: davidxl, tejohnson, dlj, erik.pilkington

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D51248

llvm-svn: 344187
 2018-10-10 21:31:01 +00:00
George Burgess IV
37a10a0055 Replace most users of UnknownSize with LocationSize::unknown(); NFC 
Moving away from UnknownSize is part of the effort to migrate us to
LocationSizes (e.g. the cleanup promised in D44748).

This doesn't entirely remove all of the uses of UnknownSize; some uses
require tweaks to assume that UnknownSize isn't just some kind of int.
This patch is intended to just be a trivial replacement for all places
where LocationSize::unknown() will Just Work.

llvm-svn: 344186
 2018-10-10 21:28:44 +00:00
Armando Montanez
d6fc714ac1 Test commit: fix typo in comment 
llvm-svn: 344185
 2018-10-10 21:16:57 +00:00
Richard Smith
6fed20d0c4 Support for remapping profile data when symbols change, for 
instrumentation-based profiling.

Reviewers: davidxl, tejohnson, dlj, erik.pilkington

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D51247

llvm-svn: 344184
 2018-10-10 21:09:37 +00:00
James Y Knight
6f1053539e llvm-ar: Darwin archive format fixes. 
* Support writing the DARWIN64 symbol table format.

* In darwin archives, emit a symbol table whenever requested, even
  when there are no members, as the apple linker will abort if given
  an archive without a symbol table.

Added tests for same, and also simplified and moved the GNU 64-bit
symbol table test into archive-symtab.test.

llvm-svn: 344183
 2018-10-10 21:07:02 +00:00
Roman Lebedev
41a99d48b6 [NFC][X86][AArch64] extract-bits.ll: add tests with constants+storing results. 
As noted in https://reviews.llvm.org/D53080#inline-467678,
this *may* get pessimized by that diff.

llvm-svn: 344182
 2018-10-10 20:50:52 +00:00
Sanjay Patel
c7ffa003de [InstCombine] reverse 'trunc X to <N x i1>' canonicalization; 2nd try 
Re-trying r344082 because it unintentionally included extra diffs.

Original commit message:
icmp ne (and X, 1), 0 --> trunc X to N x i1

Ideally, we'd do the same for scalars, but there will likely be
regressions unless we add more trunc folds as we're doing here
for vectors.

The motivating vector case is from PR37549:
https://bugs.llvm.org/show_bug.cgi?id=37549

define <4 x float> @bitwise_select(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %w) {

  %c = fcmp ole <4 x float> %x, %y
  %s = sext <4 x i1> %c to <4 x i32>
  %s1 = shufflevector <4 x i32> %s, <4 x i32> undef, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
  %s2 = shufflevector <4 x i32> %s, <4 x i32> undef, <4 x i32> <i32 2, i32 2, i32 3, i32 3>
  %cond = or <4 x i32> %s1, %s2
  %condtr = trunc <4 x i32> %cond to <4 x i1>
  %r = select <4 x i1> %condtr, <4 x float> %z, <4 x float> %w
  ret <4 x float> %r

}

Here's a sampling of the vector codegen for that case using
mask+icmp (current behavior) vs. trunc (with this patch):

AVX before:

vcmpleps        %xmm1, %xmm0, %xmm0
vpermilps       $80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
vpermilps       $250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
vorps   %xmm0, %xmm1, %xmm0
vandps  LCPI0_0(%rip), %xmm0, %xmm0
vxorps  %xmm1, %xmm1, %xmm1
vpcmpeqd        %xmm1, %xmm0, %xmm0
vblendvps       %xmm0, %xmm3, %xmm2, %xmm0

AVX after:

vcmpleps        %xmm1, %xmm0, %xmm0
vpermilps       $80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
vpermilps       $250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
vorps   %xmm0, %xmm1, %xmm0
vblendvps       %xmm0, %xmm2, %xmm3, %xmm0

AVX512f before:

vcmpleps        %xmm1, %xmm0, %xmm0
vpermilps       $80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
vpermilps       $250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
vorps   %xmm0, %xmm1, %xmm0
vpbroadcastd    LCPI0_0(%rip), %xmm1 ## xmm1 = [1,1,1,1]
vptestnmd       %zmm1, %zmm0, %k1
vblendmps       %zmm3, %zmm2, %zmm0 {%k1}

AVX512f after:

vcmpleps        %xmm1, %xmm0, %xmm0
vpermilps       $80, %xmm0, %xmm1 ## xmm1 = xmm0[0,0,1,1]
vpermilps       $250, %xmm0, %xmm0 ## xmm0 = xmm0[2,2,3,3]
vorps   %xmm0, %xmm1, %xmm0
vpslld  $31, %xmm0, %xmm0
vptestmd        %zmm0, %zmm0, %k1
vblendmps       %zmm2, %zmm3, %zmm0 {%k1}

AArch64 before:

fcmge   v0.4s, v1.4s, v0.4s
zip1    v1.4s, v0.4s, v0.4s
zip2    v0.4s, v0.4s, v0.4s
orr     v0.16b, v1.16b, v0.16b
movi    v1.4s, #1
and     v0.16b, v0.16b, v1.16b
cmeq    v0.4s, v0.4s, #0
bsl     v0.16b, v3.16b, v2.16b

AArch64 after:

fcmge   v0.4s, v1.4s, v0.4s
zip1    v1.4s, v0.4s, v0.4s
zip2    v0.4s, v0.4s, v0.4s
orr     v0.16b, v1.16b, v0.16b
bsl     v0.16b, v2.16b, v3.16b

PowerPC-le before:

xvcmpgesp 34, 35, 34
vspltisw 0, 1
vmrglw 3, 2, 2
vmrghw 2, 2, 2
xxlor 0, 35, 34
xxlxor 35, 35, 35
xxland 34, 0, 32
vcmpequw 2, 2, 3
xxsel 34, 36, 37, 34

PowerPC-le after:

xvcmpgesp 34, 35, 34
vmrglw 3, 2, 2
vmrghw 2, 2, 2
xxlor 0, 35, 34
xxsel 34, 37, 36, 0

Differential Revision: https://reviews.llvm.org/D52747

llvm-svn: 344181
 2018-10-10 20:47:46 +00:00
Thomas Lively
a446ed9fc2 [WebAssembly][NFC] Remove repetition of Defs = [ARGUMENTS] 
Summary:
By moving that line into the `I` multiclass.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D53093

llvm-svn: 344180
 2018-10-10 20:40:54 +00:00
Roman Lebedev
3838997409 [X86] Move X86DAGToDAGISel::matchBEXTRFromAnd() into X86ISelLowering 
Summary:
As discussed in [[ https://bugs.llvm.org/show_bug.cgi?id=38938 | PR38938 ]],
we fail to emit `BEXTR` if the mask is shifted.
We can't deal with that in `X86DAGToDAGISel` `before the address mode for the inc is selected`,
and we can't really do it in the normal DAGCombine, because we don't have generic `ISD::BitFieldExtract` node,
and if we simply turn the shifted mask into a normal mask + shift-left, it will be folded back.
So it would seem X86ISelLowering is the place to handle this.

This patch only moves the matchBEXTRFromAnd()
from X86DAGToDAGISel to X86ISelLowering.
It does not add support for the 'shifted mask' pattern.

Reviewers: RKSimon, craig.topper, spatel

Reviewed By: RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D52426

llvm-svn: 344179
 2018-10-10 20:40:12 +00:00
Sanjay Patel
8a4850aac2 revert r344082: [InstCombine] reverse 'trunc X to <N x i1>' canonicalization 
This commit accidentally included the diffs from D53057.

llvm-svn: 344178
 2018-10-10 20:39:39 +00:00
David Bolvansky
5db2d20226 [DwarfVerifier] Fixed -Wimplicit-fallthrough warning 
Reviewers: JDevlieghere, RKSimon

Reviewed By: JDevlieghere

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D52963

llvm-svn: 344176
 2018-10-10 20:10:37 +00:00
Thomas Lively
7a1082009c [WebAssembly][NFC] Use vnot patfrag to simplify v128.not 
Reviewers: aheejin, dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D53097

llvm-svn: 344175
 2018-10-10 19:09:16 +00:00
Renato Golin
9ed28a9f25 [LV] Add a new reduction pattern match 
Adding a new reduction pattern match for vectorizing code similar to TSVC s3111:

for (int i = 0; i < N; i++)
  if (a[i] > b)
    sum += a[i];

This patch adds support for fadd, fsub and fmull, as well as multiple
branches and different (but compatible) instructions (ex. add+sub) in
different branches.

I have forwarded to trunk, added fsub and fmul functionality and
additional tests, but the credit goes to Takahiro, who did most of the
actual work.

Differential Revision: https://reviews.llvm.org/D49168

Patch by Takahiro Miyoshi <takahiro.miyoshi@linaro.org>.

llvm-svn: 344172
 2018-10-10 18:49:49 +00:00
Francis Visoiu Mistrih
254ec48163 Reland: [OptRemarks] Add library for parsing optimization remarks 
Add a library that parses optimization remarks (currently YAML, so based
on the YAMLParser).

The goal is to be able to provide tools a remark parser that is not
completely dependent on YAML, in case we decide to change the format
later.

It exposes a C API which takes a handler that is called with the remark
structure.

It adds a libLLVMOptRemark.a static library, and it's used in-tree by
the llvm-opt-report tool (from which the parser has been mostly moved
out).

Differential Revision: https://reviews.llvm.org/D52776

Fixed the tests by removing the usage of C++11 strings, which seems not
to be supported by gcc 4.8.4 if they're used as a macro argument.

llvm-svn: 344171
 2018-10-10 18:43:42 +00:00
Scott Linder
3aeeb26969 [Support] Remove redundant qualifiers in YAMLTraits (NFC) 
llvm-svn: 344166
 2018-10-10 18:14:02 +00:00
Francis Visoiu Mistrih
ed7ac50b0a Revert "[OptRemarks] Add library for parsing optimization remarks" 
This reverts commit 1cc98e6672b6319fdb00b70dd4474aabdadbe193.

Seems to break bots: http://lab.llvm.org:8011/builders/clang-x86_64-linux-abi-test/builds/33398/steps/build-unified-tree/logs/stdio

llvm-svn: 344164
 2018-10-10 18:07:44 +00:00
Volkan Keles
a590401dc7 [GlobalISel] Fix the artifact combiner to fold G_IMPLICIT_DEF properly 
Summary:
GlobalISel generates incorrect code because the legalizer artifact
combiner assumes `G_[SZ]EXT (G_IMPLICIT_DEF)` is equivalent to
`G_IMPLICIT_DEF `.

Replace `G_[SZ]EXT (G_IMPLICIT_DEF)` with 0 because the top bits
will be 0 for G_ZEXT and 0/1 for the G_SEXT.

Reviewers: aditya_nandakumar, dsanders, aemerson, javed.absar

Reviewed By: aditya_nandakumar

Subscribers: rovka, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D52996

llvm-svn: 344163
 2018-10-10 18:01:48 +00:00
Francis Visoiu Mistrih
747fb205d0 [OptRemarks] Add library for parsing optimization remarks 
Add a library that parses optimization remarks (currently YAML, so based
on the YAMLParser).

The goal is to be able to provide tools a remark parser that is not
completely dependent on YAML, in case we decide to change the format
later.

It exposes a C API which takes a handler that is called with the remark
structure.

It adds a libLLVMOptRemark.a static library, and it's used in-tree by
the llvm-opt-report tool (from which the parser has been mostly moved
out).

Differential Revision: https://reviews.llvm.org/D52776

llvm-svn: 344162
 2018-10-10 17:58:09 +00:00
Renato Golin
0c3b7ee1d7 [VPlan] Fix CondBit quoting in dumpBasicBlock 
Quotes were being printed for VPInstructions but not the rest.

llvm-svn: 344161
 2018-10-10 17:55:21 +00:00
Craig Topper
46e8eba222 Change the timestamp of llvmcache-foo file to meet the thinLTO prune policy 
The case will randomly fail if we test it with command "
while llvm-lit test/tools/gold/X86/cache.ll ; do true; done". It is because the llvmcache-foo file is younger than llvmcache-349F039B8EB076D412007D82778442BED3148C4E and llvmcache-A8107945C65C2B2BBEE8E61AA604C311D60D58D6. But due to timestamp precision reason their timestamp is the same. Given the same timestamp, the file prune policy is to remove bigger size file first, so mostly foo file is removed for its bigger size. And the files size is under threshold after deleting foo file. That's what test case expect.

However sometimes, the precision is enough to measure that timestamp of llvmcache-349F039B8EB076D412007D82778442BED3148C4E and llvmcache-A8107945C65C2B2BBEE8E61AA604C311D60D58D6 are smaller than foo, so llvmcache-349F039B8EB076D412007D82778442BED3148C4E and llvmcache-A8107945C65C2B2BBEE8E61AA604C311D60D58D6 are deleted first. Since the files size is still above the file size threshold after deleting the 2 files, the foo file is also deleted. And then the test case fails, because it expect only one file should be deleted instead of 3.

The fix is to change the timestamp of llvmcache-foo file to meet the thinLTO prune policy.

Patch by Luo Yuanke.

Differential Revision: https://reviews.llvm.org/D52452

llvm-svn: 344158
 2018-10-10 17:37:32 +00:00
Scott Linder
b17ffe372b Relax trivial cast requirements in CallPromotionUtils 
Differential Revision: https://reviews.llvm.org/D52792

llvm-svn: 344153
 2018-10-10 16:35:47 +00:00
Guillaume Chatelet
876b0e5411 [llvm-exegesis] Fix always true assert 
llvm-svn: 344151
 2018-10-10 16:16:43 +00:00
Andrea Di Biagio
5b15ce4ae3 [llvm-mca] Minor refactoring in preparation for a patch that will fully fix PR36671. NFCI 
llvm-svn: 344149
 2018-10-10 16:08:02 +00:00
Guillaume Chatelet
ef3efb6ae2 [llvm-exegesis][NFC] Pass Instruction instead of bare Opcode 
llvm-svn: 344145
 2018-10-10 14:57:32 +00:00
Andrea Di Biagio
3cdb14d5b7 [llvm-mca][BtVer2] Add two more move-elimination tests. NFC 
These should test all the optimizable moves on Jaguar.
A follow-up patch will teach how to recognize these optimizable register moves.

llvm-svn: 344144
 2018-10-10 14:46:54 +00:00
Guillaume Chatelet
f23d9f61cd [llvm-exegesis][NFC] Code simplification 
Summary: Simplify code by having LLVMState hold the RegisterAliasingTrackerCache.

Reviewers: courbet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D53078

llvm-svn: 344143
 2018-10-10 14:22:48 +00:00
Nirav Dave
54ff49aca5 [DAGCombine] Improve Load-Store Forwarding 
Summary:
Extend analysis forwarding loads from preceeding stores to work with
extended loads and truncated stores to the same address so long as the
load is fully subsumed by the store.

Hexagon's swp-epilog-phis.ll and swp-memrefs-epilog1.ll test are
deleted as they've no longer seem to be relevant.

Reviewers: RKSimon, rnk, kparzysz, javed.absar

Subscribers: sdardis, nemanjai, hiraditya, atanasyan, llvm-commits

Differential Revision: https://reviews.llvm.org/D49200

llvm-svn: 344142
 2018-10-10 14:15:52 +00:00
Sanjay Patel
3581af214d [x86] allow single source horizontal op matching (PR39195) 
This is intended to restore horizontal codegen to what it looked like before IR demanded elements improved in:
rL343727

As noted in PR39195:
https://bugs.llvm.org/show_bug.cgi?id=39195
...horizontal ops can be worse for performance than a shuffle+regular binop, so I've added a TODO. Ideally, we'd 
solve that in a machine instruction pass, but a quicker solution will be adding a 'HasFastHorizontalOp' feature
bit to deal with it here in the DAG.

Differential Revision: https://reviews.llvm.org/D52997

llvm-svn: 344141
 2018-10-10 13:39:59 +00:00
Jonas Devlieghere
702beb445a Lift VFS from clang to llvm (NFC) 
This patch moves the virtual file system form clang to llvm so it can be
used by more projects.

Concretely the patch:
 - Moves VirtualFileSystem.{h|cpp} from clang/Basic to llvm/Support.
 - Moves the corresponding unit test from clang to llvm.
 - Moves the vfs namespace from clang::vfs to llvm::vfs.
 - Formats the lines affected by this change, mostly this is the result of
   the added llvm namespace.

RFC on the mailing list:
http://lists.llvm.org/pipermail/llvm-dev/2018-October/126657.html

Differential revision: https://reviews.llvm.org/D52783

llvm-svn: 344140
 2018-10-10 13:27:25 +00:00
John Brawn
9b7ae2203d [llvm-exegesis] Fix function return generation so it doesn't return register 0 
When fillMachineFunction generates a return on targets without a return opcode
(such as AArch64) it should pass an empty set of registers as the return
registers, not 0 which means register number zero.

Differential Revision: https://reviews.llvm.org/D53074

llvm-svn: 344139
 2018-10-10 13:03:23 +00:00
Simon Pilgrim
68d0118d67 [TargetLowering] SimplifyDemandedBits - rename demanded mask args. NFCI. 
Help stop bugs like rL343935 by making the 'original' DemandedBits arg more obviously not the mask that is actually used.

llvm-svn: 344138
 2018-10-10 13:00:49 +00:00
Guillaume Chatelet
f1de53d381 [llvm-exegesis][NFC] Fix typo 
Reviewers: courbet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D53075

llvm-svn: 344137
 2018-10-10 12:58:40 +00:00
Simon Pilgrim
65c77c706e [TargetLowering] SimplifyDemandedBits - pull out repeated getOperands. NFCI. 
Part of a minor cleanup to make all the switch statements more consistent prior to improving vector support.

llvm-svn: 344136
 2018-10-10 12:32:13 +00:00
Carlos Alberto Enciso
b4aff05571 Revert "[DebugInfo][Dexter] Unreachable line stepped onto after SimplifyCFG." 
This reverts commit r344120.

It was causing buildbot failures.

llvm-svn: 344135
 2018-10-10 12:09:34 +00:00
Valery Pykhtin
e0c17ed278 [TableGen] fix assert in !cast when used out of definition in a multiclass 
Differential Revision: https://reviews.llvm.org/D53068

llvm-svn: 344134
 2018-10-10 10:52:57 +00:00
Simon Pilgrim
ac55dda5e5 [TargetLowering] Add root node back to work list after successful SimplifyDemandedBits/SimplifyDemandedVectorElts 
Similar to what already happens in the DAGCombiner wrappers, this patch adds the root nodes back onto the worklist if the DCI wrappers' SimplifyDemandedBits/SimplifyDemandedVectorElts were successful.

Differential Revision: https://reviews.llvm.org/D53026

llvm-svn: 344132
 2018-10-10 10:44:15 +00:00
Guillaume Chatelet
7abf6cf90b [llvm-exegesis] Fix broken build. 
llvm-svn: 344131
 2018-10-10 10:09:42 +00:00
Guillaume Chatelet
b750e3e2f5 [llvm-exegesis][NFC] Simplify code now that Instruction has more semantic 
Reviewers: courbet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D53065

llvm-svn: 344130
 2018-10-10 09:45:17 +00:00
Jonas Paulsson
44725c7a8b [SystemZ] Temporarily disable high VFs with integer div/rem. 
Until mischeduler is clever enough to avoid spilling in a vectorized loop
with many (scalar) DLRs it is better to avoid high vectorization factors (8
and above).

llvm-svn: 344129
 2018-10-10 09:30:29 +00:00
Neil Henning
bf74af9c28 Fix an ordering bug in the scalarizer. 
I've added a new test case that causes the scalarizer to try and use
dead-and-erased values - caused by the basic blocks not being in
domination order within the function. To fix this, instead of iterating
through the blocks in function order, I walk them in reverse post order.

Differential Revision: https://reviews.llvm.org/D52540

llvm-svn: 344128
 2018-10-10 09:27:45 +00:00
Guillaume Chatelet
a12bd277bd [llvm-exegesis] Remove unused variable, add more semantic to Instruction. 
Reviewers: courbet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D53062

llvm-svn: 344127
 2018-10-10 09:12:36 +00:00
Carlos Alberto Enciso
e0f56f3bb6 [DebugInfo][Dexter] Unreachable line stepped onto after SimplifyCFG. 
When SimplifyCFG changes the PHI node into a select instruction, the debug line records becomes ambiguous. It causes the debugger to display unreachable source lines. 

Differential Revision: https://reviews.llvm.org/D52887

llvm-svn: 344120
 2018-10-10 08:29:55 +00:00
Craig Topper
90a3c6f55a [X86] Remove FeatureRTM from Skylake processor list 
Summary:
There are a LOT of Skylakes and later without TSX-NI. Examples:
- SKL: https://ark.intel.com/products/136863/Intel-Core-i3-8121U-Processor-4M-Cache-up-to-3-20-GHz-
- KBL: https://ark.intel.com/products/97540/Intel-Core-i7-7560U-Processor-4M-Cache-up-to-3-80-GHz-
- KBL-R: https://ark.intel.com/products/149091/Intel-Core-i7-8565U-Processor-8M-Cache-up-to-4-60-GHz-
- CNL: https://ark.intel.com/products/136863/Intel-Core-i3-8121U-Processor-4M-Cache-up-to-3_20-GHz

This feature seems to be present only on high-end desktop and server
chips (I can't find any SKX without). This commit leaves it disabled
for all processors, but can be re-enabled for specific builds with
-mrtm.

Patch by Thiago Macieira

Reviewers: erichkeane, craig.topper

Reviewed By: craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D53041

llvm-svn: 344116
 2018-10-10 07:43:35 +00:00
Jonas Paulsson
1ed2d5f64f [SystemZ] Take better care when computing needed vector registers in TTI. 
A new function getNumVectorRegs() is better to use for the number of needed
vector registers instead of getNumberOfParts(). This is to make sure that the
number of vector registers (and typically operations) required for a vector
type is accurate.

getNumberOfParts() which was previously used works by splitting the vector
type until it is legal gives incorrect results for types with a non
power of two number of elements (rare).

A new static function getScalarSizeInBits() that also checks for a pointer
type and returns 64U for it since otherwise it gets a value of 0). Used in a
few places where Ty may be pointer.

Review: Ulrich Weigand
llvm-svn: 344115
 2018-10-10 07:36:27 +00:00
George Burgess IV
e908528176 [Analysis] Make LocationSizes carry an 'imprecise' bit 
There are places where we need to merge multiple LocationSizes of
different sizes into one, and get a sensible result.

There are other places where we want to optimize aggressively based on
the value of a LocationSizes (e.g. how can a store of four bytes be to
an area of storage that's only two bytes large?)

This patch makes LocationSize hold an 'imprecise' bit to note whether
the LocationSize can be treated as an upper-bound and lower-bound for
the size of a location, or just an upper-bound.

This concludes the series of patches leading up to this. The most recent
of which is r344108.

Fixes PR36228.

Differential Revision: https://reviews.llvm.org/D44748

llvm-svn: 344114
 2018-10-10 06:39:40 +00:00
Max Kazantsev
59781375d4 [NFC] Make a variable const 
llvm-svn: 344113
 2018-10-10 04:19:38 +00:00