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c470ba9937
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205 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes
c470ba9937 Add AVX SSE2 integer packed compare instructions 
llvm-svn: 107240
 2010-06-30 02:21:09 +00:00
Bruno Cardoso Lopes
cfbebb3921 - Add AVX form of all SSE2 logical instructions 
- Add VEX encoding bits to x86 MRM0r-MRM7r

llvm-svn: 107238
 2010-06-30 01:58:37 +00:00
Bruno Cardoso Lopes
2439877e05 Add *several* AVX integer packed binop instructions 
llvm-svn: 107225
 2010-06-29 23:47:49 +00:00
Bruno Cardoso Lopes
e1b05180de Add AVX ld/st XCSR register. 
Add VEX encoding bits for MRMXm x86 form

llvm-svn: 107204
 2010-06-29 20:35:48 +00:00
Bruno Cardoso Lopes
e60533aa42 Add AVX non-temporal stores 
llvm-svn: 107178
 2010-06-29 18:22:01 +00:00
Bruno Cardoso Lopes
2dca1dd168 Add sqrt, rsqrt and rcp AVX instructions 
llvm-svn: 107166
 2010-06-29 17:26:30 +00:00
Bruno Cardoso Lopes
e4809f15bf Described the missing AVX forms of SSE2 convert instructions 
llvm-svn: 107108
 2010-06-29 00:36:02 +00:00
Bruno Cardoso Lopes
277fcdf1c1 Add AVX convert CVTSS2SI{rr,rm} and CVTDQ2PS{rr,rm} instructions 
llvm-svn: 106917
 2010-06-25 23:47:23 +00:00
Bruno Cardoso Lopes
45109dd6c1 Reapply r106896: 
Add several AVX MOV flavors
Support VEX encoding for MRMDestReg

llvm-svn: 106912
 2010-06-25 23:33:42 +00:00
Bruno Cardoso Lopes
cc4c01f859 revert this now, it's using avx instead of sse :) 
llvm-svn: 106906
 2010-06-25 23:04:29 +00:00
Bruno Cardoso Lopes
04ac570a8d Add several AVX MOV flavors 
Support VEX encoding for MRMDestReg

llvm-svn: 106896
 2010-06-25 22:27:51 +00:00
Bruno Cardoso Lopes
bde2881855 Add some AVX convert instructions 
llvm-svn: 106815
 2010-06-25 00:39:30 +00:00
Bruno Cardoso Lopes
11a236d970 - Add AVX COMI{SS,SD}{rr,rm} and UCOMI{SS,SD}{rr,rm}. 
- Fix a small VEX encoding issue.
- Move compare instructions to their appropriate place.

llvm-svn: 106787
 2010-06-24 20:48:23 +00:00
Chris Lattner
606dc0529b Teach the x86 mc assembler that %dr6 = %db6, this implements 
rdar://8013734

llvm-svn: 106725
 2010-06-24 07:29:18 +00:00
Bruno Cardoso Lopes
633f345ba9 Add AVX CMP{SS,SD}{rr,rm} instructions and encoding testcases 
llvm-svn: 106705
 2010-06-24 00:32:06 +00:00
Bruno Cardoso Lopes
b1bfbacead Add AVX MOVMSK{PS,PD}rr instructions 
llvm-svn: 106683
 2010-06-23 21:30:27 +00:00
Bruno Cardoso Lopes
c6ac26123d Add tests for different AVX cmp opcodes, also teach the x86 asm parser to understand the vcmp instruction 
llvm-svn: 106678
 2010-06-23 21:10:57 +00:00
Bruno Cardoso Lopes
8cfdcf7691 Add AVX SHUF{PS,PD}{rr,rm} instructions 
llvm-svn: 106672
 2010-06-23 20:07:15 +00:00
Nico Weber
04606293a5 Add support for the x86 instructions "pusha" and "popa". 
llvm-svn: 106671
 2010-06-23 20:00:58 +00:00
Bruno Cardoso Lopes
db9027d95d Add AVX compare packed instructions 
llvm-svn: 106600
 2010-06-22 23:37:59 +00:00
Bruno Cardoso Lopes
424b206ad4 Reapply support for AVX unpack and interleave instructions, with 
testcases this time.

llvm-svn: 106593
 2010-06-22 23:02:38 +00:00
Bruno Cardoso Lopes
93ec8dcd01 Add AVX MOV{SS,SD}{rr,rm} instructions 
llvm-svn: 106588
 2010-06-22 22:38:56 +00:00
Eric Christopher
48c062d65b Move a 64-bit test to the 64-bit file. Fixes an llvm-mc assertion 
during test runs.

llvm-svn: 106577
 2010-06-22 21:11:51 +00:00
Bruno Cardoso Lopes
c41dfa7cad Refactor aliased packed logical instructions, also add 
AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.

llvm-svn: 106374
 2010-06-19 02:44:01 +00:00
Bruno Cardoso Lopes
d6d12f37c6 Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions 
llvm-svn: 106366
 2010-06-19 00:37:31 +00:00
Chris Lattner
ed5a217085 fix rdar://7873482 by teaching the instruction encoder to emit 
segment prefixes.  Daniel wrote most of this patch.

llvm-svn: 106364
 2010-06-19 00:34:00 +00:00
Bruno Cardoso Lopes
ea44492375 Add {mix,max}{ss,sd}{rr,rm} AVX forms. 
llvm-svn: 106264
 2010-06-18 01:12:56 +00:00
Bruno Cardoso Lopes
7e28e6925c More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rm 
llvm-svn: 105870
 2010-06-12 01:53:48 +00:00
Bruno Cardoso Lopes
df3435eb33 More AVX: {ADD,SUB,MUL,DIV}{PD,PS}rr 
Handle OpSize TSFlag for AVX

llvm-svn: 105869
 2010-06-12 01:23:26 +00:00
Bruno Cardoso Lopes
69141fd639 More AVX instructions ({ADD,SUB,MUL,DIV}{SS,SD}rm) 
Introduce the VEX_X field

llvm-svn: 105859
 2010-06-11 23:50:47 +00:00
Bruno Cardoso Lopes
255fda615d Reapply r105521, this time appending "LLU" to 64 bit 
immediates to avoid breaking the build.

llvm-svn: 105652
 2010-06-08 22:51:23 +00:00
Chris Lattner
33d0622cdc revert r105521, which is breaking the buildbots with stuff like this: 
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type

llvm-svn: 105524
 2010-06-05 04:17:30 +00:00
Bruno Cardoso Lopes
b05131d907 Initial AVX support for some instructions. No patterns matched 
yet, only assembly encoding support.

llvm-svn: 105521
 2010-06-05 03:53:24 +00:00
Kevin Enderby
fbd982b12f MC/X86: Add alias for movzx. 
llvm-svn: 105005
 2010-05-28 21:20:21 +00:00
Kevin Enderby
922954fe32 MC/X86: Add alias for fwait. 
llvm-svn: 105001
 2010-05-28 20:59:10 +00:00
Kevin Enderby
3db5d4603e Fix the use of x86 control and debug registers so that the assertion failure in 
getX86RegNum() does not happen.  Patch by Shantonu Sen!

llvm-svn: 104994
 2010-05-28 19:01:27 +00:00
Kevin Enderby
7eae1aeb51 Fix the x86 move to/from segment register instructions. 
llvm-svn: 104731
 2010-05-26 20:10:45 +00:00
Kevin Enderby
392dd2b35f Changed the encoding of X86 floating point stack operations where both operands 
are st(0).  These can be encoded using an opcode for storing in st(0) or using
an opcode for storing in st(i), where i can also be 0.  To allow testing with
the darwin assembler and get a matching binary the opcode for storing in st(0)
is now used.  To do this the same logical trick is use from the darwin assembler
in converting things like this:

fmul %st(0), %st

into this:

fmul %st(0)

by looking for the second operand being X86::ST0 for specific floating point
mnemonics then removing the second X86::ST0 operand.  This also has the add
benefit to allow things like:

fmul %st(1), %st

that llvm-mc did not assemble.

llvm-svn: 104634
 2010-05-25 20:52:34 +00:00
Daniel Dunbar
15b9844a05 MC/X86: Add a hack to allow recognizing 'cmpltps' and friends. 
llvm-svn: 104626
 2010-05-25 19:49:32 +00:00
Daniel Dunbar
28018eed17 MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}. 
llvm-svn: 104622
 2010-05-25 18:40:53 +00:00
Kevin Enderby
e336aaa32b The BT64ri8 record in X86Instr64bit.td was missing a REX_W which is required 
for the 64-bit version of the Bit Test instruction.

llvm-svn: 104621
 2010-05-25 18:16:58 +00:00
Eric Christopher
627e887b3d Make sure aeskeygenassist uses an unsigned immediate field. 
Fixes rdar://8017638

llvm-svn: 104617
 2010-05-25 17:33:22 +00:00
Dan Gohman
824858ebb0 Fix an mmx movd encoding. 
llvm-svn: 104552
 2010-05-24 20:51:08 +00:00
Kevin Enderby
a911679139 MC/X86: Add aliases for CMOVcc variants. 
llvm-svn: 104549
 2010-05-24 20:32:23 +00:00
Daniel Dunbar
50265dbaf0 MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: 
addw $0xFFFF, %ax
should match the same as
  addw $-1, %ax
but we used to match it to the longer encoding.

llvm-svn: 104453
 2010-05-22 21:02:33 +00:00
Daniel Dunbar
7c60f7caa2 MC/X86: Add alias for setz, setnz, jz, jnz. 
llvm-svn: 104435
 2010-05-22 06:37:33 +00:00
Kevin Enderby
1e4a4f5899 Added retl for 32-bit x86 and added retq for 64-bit x86. 
llvm-svn: 104394
 2010-05-21 23:01:38 +00:00
Daniel Dunbar
3a0c98ca87 MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq. 
llvm-svn: 104275
 2010-05-20 20:36:29 +00:00
Dan Gohman
c8b4555a94 Fix assembly parsing and encoding of the pushf and popf family of 
instructions.

llvm-svn: 104231
 2010-05-20 16:16:00 +00:00
Dan Gohman
52dcd5fb9a Define the x86 pause instruction. 
llvm-svn: 104204
 2010-05-20 01:35:50 +00:00