of int initializers), change some methods to be static functions,
use raw_ostream::write_hex instead of a smallstring dance with
APValue::toStringUnsigned(S, 16).
llvm-svn: 93991
I really want clients of the streamer to be able to say "emit this
64-bit integer" and have it get broken down right by the streamer.
I may change this in the future, we'll see how it works out.
llvm-svn: 93934
form of an expression. This is the expression without the
post-increment adjustment made, which is useful in determining
which registers will be used by the expansion.
llvm-svn: 93921
function can support dynamic stack realignment. That's a much easier question
to answer at instruction selection stage than whether the function actually
will have dynamic alignment prologue. This allows the removal of the
stack alignment heuristic pass, and improves code quality for cases where
the heuristic would result in dynamic alignment code being generated when
it was not strictly necessary.
llvm-svn: 93885
doing global variable classification anymore) and hookized, sink almost
all target targets global variable emission code into AsmPrinter and out
of each target.
Some notes:
1. PIC16 does completely custom and crazy stuff, so it is not changed.
2. XCore has some custom handling for extra directives. I'll look at it next.
3. This switches linux/ppc to use .globl instead of .global. If .globl is
actually wrong, let me know and I'll fix it.
4. This makes linux/ppc get a lot of random cases right which were obviously
wrong before, it is probably now a bit healthier.
5. Blackfin will probably start getting .comm and other things that it didn't
before. If this is undesirable, it should explicitly opt out of these
things by clearing the relevant fields of MCAsmInfo.
This leads to a nice diffstat:
14 files changed, 127 insertions(+), 830 deletions(-)
llvm-svn: 93858
This makes a similar code dead in all the other targets, I'll clean it up
in a bit.
This also moves handling of lcomm up before acquisition of a section,
since lcomm never needs a section.
llvm-svn: 93851
simplify and commonize some of the asmprinter logic for globals.
This also avoids printing the MCSection for .zerofill, which broke
the llvm-gcc build.
llvm-svn: 93843
1. TargetLoweringObjectFileMachO should decide if something
goes in zerofill instead of having every target do it.
2. TargetLoweringObjectFileMachO should assign said symbols to
the right MCSection, the asmprinters should just emit to the
right section.
3. Since all zerofill stuff goes through mcstreamer anymore,
MAI can have a bool "haszerofill" instead of having the textual
directive to emit.
llvm-svn: 93838
idea, but unfortunately necessary.
- Default to using 4-bytes for the LSDA pointer encoding to agree with the
encoded value in the CIE.
llvm-svn: 93753
to Mangler. Now MCSymbol just decides whether to slap quotes around
a symbol when printing it.
This also fixes some weirdness where two MCSymbols could be created
for the same symbol, if one needed to be mangled and got mangled to
the other one.
llvm-svn: 93690
Mangler::getMangledName is used from lto
Mangler::setUseQuotes is used in the AsmPrinter
Mangler::setSymbolsCanStartWithDigit is used in the AsmPrinter
llvm-svn: 93652
Nodes that had children outside of the post dominator tree (infinite loops)
where removed from the post dominator tree. This seems to be wrong. Leave them
in the tree.
llvm-svn: 93633
Move the DOTGraphTraits dotty printer/viewer templates, that were developed for
the dominance tree into their own header file. This will allow reuse in future
passes.
llvm-svn: 93632
The CIE says that the LSDA point in the FDE section is an "sdata4". That's fine,
but we need it to actually be 4-bytes in the FDE for some platforms. Allow
individual platforms to decide for themselves.
llvm-svn: 93616
target-dependent memory address representation in it.
Restore X86 printing of DEBUG_VALUE; lowering is
done in X86RegisterInfo using the normal algorithm.
llvm-svn: 93565
print/dumpWithDepth allows one to dump a DAG up to N levels deep.
dump/printWithFullDepth prints the whole DAG, subject to a depth limit
on 100 in the default case (to prevent infinite recursion).
Have CannotYetSelect to a dumpWithFullDepth so it is clearer exactly
what the non-matching DAG looks like.
llvm-svn: 93538
This patch also cleans up code that expects there to be a bitcast in the first argument and testcases that call llvm.dbg.declare.
It also strips old llvm.dbg.declare intrinsics that did not pass metadata as the first argument.
llvm-svn: 93531
Remove most of old Mach-O Writer support, it has been replaced by MCMachOStreamer
Further refactoring to completely remove MachOWriter and drive the object file
writer with the AsmPrinter MCInst/MCSection logic is forthcoming.
llvm-svn: 93527
the new ParseInstruction method just parses and returns a list of
target operands. A new MatchInstruction interface is used to
turn the operand list into an MCInst.
This requires new/deleting all the operands, but it also gives
targets the ability to use polymorphic operands if they want to.
llvm-svn: 93469
and use them to avoid a copy of a string in getNameWithPrefix in
the common case. It seems like Value::setName and other places
should use this as well?
llvm-svn: 93301
that I want to completely eliminate. Add fixme's so I remember this
in the future, and add the missing helper that they should be upgraded
to use instead.
llvm-svn: 93300
instead of returning it in an std::string. Based on this change:
1. Change TargetLoweringObjectFileCOFF::getCOFFSection to take a StringRef
2. Change a bunch of targets to call makeNameProper with a smallstring,
making several of them *much* more efficient.
3. Rewrite Mangler::makeNameProper to not build names and then prepend
prefixes, not use temporary std::strings, and to avoid other crimes.
llvm-svn: 93298
For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used.
llvm-svn: 93278
instruction is copy like where the source and destination registers can
overlap. This is to be used by the coalescable to coalesce the source and
destination registers of instructions like X86::MOVSX64rr32. Apparently
some crazy people believe the coalescer is too simple.
llvm-svn: 93210
- getToken is modeled after StringRef::split but it can split on multiple
separator chars and skips leading seperators.
- SplitString is a StringRef::split variant for more than 2 elements with the
same behaviour as getToken.
llvm-svn: 93161
Compare the dominance information calculated using a dominance tree walk to the
information calculated based on DFS numbers, if XDEBUG is enabled.
llvm-svn: 92969
Remove a FIXME and unify code that was necessary to work around broken
updateDFSNumbers(). Before updateDFSNumbers() did not work correctly for post
dominators.
llvm-svn: 92968
The DFS number calculation for postdominators was broken. In the case of
multiple exits that form the post dominator root nodes, do not iterate over
all exits, but start from the virtual root node. Otherwise bbs, that are not
post dominated by any exit but by the virtual root node, will never be assigned
a DFS number.
llvm-svn: 92967
(OP (trunc x), (trunc y)) -> (trunc (OP x, y))
Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel.
This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places.
llvm-svn: 92849
memcpy, memset and other intrinsics that only access their arguments
to be readnone if the intrinsic's arguments all point to local memory.
This improves the testcase in the README to readonly, but it could in
theory be made readnone, however this would involve more sophisticated
analysis that looks through the memcpy.
llvm-svn: 92829
An instruction like this:
%reg1097:1<def> = VMOVSR %R3<kill>, 14, %reg0
Must be replaced with this when substituting physical registers:
%S0<def> = VMOVSR %R3<kill>, 14, %reg0, %D0<imp-def>
llvm-svn: 92812
a single pointer (PointerIntPair) member. In "small" mode, the
pointer field is reinterpreted as a set of bits. In "large" mode,
the pointer points to a heap-allocated object.
Also, give BitVector empty and swap functions.
And, add some simple unittests for BitVector and SmallBitVector.
llvm-svn: 92730
