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136 Commits

Author SHA1 Message Date
Jim Grosbach
d964cf8939 Assembly parsing for 4-register sequential variant of VLD2. 
llvm-svn: 142704
 2011-10-21 23:58:57 +00:00
Jim Grosbach
a6e536367e Assembly parsing for 2-register sequential variant of VLD2. 
llvm-svn: 142691
 2011-10-21 22:21:10 +00:00
Jim Grosbach
68dfc88f95 Assembly parsing for 4-register variant of VLD1. 
llvm-svn: 142682
 2011-10-21 20:35:01 +00:00
Jim Grosbach
2c1ca90ac9 Assembly parsing for 3-register variant of VLD1. 
llvm-svn: 142675
 2011-10-21 20:02:19 +00:00
Jim Grosbach
6bb38d0e97 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670
 2011-10-21 18:54:25 +00:00
Jim Grosbach
547dde4517 Tidy up. Trailing whitespace. 
llvm-svn: 142591
 2011-10-20 17:28:20 +00:00
Chad Rosier
8247682aba Removed set, but unused variables. 
Patch by Joe Abbey <jabbey@arxan.com>.

llvm-svn: 142223
 2011-10-17 18:48:30 +00:00
Richard Trieu
5370a1ef01 Fix a non-firing assert. Change: 
assert("bad SymbolicOp.VariantKind");
To:
    assert(0 && "bad SymbolicOp.VariantKind");

llvm-svn: 142000
 2011-10-14 20:50:26 +00:00
Eli Friedman
94373219c3 Fix undefined shift. Patch by Ahmed Charles. 
llvm-svn: 141914
 2011-10-13 23:36:06 +00:00
Owen Anderson
9f90e2252c SETEND is not allowed in an IT block. 
llvm-svn: 141874
 2011-10-13 17:58:39 +00:00
Jim Grosbach
b9dddb0d13 ARM addrmode5 represents the 'U' bit of the encoding backwards. 
The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.

llvm-svn: 141819
 2011-10-12 21:59:02 +00:00
Jim Grosbach
422576b6e8 Thumb2 assembly parsing and encoding for LDC/STC. 
llvm-svn: 141811
 2011-10-12 20:54:17 +00:00
Jim Grosbach
71dbc175ce addrmode2 is gone from these, so no need for the reg0 operand. 
llvm-svn: 141794
 2011-10-12 18:11:24 +00:00
Owen Anderson
dc57f29896 Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue. 
llvm-svn: 141339
 2011-10-06 23:33:11 +00:00
Kevin Enderby
5a09a8db55 Adding back support for printing operands symbolically to ARM's new disassembler 
using llvm's public 'C' disassembler API now including annotations.

Hooked this up to Darwin's otool(1) so it can again print things like branch
targets for example this:
 blx _puts
instead of this:
 blx #-36
and includes support for annotations for branches to symbol stubs like:
 bl	0x40 @ symbol stub for: _puts
and annotations for pc relative loads like this:
 ldr	r3, #8 @ literal pool for: Hello, world!
Also again can print the expression encoded in the Mach-O relocation entries for
things like this:
 movt r0, :upper16:((_foo-_bar)+1234)

llvm-svn: 141129
 2011-10-04 22:44:48 +00:00
Jim Grosbach
d94ffffc87 ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. 
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.

rdar://10211428

llvm-svn: 140834
 2011-09-30 00:50:06 +00:00
Owen Anderson
7742c81cde ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. 
llvm-svn: 140560
 2011-09-26 21:06:22 +00:00
Owen Anderson
071eb7580a Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. 
llvm-svn: 140415
 2011-09-23 21:07:25 +00:00
Owen Anderson
a2cfbf33af Revert r140412. This affects more instructions than intended. 
llvm-svn: 140413
 2011-09-23 21:02:01 +00:00
Owen Anderson
227b8c74fb Thumb2 register-shifted-register loads cannot target the PC or the SP. 
llvm-svn: 140412
 2011-09-23 21:00:32 +00:00
Owen Anderson
791a17f64a tMOVSr is not allowed in an IT block either. 
llvm-svn: 140104
 2011-09-19 23:57:20 +00:00
Owen Anderson
3920c43055 CPS instructions are UNPREDICTABLE inside IT blocks. 
llvm-svn: 140102
 2011-09-19 23:47:10 +00:00
Owen Anderson
25138827ef Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not in the middle. 
llvm-svn: 140079
 2011-09-19 22:34:23 +00:00
Jim Grosbach
6da9e6b23d Thumb2 assembly parsing and encoding for TBB/TBH. 
llvm-svn: 140078
 2011-09-19 22:21:13 +00:00
Owen Anderson
b843f3625d Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests. 
llvm-svn: 140032
 2011-09-19 18:07:10 +00:00
Owen Anderson
c1f638997d Bitfield mask instructions are unpredictable if the encoded LSB is higher than the encoded MSB. 
llvm-svn: 139972
 2011-09-16 23:30:01 +00:00
Owen Anderson
aec67a3ea1 Fix bitfield decoding based on Eli's feedback. 
llvm-svn: 139969
 2011-09-16 23:04:48 +00:00
Owen Anderson
5d23e1e5b4 Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt. 
llvm-svn: 139965
 2011-09-16 22:42:36 +00:00
Owen Anderson
eae0eee720 Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). 
llvm-svn: 139964
 2011-09-16 22:29:48 +00:00
Owen Anderson
5804085f26 Fix disassembly of Thumb2 LDRSH with a #-0 offset. 
llvm-svn: 139943
 2011-09-16 21:08:33 +00:00
Owen Anderson
e54c4beb5a Don't attach annotations to MCInst's. Instead, have the disassembler return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. 
llvm-svn: 139876
 2011-09-15 23:38:46 +00:00
Owen Anderson
04d8803035 Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them. 
llvm-svn: 139736
 2011-09-14 21:06:21 +00:00
Owen Anderson
05ef2c122d Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered. 
llvm-svn: 139522
 2011-09-12 18:56:30 +00:00
Owen Anderson
9cd21ce8c9 LDM writeback is not allowed if Rn is in the target register list. 
llvm-svn: 139432
 2011-09-09 23:13:33 +00:00
Owen Anderson
dbe77fc5a1 Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. 
llvm-svn: 139422
 2011-09-09 22:24:36 +00:00
Owen Anderson
a7838cb723 Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches. 
llvm-svn: 139415
 2011-09-09 21:48:23 +00:00
Jim Grosbach
eb2d668899 Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH. 
llvm-svn: 139381
 2011-09-09 18:37:27 +00:00
Owen Anderson
99ad1a853e All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ. 
llvm-svn: 139329
 2011-09-08 22:48:37 +00:00
Owen Anderson
d7127e0c27 Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block. 
llvm-svn: 139328
 2011-09-08 22:42:49 +00:00
Jim Grosbach
9f150bfedf Thumb2 assembly parsing and encoding for LDRD(immediate). 
Refactor operand handling for STRD as well. Tests for that forthcoming.

llvm-svn: 139322
 2011-09-08 22:07:06 +00:00
Owen Anderson
4a5ec6836f Remove the "common" set of instructions shared between ARM and Thumb2 modes. This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions. 
llvm-svn: 139268
 2011-09-08 00:11:18 +00:00
Owen Anderson
26467730c1 Create Thumb2 versions of STC/LDC, and reenable the relevant tests. 
llvm-svn: 139256
 2011-09-07 21:10:42 +00:00
James Molloy
ac057f13a5 Second of a three-patch series aiming to fix MSR/MRS on Cortex-M. This adds predicate checking to the Disassembler. 
llvm-svn: 139250
 2011-09-07 19:42:28 +00:00
Owen Anderson
4106b9fb31 Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed. 
llvm-svn: 139240
 2011-09-07 17:55:19 +00:00
James Molloy
f781d3d8e9 Refactor instprinter and mcdisassembler to take a SubtargetInfo. Add -mattr= handling to llvm-mc. Reviewed by Owen Anderson. 
llvm-svn: 139237
 2011-09-07 17:24:38 +00:00
Owen Anderson
a319b9901d Merge the ARM disassembler header into the implementation file, since it is not externally exposed. 
llvm-svn: 138982
 2011-09-01 23:35:51 +00:00
Owen Anderson
c4ec9cc45f Fix 80 columns violations. 
llvm-svn: 138980
 2011-09-01 23:23:50 +00:00
James Molloy
4a63186421 Fix up r137380 based on post-commit review by Jim Grosbach. 
llvm-svn: 138948
 2011-09-01 18:02:14 +00:00
Owen Anderson
dd71d9efb9 The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches. However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful. Specify additional fixed bits to close those gaps. 
llvm-svn: 138910
 2011-08-31 22:00:41 +00:00
Owen Anderson
adac5b2109 Fix issues with disassembly of IT instructions involving condition codes other the EQ/NE. Discovered by roundtrip testing. 
llvm-svn: 138840
 2011-08-30 22:58:27 +00:00