135280 Commits

Author SHA1 Message Date
Simon Pilgrim
0537d4bb36 [SLPVectorizer][X86] Added sqrt vectorization tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275788 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 13:20:54 +00:00
Simon Dardis
5ebefb8fd2 [inlineasm] Propagate operand constraints to the backend
When SelectionDAGISel transforms a node representing an inline asm
block, memory constraint information is not preserved. This can cause
constraints to be broken when a memory offset is of the form:

offset + frame index

when the frame is resolved.

By propagating the constraints all the way to the backend, targets can
enforce memory operands of inline assembly to conform to their constraints.

For MIPSR6, some instructions had their offsets reduced to 9 bits from
16 bits such as ll/sc. This becomes problematic when using inline assembly
to perform atomic operations, as an offset can generated that is too big to
encode in the instruction.

Reviewers: dsanders, vkalintris

Differential Review: https://reviews.llvm.org/D21615


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275786 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 13:17:31 +00:00
Nicolai Haehnle
0c05ce4746 AMDGPU: Disable AMDGPUPromoteAlloca pass for shader calling conventions.
Summary:
The work item intrinsics are not available for the shader
calling conventions. And even if we did hook them up most
shader stages haves some extra restrictions on the amount
of available LDS.

Reviewers: tstellarAMD, arsenm

Subscribers: nhaehnle, arsenm, llvm-commits, kzhuravl

Differential Revision: https://reviews.llvm.org/D20728

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275779 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 09:02:47 +00:00
Diana Picus
7e13fe031b [ARM] Update test to use CHECK-LABEL. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275777 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 07:48:42 +00:00
Diana Picus
ef2833b8f3 [ARM] Skip inline asm memory operands in DAGToDAGISel
The current logic for handling inline asm operands in DAGToDAGISel interprets
the operands by looking for constants, which should represent the flags
describing the kind of operand we're dealing with (immediate, memory, register
def etc). The operands representing actual data are skipped only if they are
non-const, with the exception of immediate operands which are skipped explicitly
when a flag describing an immediate is found.

The oversight is that memory operands may be const too (e.g. for device drivers
reading a fixed address), so we should explicitly skip the operand following a
flag describing a memory operand. If we don't, we risk interpreting that
constant as a flag, which is definitely not intended.

Fixes PR26038

Differential Revision: https://reviews.llvm.org/D22103

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275776 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 07:35:14 +00:00
Craig Topper
c9ba7aa68b [AVX512] Add EVEX versions of scalar ADD/SUB/MUL/DIV to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275775 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 06:49:32 +00:00
Craig Topper
4052e7231f [X86] Fix test checks to include leading 'v' on avx mnemonic names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275774 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 06:49:29 +00:00
Diana Picus
d504c85ea6 [ARM] Honour ABI for rem under -O0 for EABI, GNUEABI, Android and Musl
At higher optimization levels, we generate the libcall for DIVREM_Ix, which is
fine: aeabi_{u|i}divmod. At -O0 we generate the one for REM_Ix, which is the
default {u}mod{q|h|s|d}i3.

This commit makes sure that we don't generate REM_Ix calls for ABIs that
don't support them (i.e. where we need to use DIVREM_Ix instead). This is
achieved by bailing out of FastISel, which can't handle non-double multi-reg
returns, and letting the legalization infrastructure expand the REM_Ix calls.

It also updates the divmod-eabi.ll test to run under -O0 as well, and adds some
Windows checks to it to make sure we don't break things for it.

Fixes PR27068

Differential Revision: https://reviews.llvm.org/D21926

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275773 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 06:48:25 +00:00
Craig Topper
b06a386b31 [AVX512] Add KADD/KAND/KOR/KXOR to X86InstrInfo::isAssociativeAndCommutative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275771 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 06:14:59 +00:00
Craig Topper
ad7e1daba6 [X86] Add VPMULLW/D/Q instructions to X86InstrInfo::isAssociativeAndCommutative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275770 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 06:14:57 +00:00
Craig Topper
fefffbf697 [X86] Add VPADD instructions to X86InstrInfo::isAssociativeAndCommutative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275769 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 06:14:54 +00:00
Craig Topper
81c3344bd0 [X86] Add floating point packed logical ops to X86InstrInfo::isAssociativeAndCommutative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275768 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 06:14:50 +00:00
Craig Topper
4388ffce8e [X86] Add AVX512 instructions to X86InstrInfo::isAssociativeAndCommutative.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275767 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 06:14:47 +00:00
Craig Topper
224d1467d3 [X86] Add more AVX512 instructions to X86InstrInfo::isHighLatencyDef. Also add all packed fp division instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275766 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 06:14:45 +00:00
Craig Topper
3305a40150 [X86] Add AVX512 load opcodes and a couple AVX load opcodes to X86InstrInfo::areLoadsFromSameBasePtr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275765 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 06:14:43 +00:00
Craig Topper
e70f2b66e1 [X86] Add more opcodes to isFrameLoadOpcode/isFrameStoreOpcode. Mainly AVX-512 related.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275764 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 06:14:39 +00:00
Craig Topper
0c4677f3cc [AVX512] Use VMOVAPSZ128rr/VMOVAPS256rr for VR128X/VR256X physreg moves when VLX is supported.
Ideally we would use VEX encoded moves instead of EVEX if the high 16 registers aren't referenced, but this a good first step.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275763 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 06:14:34 +00:00
Craig Topper
92763c0edd [X86] Fix 80-column violations. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275762 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 06:14:26 +00:00
David Majnemer
93324fe683 [GVNHoist] Change the key for VNtoInsns to a pair
While debugging GVNHoist, I found it confusing that the entries in a
VNtoInsns were not always value numbers.  They _usually_ were except for
StoreInst in which case they were a hash of two different value numbers.

This leads to two observations:
- It is more difficult to debug things when the semantic contents of
  VNtoInsns changes over time.
- Using a single value number is not much cheaper, the value of
  VNtoInsns is a SmallVector.
- It is not immediately clear what the algorithm would do if there were
  hash collisions in the StoreInst case.

Using a DenseMap of std::pair sidesteps all of this.

N.B.  The changes in the test were due their sensitivity to the
iteration order of VNtoInsns which has changed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275761 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 06:11:37 +00:00
Vedant Kumar
4893e1f8d4 [llvm-cov] Attempt to fix a test failure on Windows
Don't make the test/tools/llvm-cov/demangle.test depend on the order in
which symbols are seen, or on the exact formatting llvm-cov emits after
a symbol is printed. This is an attempt to fix a Windows bot failure:

  http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/9141

I don't know what the root cause of the failure is, or why the
showTemplateInstantiations test doesn't fail in the same way on the
Windows bots. However, this measure can't hurt, and it'll at least get
me on the blamelists again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275758 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 04:49:42 +00:00
NAKAMURA Takumi
73585958d4 Revert r275678, "Revert "Revert r275027 - Let FuncAttrs infer the 'returned' argument attribute""
This reverts also r275029, "Update Clang tests after adding inference for the returned argument attribute"

It broke LTO build. Seems miscompilation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275756 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 03:23:25 +00:00
David Majnemer
a6f9e21635 [GVNHoist] Sink HoistedCtr into GVNHoist
HoistedCtr cannot be a mutated global variable, that will open us up to
races between threads compiling code in parallel.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275744 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 00:35:01 +00:00
David Majnemer
326770a316 [GVNHoist] Some small cleanups
No functional change is intended, just trying to clean things up a
little.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275743 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-18 00:34:58 +00:00
Davide Italiano
7f321092d8 [GVN] Move other PRE tests to a subdirectory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275742 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 23:55:20 +00:00
Davide Italiano
c2a1d898e3 [GVN] Move the PRE/LOADPRE test in a subdirectory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275741 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 23:48:18 +00:00
Davide Italiano
9cffe5e2cd [GVN] Use FileCheck instead of grep for tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275739 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 23:21:26 +00:00
Simon Pilgrim
998d31012c Strip trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275726 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 19:02:27 +00:00
Simon Pilgrim
08df0eb04c [X86] Add CTPOP/CTLZ/CTTZ scalar cost tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275725 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 18:29:19 +00:00
Justin Lebar
5e704c77a9 Add tests for max/minIntN(64).
Summary:
Given that we had a bug on max/minUIntN(64), these should have tests
too.

Reviewers: rnk

Subscribers: dylanmckay, llvm-commits

Differential Revision: https://reviews.llvm.org/D22443

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275723 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 18:19:28 +00:00
Justin Lebar
f36e8699d3 Avoid UB in maxIntN(64).
Summary:
Previously we were relying on 2's complement underflow in an int64_t.
Now we cast to a uint64_t so we explicitly get the behavior we want.

Reviewers: rnk

Subscribers: dylanmckay, llvm-commits

Differential Revision: https://reviews.llvm.org/D22445

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275722 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 18:19:26 +00:00
Justin Lebar
61e00f94a5 Clean up some comments in MathExtras.h.
Reviewers: rnk

Subscribers: llvm-commits, dylanmckay

Differential Revision: https://reviews.llvm.org/D22444

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275721 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 18:19:25 +00:00
Justin Lebar
495097a50a Add assertions checking SignExtend{32,64}'s bit width.
Summary:
The bit width must be greater than zero, otherwise we shift by the
integer's width, which is UB.  Also (more obviously) the width must be
less than or equal to the integer's width, otherwise we shift by a
negative number, which is also UB.

Reviewers: rnk

Subscribers: llvm-commits, dylanmckay

Differential Revision: https://reviews.llvm.org/D22442

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275720 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 18:19:23 +00:00
Justin Lebar
c71e1994e1 Fix isShiftedInt and isShiftedUint for widths > 32.
Summary:
Previously we were doing 1 << S.  "1" is an int, so this doesn't work
when S >= 32.

This patch also adds some static_asserts to these functions to ensure
that we don't hit UB by shifting left too much.

Reviewers: rnk

Subscribers: llvm-commits, dylanmckay

Differential Revision: https://reviews.llvm.org/D22441

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275719 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 18:19:21 +00:00
Justin Lebar
a0a694296b Use a faster implementation of maxUIntN.
Summary:
On x86-64 with clang 3.8, before:

   mov     edx, 1
   mov     cl, dil
   shl     rdx, cl
   cmp     rdi, 64
   mov     rax, -1
   cmovne  rax, rdx
   ret

after:

  mov     ecx, 64
  sub     ecx, edi
  mov     rax, -1
  shr     rax, cl
  ret

Reviewers: rnk

Subscribers: dylanmckay, mkuper, llvm-commits

Differential Revision: https://reviews.llvm.org/D22440

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275718 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 18:19:19 +00:00
Justin Lebar
bac9a5d5cf Fix warnings in ImmutableSetTest and SequenceTest.
Doing "I++" inside of an EXPECT_* triggers

  warning: expression with side effects has no effect in an unevaluated context

because EXPECT_* partially expands to

  EqHelper<(sizeof(::testing::internal::IsNullLiteralHelper(i++)) == 1)>

which is an unevaluated context.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275717 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 18:10:30 +00:00
Simon Pilgrim
5bf69d80fb [X86][AVX] Added VBROADCASTF128/VBROADCASTI128 tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275713 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 17:44:18 +00:00
Simon Pilgrim
0aff5d2239 [X86] Regenerated ctlz/cttz scalar tests for 32/64-bit targets with/without LZCNT/TZCNT support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275710 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 16:15:51 +00:00
Simon Pilgrim
506afb80d9 [X86] Regenerated popcnt scalar tests for 32/64-bit targets with/without POPCNT support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275709 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 16:04:19 +00:00
Simon Pilgrim
43973299d3 [X86][SSE] lowerVectorShuffleAsPermuteAndUnpack tidyup. NFCI.
Moved unpack type determination into TryUnpack lambda.

Added missing comment describing lowerVectorShuffleAsPermuteAndUnpack call.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275708 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 15:48:25 +00:00
Teresa Johnson
e2f34269f3 [ThinLTO] Perform profile-guided indirect call promotion
Summary:
To enable profile-guided indirect call promotion in ThinLTO mode, we
simply add call graph edges for each profitable target from the profile
to the summaries, then the summary-guided importing will consider the
callee for importing as usual.

Also we need to enable the indirect call promotion pass creation in the
PassManagerBuilder when PerformThinLTO=true (we are in the ThinLTO
backend), so that the newly imported functions are considered for
promotion in the backends.

The IC promotion profiles refer to callees by GUID, which required
adding GUIDs to the per-module VST in bitcode (and assigning them
valueIds similar to how they are assigned valueIds in the combined
index).

Reviewers: mehdi_amini, xur

Subscribers: mehdi_amini, davidxl, llvm-commits

Differential Revision: http://reviews.llvm.org/D21932

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275707 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 14:47:01 +00:00
Teresa Johnson
350718ee80 Address review comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275706 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 14:46:58 +00:00
Teresa Johnson
c64254e223 Refactor indirect call promotion profitability analysis (NFC)
Summary:
Refactored the profitability analysis out of the IC promotion pass and
into lib/Analysis so that it can be accessed by the summary index
builder in a follow-on patch to enable IC promotion in ThinLTO (D21932).

Reviewers: davidxl, xur

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D22182

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275705 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 14:46:54 +00:00
Guy Blank
611890892a test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275703 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 12:10:35 +00:00
Elena Demikhovsky
562b267d41 X86: Updated a test file. NFC.
This test shows subotimal code generated for AVX-512 vs PENTIUM4.
The issue will be fixed in an upcomming commit.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275702 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-17 07:03:13 +00:00
Dehao Chen
78ee4b6ec0 [PM] Convert IVUsers analysis to new pass manager.
Summary: Convert IVUsers analysis to new pass manager.

Reviewers: davidxl, silvas

Subscribers: junbuml, sanjoy, llvm-commits, mzolotukhin

Differential Revision: https://reviews.llvm.org/D22434

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275698 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-16 22:51:33 +00:00
Sanjay Patel
2e9433d42d [InstCombine] allow X + signbit --> X ^ signbit for vector splats
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275691 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-16 18:29:26 +00:00
Sanjay Patel
713ceaf392 add vector test to show missing transform
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275690 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-16 18:24:18 +00:00
Mehdi Amini
bf11cc79f2 IPRA: avoid double query to the map (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275689 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-16 18:20:26 +00:00
Sanjay Patel
5de5eb94ef update tests to use FileCheck, consolidate tests, fix comments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275688 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-16 18:08:22 +00:00
Sanjay Patel
32507fc5f7 update test to use FileCheck
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275687 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-16 16:31:58 +00:00