157572 Commits

Author SHA1 Message Date
Pavel Labath
3f2a29c060 Revert "[cmake] Enable zlib support on windows"
This reverts commit r319533 as it broke llvm-config --system-libs output
and everything that depends on it (which is mostly out of tree or
downstream folks, but includes a couple of llvm buildbots as well).

I think I have a fix for this in D40779, but I want someone to look
review it first. In the mean time, I am reverting this change, as it
seems to break a lot of people.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319663 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 16:46:20 +00:00
Sam Kolton
cf56d5d898 [AMDGPU] SDWA: add support for PRESERVE into SDWA peephole.
Summary:

Reviewers: arsenm, vpykhtin, rampitec

Subscribers: kzhuravl, wdng, nhaehnle, mgorny, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D37817

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319662 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 16:22:32 +00:00
Sam Parker
4effab6b15 [ARM] CodeGen test
Add another and + load DAG combine test.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319660 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 15:14:59 +00:00
Anna Thomas
7c3eddc7d6 [Loop Predication] Teach LP about reverse loops
Summary:
Currently, we only support predication for forward loops with step
of 1.  This patch enables loop predication for reverse or
countdownLoops, which satisfy the following conditions:
   1. The step of the IV is -1.
   2. The loop has a singe latch as B(X) = X <pred>
latchLimit with pred as s> or u>
   3. The IV of the guard is the decrement
IV of the latch condition (Guard is: G(X) = X-1 u< guardLimit).

This patch was downstream for a while and is the last series of patches
that's from our LP implementation downstream.

Reviewers: apilipenko, mkazantsev, sanjoy

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D40353

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319659 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 15:11:48 +00:00
Jonas Hahnfeld
ba19c689aa [NVPTX] Assign valid global names
PTX requires that identifiers consist only of [a-zA-Z0-9_$]. The
existing pass already ensured this for globals and this patch adds
the cleanup for functions with local linkage.

However, there was a different problem in the case of collisions
of the adjusted name: The ValueSymbolTable then automatically
appended ".N" with increasing Ns to get a unique name while helping
the ABI demangling. Special case this behavior to omit the dots and
append N directly. This will always give us legal names according
to the PTX requirements.

Differential Revision: https://reviews.llvm.org/D40573

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319657 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 14:19:33 +00:00
Jonas Devlieghere
e0e7476d4c [NFC][lit] Use proper semantic versioning names for variables
The variable named `minor` was actually pointing to the patch part of
the version. While I was changing this I also made the check for Apple
clang more robust by checking both patch and minor rather than just
minor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319656 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 14:01:34 +00:00
Oliver Stannard
9d9981028d Revert r319649 - [Asm, ARM] Add fallback diag for multiple invalid operands
This is causing a failure in the llvm-clang-x86_64-expensive-checks-win
buildbot, and I can't reproduce it locally, so reverting until I can work out
what is wrong.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319654 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 13:42:22 +00:00
Sam McCall
c7ae88e8a9 Revert "[ValueTracking] Pass only a single lambda to computeKnownBitsFromShiftOperator by using KnownBits struct instead of separate APInts. NFCI"
This reverts commit r319624, which seems to cause a miscompile (breaks the
multistage PPC buildbots)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319652 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 12:51:49 +00:00
Tim Corringham
1e6aa1171d AMDGPU: fix missing s_waitcnt
Summary:
The pass that inserts s_waitcnt instructions where needed propagated
info used to track dependencies for each block by iterating over the
predecessor blocks. The iteration was terminated when a predecessor
that had not yet been processed was encountered. Any info in blocks
later in the list was therefore not processed, leading to the
possiblility of a required s_waitcnt not being inserted.

The fix is simply to change the "break" to "continue" for the
relevant loops, so that all visited blocks are processed. This
is likely what was intended when the code was written.

There is no test case provided for this fix because:
1) the only example that reproduces this is large and resistant to
being reduced
2) the change is trivial

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye

Differential Revision: https://reviews.llvm.org/D40544

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319651 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 12:30:49 +00:00
Oliver Stannard
a53a7f0627 [Asm, ARM] Add fallback diag for multiple invalid operands
This adds a "invalid operands for instruction" diagnostic for
instructions where there is an instruction encoding with the correct
mnemonic and which is available for this target, but where multiple
operands do not match those which were provided. This makes it clear
that there is some combination of operands that is valid for the current
target, which the default diagnostic of "invalid instruction" does not.

Since this is a very general error, we only emit it if we don't have a
more specific error.

Differential revision: https://reviews.llvm.org/D36747



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319649 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 12:02:32 +00:00
Jonas Paulsson
62f11d908e [TwoAddressInstructionPass] Bugfix in handling of sunk instructions.
An instruction returned by TII->convertToThreeAddress() may contain a %noreg
(undef) operand, which is not expected by tryInstructionTransform(). So if
this MI is sunk to a lower point in MBB, it must be skipped when later
encountered.

A new set SunkInstrs is used for this purpose.

Note: there is no test supplied here, as this was triggered on SystemZ while
working on a review of instruction flags. A test case for this bugfix will be
included in the upcoming SystemZ commit.

Review: Quentin Colombet
https://reviews.llvm.org/D40711

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319646 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 10:03:14 +00:00
Sam Parker
5022455191 [DAGCombine] Remove isAndLoadExtLoad arguments
Both LoadedVT and NarrowLoad are passed as references and neither
of them are used by any of its callers.

Differential Revision: https://reviews.llvm.org/D40713


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319645 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 09:48:26 +00:00
Martin Storsjo
ed04373440 [AArch64] Allow using emulated tls on platforms other than ELF
This matches how it is done on X86.

This allows using emulated tls on windows; in MinGW environments,
native tls isn't supported at the moment.

Set the right Data*bitsDirective for windows to match the existing
tests for other platforms. Make parts of the existing tests a regex,
to allow matching .section .rdata for windows, to avoid having to
duplicate the rest of the tests for windows.

Differential Revision: https://reviews.llvm.org/D40770

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319644 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 09:09:04 +00:00
Martin Storsjo
57337feb58 [ARM] Allow using emulated tls on platforms other than ELF
This matches how it is done on X86.

This allows using emulated tls on windows; in MinGW environments,
native tls isn't supported at the moment.

Differential Revision: https://reviews.llvm.org/D40769

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319643 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 09:08:55 +00:00
Craig Topper
079e93a26a [X86] Allow VPMAXUQ/VPMAXSQ/VPMINUQ/VPMINSQ to be used with 128/256 bit vectors when AVX512 is enabled.
These instructions can be used by widening to 512-bits and extracting back to 128/256. We do similar to several other instructions already.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319641 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 07:21:01 +00:00
Craig Topper
18d898c462 [X86] Don't turn UINT_TO_FP into SINT_TO_FP during lowering.
We already do this as a DAG combine. The version during lowering can only trigger if known bits changes something that improves known bits analysis. But this means we should be improving known bits analysis to work on the unlowered form instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319640 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 05:38:44 +00:00
Craig Topper
7cd55ac3b8 [SelectionDAG] Teach computeKnownBits some improvements to ISD::SRL with a non-splat constant shift amount.
If we have a non-splat constant shift amount, the minimum shift amount can be used to infer the number of zero upper bits of the result. There's probably a lot more that we can do here, but this
fixes a case where I wanted to infer the sign bit as zero when all the shift amounts are non-zero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319639 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-04 05:38:42 +00:00
Simon Pilgrim
0d0f8ed798 [X86][AVX512] Tag PH2PS/PS2PH conversion instructions scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319637 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-03 21:43:54 +00:00
Simon Pilgrim
ad08404099 [X86][AVX512] Tag packed F2I/I2F/F2F conversion instructions scheduler class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319636 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-03 21:16:12 +00:00
Simon Pilgrim
fbeb20aced [X86][AVX512] Regenerate schedule tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319635 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-03 21:07:36 +00:00
Simon Pilgrim
af7247c2d3 [X86][SSE] Remove unused IIC_SSE_CVT_PI2PS_RR/IIC_SSE_CVT_PI2PS_RM itineraries
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319634 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-03 20:57:04 +00:00
Yaxun Liu
8b47f7bedd CodeGen: Fix SelectionDAGISel::LowerArguments for sret addr space
SelectionDAGISel::LowerArguments assumes sret addr space is 0, which is
not true for amdgcn---amdgiz target.

This patch fixes that.

Differential Revision: https://reviews.llvm.org/D40255


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319630 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-03 03:31:45 +00:00
Craig Topper
fec09ca00e [SelectionDAG] Use the inlined APInt shift methods since we've already bounds checked the shift.
The version that takes APInt is out of line. The 'unsigned' version optimizes for the common case of single word APInts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319628 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-03 03:07:09 +00:00
Sam Clegg
1f4bd62fa3 Reland "[WebAssembly] Add visibility flag to Wasm symbol flags""
Original change was rL319488.

This was reverted rL319602 due to a gcc 7.1 warning.

Differential Revision: https://reviews.llvm.org/D40772

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319626 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-03 01:19:23 +00:00
Matt Arsenault
e87334bb7c Fix typo in emitted attribute name
Fixes build when using this attribute combination
on an intrinsic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319625 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-03 00:03:01 +00:00
Craig Topper
aa18cf610f [ValueTracking] Pass only a single lambda to computeKnownBitsFromShiftOperator by using KnownBits struct instead of separate APInts. NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319624 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02 23:42:17 +00:00
Yaxun Liu
dcc00b1fac CodeGen: Fix pointer info in SplitVecOp_EXTRACT_VECTOR_ELT/SplitVecRes_INSERT_VECTOR_ELT
Two issues found when doing codegen for splitting vector with non-zero alloca addr space:

DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT/SplitVecOp_EXTRACT_VECTOR_ELT uses dummy pointer info for creating
SDStore. Since one pointer operand contains multiply and add, InferPointerInfo is unable to
infer the correct pointer info, which ends up with a dummy pointer info for the target to lower
store and results in isel failure. The fix is to introduce MachinePointerInfo::getUnknownStack to
represent MachinePointerInfo which is known in alloca address space but without other information.

TargetLowering::getVectorElementPointer uses value type of pointer in addr space 0 for
multiplication of index and then add it to the pointer. However the pointer may be in an addr
space which has different size than addr space 0. The fix is to use the pointer value type for
index multiplication.

Differential Revision: https://reviews.llvm.org/D39758


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319622 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02 22:13:22 +00:00
Don Hinton
f4f388171b [cmake] Re-commit: Remove redundant call to cmake when building host tools.
Also pass CMAKE_(C|CXX)_COMPILER to add_custom_command.

Summary:
Remove the redundant, config-time call to cmake when
building host tools for cross compiles or optimized tablegen..

The config-time call to cmake is redundant because it will always get
called again when the CONFIGURE_LLVM_${target_name} target fires at
build-time.  This speeds up initial configuration, but has no affect
on build behavior.

Differential Revision: https://reviews.llvm.org/D40229

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319620 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02 19:12:38 +00:00
Simon Atanasyan
649eb90a70 [llvm-readobj] Remove redundant local variables to reduce the code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319617 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02 13:06:40 +00:00
Simon Atanasyan
0eba9bcf82 [llvm-readobj] Print static MIPS GOT
If a linked binary file contains a dynamic section, the GOT layout
defined by the dynamic section entries. In a statically linked file
the GOT is just a series of entries. This change teaches `llvm-readobj`
to print the GOT in that case. That provides a feature parity with GNU
`readelf`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319616 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02 13:06:35 +00:00
Simon Atanasyan
2a502f2ce1 [llvm-readobj] Delete unused method argument. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319615 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02 13:06:27 +00:00
Simon Pilgrim
72e0a2708d [X86][SSE] Cleanup float/int conversion scheduler itinerary classes
Makes it easier to grok where each is supposed to be used, mainly useful for adding to the AVX512 instructions but hopefully can be used more in SSE/AVX as well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319614 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02 12:27:44 +00:00
Craig Topper
212549ca81 [X86] Fix copy paste mistake in test case for r319612.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319613 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02 08:39:02 +00:00
Craig Topper
6d12eb2d5b [X86] Teach the assembler to support %db8-%db15 as aliases for %dr8-%dr15.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319612 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02 08:27:46 +00:00
Craig Topper
9f0c43a804 [X86] Support %dr8-%dr15 in the assembler.
Apparently I failed to make this work when I fixed it in the disassembler way back in r224862.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319611 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02 08:27:45 +00:00
Martell Malone
abd7f8c4bd CMAKE: help CheckAtomic find check_library_exists
lldb fails to build standalone on x86

-- Performing Test HAVE_CXX_ATOMICS64_WITHOUT_LIB - Failed
CMake Error at CheckAtomic.cmake:66 (check_library_exists):
  Unknown CMake command "check_library_exists".
Call Stack (most recent call first):
  LLDBStandalone.cmake:90 (include)
CMakeLists.txt:3 (include)

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D40220

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319610 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02 07:17:01 +00:00
Tatyana Krasnukha
4ab42623aa [ARC] Add instruction subset for the ARC backend.
Reviewers: petecoup, kparzysz

Reviewed By: petecoup

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D37983

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319609 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02 05:25:17 +00:00
Nirav Dave
deae672db6 [DAG][AArch64] Disable post-legalization store
Disable post-legalization store for AArch64 backend which is causing
errors out-of-tree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319607 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02 04:01:26 +00:00
Heejin Ahn
527f9bdad5 [WebAssembly] Revert r319488 "Add visibility flag to Wasm symbol flags"
This patch reportedly broke one of LLVM bots (ubuntu-gcc7.1-werror).

See http://lab.llvm.org:8011/builders/ubuntu-gcc7.1-werror/builds/3369 for
details.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319602 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-02 02:05:06 +00:00
Matt Morehouse
79f1f0032c Revert "[X86] Improvement in CodeGen instruction selection for LEAs."
This reverts r319543, due to ASan bot breakage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319591 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-01 22:20:26 +00:00
Kostya Serebryany
1fe1bd128c [libFuzzer] add a flag -malloc_limit_mb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319590 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-01 22:12:04 +00:00
Jessica Paquette
55c1b415d4 [MachineOutliner] NFC: Throw out self-intersections on candidates early
Currently, the outliner considers candidates that intersect with themselves in
the candidate pruning step. That is, candidates of the form "AA" in ranges like
"AAAAAA". In that range, it looks like there are 5 instances of "AA" that could
possibly be outlined, and that's considered in the benefit calculation.

However, only at most 3 instances of "AA" could ever be outlined in "AAAAAA".
Thus, it's possible to pass through "AA" to the candidate selection step even
though it's *never* the case that "AA" could be outlined. This makes it so that
when we find candidates, we consider only non-overlapping occurrences of that
candidate.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319588 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-01 21:56:56 +00:00
Nirav Dave
ea21b4dca9 [DAG][ARM] Revert "Reenable post-legalize store merge"
due to failures in AArch and ARM code gen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319587 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-01 21:55:47 +00:00
Jake Ehrlich
977b537d0f [MC] Handle unknown literal register numbers in .cfi_* directives
r230670 introduced a step to map EH register numbers to standard
DWARF register numbers. This failed to consider the case when a
user .cfi_* directive uses an integer literal rather than a
register name, to specify a DWARF register number that has no
corresponding LLVM register number (e.g. a special register that
the compiler and assembler have no name for).

Fixes PR34028.

Patch by Roland McGrath

Differential Revision: https://reviews.llvm.org/D36493

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319586 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-01 21:44:27 +00:00
Philip Reames
0fed3ad4cb [IndVars] Fix a bug introduced in r317012
Turns out we can have comparisons which are indirect users of the induction variable that we can make invariant.  In this case, there is no loop invariant value contributing and we'd fail an assert.

The test case was found by a java fuzzer and reduced.  It's a real cornercase.  You have to have a static loop which we've already proven only executes once, but haven't broken the backedge on, and an inner phi whose result can be constant folded by SCEV using exit count reasoning but not proven by isKnownPredicate.  To my knowledge, only the fuzzer has hit this case.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319583 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-01 20:57:19 +00:00
Don Hinton
8ad3e8644f [cmake] Revert (rL319574): Resubmit Remove redundant call to cmake when building host tools.
Still fails for some bots.

Differential Revision: https://reviews.llvm.org/D40229

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319582 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-01 20:46:45 +00:00
Adam Nemet
c4f204db88 [opt-remarks] If hotness threshold is set, ignore remarks without hotness
These are blocks that haven't not been executed during training.  For large
projects this could make a significant difference.  For the project, I was
looking at, I got an order of magnitude decrease in the size of the total YAML
files with this and r319235.

Differential Revision: https://reviews.llvm.org/D40678

Re-commit after fixing the failing testcase in rL319576, rL319577 and
rL319578.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319581 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-01 20:41:38 +00:00
Don Hinton
4b50cdffe5 [cmake] Resubmit Remove redundant call to cmake when building host tools.
Only pass Native to LLVM_TARGETS_TO_BUILD.

Summary:
Remove the redundant, config-time call to cmake when
building host tools for cross compiles or optimized tablegen..

The config-time call to cmake is redundant because it will always get
called again when the CONFIGURE_LLVM_${target_name} target fires at
build-time.  This speeds up initial configuration, but has no affect
on build behavior.

Differential Revision: https://reviews.llvm.org/D40229

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319574 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-01 19:35:56 +00:00
Eli Friedman
52eba828c1 [DAGCombine] Simplify ISD::AND handling in ReduceLoadWidth
Followup to D39595. Removes a bunch of redundant checks.

Differential Revision: https://reviews.llvm.org/D40667



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319573 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-01 19:33:56 +00:00
Simon Pilgrim
bfae8814e3 [X86][AVX512] Tag subvector extract/insert instructions scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319568 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-01 18:40:32 +00:00