157572 Commits

Author SHA1 Message Date
Peter Collingbourne
b45fa1a537 LowerTypeTests: Deduplicate code. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319390 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-30 00:27:08 +00:00
Peter Collingbourne
1edbc9f1bc LowerTypeTests: Remove unnecessary cast. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319387 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-30 00:02:55 +00:00
Craig Topper
0a78cd8e7f [X86] Remove some questionable looking code that seems to be looking through a VZEXT to create a larger VSEXT.
If the input the vzext was signed this would do the wrong thing.

Not sure how to test this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319382 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 23:08:25 +00:00
Joerg Sonnenberger
4ee291ace8 First step towards more human-friendly PPC assembler output:
- add -ppc-reg-with-percent-prefix option to use %r3 etc as register
  names
- split off logic for Darwinish verbose conditional codes into a helper
  function
- be explicit about Darwin vs AIX vs GNUish assembler flavors

Based on the patch from Alexandre Yukio Yamashita

Differential Revision: https://reviews.llvm.org/D39016


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319381 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 23:05:56 +00:00
Sam Clegg
066e89ae6f [WebAssembly] Update test expectations for gcc torture tests
I believe these were recently fixed by:
https://reviews.llvm.org/rL319186

Differential Revision: https://reviews.llvm.org/D40619

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319380 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 23:05:50 +00:00
Zachary Turner
7448686a65 [CodeView] Factor some code out of TypeTableBuilder.
This class had some code that would automatically remap type
indices before hashing and serializing.  The only caller of
this method was the TypeStreamMerger anyway, and the method
doesn't make general sense, and prevents making certain future
improvements to the class.  So, factoring this up one level
into the TypeStreamMerger where it belongs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319377 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 22:41:56 +00:00
Craig Topper
f1a319a05f [SelectionDAG][X86] Teach promotion legalization for fp_to_sint/fp_to_uint to insert an assertsext/assertzext based on the original type
If we put in an assertsext/zext here, we're able to generate better truncate code using pack on pre-avx512 targets.

Similar is already done during type legalization. This is the equivalent for op legalization

Differential Revision: https://reviews.llvm.org/D40591

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319368 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 22:15:43 +00:00
Dan Gohman
685c102164 [WebAssembly] Fix fptoui lowering bounds
To fully avoid trapping on wasm, fptoui needs a second check to ensure that
the operand isn't below the supported range.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319354 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 20:20:11 +00:00
Sam Clegg
9bb51631d1 Add libstd++-4.8 exceptions to ubsan_blacklist.txt
Differential Revision: https://reviews.llvm.org/D40589

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319353 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 20:10:14 +00:00
Krzysztof Parzyszek
433d3104b8 [Hexagon] Remove HexagonISD::PACKHL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319352 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 19:59:29 +00:00
Krzysztof Parzyszek
743fb60a4e [Hexagon] Create helpers extractVector and insertVector in lowering
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319351 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 19:58:10 +00:00
Simon Pilgrim
5c698e3437 [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes (REVERSION)
Accidental commit of incomplete patch

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319346 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 19:37:38 +00:00
Zachary Turner
7fe0c00835 Make TypeTableBuilder inherit from TypeCollection.
A couple of places in LLD were passing references to
TypeTableCollections around, which makes it hard to change the
implementation at runtime.  However, these cases only needed to
iterate over the types in the collection, and TypeCollection
already provides a handy abstract interface for this purpose.

By implementing this interface, we can get rid of the need to
pass TypeTableBuilder references around, which should allow us
to swap the implementation at runtime in subsequent patches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319345 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 19:35:21 +00:00
Zachary Turner
4c20574874 Fix line endings in llvm-pdbutil.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319340 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 19:29:25 +00:00
Simon Pilgrim
ae007cec62 [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319338 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 19:19:59 +00:00
Simon Pilgrim
02c5c78684 [X86][AVX512] Tag 3OP (shuffles, double-shifts and GFNI) instructions scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319337 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 18:52:20 +00:00
Nirav Dave
17820125d4 [ARM][DAG] Revert Disable post-legalization store merge for ARM
Partially reverting enabling of post-legalization store merge
(r319036) for just ARM backend as it is causing incorrect code
in some Thumb2 cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319331 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 18:06:13 +00:00
Greg Bedwell
3a42cace77 [cmake] Replace -Wall with /W4 in clang-cl options now that -Wall aliases -Weverything
Instead, reuse the code-path for cl.exe that adds /W4 , which for clang-cl
aliases clang's "-Wall -Wextra" which matches what clang-cl's /Wall
previously aliased.

This should restore the verbosity of a Windows selfhost build back to
its previous levels.

Differential Revision: https://reviews.llvm.org/D40603

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319330 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 18:05:32 +00:00
Greg Bedwell
e081e350cb Make check-lit tests respect LLVM_LIT_TOOLS_DIR
Differential Revision: https://reviews.llvm.org/D40520

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319329 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 18:05:26 +00:00
Zaara Syeda
1a60893597 [Power9] add more tests for D38287; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319328 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 17:26:20 +00:00
Sanjay Patel
0221a1478f [InstCombine] add tests for select-of-constants; NFC
These are variants of a test that was originally added in:
https://reviews.llvm.org/rL75531
...but removed with:
https://reviews.llvm.org/rL159230



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319327 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 17:21:39 +00:00
Simon Pilgrim
1c969b0dcc [X86][AVX512] Add itinerary argument to all AVX512_maskable_* wrappers. NFCI
All default to NoItinerary

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319326 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 17:21:15 +00:00
Adam Nemet
d3ee0657bc Add opt-viewer testing
Detects whether we have the Python modules (pygments, yaml) required by
opt-viewer and hooks this up to REQUIRES.

This fixes https://bugs.llvm.org/show_bug.cgi?id=34129 (the lack of opt-viewer
testing).

It's also related to https://github.com/apple/swift/pull/12938 and the idea is
to expose LLVM_HAVE_OPT_VIEWER_MODULES to the Swift cmake.

Differential Revision: https://reviews.llvm.org/D40202

Fixes since the first commit:
1. Disable syntax highlighting as different versions of pygments generate
different HTML
2. Use llvm-cxxfilt from the build

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319324 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 17:07:41 +00:00
Sander de Smalen
ff77244792 Reverted r319315 because of unused functions (due to PPR not yet being
used by any instructions).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319321 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 15:14:39 +00:00
Simon Pilgrim
bc89401e6c [X86][AVX512] Tag VPERMILV instruction scheduler class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319316 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 14:58:34 +00:00
Sander de Smalen
a150a5ac82 [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing support
Summary: Patch [1/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions.

Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro, echristo, efriedma

Reviewed By: fhahn

Subscribers: aemerson, javed.absar, llvm-commits, tschuett

Differential Revision: https://reviews.llvm.org/D40360

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319315 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 14:34:18 +00:00
Diana Picus
c7436ce110 [ARM GlobalISel] Fix selecting G_BRCOND
When lowering a G_BRCOND, we generate a TSTri of the condition against
1, which sets the flags, and then a Bcc which branches based on the
value of the flags.

Unfortunately, we were using the wrong condition code to check whether
we need to branch (EQ instead of NE), which caused all our branches to
do the opposite of what they were intended to do. This patch fixes the
issue by using the correct condition code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319313 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 14:20:06 +00:00
Simon Pilgrim
abf3849506 [X86][AVX512] Setup unary (PABS/VPLZCNT/VPOPCNT/VPCONFLICT/VMOV*DUP) instruction scheduler classes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319312 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 13:49:51 +00:00
Dmitry Preobrazhensky
e211444e8b [AMDGPU][MC][GFX9] Corrected mapping of GFX9 v_add/sub/subrev_u32
When translating pseudo to MC, v_add/sub/subrev_u32 shall be mapped via a separate table as GFX8 has opcodes with the same names.
These instructions shall also be labelled as renamed for pseudoToMCOpcode to handle them correctly.

Reviewers: arsenm

Differential Revision: https://reviews.llvm.org/D40550

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319311 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 13:33:40 +00:00
Simon Pilgrim
7dfadbc71c [X86][SSE] Merged sse2_unpack and sse2_unpack PUNPCK instruction templates. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319310 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 12:12:27 +00:00
Simon Pilgrim
7bef62dc08 [X86][SSE] Merged sse2_pack and sse2_pack_y PACKSS/PACKUS instruction templates. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319308 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 11:35:45 +00:00
Max Kazantsev
dd9c0f58f9 [SCEV][NFC] Break from loop after we found first non-Phi in getAddRecExprPHILiterally
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319306 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 10:54:16 +00:00
Oliver Stannard
3aae870071 [ARM] Add support for armv7e-m to the .arch directive
This will allow compilation of assembly files targeting armv7e-m without having
to specify the Tag_CPU_arch attribute as a workaround.

Differential revision: https://reviews.llvm.org/D40370

Patch by Ian Tessier!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319303 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 10:12:15 +00:00
Serguei Katkov
ef36801a14 [CGP] Enable complex addr mode
Enable complex addr modes after two critical fixes: rL319109 and rL319292


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319302 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 09:48:50 +00:00
Jonas Paulsson
3bee26a969 Comment fix in SelectionDAG.h
/// Replace any uses of From with To, leaving
-  /// uses of other values produced by From.Val alone.
+  /// uses of other values produced by From.getNode() alone.
   void ReplaceAllUsesOfValueWith(SDValue From, SDValue To);

(this is what it says in the .cpp file above this method)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319301 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 09:16:37 +00:00
Craig Topper
acbaefa2f4 [X86] Remove setOperationAction Promote for ISD::SINT_TO_FP MVT::v8i16/v16i8/v16i16.
A DAG combine ensures these ops are always promoted to vXi32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319298 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 08:19:36 +00:00
Max Kazantsev
bee1015aa6 [SCEV][NFC] Remove condition that can never happen due to check few lines above
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319293 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 06:10:36 +00:00
Serguei Katkov
c2659f12f7 [CGP] Fix common type handling in optimizeMemoryInst
If common type is different we should bail out due to we will not be
able to create a select or Phi of these values.

Basically it is done in ExtAddrMode::compare however it does not work
if we handle the null first and then two values of different types.
so add a check in initializeMap as well. The check in ExtAddrMode::compare
is used as earlier bail out.

Reviewers: reames, john.brawn
Reviewed By: john.brawn
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40479


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319292 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 05:51:26 +00:00
Sean Fertile
98e460471c [PowerPC] Relax the checking on AND/AND8 in isSignOrZeroExtended.
Separate the handling of AND/AND8 out from PHI/OR/ISEL checking. The reasoning
is the others need all their operands to be sign/zero extended for their output
to also be sign/zero extended. This is true for AND and sign-extension, but for
zero-extension we only need at least one of the input operands to be zero
extended for the result to also be zero extended.

Differential Revision: https://reviews.llvm.org/D39078

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319289 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 04:09:29 +00:00
Matt Arsenault
c7ecbb28c3 AMDGPU: Use stricter regexes for add instructions
Match the entire _co as one optional piece rather than
a set of characters to match multiple times.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319275 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 02:25:14 +00:00
Bruno Cardoso Lopes
542c83c8b8 [Modules] Add textual headers for recently added .def files
Keep module.modulemap up to date and get rid of -Wincomplete-umbrella warnings

rdar://problem/35711925

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319273 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 01:53:49 +00:00
Matt Arsenault
ff838de892 DAG: Add nuw when splitting loads and stores
The object can't straddle the address space
wrap around, so I think it's OK to assume any
offsets added to the base object pointer can't
overflow. Similar logic already appears to be
applied in SelectionDAGBuilder when lowering
aggregate returns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319272 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 01:25:12 +00:00
Adrian Prantl
c97df2361b llvm-dwarfdump: honor the --show-children option when dumping a specific DIE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319271 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 01:12:22 +00:00
Matt Arsenault
9516b8f458 AMDGPU: Select DS insts without m0 initialization
GFX9 stopped using m0 for most DS instructions. Select
a different instruction without the use. I think this will
be less error prone than trying to manually maintain m0
uses as needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319270 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 00:55:57 +00:00
Don Hinton
0a7ff1af78 Rollback r319176.
The ';' separators in LLVM_TARGETS_TO_BUILD disappear when list
variables are evaluated in custom commands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319268 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 00:47:16 +00:00
Craig Topper
3c8bef9341 [X86] Promote fp_to_sint v16f32->v16i16/v16i8 to avoid scalarization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319266 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 00:32:09 +00:00
Zachary Turner
f125f8f5d1 Fix a warning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319263 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 00:13:44 +00:00
Adam Nemet
4418c09eb3 Revert "Add opt-viewer testing"
This reverts commit r319188.

Breaks when c++filt is not available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319262 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 00:10:48 +00:00
Craig Topper
115c91a3b2 [X86] Add test cases for fptosi v16f32->v16i8/v16i16 to show scalarization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319261 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-29 00:02:22 +00:00
Zachary Turner
dc4f5ff552 [NFC] Minor cleanups in CodeView TypeTableBuilder.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@319260 91177308-0d34-0410-b5e6-96231b3b80d8
2017-11-28 23:57:13 +00:00