185399 Commits

Author SHA1 Message Date
Simon Pilgrim
dd0433477f WasmEmitter - Don't dereference a dyn_cast result. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372165 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 19:14:11 +00:00
Jessica Paquette
ff0592d770 [AArch64][GlobalISel][NFC] Refactor tail call lowering code
When you begin implementing -tailcallopt, this gets somewhat hairy. Refactor
the call lowering code so that the tail call lowering stuff gets its own
function.

Differential Revision: https://reviews.llvm.org/D67577

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372164 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 19:08:44 +00:00
GN Sync Bot
f60ceb9328 gn build: Merge r372162
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372163 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 19:00:41 +00:00
Bardia Mahjour
11e505acf5 Data Dependence Graph Basics
Summary:
This is the first patch in a series of patches that will implement data dependence graph in LLVM. Many of the ideas used in this implementation are based on the following paper:
D. J. Kuck, R. H. Kuhn, D. A. Padua, B. Leasure, and M. Wolfe (1981). DEPENDENCE GRAPHS AND COMPILER OPTIMIZATIONS.
This patch contains support for a basic DDGs containing only atomic nodes (one node for each instruction). The edges are two fold: def-use edges and memory-dependence edges.
The implementation takes a list of basic-blocks and only considers dependencies among instructions in those basic blocks. Any dependencies coming into or going out of instructions that do not belong to those basic blocks are ignored.

The algorithm for building the graph involves the following steps in order:

  1. For each instruction in the range of basic blocks to consider, create an atomic node in the resulting graph.
  2. For each node in the graph establish def-use edges to/from other nodes in the graph.
  3. For each pair of nodes containing memory instruction(s) create memory edges between them. This part of the algorithm goes through the instructions in lexicographical order and creates edges in reverse order if the sink of the dependence occurs before the source of it.

Authored By: bmahjour

Reviewer: Meinersbur, fhahn, myhsu, xtian, dmgreen, kbarton, jdoerfert

Reviewed By: Meinersbur, fhahn, myhsu

Subscribers: ychen, arphaman, simoll, a.elovikov, mgorny, hiraditya, jfb, wuzish, llvm-commits, jsji, Whitney, etiotto

Tag: #llvm

Differential Revision: https://reviews.llvm.org/D65350

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372162 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 18:55:44 +00:00
Jinsong Ji
a5225558ed [docs][Bugpoint] Revert 5584ead50 a5aa3353
No sure why there are still warnings, revert while I investigate.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372161 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 18:39:04 +00:00
Jinsong Ji
d2d94c62df [docs][Bugpoint] Fix build break.
Bugpoint.rst:124: WARNING: Mismatch: both interpreted text role prefix
and reference suffix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372160 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 18:23:06 +00:00
Craig Topper
6b70998cd8 [X86] Use APInt::operator<<= and APInt::lshrInPlace. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372159 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 18:19:06 +00:00
Craig Topper
301db41084 [SimplifyDemandedBits] Use APInt::intersects to instead of ANDing and comparing to 0 separately. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372158 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 18:19:02 +00:00
Jinsong Ji
733e633061 [docs][Bugpoint]Add notes about multiple crashes
Summary:
    When reducing case for a CodeGenCrash, bugpoint may generate a new
    reduced
    testcase that exposes/causes another crash or break something due to
    limitation.

    Bugpoint does not distiguish different crashes currently,
    so when this happens, bugpoint will go on reducing for the new crash,
    or just abort, we can't get the case reduced for the origial crash.

    An advice is added into usage doc to connect to recommend checking error
    message with scripts and `-compile-command`.

Reviewers: modocache, bogner, sebpop, reames, vsk, MatzeB

Reviewed By: vsk

Subscribers: mehdi_amini, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66832

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372157 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 18:10:09 +00:00
Craig Topper
9bb2585bad [X86] Simplify b2b KSHIFTL+KSHIFTR using demanded elts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372155 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 18:02:56 +00:00
Craig Topper
684413690b [X86] Call SimplifyDemandedVectorElts on KSHIFTL/KSHIFTR nodes during DAG combine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372154 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 18:02:52 +00:00
Craig Topper
05632ac88d [X86] Simplify some code in LowerBUILD_VECTORvXi1. NFCI
The case were Immediate is 0 and HasConstElts is true should never
happen since that would mean the constant elts were all zero. But
we check for all zero build vector earlier. So just use HasConstElts
and blindly take Immediate without checking if its 0.

Move the code that bitcasts and extract the immediate into the
the HasConstElts case since the other code just creates an undef
with the right type. No casting needed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372153 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 18:02:46 +00:00
Stanislav Mekhanoshin
a5917e7992 [AMDGPU] Added MI bit IsDOT
NFC, needed for future commit.

Differential Revision: https://reviews.llvm.org/D67669

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372151 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 17:56:13 +00:00
GN Sync Bot
d343c49792 gn build: Merge r372149
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372150 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 17:51:27 +00:00
Greg Clayton
c7e2fdea40 GSYM: Add the llvm::gsym::Header header class with tests
This patch adds the llvm::gsym::Header class which appears at the start of a stand alone GSYM file, or in the first bytes of the GSYM data in a GSYM section within a file. Added encode and decode methods with full error handling and full tests.

Differential Revision: https://reviews.llvm.org/D67666



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372149 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 17:46:13 +00:00
Simon Pilgrim
8880d6274d [TableGen] CodeGenMapTable - Don't dereference a dyn_cast result. NFCI.
The static analyzer is warning about potential null dereferences of dyn_cast<> results - in these cases we can safely use cast<> directly as we know that these cases should all be the correct type, which is why its working atm and anyway cast<> will assert if they aren't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372146 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 17:32:15 +00:00
Simon Pilgrim
34ac6f6912 [ARM][AsmParser] Don't dereference a dyn_cast result. NFCI.
The static analyzer is warning about potential null dereferences of dyn_cast<> results - in these cases we can safely use cast<> directly as we know that these cases should all be the correct type, which is why its working atm and anyway cast<> will assert if they aren't.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372145 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 17:26:14 +00:00
Simon Pilgrim
7583a6bc10 Fix MSVC lambda capture warnings. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372144 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 17:24:55 +00:00
David Bolvansky
833ff6adf3 Reland "[SLC] Preserve attrs for strncpy(x, "", y) -> memset(align 1 x, '\0', y)"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372142 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 17:12:24 +00:00
Nemanja Ivanovic
1d6894b4f8 [PowerPC] Exploit single instruction load-and-splat for word and doubleword
We currently produce a load, followed by (possibly a move for integers and) a
splat as separate instructions. VSX has always had a splatting load for
doublewords, but as of Power9, we have it for words as well. This patch just
exploits these instructions.

Differential revision: https://reviews.llvm.org/D63624


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372139 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 16:45:20 +00:00
Alina Sbirlea
b68c01e0d7 [MemorySSA] Fix phi insertion when inserting a def.
Summary:
When inserting a Def, the current algorithm is walking edges backward
and inserting new Phis where needed. There may be additional Phis needed
in the IDF of the newly inserted Def and Phis.
Adding Phis in the IDF of the Def was added ina  previous patch, but we
may also need other Phis in the IDF of the newly added Phis.

Reviewers: george.burgess.iv

Subscribers: Prazek, sanjoy.google, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67637

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372138 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 16:33:35 +00:00
Alina Sbirlea
831fe3501a [MemorySSA] Update MSSA for non-conventional AA.
Summary:
Regularly when moving an instruction that may not read or write memory,
the instruction is not modelled in MSSA, so not action is necessary.
For a non-conventional AA pipeline, MSSA needs to explicitly check when
creating accesses, so as to not model instructions that may not read and
write memory.

Reviewers: george.burgess.iv

Subscribers: Prazek, sanjoy.google, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67562

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372137 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 16:31:37 +00:00
Petr Hosek
7ce325b60c Move DK_Misexpect for compatability with getNextAvailablePluginDiagnosticKind
First identified after D66324 landed.

Patch By: paulkirth
Differential Revision: https://reviews.llvm.org/D67648

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372136 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 16:27:36 +00:00
Greg Clayton
d4f9d51f7e GSYM: add encoding and decoding to FunctionInfo
This patch adds encoding and decoding of the FunctionInfo objects along with full error handling and tests. Full details of the FunctionInfo encoding format appear in the FunctionInfo.h header file.

Differential Revision: https://reviews.llvm.org/D67506



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372135 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 16:15:49 +00:00
David Green
fa16ddf26f [ARM] Add a SelectTAddrModeImm7 for MVE narrow loads and stores
We were previously using the SelectT2AddrModeImm7 for both normal and narrowing
MVE loads/stores. As the narrowing instructions do not accept sp as a register,
it makes little sense to optimise a FrameIndex into the load, only to have to
recover that later on. This adds a SelectTAddrModeImm7 which does not do that
folding, and uses it for narrowing load/store patterns.

Differential Revision: https://reviews.llvm.org/D67489


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372134 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 15:32:28 +00:00
David Green
f6b2271403 [ARM] Fixup pipeline test. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372133 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 15:25:24 +00:00
David Green
c399770b5c [ARM] Reserve an emergency spill slot for fp16 addressing modes that need it
Similar to D67327, but this time for the FP16 VLDR and VSTR instructions that
use the AddrMode5FP16 addressing mode. We need to reserve an emergency spill
slot for instructions that will be out of range to use sp directly.
AddrMode5FP16 is 8 bits with a scale of 2.

Differential Revision: https://reviews.llvm.org/D67483


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372132 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 15:23:09 +00:00
Benjamin Kramer
407502440c [RISCV] Unbreak the build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372127 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 14:27:31 +00:00
Sam Parker
f4c9416b67 [ARM] Fix for buildbots
Remove setPreservesCFG from ARMConstantIslandPass and add a couple
of -verify-machine-dom-info instances into the existing codegen
tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372126 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 14:21:36 +00:00
Krasimir Georgiev
d5f8516fb7 Revert "[SLC] Preserve attrs for strncpy(x, "", y) -> memset(align 1 x, '\0', y)"
Summary:
This reverts commit r372101.

Causes ASAN build bot failures:

http://lab.llvm.org:8011/builders/sanitizer-ppc64be-linux/builds/14176
From http://lab.llvm.org:8011/builders/sanitizer-ppc64be-linux/builds/14176/steps/64-bit%20check-asan/logs/stdio:

```
[ RUN      ] AddressSanitizer.StrNCatOOBTest
/home/buildbots/ppc64be-sanitizer/sanitizer-ppc64be/build/llvm-project/compiler-rt/lib/asan/tests/asan_str_test.cpp:462: Failure
Death test: strncat(to - 1, from, 0)
    Result: failed to die.
```

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67658

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372125 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 14:15:23 +00:00
Nico Weber
7166e93a27 gn build: (manually) merge r372076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372123 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 14:06:05 +00:00
George Rimar
95e4c59cb3 [llvm-readobj/llvm-objdump] - Improve how tool locate the dynamic table and report warnings about that.
Before this patch we gave a priority to a dynamic table found
from the section header.

It was discussed (here: https://reviews.llvm.org/D67078?id=218356#inline-602082)
that probably preferring the table from PT_DYNAMIC is better,
because it is what runtime loader sees.

This patch makes the table from PT_DYNAMIC be chosen at first place if it is available.
But also it adds logic to fall back to SHT_DYNAMIC if the table from the dynamic segment is
broken or fall back to use no table if both are broken.

It adds a few more diagnostic warnings for the logic above.

Differential revision: https://reviews.llvm.org/D67547

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372122 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 13:58:46 +00:00
Sam Parker
ec6d4897ce [ARM] Fix for buildbots
Add --verifymachineinstrs and update the remaining low overhead loop
tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372121 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 13:46:26 +00:00
Luis Marques
29210e68f6 [RISCV][NFC] Use NoRegister instead of 0 literal
Summary: Trivial cleanup.

Reviewers: asb, lenary

Reviewed By: lenary

Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67526

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372120 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 13:34:17 +00:00
Simon Pilgrim
65c71da7ab [X86] X86DAGToDAGISel::tryFoldLoad - assert root/parent pointers are non-null. NFCI.
Silences a static analyzer warning.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372118 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 13:27:02 +00:00
Simon Pilgrim
3ea033d82c InterleavedAccessInfo - Don't dereference a dyn_cast result. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372117 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 13:25:56 +00:00
Simon Pilgrim
f2aa921cfe [LoopVectorize] Don't dereference a dyn_cast result. NFCI.
The static analyzer is warning about potential null dereferences of dyn_cast<> results, we can use cast<> directly as we know that these cases should all be CastInst, which is why its working atm and anyway cast<> will assert if they aren't.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372116 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 13:24:54 +00:00
David Green
59654524ce [ARM] Fix for MVE load/store stack accesses
MVE loads and stores have a 7 bit immediate range, scaled by the length of the type. This needs to be taught to the stack estimation code to ensure that an emergency spill slot is reserved in case we run out of registers when materialising stack indices.

Also the narrowing loads/stores can be created with frame indices even though they do not accept SP as a register. We need in those cases to make sure we have an emergency register to use as the frame base, as SP can never be used.

Differential Revision: https://reviews.llvm.org/D67327


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372114 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 12:58:51 +00:00
Benjamin Kramer
1d7df59e12 Hide implementation details in namespaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372113 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 12:56:29 +00:00
Sam Parker
81c57d04ce [ARM][LowOverheadLoops] Add LR def safety check
Converting the *LoopStart pseudo instructions into DLS/WLS results in
LR being defined. These instructions were inserted on the assumption
that LR would already contain the loop counter because a mov is
introduced during ISel as the the consumers in the loop can only use
LR. That assumption proved wrong!

So perform a safety check, finding an appropriate place to insert the
DLS/WLS instructions or revert if this isn't possible.

Differential Revision: https://reviews.llvm.org/D67539

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372111 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 12:19:32 +00:00
George Rimar
5ca1bec788 [llvm-readobj] - Test PPC64 relocations properly.
We had a precompiled binary committed and not all of the relocations
supported were tested. This patch fixes this.

Differential revision: https://reviews.llvm.org/D67617

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372110 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 12:05:39 +00:00
George Rimar
beff567c6d [obj2yaml] - Support PPC64 relocation types.
We do not support them and fail with llvm_unreachable currently.
This is not the only target we do not support and also seems we are missing
the tests for those we have already. But I needed this one for another patch,
so posted it separatelly.

Relocation names are taken from llvm\include\llvm\BinaryFormat\ELFRelocs\PowerPC64.def

Differential revision: https://reviews.llvm.org/D67615

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372109 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 12:00:55 +00:00
George Rimar
d81d976861 [yaml2obj/obj2yaml] - Allow setting an arbitrary values for e_machine.
Currently we only allow using a known named constants
for `Machine` field in YAML documents.

This patch allows using any numbers (valid or "unknown")
and adds test cases for current and new functionality.

With this it is possible to write a test cases for really unknown
EM_* targets.

Differential revision: https://reviews.llvm.org/D67652

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372108 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 11:51:26 +00:00
James Henderson
e2fbdd44a6 [docs] Make --version text more correct
Follow-up to r371983. Referring to "this program" in the description of
the --version option in the documentation isn't exactly correct, because
the docs are not part of the program, and so "this program" doesn't
really refer to anything. This patch brings the other users of this
terminology into line with the new updates to llvm-size and
llvm-strings.

Reviewed by: alexshap, MaskRay

Differential Revision: https://reviews.llvm.org/D67618

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372107 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 11:43:42 +00:00
Luis Marques
85abf858b2 [RISCV] Switch to the Machine Scheduler
Most of the test changes are trivial instruction reorderings and differing
register allocations, without any obvious performance impact.

Differential Revision: https://reviews.llvm.org/D66973

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372106 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 11:15:35 +00:00
Johannes Doerfert
80781fec87 [Attributor][Fix] Initialize the cache prior to using it
Summary:
There were segfaults as we modified and iterated the instruction maps in
the cache at the same time. This was happening because we created new
instructions while we populated the cache. This fix changes the order
in which we perform these actions. First, the caches for the whole
module are created, then we start to create abstract attributes.

I don't have a unit test but the LLVM test suite exposes this problem.

Reviewers: uenoku, sstefan1

Subscribers: hiraditya, bollu, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67232

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372105 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 10:52:41 +00:00
Luis Marques
3049bc0fef Revert Patch from Phabricator
This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372104 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 10:52:09 +00:00
Simon Pilgrim
e1592a6777 [X86] Use APInt::getLowBitsSet helper. NFCI.
Also avoids a static analyzer warning about out of range shifts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372103 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 10:51:30 +00:00
David Bolvansky
d15afd3638 [SLC] Preserve attrs for strncpy(x, "", y) -> memset(align 1 x, '\0', y)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372101 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 10:25:38 +00:00
Graham Hunter
464b4d0dfb [SVE][MVT] Fixed-length vector MVT ranges
* Reordered MVT simple types to group scalable vector types
    together.
  * New range functions in MachineValueType.h to only iterate over
    the fixed-length int/fp vector types.
  * Stopped backends which don't support scalable vector types from
    iterating over scalable types.

Reviewers: sdesmalen, greened

Reviewed By: greened

Differential Revision: https://reviews.llvm.org/D66339


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372099 91177308-0d34-0410-b5e6-96231b3b80d8
2019-09-17 10:19:23 +00:00