Commit Graph

26842 Commits

Author SHA1 Message Date
Krzysztof Parzyszek 4cd3487f7f [Hexagon] Fix extracting subvectors of non-HVX vNi1
Patch by Brendon Cahoon.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343596 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 15:05:43 +00:00
Roman Lebedev fc829e82f6 [NFC][CodeGen][X86] fma.ll, lwp-intrinsics.ll: actually spell --check-prefixes correctly :/
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343588 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 13:34:50 +00:00
Roman Lebedev 67253e401e [NFC][CodeGen][X86] lwp-intrinsics.ll: fix check prefixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343585 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 13:11:08 +00:00
Roman Lebedev d3241c7821 [NFC][CodeGen][X86] fma.ll: fix check prefixes for -mcpu=bdver2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343584 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 13:10:55 +00:00
Simon Pilgrim 16b860b6ae [X86] Standardize floating point assembly comments
Consistently try to use APFloat::toString for floating point constant comments to get rid of differences between Constant / ConstantDataSequential values - it should help stop some of the linux-windows buildbot failures matching NaN/INF etc. as well.

Differential Revision: https://reviews.llvm.org/D52702

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343562 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 09:08:51 +00:00
Matt Arsenault b3a02e1925 AMDGPU: Expand atomicrmw nand in IR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343559 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 03:50:56 +00:00
Thomas Lively 73aeabb0f0 [WebAssembly] Restore slashes in SIMD conversion names
Summary: Depends on D52372 and D52442.

Reviewers: aheejin, dschuff, aardappel

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D52512

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343558 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 01:52:21 +00:00
Fangrui Song 8ffa63b4d5 [AArch64][DAGCombiner]: change -stop-after=isel to instruction-select
"isel" is registered by AMDGPU. The test will break if the AMDGPU target
is not built.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343553 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-02 00:22:51 +00:00
Daniel Sanders d31f3f6227 Revert: r343521 and r343541: [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
There's a strange assertion on two of the Green Dragon bots that goes away when
this is reverted. The assertion is in RegBankAlloc and if it is this commit then
-verify-machine-instrs should have caught it earlier in the pipeline.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343546 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 22:32:08 +00:00
Reid Kleckner 6d4c271eeb [codeview] Emit S_FRAMEPROC and use S_DEFRANGE_FRAMEPOINTER_REL
Summary:
Before this change, LLVM would always describe locals on the stack as
being relative to some specific register, RSP, ESP, EBP, ESI, etc.
Variables in stack memory are pretty common, so there is a special
S_DEFRANGE_FRAMEPOINTER_REL symbol for them. This change uses it to
reduce the size of our debug info.

On top of the size savings, there are cases on 32-bit x86 where local
variables are addressed from ESP, but ESP changes across the function.
Unlike in DWARF, there is no FPO data to describe the stack adjustments
made to push arguments onto the stack and pop them off after the call,
which makes it hard for the debugger to find the local variables in
frames further up the stack.

To handle this, CodeView has a special VFRAME register, which
corresponds to the $T0 variable set by our FPO data in 32-bit.  Offsets
to local variables are instead relative to this value.

This is part of PR38857.

Reviewers: hans, zturner, javed.absar

Subscribers: aprantl, hiraditya, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D52217

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343543 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 21:59:45 +00:00
Craig Topper d8de965221 Recommit r343499 "[X86] Enable load folding in the test shrinking code"
Original message:
This patch adds load folding support to the test shrinking code. This was noticed missing in the review for D52669

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343540 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 21:35:28 +00:00
Craig Topper 6ba8c38c50 Recommit r343498 "[X86] Improve test instruction shrinking when the sign flag is used and the output of the and is truncated."
This includes a fix to prevent i16 compares with i32/i64 ands from being shrunk if bit 15 of the and is set and the sign bit is used.

Original commit message:
Currently we skip looking through truncates if the sign flag is used. But that's overly restrictive.

It's safe to look through the truncate as long as we ensure one of the 3 things when we shrink. Either the MSB of the mask at the shrunken size isn't set. If the mask bit is set then either the shrunk size needs to be equal to the compare size or the sign

There are still missed opportunities to shrink a load and fold it in here. This will be fixed in a future patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343539 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 21:35:26 +00:00
Stefan Pintilie e957cca256 [PowerPC] Folding XForm to DForm loads requires alignment for some DForm loads.
Going from XForm Load to DSForm Load requires that the immediate be 4 byte
aligned.
If we are not aligned we must leave the load as LDX (XForm).
This bug is causing a compile-time failure in the benchmark h264ref.

Differential Revision: https://reviews.llvm.org/D51988

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343525 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 20:16:27 +00:00
Daniel Sanders 55eda328c5 [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
Summary: Depends on D45541

Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar, aemerson

Subscribers: aemerson, rengolin, mgorny, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D45543

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343521 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 18:56:47 +00:00
Matthias Braun 79816c8fee X86, AArch64, ARM: Do not attach debug location to spill/reload instructions
Spill/reload instructions are artificially generated by the compiler and
have no relation to the original source code. So the best thing to do is
not attach any debug location to them (instead of just taking the next
debug location we find on following instructions).

Differential Revision: https://reviews.llvm.org/D52125

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343520 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 18:56:39 +00:00
Craig Topper f6d7cdc06b [X86] Add more test shrinking with truncate and sign bit usage tests. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343519 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 18:52:19 +00:00
Craig Topper 5c1f4358a9 Revert r343499 and r343498. X86 test improvements
There's a subtle bug in the handling of truncate from i32/i64 to i32 without minsize.

I'll be adding more test cases and trying to find a fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343516 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 18:40:44 +00:00
Krzysztof Parzyszek beae29ccd4 [Hexagon] Remove incorrect pattern for swiz
The pattern had a couple of problems:
- It was checking for loads of bytes in the reverse order to what it
  should have been looking for.
- It would replace loads of bytes with a load of a word without making
  sure that the alignment was correct.

Thanks to Eli Friedman for pointing it out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343514 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 18:24:40 +00:00
Matthias Braun 429bce6ae9 MIRParser: Check that instructions only reference DILocation metadata
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343505 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 17:50:52 +00:00
Craig Topper f0bd8cc308 [X86] Enable load folding in the test shrinking code
This patch adds load folding support to the test shrinking code. This was noticed missing in the review for D52669

Differential Revision: https://reviews.llvm.org/D52699

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343499 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 17:10:50 +00:00
Craig Topper b023cfc60d [X86] Improve test instruction shrinking when the sign flag is used and the output of the and is truncated
Currently we skip looking through truncates if the sign flag is used. But that's overly restrictive.

It's safe to look through the truncate as long as we ensure one of the 3 things when we shrink. Either the MSB of the mask at the shrunken size isn't set. If the mask bit is set then either the shrunk size needs to be equal to the compare size or the sign flag needs to be unused.

There are still missed opportunities to shrink a load and fold it in here. This will be fixed in a future patch.

Differential Revision: https://reviews.llvm.org/D52669

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343498 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 17:10:45 +00:00
Simon Pilgrim c442198d91 [X86][Btver2] Fix BT(C|R|S)mr & BT(C|R|S)mi schedule latency + uop counts
Match AMD Fam16h SOG + llvm-exegesis tests

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343494 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 16:31:30 +00:00
Matthias Braun c2625345a6 DAGCombiner: StoreMerging: Fix bad index calculating when adjusting mismatching vector types
This fixes a case of bad index calculation when merging mismatching
vector types. This changes the existing code to just use the existing
extract_{subvector|element} and a bitcast (instead of bitcast first and
then newly created extract_xxx) so we don't need to adjust any indices
in the first place.

rdar://44584718

Differential Revision: https://reviews.llvm.org/D52681

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343493 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 16:25:50 +00:00
Sanjay Patel f8aaa5b2fb [x86] add tests for 256- and 512-bit vector types for scalar-to-vector transform; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343491 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 16:17:18 +00:00
Simon Atanasyan b4f7a97945 [mips] Generate tests expectations using update_llc_test_checks. NFC
Generate tests expectations using update_llc_test_checks and reduce
number of "check prefixes" used in the tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343485 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 14:43:07 +00:00
Clement Courbet d80543967d [X86][Sched] Update scheduling information for VZEROALL on HWS, BDW, SKX, SNB.
Summary:
    While looking at PR35606, I found out that the scheduling info is incorrect.

    One can check that it's really a P5+P6 and not a 2*P56 with:
    echo -e 'vzeroall\nvandps %xmm1, %xmm2, %xmm3' | ./bin/llvm-exegesis -mode=uops -snippets-file=-
    (vandps executes on P5 only)

    Reviewers: craig.topper, RKSimon

    Subscribers: llvm-commits

    Differential Revision: https://reviews.llvm.org/D52541

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343447 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 08:37:48 +00:00
Carlos Alberto Enciso 42b5443507 [DebugInfo][Dexter] Incorrect DBG_VALUE after MCP dead copy instruction removal.
When MachineCopyPropagation eliminates a dead 'copy', its associated debug information becomes invalid. as the recorded register has been removed.  It causes the debugger to display wrong variable value.

Differential Revision: https://reviews.llvm.org/D52614

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343445 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 08:14:44 +00:00
Clement Courbet e7e54cd186 [CodeGen][NFC] Add tests for heterogeneous types in MergeConsecutiveStores
Reviewers: efriedma

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D52643

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343444 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 07:16:22 +00:00
Craig Topper 62c612fdec [X86] Stop X86DomainReassignment from creating copies between GR8/GR16 physical registers and k-registers.
We can only copy between a k-register and a GR32/GR64 register.

This patch detects that the copy will be illegal and prevents the domain reassignment from happening for that closure.

This probably isn't the best fix, and we should probably figure out how to handle this correctly.

Fixes PR38803.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343443 91177308-0d34-0410-b5e6-96231b3b80d8
2018-10-01 07:08:41 +00:00
Simon Pilgrim abccef1dfd [X86] Fix scheduler class for BTmi instructions
This wasn't treated as a folded load instruction

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343424 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-30 20:19:16 +00:00
Bjorn Pettersson cce9df6525 [PHIElimination] Lower a PHI node with only undef uses as IMPLICIT_DEF
Summary:
The lowering of PHI nodes used to detect if all inputs originated
from IMPLICIT_DEF's. If so the PHI node was replaced by an
IMPLICIT_DEF. Now we also consider undef uses when checking the
inputs. So if all inputs are implicitly defined or undef we
lower the PHI to an IMPLICIT_DEF. This makes
PHIElimination::LowerPHINode more consistent as it checks
both implicit and undef properties at later stages.

Reviewers: MatzeB, tstellar

Reviewed By: MatzeB

Subscribers: jvesely, nhaehnle, llvm-commits

Differential Revision: https://reviews.llvm.org/D52558

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343417 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-30 17:26:58 +00:00
Bjorn Pettersson e299be6492 [PHIElimination] Update the regression test for PR16508
Summary:
When PR16508 was solved (in rL185363) a regression test was
added as test/CodeGen/PowerPC/2013-07-01-PHIElimBug.ll.
I discovered that the test case no longer reproduced the
scenario from PR16508. This problem could have been amended
by adding an extra RUN line with "-O1" (or possibly "-O0"),
but instead I added a mir-reproducer
  test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir
to get a reproducer that is less sensitive to changes in
earlier passes (including O-level).

While being at it I also corrected a code comment in
PHIElimination::EliminatePHINodes that has been incorrect
since the related bugfix from rL185363.

Reviewers: MatzeB, hfinkel

Reviewed By: MatzeB

Subscribers: nemanjai, jsji, llvm-commits

Differential Revision: https://reviews.llvm.org/D52553

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343416 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-30 17:23:21 +00:00
Roman Lebedev 219704f8ee [NFC][CodeGen][X86][AArch64] Add 64-bit constant bit field extract pattern tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343404 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-30 12:42:08 +00:00
Simon Pilgrim d09ede4828 [X86] Regenerate MMX coalescing test
Exposes another extractelement(bitcast(scalartovector())) pattern

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343403 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-30 09:42:04 +00:00
Craig Topper ecbe2f8e5e [X86] Disable BMI BEXTR in X86DAGToDAGISel::matchBEXTRFromAnd unless we're on compiling for a CPU with single uop BEXTR
Summary:
This function turns (X >> C1) & C2 into a BMI BEXTR or TBM BEXTRI instruction. For BMI BEXTR we have to materialize an immediate into a register to feed to the BEXTR instruction.

The BMI BEXTR instruction is 2 uops on Intel CPUs. It looks like on SKL its one port 0/6 uop and one port 1/5 uop. Despite what Agner's tables say. I know one of the uops is a regular shift uop so it would have to go through the port 0/6 shifter unit. So that's the same or worse execution wise than the shift+and which is one 0/6 uop and one 0/1/5/6 uop. The move immediate into register is an additional 0/1/5/6 uop.

For now I've limited this transform to AMD CPUs which have a single uop BEXTR. If may also might make sense if we can fold a load or if the and immediate is larger than 32-bits and can't be encoded as a sign extended 32-bit value or if LICM or CSE can hoist the move immediate and share it. But we'd need to look more carefully at that. In the regression I looked at it doesn't look load folding or large immediates were occurring so the regression isn't caused by the loss of those. So we could try to be smarter here if we find a compelling case.

Reviewers: RKSimon, spatel, lebedev.ri, andreadb

Reviewed By: RKSimon

Subscribers: llvm-commits, andreadb, RKSimon

Differential Revision: https://reviews.llvm.org/D52570

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343399 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-30 03:01:46 +00:00
David Bolvansky 21b46b07d7 [DAGCombiner][NFC] Tests for X div/rem Y single bit fold
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343392 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-29 21:00:37 +00:00
Simon Pilgrim ca85b1757c [X86][AVX2] Cleanup shuffle combining tests - add common prefixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343391 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-29 20:34:16 +00:00
Simon Pilgrim bbb291c0d3 [X86] SimplifyDemandedVectorEltsForTargetNode - remove identity target shuffles before simplifying inputs
By removing demanded target shuffles that simplify to zero/undef/identity before simplifying its inputs we improve chances of further simplification, as only the immediate parent user of the combined is added back to the work list - this still doesn't help us if its passed through other ops though (bitcasts....).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343390 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-29 18:15:26 +00:00
Craig Topper 59b80ed4d5 [X86] Add fast-isel test cases for unaligned load/store intrinsics recently added to clang
This adds tests for:
_mm_loadu_si16
_mm_loadu_si32
_mm_loadu_si16
_mm_storeu_si64
_mm_storeu_si32
_mm_storeu_si16

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343389 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-29 18:03:52 +00:00
Simon Pilgrim bb664accc2 [X86] getTargetConstantBitsFromNode - add support for rearranging constant bits via shuffles
Exposed an issue that recursive calls to getTargetConstantBitsFromNode don't handle changes to EltSizeInBits yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343384 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-29 17:01:55 +00:00
Simon Pilgrim db283fd1bb [X86] Regenerate fma comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343376 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-29 14:31:00 +00:00
Simon Pilgrim 2a55d07e77 [X86] getTargetConstantBitsFromNode - add support for peeking through ISD::EXTRACT_SUBVECTOR
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343375 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-29 14:17:32 +00:00
Simon Pilgrim a1ab644481 [X86][SSE] Fixed issue with v2i64 variable shifts on 32-bit targets
The shift amount might have peeked through a extract_subvector, altering the number of vector elements in the 'Amt' variable - so we were incorrectly calculating the ratio when peeking through bitcasts, resulting in incorrectly detecting splats.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343373 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-29 13:25:22 +00:00
Eli Friedman b10248393f [ARM] Fix correctness checks in promoteToConstantPool.
Correctly check for relocations in the constant to promote. And don't
allow promoting a constant multiple times.

This partially fixes https://bugs.llvm.org//show_bug.cgi?id=32780 ;
it's not a complete fix because we also need to prevent
ARMConstantIslands from cloning the constant.

(-arm-promote-constant is currently off by default, and it stays off
with this patch. I'll look into turning it on again when all the known
issues are fixed.)

Differential Revision: https://reviews.llvm.org/D51472



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343361 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-28 20:27:31 +00:00
Eli Friedman 770516eb32 [ARM] Use preferred alignment for constants in promoteToConstantPool.
This mostly affects IR generated by non-clang frontends because clang
generally sets the alignment of globals explicitly.

Fixes https://bugs.llvm.org//show_bug.cgi?id=32394 .

(-arm-promote-constant is currently off by default, and it stays off
with this patch. I'll look into turning it on again when all the known
issues are fixed.)

Differential Revision: https://reviews.llvm.org/D51469



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343359 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-28 20:21:51 +00:00
Craig Topper 46f964d38a [X86] Add test cases for failures to use narrow test with immediate instructions when a truncate is beteen the CMP and the AND and the sign flag is used.
The code in X86ISelDAGToDAG only looks through truncates if the sign flag isn't used, but that is overly restrictive. A future patch will improve this.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343355 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-28 19:06:28 +00:00
Evandro Menezes 6fbdafa0d5 [AArch64] Split zero cycle feature more granularly
Split the `zcz` feature into specific ones got GP and FP registers, `zcz-gp`
and `zcz-fp`, respectively, while retaining the original feature option to
mean both.

Differential revision: https://reviews.llvm.org/D52621

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343354 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-28 19:05:09 +00:00
Luke Cheeseman 4c6cb9f427 Revert r343317
- asan buildbots are breaking and I need to investigate the issue



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343341 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-28 17:01:50 +00:00
Aditya Nandakumar 88ba134609 [GISel]: Remove an incorrect assert in CallLowering
https://reviews.llvm.org/D51147

Asserting if any extend of vectors should be up to the target's
legalizer/target specific code not in CallLowering.

reviewed by : dsanders.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343325 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-28 15:08:49 +00:00
Luke Cheeseman 96f82d5c18 Reapply changes reverted by r343235
- Add fix so that all code paths that create DWARFContext
  with an ObjectFile initialise the target architecture in the context
- Add an assert that the Arch is known in the Dwarf CallFrameString method



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343317 91177308-0d34-0410-b5e6-96231b3b80d8
2018-09-28 13:37:27 +00:00